1
Zarlink Semiconductor Inc.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 1997-2011, Zarlink Semiconductor Inc. All Rights Reserved.
Features
• Internal control latches and address decoder
• Short set-up and hold times
• Wide operating voltage: 4.5V to 13.2V
• 12Vpp analog signal capability
•R
ON 65 max. @ VDD=12V, 25×C
•RON 10 @ VDD=12V, 25C
• Full CMOS switch for low distorti on
• Minimum feedthrough and crosstalk
• Separate analog and digital reference supplies
• Low power consumption ISO-CMOS technology
Applications
• Key systems
• PBX systems
• Mobile radio
• Test equipment /instrumentation
• Analog/digital multiplexers
• Audio/Video switching
Description
The Zarlink MT8815 is fabricated in Zarlink’s ISO-
CMOS technology providing low power dissipation and
high reliability. The device contains a 8 x 12 array of
crosspoint switches along with a 7 to 96 line decoder
and latch circuits. Any one of the 96 switches can be
addressed by selecting the appropriate seven address
bits. The selected switch can be turned on or off by
applying a logical one or zero to the DATA input. VSS is
the ground reference of the digital inputs. The range of
the analog signal is from VDD to VEE.
September 2011
Ordering Information
MT8815AP1 44 Pin PLCC* Tubes
MT8815APR1 44 Pin PLCC* Tape & Reel
MT8815AE1 40 Pin PDIP* Tubes
*Pb Free Matte Tin
-40C to +85C
MT8815
8 x 12 Analog Switch Array
Data Sheet
Figure 1 - Functional Block Diagram
7 to 96
Decoder Latches
8 x 12
Switch
Array
STROBE DATA RESET VDD VEE VSS
Xi I/O
(i=0-11)
Yi I/O (i=0-7)
11
9696
• • • • • • • • • • • • • • • • • • •
• • • • • • • • • • • • • • • •
AX0
AX1
AY0
AY1
AY2
AX2
AX3
MT8815 Data Sheet
2
Zarlink Semiconductor Inc.
Change Summary
Changes from the December 2008 issue to the September 2011 issue.
Changes from August 2005 to December 2008 issue.
Figure 2 - Pin Connections
Page Item Change
1 Ordering Information Removed leaded packag es as per PCN notice.
Page Item Change
1 Ordering Information MT8815AE removed - obsolete. Added pb free part numbers.
Pin Description
Pin # Name Description
PDIP PLCC
11Y3Y3 Analog (Input/Output): this is connected to the Y3 column of the switch
array.
22AY2Y2 Address Line (Input).
3 3 RESET Master RESET (Input): this is used to turn off all switches. Active High.
4,5 4,5 AX3,AX0 X3 and X0 Address Lines (Inputs): these are used to select X3 and X0 rows of
switches.
6,7 6-8 NC No Connection.
8-13 9-14 X6-X11 X6-X11 Analog (Input s/Outputs): these are con nected to the X6 -X11 rows of the
switch array.
40 PIN PLASTIC DIP 44 PIN PLCC
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
140
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
AY2
RESET
AX3
AX0
NC
NC
X6
X7
X8
X9
X10
X11
NC
Y7
VSS
Y6
STROBE
Y5
VEE
Y3 Y2
DATA
Y1
VDD
Y0
NC
X0
X1
X2
X3
X4
X5
NC
NC
AY1
AY0
AX2
AX1
Y4
NC
NC
NC
X6
X7
X8
X9
X10
X11
NC
NC
Y7
VSS
Y6
STROBE
Y5
VEE
AX1
AX2
AY0
AY1
NC
Y4
1
6 5 4 3 2 4443424140
7
8
9
10
11
12
13
14
15
16
39
38
37
36
35
34
33
32
31
30
231819202122 2425262728
17 29
Y0
NC
X0
X1
X2
X3
X4
X5
NC
NC
NC
VDD
Y1
DATA
Y2
NC
Y3
AY2
RESET
AX3
AX0
NC
MT8815 Data Sheet
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Zarlink Semiconductor Inc.
14 15,16 NC No Connection
15 17 Y7 Y7 Analog (Input/Output): this is connected to the Y7 column of the switch
array.
16 18 VSS Digital Ground Reference (Input).
17 19 Y6 Y6 Analog (Input/Output): this is connected to the Y6 column of the switch
array.
18 20 STROBE STROBE (Input): enables function selected by address and data. Address must
be stable before ST ROBE goes high a nd D ATA must be stable on the fallin g ed ge
of the STROBE. Active High.
19 21 Y5 Y5 Analog (Input/Output): this is connected to the Y5 column of the switch
array.
20 22 VEE Negative Power Supply.
21 23 Y4 Y4 Analog (Input/Output): this is connected to the Y4 column of the switch
array.
22, 23 24,25 AX1,AX2 X1 and X2 Address Lines (Inputs).
24, 25 26,27 AY0,AY1 Y0 and Y1 Address Lines (Inputs).
26, 27 28-31 NC No Connection.
28 - 33 32-37 X 5-X0 X5-X0 Analog (Inputs/Outputs): these are connected to the X5-X0 rows of the
switch array.
34 38 NC No Connection.
35 39 Y0 Y0 Analog (Input/Output): this is conne cted to the Y0 column of the switch array.
36 40 VDD Positive Power Supply.
37 41 Y1 Y1 Analog (Input/Output): this is conne cted to the Y1 column of the switch array.
38 42 DATA DATA (Input): a lo gic high input will turn on the selected switch and a logic low will
turn off the selected switch. Active High.
39 43 Y2 Y2 Analog (Input/Output): this is conne cted to the Y2 column of the switch array.
40 44 NC No Connection.
Pin Description
Pin # Name Description
PDIP PLCC
MT8815 Data Sheet
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Zarlink Semiconductor Inc.
Functional Description
The MT8815 is an analog switch matrix with an array size of 8×12. The switch array is arranged such that there are
8 columns by 12 rows. The columns are referred to as the Y inputs/outputs and the rows are the X inputs/outputs.
The crosspoint analog switch array will interconnect any X I/O with any Y I/O when turned on and provide a high
degree of isolation when turned off. The control memory consists of a 96 bit write only RAM in which the bits are
selected by the address inputs (AY0-AY2, AX0-AX3). Data is presented to the memory on the DATA input. Data is
asynchronously written into memory whenever the STROBE input is high and is latched on the falling edge of
STROBE. A logical “1” written into a memory cell turns the corresponding crosspoint switch on and a logical “0”
turns the crosspoint off. Only the crosspoint switches corresponding to the addressed memory location are altered
when data is written into memory. The remaining switches retain their previous states. Any combination of X and Y
inputs/outputs can be interconnected by establishing appropriate patterns in the control memory. A logical “1” on
the RESET input will asynchronously return all memory locations to logical “0” turning off all crosspoint
switches. Two voltage reference pins (VSS and VEE) are provided for the MT8815 to enable switching of negative
analog signals. The range for digital signals is from VDD to VSS while the range for analog signals is from VDD to
VEE. VSS and VEE pins can be tied together if a single voltage reference is needed.
Address Decode
The seven address inputs along with the STROBE are logically ANDed to form an enable signal for the resettable
transparent latch es. The DATA input is buffered and is u sed as the input to all latches. To write to a location, RESET
must be low while the address and data are set up. Then the STROBE input is set high and then low causing the
data to be latched. The data can be changed while STROBE is high, however, the corresponding switch will turn on
and off in accordance with the DATA input. DATA must be stable on the falling edge of STROBE in order for correct
data to be written to the latch.
MT8815 Data Sheet
5
Zarlink Semiconductor Inc.
* Exceeding these values may cause permanent damage. Functional operation under these conditi ons is not implied.
† DC Electrical Charac teristics are over recommende d temperature range.
‡ Typical fi gures are at 25C and are for design aid only; not guaranteed and not subject to production testing.
Absolute Maximum Ratings*- Voltages are with respect to VEE unless otherwise stated.
Parameter Symbol Min. Max. Units
1 Supply Voltage VDD
VSS -0.3
-0.3 15.0
VDD+0.3 V
V
2 Analog Input Voltage VINA -0.3 VDD+0.3 V
3 D igital Input Voltage VIN VSS-0.3 VDD+0.3 V
4 C urrent on any I/O Pin I ±15 mA
5 Storage Temperature TS-65 +150 C
6 P ackage Power Dissipation PLASTIC DIP PD0.6 W
Recommended Operating Conditions - Voltages are with respect to VEE unless otherwise stated.
Characteristics Sym. Min. Typ. Max. Units Tes t Conditions
1 Operating Temperature TO-40 25 85 C
2 Supply Voltage VDD
VSS 4.5
VEE 13.2
VDD-4.5 V
V
3 Analog Input V oltage VINA VEE VDD V
4 Digital Input Voltage VIN VSS VDD V
DC Electrical Characteristics†- Voltages are with respect to VEE=VSS=0V, VDD =12V unless ot herwise stated.
Characteristics Sym. Min. Typ.‡Max. Units Test Conditions
1 Quiescent Supply Current IDD 1 100 A All digital inputs at VIN=VSS or
VDD
0.4 1.5 mA All digital inputs at VIN=2.4V +
VSS; VSS=7.0V
5 1 5 mA All digital inputs at VIN=3.4V
2 Off-state Leakage Current
(See G.9 in Appendix) IOFF 1500 nA IVXi - VYjI = VDD - VEE
See Appendix, Fig. A.1
3 Input Logic “0” level VIL 0.8+VSS VV
SS=7.5V; VEE=0V
4 Input Logic “1” level VIH 2.0+VSS VV
SS=6.5V; VEE=0V
5 Input Logic “1” level VIH 3.3 V
6 Input Leakage (digital pins) ILEAK 0.1 10 A All digital inputs at VIN = VSS
or VDD
MT8815 Data Sheet
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Zarlink Semiconductor Inc.
† Timing is over recommended temperature range. See Fig. 3 for control and I/O timing details.
‡ Typical fi gures are at 25C and are for design aid only; not guaranteed and not subject to production testing.
Crosstalk measureme nts are for Plastic D IPS only, crosstalk values for PLCC packages are approximat ely 5 dB better.
DC Electrical Characteristics- Switch Resistance - VDC is the external DC offset applied at the analog I/O pins.
Characteristics Sym 25C70C85C Units Test Conditions
Typ. Max. Typ. Max. Typ. Max.
1 On-state VDD=12V
Resistance VDD=10V
VDD= 5V
(See G.1, G.2, G.3 in
Appendix)
RON 45
55
120
65
75
185
75
85
215
80
90
225
VSS=VEE=0V,VDC=VDD/2,
IVXi-VYjI = 0.4V
See Appendix, Fig. A.2
2 Difference in on-state
resistance between two
switches
(See G.4 in Appendix)
RON 510 10 10 VDD=12V, VSS=VEE=0,
VDC=VDD/2,
IVXi-VYjI = 0.4V
See Appendix, Fig. A.2
AC Electrical Characteristics† - Crosspoint Performance-Voltages are with respect to VDD=5V, VSS=0V,
VEE=-7V, unless otherwise stated.
Characteristics Sym. Min. Typ.‡Max. Units Test Conditions
1 Switch I/O Capacitance CS20 pF f=1 MHz
2 Feedthrough Capacitance CF0.2 pF f=1 MHz
3 Frequency Response
Channel “ON”
20LOG(VOUT/VXi)=-3dB
F3dB 45 MHz Switch is “ON”; VINA = 2Vpp
sinewave; RL = 1k
See Appendix, Fig. A.3
4 Total Harmonic Distortion
(See G.5, G.6 in Appendix) THD 0.01 % Switch is “ON”; VINA = 2Vpp
sinewave f= 1kHz; RL=1k
5 Feedthrough
Channel “OFF”
Feed.=20LOG (VOUT/VXi)
(See G.8 in Appendix)
FDT -95 dB All Switches “OFF”; VINA=
2Vpp sinewave f= 1kHz;
RL= 1k.
See Appendix, Fig. A.4
6 Crosstalk between any two
channels for switches Xi-Yi and
Xj-Yj.
Xtalk=20LOG (VYj/VXi).
(See G.7 in Appendix).
Xtalk -45 dB VINA=2Vpp sinewave
f= 10MHz; RL = 75.
-90 dB VINA=2Vpp sinewave
f= 10kHz; RL = 600.
-85 dB VINA=2Vpp sinewave
f= 10kHz; RL = 1k.
-80 dB VINA=2Vpp sinewave
f= 1kHz; RL = 10k.
Refer to Appendix , Fig. A .5
for test circuit.
7 Propagation delay through
switch tPS 30 ns RL=1k; CL=50pF
MT8815 Data Sheet
7
Zarlink Semiconductor Inc.
† Timing is over recommended temperature range. See Fig. 3 for control and I/O timing details.
Digital Input rise time (tr) and fall time (tf) = 5ns.
‡ Typical fi gures are at 25C and are for design aid only; not guaranteed and not subject to production testing.
1 Refer to Appendix, Fig. A.7 for test circuit.
Figure 3 - Control Memory Timing Diagram
* See Appendix, Fig. A.7 for switching waveform
AC Electrical Characteristics† - Control and I/O Timings- Voltages are with respect to VDD=5V, VSS=0V,
VEE=-7V, unless otherwise stated.
Characteristics Sym. Min. Typ.‡Max. Units Test Conditions
1 Control Input crosstalk to switch
(for DATA, STROBE, Address) CXtalk 30 mVpp VIN=3V squarewave;
RIN=1k, RL=10k.
See Appendix, Fig. A.6
2 Digital Input Cap acitance CDI 10 pF f=1MHz
3 Switching Frequency FO20 MHz
4 Setup Time DATA to STROBE tDS 10 ns RL= 1k, CL=50pF
5 Hold Time DATA to STROBE tDH 10 ns RL= 1k, CL=50pF 1
6 Setup Time Address to STROBE tAS 10 ns RL= 1k, CL=50pF 1
7 Hold Time Address to STROBE tAH 10 ns RL= 1k, CL=50pF 1
8 STROBE Pulse Width tSPW 20 ns RL= 1k, CL=50pF 1
9 RESET Pulse Width tRPW 40 ns RL= 1k, CL=50pF 1
10 STROBE to Switch Status Delay tS40 100 ns RL= 1k, CL=50pF 1
11 DATA to Switch Status Delay tD50 100 ns RL= 1k, CL=50pF 1
12 RESET to Switch Status Delay tR35 100 ns RL= 1k, CL=50pF 1
tRPW
tSPW
tAS
tAH
tDH
tDtStRtR
tDS
50% 50%
50%50%50%
50% 50%
50% 50%
RESET
STROBE
ADDRESS
DATA
SWITCH* ON
OFF
MT8815 Data Sheet
8
Zarlink Semiconductor Inc.
Table 1 - Address Decode Truth Table
This address has no effect on device status.
AX0 AX1 AX2 AX3 AY0 AY1 AY2 Connection
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
X0-Y0
X1-Y0
X2-Y0
X3-Y0
X4-Y0
X5-Y0
No Connection
No Connection
X6-Y0
X7-Y0
X8-Y0
X9-Y0
X10-Y0
X11-Y0
No Connection
No Connection
0
1
0
0
0
1
0
1
1
1
0
0
0
0
X0-Y1
X11-Y1
0
1
0
0
0
1
0
1
0
0
1
1
0
0
X0-Y2
X11-Y2
0
1
0
0
0
1
0
1
1
1
1
1
0
0
X0-Y3
X11-Y3
0
1
0
0
0
1
0
1
0
0
0
0
1
1
X0-Y4
X11-Y4
0
1
0
0
0
1
0
1
1
1
0
0
1
1
X0-Y5
X11-Y5
0
1
0
0
0
1
0
1
0
0
1
1
1
1
X0-Y6
X11-Y6
0
1
0
0
0
1
0
1
1
1
1
1
1
1
X0-Y7
X11-Y7
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Information relating to products and services furnished herein by Zarlink Semiconductor Inc. or its subsidiaries (collectively “Zarlink”) is believed to be reliable.
However, Zarlink assumes no liability for errors that may appear in this publication, or for liability otherwise arising from the application or use of any such
information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may result from such application or
use. Neither the supply of such information or purchase of product or service conveys any license, either express or implied, under patents or other intellectual
property rights owned by Zarlink or licensed from third parties by Zarlink, whatsoever. Purchasers of products are also hereby notified that the use of product in
certain ways or in combination with Zarlink, or non-Za rlink furnished goods or services may infringe patents or other intellectual property rights owned by Zarlink.
This publication is issued to provide information only and (unless agreed by Zarlink in writing) may not be used, applied or reproduced for any purpose nor form part
of any order or contract nor to be regarded as a representation relating to the products or services concerned. The pr oducts, their specifications, services a nd other
information appearing in this publication are subject to change by Zarlink without notice. No warranty or guarantee express or implied is made regarding the
capability, performance or suitability o f any pro duct or service. I nformatio n concer ning po ssible met hods of use is p rovide d as a guide only and doe s not constit ute
any guarantee th at such methods of use will be satisfactory in a sp ecific piece of equip ment. It is the user ’s responsibili ty to fully determine the performance and
suitability of any equipment using such information and to ensure that any publication or data used is up t o date and has not been superseded. Manufacturing does
not necessarily include testing of all functions or paramete rs. These products are not suitable for use in any medical products whose failure to perform may result in
significant injury or death to the user . All products and materials are sold and services provided subject to Zarlink’s conditions of sa le w hich are avai la ble on req ues t.
Purchase of Zarlink’s I2C components conveys a license un der the Philips I2C Patent rights to use thes e components in an I2C System, provided that the syste m
conforms to the I2C Standard Specification as defined by Philips.
Zarlink, ZL, the Zarlink Semiconductor logo and the Legerity logo and combinations thereof, VoiceEdge, VoicePort, SLAC, ISLIC, ISLAC and VoicePath are
trademarks of Zarlink Semiconductor Inc.
TECHNICAL DOCUMENTATION - NOT FOR RESALE
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