www.ti.com SLVS426 - MAY 2002 FEATURES APPLICATIONS D Notebook PCs, PDAs D Consumer Game Systems D DSP Application D Three Independent Step-Down DC/DC Controllers and One LDO Controller D Input Voltage Range - Switcher: 4.5 V ~ 28 V - LDO: 1.1 V ~ 3.6 V DESCRIPTION The TPS5130 is composed of three independent synchronous buck regulator controllers (SBRC) and one low drop-out (LDO) regulator controller. On-chip high-side and low-side synchronous rectifier drivers are integrated to drive less expensive N-channel MOSFETs. The LDO controller can also drive an external N-channel MOSFET. Since the input current ripple is minimized by operating 180 degree out of phase, it allows a smaller input capacitance resulting in reduced power supply cost. The SBRC of the TPS5130 automatically adjusts from PWM mode to SKIP mode to maintain high efficiency under light load conditions. Resistor-less current protection for the synchronous buck controller and the fixed high-side driver voltage simplifies the system design and reduces the external parts count. The LDO controller has a current limit protection and overshoot protection to suppress output voltage hump at load transient. To further extend battery life, the TPS5130 features dead-time control and very low quiescent current. D Output Voltage Range - Switcher: 0.9 V ~ 5.5 V - LDO: 0.9 V ~ 2.5 V D D D D D D Synchronous for High Efficiency D D D D Overvoltage and Undervoltage Protection Precision Vref (1.5%) PWM Mode Control : Max. 500 kHz Operation Auto PWM/SKIP Mode Available High Speed Error Amplifier Over Current Protection With Temperature Compensation Circuit for Each Channel Programmable Short-Circuit Protection Powergood With Programmable Delay Time 5-V and 3.3-V Linear Regulators VIN VIN OUT3_u Vo3 OUT1_u LL3 LL1 OUT3_d Vo1 5V OUT1_d TPS5130 INV3 INV1 REG5V_IN LDO_IN OUT2_u LDO_CUR LL2 Vo3 LDO_GATE OUT2_d Vo_LDO INV_LDO GND INV2 See application section of this data sheet for more detailed information. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. ! "#$ ! %#&'" ($) (#"! " !%$""! %$ *$ $! $+! !#$! !(( ,-) (#" %"$!!. ($! $"$!!'- "'#($ $!. '' %$$!) Copyright 2002, Texas Instruments Incorporated www.ti.com SLVS426 - MAY 2002 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. ORDERING INFORMATION PACKAGED DEVICES PLASTIC TQFP (PT)(1) TA -40C to 85C TPS5130PT (1) The PT package is also available taped and reeled. Add an R suffix to the device type (i.e., TPS5130PTR). PACKAGE DISSIPATION RATINGS PACKAGE(1) TA 25C POWER RATING DERATING FACTOR ABOVE TA = 25C 25.7 mW/C TA = 85C POWER RATING 48 pin PT 3210 mW 1670 mW (1) These devices are mounted on a JEDEC high-k board (2 oz. traces on surface, 2-layer 1 oz. plane inside). (Assumes the maximum junction temperature is 150C) ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range unless otherwise noted(1) TPS5130 Supply voltage, (2) VIN Input voltage range(2), VI Output voltage range, VO (2) -0.3 V to 30 V LH1/2/3 -0.3 V to 35 V VIN_SENSE12/3, LL1/2/3, STBY_LDO, STBY_VREF3.3/5, TRIP1/2/3 -0.3 V to 30 V INV1/2/3, CT, SS_STBY1/2/3, INV_LDO, LDO_OUT, FLT, PG_DELAY, VREF3.3/5, LDO_IN, LDO_CUR, PWM_SEL, REG5V_IN -0.3 V to 7 V OUT1/2/3_u -0.3 V to 35 V FB1/2/3, PGOUT, OUT1/2/3_d -0.3 V to 7 V LDO_GATE -0.3 V to 9 V REF Operating ambient temperature range, TA -0.3 V to 3 V -40C to 85C Storage temperature, Tstg -55C to 150C (1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) All voltage values are with respect to the network ground terminal. 2 www.ti.com SLVS426 - MAY 2002 RECOMMENDED OPERATING CONDITIONS MIN Supply voltage MAX UNIT 4.5 28 LDO_IN 1.1 3.6 REG5V_IN 4.5 5.5 -0.1 33 4.5 28 STBY_LDO, LL1/2/3, TRIP, STBY_VREF3.3/5 -0.1 28 LDO_GATE -0.1 8 INV1/2/3, INV_LDO, CT, PWM_SEL, FLT, PG_DELAY, SS_STBY1/2/3 -0.1 6 PGOUT, FB1/2/3, OUT1/2/3_d -0.1 5.5 LDO_CUR, LDO_OUT -0.1 3.5 OUT1/2/3_u, LH1/2/3 VIN_SENSE1/2/3 Input voltage, VI NOM VIN Oscillator frequency, fosc 300 Operating free-air temperature, TA V V 500 kHz 85 C -40 ELECTRICAL CHARACTERISTICS over operating free-air temperature range, V(VIN) = V(VIN_SENSE12) = V(VIN_SENSE3) = 12 V (unless otherwise noted) Supply Current PARAMETER ICC Supply current ICC(STBY) Standby current ICC(S) Shutdown current TEST CONDITIONS TA = 25C, V(LDO_IN) = 3.6 V, V(CT) = V(INVx) = V(INV_LDO) = 0 V, V(SS_STBYx) = 0 V, V(STBY_LDO) = 0V, V(STBY_VREF3.3/5) = 5 V V(SS_STBYx) = 0 V, V(STBY_LDO) = 0V, V(STBY_VREF3.3/5) = 0 V MIN V(PWM_SEL) = 0 V TYP MAX UNIT 2 3 mA 150 250 A 0.001 10 A TYP MAX Reference Voltage PARAMETER Vref TEST CONDITIONS MIN Reference voltage 0.85 V TA = 25C, TA = 0C to 85C, Iref = 50 A Iref = 50 A -1.5% -2% 2% Iref = 50 A Iref = 50 A -2.5% 2.5% Line regulation TA = -40C to 85C, V(VIN) = 4.5 V to 28 V, Load regulation Iref = 0.1 A to 1 mA Vref(tol) Reference voltage tolerance UNIT 1.5% 0.05 5 mV 0.15 5 mV TYP MAX 5 V Internal Switch PARAMETER VT(LH) VT(HL) Threshold voltage Vhys Hysteresis TEST CONDITIONS High Low REG5V_IN voltage REG5V_IN voltage MIN UNIT 4.2 4.8 4.1 4.7 30 200 mV MAX UNIT V VREF5 PARAMETER VO TEST CONDITIONS IO = 0 mA to 50 mA, V(VIN) = 5.5 V to 28 V, V(VIN) = 5.5 V to 28 V, Output voltage Line regulation Load regulation IOS VT(LH) VT(HL) Vhys IO = 1 mA to 10 mA, V(VREF5) = 0 V, Short-circuit output current High UVLO threshold voltage Hysteresis Low VREF5 voltage VREF5 voltage TA = 25C IO = 10 mA V(VIN) = 5.5 V TA = 25C MIN 4.8 TYP 5.2 V 20 mV 40 mV 65 mA 3.6 4.2 3.5 4.1 30 200 V mV 3 www.ti.com SLVS426 - MAY 2002 ELECTRICAL CHARACTERISTICS (continued) over operating free-air temperature range, V(VIN) = V(VIN_SENSE12) = V(VIN_SENSE3) = 12 V (unless otherwise noted) VREF3.3 PARAMETER VO TEST CONDITIONS IO = 0 mA to 30 mA, TA = 25C V(VIN) = 5.5 V to 28 V, Output voltage Line regulation Load regulation IOS Short circuit output current IO = 1 mA to 10 mA, V(VREF3.3) = 0 V, V(VIN) = 5.5 V to 28 V, MIN TYP MAX UNIT 3.15 3.30 3.45 V IO = 10 mA V(VIN) = 5.5 V TA = 25C -30 TEST CONDITIONS MIN 20 mV 40 mV mA Control PARAMETER VIH VIL High-level input voltage SS_STBYx, STBY_LDO, PWM_SEL, STBY_VREF3.3/5 Low-level input voltage SS_STBYx, STBY_LDO, PWM_SEL, STBY_VREF3.3/5 TYP MAX 2.2 UNIT V 0.3 V Output Voltage Monitor MIN TYP MAX UNIT OVP comparator threshold PARAMETER SBRC, LDO TEST CONDITIONS 0.91 0.95 0.99 V UVP comparator threshold SBRC, LDO 0.51 0.55 0.59 V PG comparator low-level threshold 0.75 0.79 0.81 V PG comparator high-level threshold 0.88 0.91 0.94 V PG propagation delay from INVx, INV_LDO to PGOUT (no load at PG_DELAY) I(PG_DELAY) Powergood H to L 6.5 Powergood L to H 16 PG_DELAY source current ss A -1.8 Timer latch current source UVP protection -1.5 -2.3 -3.1 OVP protection -80 -125 -180 MIN TYP MAX A Oscillator PARAMETER fosc Oscillation frequency VOH High level output voltage VOL Low level output voltage TEST CONDITIONS PWM mode, C(CT) = 44 pF, dc TA = 25C fosc = 300 kHz dc 300 1 1.1 kHz 1.2 V 1.17 0.4 fosc = 300 kHz 0.5 UNIT 0.6 V 0.43 Error Amplifier for SBRC PARAMETER VIO Input offset voltage TEST CONDITIONS INVx voltage, MIN TA = 25C Open loop voltage gain Output sink current Output source current MAX 2 10 50 Unity-gain bandwidth IO(snk) IO(src) TYP V(FBx) = 1 V V(FBx) = 1 V UNIT mV dB 2.5 MHz 0.2 0.7 mA -0.2 -0.9 mA Duty Control PARAMETER Maximum duty control 4 TEST CONDITIONS CH1/3, fosc = 300 kHz, V(INVx) = 0 V CH2, fosc = 300 kHz, V(INVx) = 0 V MIN TYP 82% 97% MAX UNIT www.ti.com SLVS426 - MAY 2002 ELECTRICAL CHARACTERISTICS (continued) over operating free-air temperature range, V(VIN) = V(VIN_SENSE12) = V(VIN_SENSE3) = 12 V (unless otherwise noted) Output Drivers PARAMETER OUT_u sink current OUT_u source current OUT_d sink current OUT_d source current LDO_GATE sink current I(TRIPx) TEST CONDITIONS MIN V(OUTx_u) - V(LLx) = 3 V V(LHx) - V(OUTx_u) = 3 V V(OUTx_d) = 3 V V(OUTx_d) = 2 V LDO_GATE source current V(LDO_GATE) = 2 V V(LDO_GATE) = 2 V TRIP current TA = 25C TYP MAX UNIT 1.2 A -1.2 A 1.5 A -1.5 A 2 mA -1.4 mA A 11 13 15 MIN TYP MAX UNIT -1.6 -2.3 -2.9 A TEST CONDITIONS MIN TYP MAX UNIT V(LDO_IN) = 3.3 V, TA = 25 C V(LDO_IN) = 3.3 V 2 10 Open loop voltage gain 50 Unity-gain bandwidth V(LDO_IN) = 3.3 V, CL = 2000 pF Soft Start PARAMETER I(SS_STBYx) Soft start current TEST CONDITIONS V(SS_STBYx) = 0.7 V Error Amplifier for LDO Controller PARAMETER VIO Input offset voltage mV dB 1.4 MHz Current Limit for LDO Controller PARAMETER Current limit comparator threshold voltage TEST CONDITIONS V(LDO_IN) = 3.3 V MIN TYP MAX 40 50 60 MIN TYP MAX UNIT mV Overshoot Protection for LDO Controller PARAMETER LDO_OUT sink current TEST CONDITIONS V(LDO_OUT) = V(LDO_GATE) = 1.5 V 25 UNIT mA 5 www.ti.com SLVS426 - MAY 2002 PIN ASSIGNMENTS VIN_SENSE12 41 40 39 38 37 TRIP2 OUT2_d 43 42 TRIP1 OUTGND1 OUT1_d LL1 OUT1_u 46 45 44 OUTGND2 48 47 LH1 FLT INV1 PT (TOP VIEW) 36 LL2 SS_STBY1 2 35 OUT2_u INV2 3 34 LH2 FB2 4 33 VIN SS_STBY2 5 32 VREF3.3 PWM_SEL 6 31 VREF5 CT 7 30 REG5V_IN GND 8 29 LDO_IN REF 9 28 LDO_CUR STBY_VREF5 10 27 LDO_GATE STBY_VREF3.3 11 26 LDO_OUT STBY_LDO 12 25 INV_LDO 24 OUTGND3 OUT3_d LL3 OUT3_u 20 21 22 23 LH3 VIN_SENSE3 18 19 TRIP3 PG_DELAY PGOUT 15 16 17 FB3 13 14 INV3 1 SS_STBY3 FB1 Terminal Functions TERMINAL NAME NO. I/O DESCRIPTION CT 7 I/O External capacitor from CT to GND adjusts frequency of the triangle oscillator. FB1 1 O Feedback output of SBRC-CH1 error amplifier FB2 4 O Feedback output of SBRC-CH2 error amplifier FB3 14 O Feedback output of SBRC-CH3 error amplifier FLT 47 I/O Fault latch timer pin. An external capacitor connected between FLT and GND sets FLT enable time up. GND 8 - Signal GND INV1 48 I Inverting inputs of SBRC-CH1 error amplifier, skip comparator, OVP1/UVP1 comparator and PG comparator INV2 3 I Inverting inputs of SBRC-CH2 error amplifier, skip comparator, OVP2/UVP2 comparator and PG comparator INV3 15 I Inverting inputs of SBRC-CH3 error amplifier, skip comparator, OVP3/UVP3 comparator and PG comparator INV_LDO 25 I Inverting inputs of LDO error amplifier, OVP/UVP comparators and PG comparator. LDO_CUR 28 I Current sense input of LDO regulator. LDO_GATE 27 O Gate control output of external MOSFET for LDO regulator LDO_OUT 26 I/O LDO regulator's output connection. If output voltage has an overshoot when output current changes high to low quickly, it absorbs electrical charge from this pin. LDO_IN 29 I 6 Supply voltage input and current sense input of LDO regulator www.ti.com SLVS426 - MAY 2002 Terminal Functions (Continued) TERMINAL NAME NO. I/O DESCRIPTION LH1 46 I/O Bootstrap capacitor connection for SBRC-CH1 high-side gate driver. LH2 34 I/O Bootstrap capacitor connection for SBRC-CH2 high-side gate driver. LH3 20 I/O Bootstrap capacitor connection for SBRC-CH3 high-side gate driver. LL1 44 I/O SBRC-CH1 high-side gate driving return. Connect this pin to the junction of the high-side and low-side MOSFETs for floating drive configuration. This pin is also an input terminal for current comparator. LL2 36 I/O SBRC-CH2 high-side gate driving return. Connect this pin to the junction of the high-side and low-side MOSFETs for floating drive configuration. This pin is also an input terminal for current comparator. LL3 22 I/O SBRC-CH3 high-side gate driving return. Connect this pin to the junction of the high-side and low-side MOSFETs for floating drive configuration. This pin is also an input terminal for current comparator. OUT1_d 43 O Gate drive output for SBRC-CH1 low-side MOSFETs OUT2_d 37 O Gate drive output for SBRC-CH2 low-side MOSFETs OUT3_d 23 O Gate drive output for SBRC-CH3 low-side MOSFETs OUT1_u 45 O Gate drive output for SBRC-CH1 high-side MOSFETs. OUT2_u 35 O Gate drive output for SBRC-CH2 high-side MOSFETs. OUT3_u 21 O Gate drive output for SBRC-CH3 high-side MOSFETs. OUTGND1 42 O Ground for SBRC-CH1 MOSFETs drivers. It is connected to the current limiting comparator's negative input. OUTGND2 38 O Ground for SBRC-CH2 MOSFETs drivers. It is connected to the current limiting comparator's negative input. OUTGND3 24 O Ground for SBRC-CH3 MOSFETs drivers. It is connected to the current limiting comparator's negative input. PGOUT 16 O Powergood open drain output. PG comparators monitor all SBRC's and LDO's over voltage and under voltage. The threshold is 7%. When one of the output is beyond this condition, powergood output goes low. PG_DELAY 17 I/O Programmable delay for Powergood. Connect an external capacitor between this pin and GND to specify time delay. PWM_SEL 6 I PWM or auto PWM/SKIP mode select. H : auto PWM/SKIP L : PWM fixed REF 9 O 0.85-V reference voltage output. This 0.85-V reference voltage is used to set the output voltage and the reference for the over and undervoltage protections. This reference voltage is dropped down from the internal 5-V regulator. REG5V_IN 30 I External 5-V input SS_STBY1 2 I/O Soft start control and stand by control for SBRC-CH1. Connect an external capacitor between this pin and GND to specify soft start time. SS_STBY2 5 I/O Soft start control and stand by control for SBRC-CH2. Connect an external capacitor between this pin and GND to specify soft start time. SS_STBY3 13 I/O Soft start control and stand by control for SBRC-CH3. Connect an external capacitor between this pin and GND to specify soft start time. STBY_LDO 12 I Standby control input for LDO regulator. LDO regulator can be switched into standby mode by grounding the STBY_LDO pin. STBY_VREF3.3 11 I Standby control for 3.3-V linear regulator. STBY_VREF5 10 I Standby control for 5-V linear regulator. TRIP1 41 I External resistor connection for SBRC-CH1 output current protection control. TRIP2 39 I External resistor connection for SBRC-CH2 output current protection control. TRIP3 18 I External resistor connection for SBRC-CH3 output current protection control. VIN 33 I Supply voltage input VIN_SENSE12 40 I SBRC-CH1/2 supply voltage monitor for reference of current limit. Input range is 4.5 V to 28 V. VIN_SENSE3 19 I SBRC-CH 3 supply voltage monitor for reference of current limit. Input range is 4.5 V to 28 V. VREF3.3 32 O 3.3-V linear regulator output VREF5 31 O 5-V linear regulator output. 7 www.ti.com SLVS426 - MAY 2002 FUNCTIONAL BLOCK DIAGRAM PWM_SEL SBRC-CH1 SOFTSTART /STBY SS_STBY1 Duplicate for CH2 and CH3. SKIP Comp. - 0.85 V + FB1 LH1 ERROR Amp. INV1 - Oscillator CT OUT1_u PWM Comp. + + + - LL1 0.85 V OUT1_d OUTGND1 Phase Inverter Current Comp. 1 OVP Comp. - + + Current Protection Trigger 0.85 V + 12 % UVP Comp. + SS_STBY - -(VIN_SENSE-TRIP) - - VIN_SENSE12 + TRIP1 Current Comp. 2 0.85 V - 35 % LH2 SS_STBY2 SBRC-CH2 FB2 OUT2_u LL2 OUT2_d INV2 OUTGND2 TRIP2 SS_STBY3 FB 3 INV3 LH3 SBRC-CH3 + OUT3_u + LL3 + OUT3_d + OUTGND3 - VIN_SENSE3 TRIP3 - - TIMER - - 0.85 V + 7 % + 0.85 V - 7 % Fault Latch Timer PG_DELAY PGOUT FLT STBY_LDO INV_LDO UVLO VIN SS_STBY STBY_LDO STBY_LDO STBY_VREF5 VREF3.3 ERROR Amp. STBY_VREF3.3 VIN_SENSE - 3.3 V REG. 5V REG. VREF5 VREF 0.85 V 0.85 V + 0.85 V + 12 % Current Limit + REG5V_IN GND - + - LDO Overshoot Protection 0.85 V - 35 % LDO 8 LDO_IN LDO_CUR UVP Comp. 4.5 V REF LDO_GATE + OVP Comp. - LDO_OUT www.ti.com SLVS426 - MAY 2002 DETAILED DESCRIPTION PWM OPERATION The SBRC block has a high-speed error amplifier to regulate the output voltage of the synchronous buck converter. The output voltage of the SBRC is fed back to the inverting input (INVx (x=1,2,3)) of the error amplifier. The noninverting input is internally connected to a 0.85-V precise band gap reference circuit. The unity gain bandwidth of the amplifier is 2.5 MHz. This decreases the amplifier delay during fast load transients and contributes to a fast response. Loop gain and phase compensation is programmable by an external C, R network between the FBx and INVx pins. The output signal of the error amplifier is compared with a triangular wave to achieve the PWM control signal. The oscillation frequency of this triangular wave sets the switching frequency of the SBRC and is determined by the capacitor connected between the CT and GND pins. The PWM mode is used for the entire load range if the PWM_SEL pin is set LOW, or used in high output current condition if auto PWM/SKIP mode is selected by setting the same pin to HIGH. SKIP MODE OPERATION The PWM_SEL pin selects either the auto PWM/SKIP mode or fixed PWM mode. If this pin is lower than 0.3-V, the SBRC operates in the fixed PWM mode. If 2.5 V (min.) or higher is applied, it operates in auto PWM/SKIP mode. In the auto PWM/SKIP mode, the operation changes from constant frequency PWM mode to an energy-saving SKIP mode automatically in accordance with load conditions. Using a MOSFET with ultra-low rDS(on) when the auto SKIP function is implemented is not recommended. The SBRC block has a hysteretic comparator to regulate the output voltage of the synchronous buck converter during SKIP mode. The delay from the comparator input to the driver output is typically 1.2 s. In the SKIP mode, the frequency varies with load current and input voltage. HIGH-SIDE DRIVER The high-side driver is designed to drive high current and low rDS(on) N-channel MOSFET(s). The current rating of the driver is 1.2 A at source and sink. When configured as a floating driver, a 5-V bias voltage is delivered from VREF5 pin. The instantaneous drive current is supplied by the flying capacitor between the LHx and LLx pins since a 5-V power supply does not usually have low impedance. It is recommended to add a 5 to 10 resistor between the gate of the high-side MOSFET(s) and the OUTx_u pin to suppress noise. The maximum voltage that can be applied between the LHx and OUTGNDx pins is 33 V. When selecting the high current rating MOSFET(s), it is important to pay attention to both gate drive power dissipation and the rise/fall time against the dead-time between high-side and low-side drivers. The gate drive power is dissipated from the controller IC and it is proportional to the gate charge at VGS = 5 V, PWM switching frequency, and the numbers of all MOSFETs used for low-side and high-side switches. This gate drive loss should not exceed the maximum power dissipation of the device. LOW-SIDE DRIVER The low-side driver is designed to drive high current and low rDS(on) N-channel MOSFET(s). The maximum drive voltage is 5 V from the internal regulator or REG5V_IN pin. The current rating of the driver is typically 1.5 A at source and sink. Gate resistance is not necessary for the low-side MOSFET for switching noise suppression since it turns on after the parallel diode is turned on (ZVS). It needs the same dissipation consideration when using high current rating MOSFET(s). Another issue that needs precaution is the gate threshold voltage. Even though the OUTx_d pin is shorted to the OUTGNDx pin with low resistance when the low-side MOSFET(s) is OFF, high dv/dt of the LLx pin during turnon of the high-side arm will generate a voltage peak at the OUTx_d pin through the drain to gate capacitance, Cdg, of the low-side MOSFET(s). To prevent a short period shoot-through during this switching event, the application designer should select MOSFET(s) with adequate threshold voltage. 9 www.ti.com SLVS426 - MAY 2002 DEAD-TIME The internally defined dead-time prevents shoot-through-current flowing through the main power MOSFETs during switching transitions. Typical value of the dead-time is 100 ns. STANDBY The SBRC controller, the LDO controller, and the internal regulators can be switched into standby mode separately as shown in Table 1. The standby mode current, when both controllers and regulators are off, can be as low as 1 nA. Table 1. Standby Logic INPUT FUNCTION STBY_VREF5 SS_STBYx STBY_VREF3.3 STBY_LDO VREF5 VREF3.3 SBRCx LDO L (1) L V(REG5V_IN) > 4.5V False True(1) L (1) L L (1) L L (1) L OFF ON(1) OFF OFF(1) OFF OFF(1) OFF OFF(1) H L L L x ON OFF OFF OFF L H L L x OFF OFF OFF OFF H H L L x ON OFF ON OFF L L H L x ON ON OFF OFF H L H L x ON ON OFF OFF L H H L x ON ON OFF OFF H H H L x ON ON ON OFF L L L H x ON OFF OFF ON H L L H x ON OFF OFF ON L H L H x ON OFF OFF ON H H L H x ON OFF ON ON L L H H x ON ON OFF ON H L H H x ON ON OFF ON L H H H x ON ON OFF ON H H H (1) This functional mode is not recommended. x = true or false H x ON ON ON ON SOFT START Soft start ramp up of the SBRC is controlled by the SS_STBYx pin voltage, which is controlled by an internal current source and an external capacitor connected between the SS_STBYx and GND pins. When the STBY_VREF5 and/or SS_STBYx pin voltages are forced to LOW, the SBRCx is disabled. When the STBY_VREF5 pin voltage is set to HIGH and the SS_STBYx pin floats, the internal current source starts to charge the external capacitor. The output voltage ramps up as the SS_STBYx pin voltage increases from 0 V to 0.85 V. The soft start time is easily calculated from the supply current and the capacitance value (see application information). The soft start timing circuit for the LDO is integrated into the device. The soft start time is fixed and can be as short as 600 s. This is observed when the LDO is turned on separately from the SBRC. Simultaneous start-up of one of the SBRC and the LDO, is also possible. Tie the LDO input to the SBRCx's output, let both the STBY_VREF5 and STBY_LDO voltages rise to the HIGH level, and invoke Soft start on the SS_STBYx pin; then the LDO's output follows the ramp of the SBRCx's output. 10 www.ti.com SLVS426 - MAY 2002 OVER CURRENT PROTECTION Over current protection (OCP) is achieved by comparing the drain-to-source voltage of the high-side and low-side MOSFET to a set-point voltage, which is defined by both the internal current source, I(TRIP), and the external resistor connected between the VIN_SENSEx and the TRIPx pins. I(TRIP) has a typical value of 13 A at 25C. When the drain-to-source voltage exceeds the set-point voltage during low-side conduction, the high-side current comparator becomes active, and the low-side pulse is extended until this voltage comes back below the threshold. If the set-point voltage is exceeded during high-side conduction in the following cycle, the current limit circuit terminates the high-side driver pulse. Together this action has the effect of decreasing the output voltage until the under voltage protection circuit is activated to latch both the high-side and low-side drivers OFF. In the TPS5130, trip current I(TRIP) has a temperature coefficient of 3400 ppm/C in order to compensate for temperature drift of the MOSFET on-resistance. OCP FOR THE LDO To achieve the LDO current limit, a sense resistor must be placed in series with the N-channel MOSFET drain, connected between the LDO_IN and LDO_CUR pins (see reference schematic). If the voltage drop across this sense resistor exceeds 50 mV, the output voltage is reduced to approximately 22% of the nominal value, thus it activates the UVP to start the FLT latch timer. When the time is up, the LDO_GATE pin is pulled LOW to makes the LDO regulator shut down. Note that all of the SBRCs are latched OFF at the same time since the LDO and the SBRCs share the same FLT capacitor. OVER VOLTAGE PROTECTION For overvoltage protection (OVP), the TPS5130 monitors the INVx and INV_LDO pin voltages. When the INVx or INV_LDO pin voltage is higher than 0.95 V (0.85 V +12%), the OVP comparator output goes low and the FLT timer starts to charge an external capacitor connected to FLT pin. After a set time, the FLT circuit latches the high-side MOSFET driver, the low-side MOSFET drivers, and the LDO. The latched state of each block is summarized in Table 2. The timer source current for the OVP latch is 125 A(typ.), and the time-up voltage is 1.185 V (typ.). The OVP timer is designed to be 50 times faster than the under voltage protection timer described in Table 2. Table 2. OVP Logic OVP OCCURRED AT HIGH-SIDE MOSFET DRIVER LOW-SIDE MOSFET DRIVER LDO SBRC OFF ON OFF LDO OFF OFF OFF UNDER VOLTAGE PROTECTION For under voltage protection (UVP), the TPS5130 monitors the INVx and INV_LDO pin voltages. When the INVx or INV_LDO pin voltage is lower than 0.55 V (0.85 V - 35 %), the UVP comparator output goes low, and the FLT timer starts to charge the external capacitor connected to FLT pin. Also, when the current comparator triggers the OCP, the UVP comparator detects the under voltage output and starts the FLT capacitor charge, too. After a set time, the FLT circuit latches all of the MOSFET drivers to the OFF state. The timer latch source current for UVP is 2.3 A (typ.), and the time-up voltage is also 1.185 V (typ.). The UVP function of the LDO controller is disabled when voltage across the pass transistor is less than 0.23 V (typ.). FLT When an OVP or UVP comparator output goes low, the FLT circuit starts to charge the FLT capacitor. If the FLT pin voltage goes beyond a constant level, the TPS5130 latches the MOSFET drivers. At this time, the state of MOSFET is different depending on the OVP alert and the UVP alert (see Table 2). The enable time used to latch the MOSFET drivers is decided by the value of the FLT capacitor. The charging constant current value depends on whether it is an OVP alert or a UVP alert as shown in the following equation: FLT source current (OVP) = FLT source current (UVP) x 50 11 www.ti.com SLVS426 - MAY 2002 UNDER VOLTAGE LOCK OUT (UVLO) When the output voltage of the internal 5-V regulator or the REG5V_IN voltage decreases below about 4 V, the output stages of all the SBRCs and the LDO are turned off. This state is not latched, and the operation recovers immediately after the input voltage becomes higher than the turnon value again. The typical hysteresis voltage is 100 mV. UVLO FOR LDO The LDO_IN voltage is monitored with a hysteretic comparator. When this voltage is less than 1 V, the UVLO circuit disables the UVP/OVP comparators that monitor the INV_LDO voltage. In case the SBRC overcurrent protection is activated prior to that of the LDO's, this protection function may also be observed. LDO CONTROL The LDO controller can drive an external N-channel MOSFET. This realizes a fast response as well as an ultralow dropout voltage regulator. For example, it is easy to configure both a 1.8-V and a 1.5-V high current power supply for core and I/O of modern digital processors, one from the SBRC and the other from the LDO. The LDO_IN voltage range is from 1.1 V to 3.6 V, and the output voltage is adjustable from 0.9 V to 2.5 V by an external resistor divider. Gain and phase of the high-speed error amplifier for this LDO control is internally compensated and is connected to the 0.85-V band gap reference circuit. The gate driver buffer is supplied by VIN_SENSE voltage. In the relatively high output voltage applications, make sure that output voltage plus threshold voltage of the pass transistor is less than the minimum VIN. More precisely, VIN - 0.7 Vthn + V(LDO_OUT) where Vthn is the threshold voltage of the Nch MOSFET. The LDO controller is also equipped with OVP, UVP, overcurrent limit, and overshoot protection functions. OVERSHOOT PROTECTION In the event that load current changes from high to low very quickly, the LDO regulator output voltage may start to overshoot. In order to resist this phenomenon, the LDO controller has an overshoot protection function. If the LDO regulator output overshoots, the controller draws electrical charge out from the LDO_OUT pin to hold it stable. POWERGOOD A single powergood circuit monitors the SBRCx output voltages and the LDO output voltage. The powergood pin is an open drain output. When the INV or INV_LDO voltage goes beyond 7% of 0.85 V, the powergood pin is pulled down to the LOW level. Powergood propagation delay is programmable by controlling rising time using an external capacitor connected to the PG_DELAY pin. During the soft start period, powergood indicates LOW, in other words power bad. Table 3. Powergood Logic 12 SS_STBY1 SS_STBY2 SS_STBY3 STBY_LDO POWERGOOD L L L L L H L L L H L H L L H H H L L H L L H L H H L H L H L H H L H H H H L H H or L H or L H or L H H www.ti.com SLVS426 - MAY 2002 5-V REGULATOR An internal linear voltage regulator is used for the high-side driver bootstrap. Since the input voltage ranges from 4.5 V to 28 V, this feature offers a fixed bootstrap voltage to simplify the drive design. It is active if the STBY_VREF5 is HIGH and has a tolerance of 4%. The 5-V regulator is used for powering the low-side driver and the VREF. When this regulator is disconnected from the MOSFET drivers, it is used only for the source of VREF. 3.3-V REGULATOR The TPS5130 has a 3.3-V linear regulator. The output is made from the internal 5-V regulator or an external 5 V from the REG5V_IN pin. The maximum output current of this regulator is limited to 30 mA by an output current limit control. A ceramic capacitor of 4.7 F should be connected between the VREF3.3 and GND pins to stabilize the output voltage. EXTERNAL 5-V INPUT AND 5-V SWITCH If the internal 5-V switch detects 5-V input from the REG5V_IN pin, the internal 5-V regulator is disconnected from the MOSFET drivers. The external 5 V is used for both the high-side bootstrap and the low-side driver, thus increasing the efficiency. When an excess voltage is applied to the REG5V_IN pin, the OVP timer starts to charge the FLT capacitor and latches all the MOSFET drivers and the LDO at OFF state after a set time. PHASE INVERTER The SBRC3 of the TPS5130 operates in the same phase as the internal triangular oscillator output while the SBRC1 and the SBRC2 operate 180 degrees out of phase. When the SBRC1 and the SBRC3 (or the SBRC2 and the SBRC3) share the same input power supply, the TPS5130 realizes 180 degrees out of phase operation that reduces input current ripple and enables the input capacitor value smaller. 13 www.ti.com SLVS426 - MAY 2002 TYPICAL CHARACTERISTICS SUPPLY CURRENT vs JUNCTION TEMPERATURE SUPPLY CURRENT (SHUTDOWN) vs JUNCTION TEMPERATURE 3 250 I CC - Supply Current (Shutdown) - nA I CC - Supply Current - mA V(LDO_IN) = V(LDO_CUR) = 3.6 V, V(PWM_ESL) = V(FLT) = V(CT) = 0 V 2.5 2 1.5 1 V(LDO_IN) = V(LDO_CUR) = 3.6 V, V(INX) = V(INV_LDO) = 0 V V(SS_STBYx) = 0 V V(STBY_VREF 3.3/5) = 0 V V(PWM_SEL) = 0 V 200 150 100 50 0 -50 0 50 100 150 -50 0 50 SOURCE CURRENT FLT(OVP) vs JUNCTION TEMPERATURE SOURCE CURRENT FLT(UVP) vs JUNCTION TEMPERATURE -3 I S - Source Current - FLT(UVP) - A I S - Source Current - FLT(OVP) - A -160 -140 -120 -100 -80 -60 -40 V(LDO_IN) = V(LDO_CUR) = 3.3 V, V(INV_LDO) = 1 V -2.5 -2 -1.5 -1 -0.5 0 0 -50 0 50 100 TJ - Junction Temperature - C 150 V(LDO_IN) = V(LDO_CUR) = 3.3 V, V(INV_LDO) = 5 V -50 0 150 SINK CURRENT (LDO_GATE) vs OUTPUT VOLTAGE 3 25 V(INV_LDO) = 2 V V(LDO_IN) = V(LDO_CUR) = 3.3 V Sink Current (LDO_GATE) - mA V(Trip) = V(VIN_SENSE) - 0.1 V 20 Trip Current - A 100 Figure 4 TRIP CURRENT vs JUNCTION TEMPERATURE 15 10 5 2.5 2 1.5 1 0.5 0 0 50 100 TJ - Junction Temperature - C Figure 5 V(VIN_SENSE) = 12 V, unless otherwise noted 14 50 TJ - Junction Temperature - C Figure 3 0 -50 150 Figure 2 Figure 1 -20 100 TJ - Junction Temperature - C TJ - Junction Temperature - C 150 0 2 4 6 VO - Output Voltage - V Figure 6 8 10 www.ti.com SLVS426 - MAY 2002 TYPICAL CHARACTERISTICS SOURCE CURRENT (LDO_GATE) vs OUTPUT VOLTAGE 955 V(INV_LDO) = 0 V V(LDO_IN) = V(LDO_CUR) = 3.3 V Threshold Voltage (OVP) - mV Source Current (LDO_GATE) - mA -2 THRESHOLD VOLTAGE (OVP) vs JUNCTION TEMPERATURE -1.5 -1 -0.5 950 945 940 935 0 0 2 4 6 8 -50 10 0 VO - Output Voltage - V OSCILLATOR FREQUENCY vs CAPACITANCE 150 OUTPUT MAXIMUM DUTY CYCLE vs JUNCTION TEMPERATURE 1000 100 Output Maximum Duty Cycle - % TJ = 25C Oscillator Frequency - kHz 100 Figure 8 Figure 7 100 95 0 50 100 150 200 250 300 CH2 90 85 CH1/3 80 V(LH) = 5 V, C(CT) = 45 pF, V(PWM_SEL) = V(FLT) = V(LL) = V(INV) =0V 75 10 70 350 -50 C - Capacitance - pF 0 50 100 TJ - Junction Temperature - C 150 Figure 10 Figure 9 DELAY TIME FLT(OVP) vs CAPACITANCE DELAY TIME FLT(UVP) vs CAPACITANCE 100000 100000 VINV = 0.85 to 1.05 V, TJ = 25C 10000 t d - Delay Time FLT (UVP) - s t d - Delay Time FLT (OVP) - s 50 TJ - Junction Temperature - C 10000 1000 100 10 1 0.1 10 100 VINV = 0.65 to 0.05 V, TJ = 25C 1000 10000 1000 100 10 1 0.1 10 100 1000 C - Capacitance - pF C - Capacitance - pF Figure 11 Figure 12 10000 VVIN_SENSE = 12 V, unless otherwise noted 15 www.ti.com SLVS426 - MAY 2002 TYPICAL CHARACTERISTICS CURRENT LIMIT THRESHOLD VOLTAGE FOR LDO vs JUNCTION TEMPERATURE 100000 TJ = 25C Soft Start Time - s 10000 1000 100 10 1 1 10 100 1000 10000 C - Capacitance - pF 100000 Current Limit Threshold Voltage For LDO - mV SOFT START TIME vs CAPACITANCE 60 50 40 30 20 V(LDO_IN) = 3.3 V V(INV_LDO) = 0.5 V 10 0 -50 Figure 13 50 100 150 Figure 14 LDO UVLO THRESHOLD VOLTAGE vs JUNCTION TEMPERATURE POWERGOOD DELAY TIME vs CAPACITANCE 10000 1.2 VTLH Powergood Delay Time - s LDO UVLO Threshold Voltage - V 0 TJ - Junction Temperature - C 1 VTHL 0.8 0.6 0.4 VIN = 12 V, TJ = 25C V(INV_LDO) = 1 V 0.85 V 1000 100 10 0.2 V(INV_LDO) = 1.2 V 1 0 -50 0 50 100 TJ - Junction Temperature - C Figure 15 VVIN_SENSE = 12 V, unless otherwise noted 16 150 1 10 100 1000 C - Capacitance - pF Figure 16 10000 www.ti.com SLVS426 - MAY 2002 APPLICATION INFORMATION The design shown is a reference design for a notebook PC application. An evaluation module (EVM) is available for customer testing and evaluation. The following key design procedures aid in the design of the notebook PC power supply using TPS5130. Q01A R25 5-8 4 C35 Q01B 5-8 4 1-3 1-3 L01 C41 VO1-1 Q02A 5-8 4 1-3 4 1-3 D01 Q02B 5-8 4 1-3 4 1-3 C37 D02 C38 C39 D07 C40 VO1-2 R09 R23 C43 R49 R03A C03 R01A C02 R03B R04 R01B R02 R24 C44 2SC4617 R46 1 Q08 R26 D03 JP01 JP11 3 R28 C42 2 R27 Q11 Q09 47 46 45 44 43 42 41 40 39 38 37 LL1 OUT1_d OUTGND1 TRIP1 VIN_SENSE12 TRIP2 OUTGND2 OUT2_d 48 OUT1_u JP02 VO2-1 R29 C28 STBY_VREF5 3 2 LDO_OUT 4 26 1-3 3 Q07B OUTGND3 JP10 R21C C13 GND-1 GND-2 LDO_OUT-1 R18 C23 C22 C24 LDO_OUT-2 R19 Q10 R32 D05 4 R33 C14 1-3 5-8 Q06A 4 C17 C18 1-3 C19 D09 C20 5-8 Q06B L03 VO3-1 4 C21 R17 R15 VIN1-2 LDO_IN R21B 1 Q07A 25 R16 PWR_GD C01A C01B 2 5-8 R20 27 24 OUT3_d R21A C45 28 R14B C12 29 R34 R13 C11 R11 Q13 VREF5 VIN1-1 2SC4617 C10 JP07 INV_LDO 23 STBY_LDO LL3 STBY_VREF3.3 12 JP13 C36 LDO_GATE 11 13 1 C27 LDO_VIN 22 3 2 R48 1 VREF3.3 32 LDO_CUR OUT3_u JP06 3 35 C26 REF SS_STBY3 1 2 5-8 36 LH2 34 33 GND 21 3 2 VO2-2 JP08 REG5V_IN LH3 JP05 C29 VREF5 31 30 TPS5130PT CT 20 1 9 10 Q03B 1-3 D04 VREF3.3 PWM_SEL VIN_SENSE3 C09 3 SS_STBY2 19 8 JP04 2 4 VIN TRIP3 1 7 FB2 18 6 C08 5-8 Q03A OUT2_u INV2 PG_DELAY 5 3 2 SS_STBY1 17 C07 JP03 4 R14 1 R08 1-3 4 R30 R22 PGOUT 3 C06 INV3 R07 R31 LL2 16 2 FB1 FB3 C05 1 14 Q12 R06 R12 15 C04 C30 C33 D08 C34 L02 VIN_SLIT 2 FLT INV1 JP12 3 LH1 U01 1 C31 C32 5-8 Q04B 2SC4617 R05 C16 R47 5-8 Q04A 1-3 4 5-8 Q05A 1-3 C15 VO3-2 5-8 Q05B D06 Figure 17. EVM Schematic An optional circuit composed of Q08, Q09, Q10, R26, R27, R28, R29, R30, R31, R32, R33, and R34 can be used to increase temperature coefficient of the trip current. OUTPUT VOLTAGE SETPOINT CALCULATION In the following calculation, assume the output voltage of SBRC1 (VO1), SBRC2 (VO2), SBRC3 (VO3), and LDO (VO4) are 3.3 V, 5 V, 1.8 V, and 1.5 V respectively. The reference voltage and the voltage divider set the output voltage. In the TPS5130, the reference voltage is 0.85 V, and the divider is composed of three resistors in the EVM design that are R01A, R01B, and R05 for the first SBRC output; R03A, R03B, and R07 for the second SBRC output ; R14A, R14B, and R11 for the third SBRC output ; R18 and R19 for LDO regulator output. VO + R1 V ref R2 ) V ref or R2 + R1 Vref V O * V ref where R1 is the top resistor (k) (R01A + R01B or R03A + R03B or R14A + R14B or R18); R2 is the bottom resistor (k) (R05 or R07 or R11 or R19); VO is the required output voltage (V); Vref is the reference voltage (0.85 V in TPS5130). The value for R1 is set as a part of the compensation circuit and the value of R2 may be 17 www.ti.com SLVS426 - MAY 2002 calculated to achieve the desired output voltage. In the EVM design, the value of R1 is determined as R01A = 27 k and R01B = 1.8 k for VO1, R03A = 47 k and R03B = 1.8 k for VO2, R14A = 10 k and R14B = 1.2 k for VO3, and R18 = 6.8 k + 820 for VO4 considering stability. For VO1: R05 + (27 k ) 1.8 k) 0.85 + 9.99 kW 3.3 * 0.85 Therefore, use 10 k. In a same manner, R07 = R11 = R19 = 10 k as follows. R07 + (47 k ) 1.8 k) 0.85 + 10.00 kW 5 * 0.85 R11 + (10 k ) 1.2 k) 0.85 + 10.02 kW 1.8 * 0.85 R19 + (6.8 k ) 820) 0.85 + 9.96 kW 1.5 * 0.85 The values of R01B, R03B, R14B and R19 are chosen so that the calculated values of R05, R07, R11, and R19 are standard value resistors and the VO setpoint maintains the highest precision. This is best accomplished by combining two resistor values. If a standard value resistor can not be applied, use a value for R01A, R03A, R14A, and R18 that is just slightly less than the desired total. A small resistor value in the range of tens or hundreds of ohms for R01B, R03B, R14B and R18 can then be added to generate the desired final value. OUTPUT INDUCTOR SELECTION The required value for the output filter inductor can be calculated by using the equation below, assuming the magnitude of the ripple current is 20 % of the maximum output current: L (out) + VIN * V O 0.2 I O VO VIN 1 fS Where L(out) is output filter inductor value (H), VIN is the input voltage (V), IO is the maximum output current (A), fs is the switching frequency (Hz). Example : VIN = 8 V; VO = 3.3 V; IO = 4 A; fs = 300 kHz. Then, L(out) = 8.1 H. If faster output response is required for a sudden transition of the load, smaller inductance value is recommended. OUTPUT INDUCTOR RIPPLE CURRENT The output inductor current can affect not only the efficiency, but also the output voltage ripple. The equation is exhibited below: I (ripple) + VIN * V O * I O r DS(on) ) RL L (out) VO VIN 1 fS where I(ripple) is the peak-to-peak ripple current (A) through the inductor; Io is the output current; rDS(on) is the on-time resistance of MOSFET (); RL is the inductor dc resistance (). From the equation, it can be seen that the current ripple can be adjusted by changing the output inductor value. Example: VIN = 8 V; VO = 3.3 V; IO = 4 A; rDS(on) = 25 m; RL = 10 m; fs = 300 kHz; L(out) = 4 H. Then, the ripple current I(ripple) = 1.57 A 18 www.ti.com SLVS426 - MAY 2002 OUTPUT CAPACITOR SELECTION Selection of the output capacitor is basically dependent on the amount of peak-to-peak ripple voltage allowed on the output and the ability of the capacitor to dissipate the RMS ripple current. Assuming that the ESR of the output filter sees the entire inductor ripple current then: V pp + I (ripple) R(esr) And a suitable capacitor must be chosen so that the peak-to-peak output ripple is within the limits allowable for the application. OUTPUT CAPACITOR RMS CURRENT Assuming the inductor ripple current totally goes through the output capacitor to ground, the RMS current in the output capacitor can be calculated as: I O(rms) + I (ripple) 12 where IO(rms) is maximum RMS current in the output capacitor (A); I(ripple) is the peak-to-peak inductor ripple current (A). Example: I(ripple) = 1.57 A, then, IO(rms) = 0.45 A INPUT CAPACITOR RMS CURRENT Since the SBRC3 of the TPS5130 operates 180 degree off phase against the SBRC1 and SBRC2, total RMS current in the input capacitor is calculated as follows, assuming the input current totally goes into the input capacitor to the power ground, and ignoring ripple current in the inductor. When the duty cycle of the SBRC2 (D2) is over 50 %, I I(rms) + (D1 I O12) ) (D2 I Ox + (D1 I O2 2) ) (D3 I O1) ) (D2 I O2) ) (D3 I O3 2) ) (2D1 I O2) ) (2D2 * 1) I O1 I O2 I O3 * I Ox 2 D2 w 0.5 w D1 w D3 I O3) II(rms) is the input RMS current in the input capacitor; DX is duty cycles, defined as VO/VI in this case, of the SBRCx. When D2 is less than 50%, I I(rms) + (D1 I O1 2) ) (D2 I O22) ) (D3 I O32) ) (2D1 I O1 I O2) * I Ox 2 Example: VIN = 12 V, VO1 = 3.3 V, VO2 = 5 V (D2 = 0.42), VO3 = 1.8V, IO1 = IO2 = 4 A, IO3 = 6 A Then, II(rms) = 3.44 A On the contrary, if three SBRCs operate in a same phase the RMS current is calculated as follows. I I(rms) + (D1 I O12) ) (D2 I O2 2) ) (D3 I O3 2) ) (2D1 I O1 I O2) ) (2D3 I O3) IO1 ) IO2 * I Ox2 Under the same operation condition, II(rms) = 5.13 A Therefore, 180 degree out of phase operation is effective in reducing input RMS current, and it allows a smaller input capacitance value. The input capacitors must be chosen so that together they can safely handle the input ripple current. Depending on the input filtering and the dc input voltage source, not all the ripple current flows through the input capacitors, but some may be present on the input leads to the EVM. 19 www.ti.com SLVS426 - MAY 2002 SOFT START The soft start timing can be adjusted by selecting the soft-start capacitor value. The equation is; C(soft) + 2.3 10-6 T(soft) 0.85 where C(soft) is the soft-start capacitor (F) (C05, C07 and C10 in EVM design): T(soft) is the start-up time (s). Example: T(soft) = 5 ms, therefore, C(soft) = 0.0135 F. CURRENT PROTECTION The current limit in TPS5130 is set using an internal current source and an external resistor (R17, R23 and R24). The current limit protection circuit compares the drain to source voltage of the high-side and low-side MOSFET(s) with respect to the set-point voltage. If the voltage up exceeds the limit during high-side conduction, the current limit circuit terminates the high-side driver pulse. If the set point voltage is exceeded during low-side conduction, the low side pulse is extended through the next cycle. Together this action has the effect of decreasing the output voltage until the under voltage protection circuit is activated and the fault latch is set and both the high-side and low-side MOSFET drivers are shut off. The equation below should be used for calculating the external resistor value for current protection set point: r DS(on) R(cl) + I (trip) ) 13 I (ripple) 2 10 -6 where R(cl) is the external current limit resistor (R17, R23 and R24); rDS(on) is the low-side MOSFET(Q02, Q04 and Q06) on-time resistance. I(trip) is the required current limit. Example: rDS(on) = 25 m, I(trip) = 4 A, I(ripple) = 1.57 A, therefore, R(cl)= 9.2 k. It should be noted that rDS(on) of a FET is highly dependent on temperature, so to insure full output at maximum operating temperature, the value of rDS(on) in the above equation should be adjusted. For maximum stability, it is recommended that the high-side MOSFET(s) has the same, or slightly higher rDS(on)than the low-side MOSFET(s). If the low-side MOSFET(s) has a higher rDS(on), in certain low duty cycle applications it may be possible for the device to regulate at an output current higher than that set by the above equation by increasing the high-side conduction time to compensate for the missed conduction cycle caused by the extension of the previous low-side pulse. TIMER-LATCH The TPS5130 includes fault latch function with a user adjustable timer to latch the MOSFET drivers in case of a fault condition. When either the OVP or UVP comparator detect a fault condition, the timer starts to charge FLT capacitor (C42), which is connected with FLT pin. The circuit is designed so that for any value of FLT capacitor, the undervoltage latch time t(uvplatch) is about 50 times larger than the overvoltage latch time t(ovplatch). The equations needed to calculate the required value of the FLT capacitor for the desired over and undervoltage latch delay times are: C (lat) + 2.3 10 *6 C (lat) + 125 10 *6 t (uvplatch) 1.185 and t (ovplatch) 1.185 where C(lat) is the external capacitor, t(uvplatch) is the time from UVP detection to latch. t(ovplatch) is the time from OVP detection to latch. For the EVM, t(uvplatch) = 5 ms and t(ovplatch) = 0.1 ms, so C(lat) = 0.01 F. If the voltage on the FLT pin reaches 1.185 V, the fault latch is set, and the MOSFET drivers are set as follows: 20 www.ti.com SLVS426 - MAY 2002 Undervoltage Protection The undervoltage comparator circuit continually monitors the voltage at the INV and INV_LDO pins. If the voltage at either pin falls below 65 % of the 0.85 V reference, the timer begins to charge the FLT capacitor. if the fault condition persists beyond the time t(uvplatch), the fault latch is set and both the high-side and low-side drivers, and LDO regulator drivers are forced OFF. Short-Circuit Protection The short-circuit protection circuitry uses the UVP circuit to latch the MOSFET drivers. When the current limit circuit limits the output current, then the output voltage goes below the target output voltage and UVP comparator detects a fault condition as described above. Overvoltage Protection The overvoltage comparator circuit continually monitors the voltage at the INV and INV_LDO pins. If the voltage at either pin rises above 112 % of the 0.85 V reference, the timer begins to charge the FLT capacitor. If the fault condition persists beyond the time t(ovplatch), the fault latch is set and the high-side drivers are forced OFF, while the low-side drivers are forced ON, and LDO regulator drivers are forced OFF. CAUTION: Do not set the FLT terminal to a lower voltage (or GND) while the device is timing out an OVP or UVP event. If the FLT terminal is manually set to a lower voltage during this time, output overshoot may occur. The TPS5130 must be reset by grounding SS_STBYx and STBY_LDO, or dropping down REG5V_IN. Disablement of the Protection Function If it is necessary to inhibit the protection functions of the TPS5130 for troubleshooting or other purposes, the OCP,OVP, and UVP circuits may be disabled. D OCP(SBRC): Remove the current limit resistors R17, R23 and R24 to disable the current limit function. D OCP(LDO): Short-circuit R21 to disable the current limit function. D OVP, UVP: Grounding the FLT terminal can disable OVP and UVP. LDO REGULATOR APPLICATION INFORMATION Output Capacitor Selection To keep stable operation of the LDO, capacitance of more than 33 F and R(esr) of more than 30 m are recommended for the output capacitor. Power MOSFET Selection Also, to keep stable operation of LDO, lower input capacitance is recommended for the external power MOSFET. However, input capacitance that is too small may lead the feedback loop into an unstable region. In this case, the gate resistor of several hundreds ohms keeps the LDO operation in the stable state. Current Protection If excess output current flows through sense resistor (R21) and the voltage drop exceeds 50 mV, the output voltage is reduced to approximately 22% of the nominal value, thus activates UVP to start the FLT latch timer. When the set current is 3 A, the value of R21 is 16.7 m. 21 www.ti.com SLVS426 - MAY 2002 Layout Guidelines Good power supply results only occur when care is given to proper design and layout. Layout affects noise pickup and generation and can cause a good design to perform with less than expected results. With a range of currents from milliamps to tens amps, good power supply layout is much more difficult than most general PCB designs. The general design should proceed from the switching node to the output, then back to the driver section and, finally, parallel the low-level components. Below are specific points to consider before the layout of a TPS5130 design begins. D A four-layer PCB design is recommended for design using the TPS5130. For the EVM design, the top layer contains the interconnection to the TPS5130, plus some additional signal traces. Layer2 is fully devoted to the ground plane. Layer3 has some signal traces. The bottom layer is almost devoted to ANAGND, and the rest is to other signal trace. D All sensitive analog components such as INV, REF, CT, GND, FLT, and SS_STBY should be referenced to ANAGND. D Ideally, all of the area directly under the TPS5130 chip should also be ANAGND. D ANAGND and DRVGND should be isolated as much as possible, with a single point connection between them. CTRIP TRIP VIN VIN_SENSE VREF5 CBS LH CBP CIN OUT_u INV Vox LL FB COUT SOFT_START ANAGND CT GND REF OUT_d OUTGND DRVGND VoxGND LDO_IN LDO_CUR FLT LDO_GATE INV_LDO LDO_OUT Vo_LDO Figure 18. PCB Diagram Low-Side MOSFET(s) D The source of low-side MOSFET(s) should be referenced to DRVGND, otherwise ANAGND is subject to the noise of the outputs. D DRVGND should be connected to the main ground plane close to the source of the low-side MOSFET. D OUTGND should be placed close to the source of low side MOSFET(s). D The Schottky diode anode, the returns for the high frequency bypass capacitor for the MOSFETs, and the source of the low-side MOSFET(s) traces should be routed as close together as possible. 22 www.ti.com SLVS426 - MAY 2002 Connections D Connections from the drivers to the gate of the power MOSFETs should be as short and wide as possible to reduce stray inductance. This becomes more critical if external gate resistors are not being used. In addition, as for the current limit noise issue, use of a gate resistor on the high-side MOSFET(s) considerably reduces the noise at the LL node, improving the performance of the current limit function. D The connection from LL to the power MOSFETs should be as short and wide as possible. Bypass Capacitor D The bypass capacitor for VIN_SENSE should be placed close to the TPS5130. D The bulk storage capacitors across VIN should be placed close to the power MOSFETs. High-frequency bypass capacitors should be placed in parallel with the bulk capacitors and connected close to the drain of the high-side MOSFET(s) and to the source of the low-side MOSFET(s). D For aligning phase between the drain of high-side MOSFET(s) and the trip-pin, and for noise reduction, a 0.1 F capacitor C(TRIP) should be placed in parallel with the trip resistor. Bootstrap Capacitor D The bootstrap capacitor C(BS) (connected from LH to LL) should be placed close to the TPS5130. D LH and LL should be routed close to each other to minimize noise coupling to these traces. D LH and LL should not be routed near the control pin area (ex. INV, FB, REF, etc.). Output Voltage D The output voltage sensing trace should be isolated by either ground plane. D The output voltage sensing trace should not be placed under the inductors on same layer. D The feedback components should be isolated from output components, such as, MOSFETs, inductors, and output capacitors. Otherwise the feedback signal line is susceptible to output noise. D The resistors for setup output voltage should be referenced to ANAGND. D The INV trace should be as short as possible. VIN = 8 V VIN = 8 V 80 VIN = 12 V 60 VIN = 20 V 40 SBRC CH1 External 5 V VO1 = 3.3 V 20 0.1 1 IO - Output Current - A Figure 19 10 VIN = 8 V Efficiency (PWM MODE) - % Efficiency (PWM MODE) - % Efficiency (PWM MODE) - % 100 100 100 0 0.01 EFFICIENCY (PWM MODE) vs OUTPUT CURRENT EFFICIENCY (PWM MODE) vs OUTPUT CURRENT EFFICIENCY (PWM MODE) vs OUTPUT CURRENT 80 VIN = 12 V 60 VIN = 20 V 40 SBRC CH2 External 5 V VO2 = 5 V 20 0 0.01 0.1 1 IO - Output Current - A Figure 20 10 80 VIN = 12 V 60 VIN = 20 V 40 SBRC CH3 External 5 V VO3 = 1.8 V 20 0 0.01 0.1 1 10 IO - Output Current - A Figure 21 23 www.ti.com SLVS426 - MAY 2002 EFFICIENCY (AUTO SKIP MODE) vs OUTPUT CURRENT EFFICIENCY (AUTO SKIP MODE) vs OUTPUT CURRENT Efficiency (AUTO SKIP MODE) - % Efficiency (AUTO SKIP MODE) - % 80 VIN = 8 V VIN = 12 V VIN = 20 V 60 40 SBRC CH1 External 5 V VO1 = 3.3 V 20 0 0.01 0.1 1 IO - Output Current - A 100 VIN = 8 V VIN = 12 V VIN = 20 V 80 60 40 SBRC CH2 External 5 V VO2 = 5 V 20 0 0.01 10 0.1 1 IO - Output Current - A Figure 22 VIN = 20 V 40 SBRC CH3 External 5 V VO3 = 1.8 V 20 IO = 6 A 1.764 3.264 3.262 VO - Output Voltage - V VO - Output Voltage - V 3.266 5 4.998 4.996 5 10 15 VI - Input Voltage - V Figure 25 LDO OUTPUT LINE REGULATION 1.758 20 5.030 PWM Mode VIN = 12 V VO - Output Voltage - V 1.462 1.456 3.280 3.275 3.270 3.260 20 5.020 5.015 5.010 5.005 3.265 1.454 PWM Mode VIN = 12 V 5.025 VO - Output Voltage - V 3.285 1.458 20 Figure 27 3.290 1.460 10 15 VI - Input Voltage - V SBRC CH1 OUTPUT LOAD REGULATION SBRC CH2 OUTPUT LOAD REGULATION V(LDO_IN = VO3 IO = 3 A Figure 28 1.760 Figure 26 1.464 10 15 VI - Input Voltage - V 1.762 1.756 5 4.994 20 10 SBRC CH3 OUTPUT LINE REGULATION 5.002 3.268 10 15 VI - Input Voltage - V 0.1 1 IO - Output Current - A 1.766 IO = 4 A IO = 4 A VO - Output Voltage - V 60 Figure 24 5.004 5 VIN = 8 V VIN = 12 V 0 0.01 10 SBRC CH2 OUTPUT LINE REGULATION SBRC CH1 OUTPUT LINE REGULATION 3.260 5 80 Figure 23 3.270 VO - Output Voltage - V Efficiency (AUTO SKIP MODE) - % 100 100 24 EFFICIENCY (AUTO SKIP MODE) vs OUTPUT CURRENT 5 0 1 2 3 IO- Output Current - A Figure 29 4 0 1 2 3 IO- Output Current - A Figure 30 4 www.ti.com SLVS426 - MAY 2002 SBRC CH3 OUTPUT LOAD REGULATION LDO OUTPUT LOAD REGULATION 1.790 1.480 PWM Mode VIN = 12 V V(LDO_IN)= VO3 1.475 VO - Output Voltage - V VO - Output Voltage - V 1.785 1.780 1.775 1.770 1.765 1.760 0 1.470 1.465 1.460 1.455 1.450 1 2 3 4 IO- Output Current - A 5 0 6 Figure 31 SBRC CH1 OUTPUT VOLTAGE RIPPLE 50 mV/div 2 3 Figure 32 SBRC CH2 OUTPUT VOLTAGE RIPPLE SBRC CH3 OUTPUT VOLTAGE RIPPLE 20 mV/div 50 mV/div VIN = 12 V, VO1 = 3.3 V 1 IO- Output Current - A IO1 = 0 A IO2 = 0 A IO2 = 0 A 2A 2A 4A 4A 4A 6A VIN = 12 V, VO2 = 5 V 1 s/div Figure 33 LDO OUTPUT VOLTAGE RIPPLE 1 s/div VIN = 12 V, VO3 = 1.8 V 1 s/div Figure 34 Figure 35 SBRC CH1 LOAD TRANSIENT RESPONSE SBRC CH2 LOAD TRANSIENT RESPONSE 10 mV/div VO2 20 mV/div VO1 20 mV/div IO= 0.3 A 1A 4A 4A 3A VIN = 12 V, V(LDO_IN) = VO3 = 1.8 V, IO3 = 0 A 1 s/div Figure 36 IO1 2 A/div 0A VIN = 12 V, VO1 = 3.3 V 100 s/div Figure 37 IO2 2 A/div 0A VIN = 12 V, VO2 = 5 V 100 s/div Figure 38 25 www.ti.com SLVS426 - MAY 2002 LDO LOAD TRANSIENT RESPONSE SBRC CH3 LOAD TRANSIENT RESPONSE VIN = 12 V, V(LDO_IN) = VO3 = 1.8 V, V(LDO) = 1.5 V VO 50 mV/div VO3 20 mV/div 3A 6A IO3 2 A/div 0A IO 1 A/div 30 mA 100 s/div 100 s/div Figure 39 Figure 40 SBRC CH1 GAIN AND PHASE 80 SBRC CH2 GAIN AND PHASE 80 240 120 Phase 60 20 0 0 -20 -40 100 1K 120 40 Phase 60 20 0 0 Gain 10K 100K f - Frequency - Hz 180 -60 -20 -120 -40 100 1M -120 1K 40 120 Phase 60 20 0 0 26 60 Gain 1M 180 120 40 Gain - dB 180 Phase - Degrees Gain - dB Phase Margin = 37 Degrees Figure 43 240 Phase Margin = 74 Degrees 60 10K 100K f - Frequency - Hz 1M 80 240 1K 10K 100K f - Frequency - Hz LDO GAIN AND PHASE SBRC CH3 GAIN AND PHASE -40 100 -60 Figure 42 80 -20 Gain VIN = 12 V, VO2 = 5 V, IO2 = 4 A Figure 41 VIN = 12 V, VO3 = 1.8 V, IO3 = 6 A Phase - Degrees 40 60 Gain - dB 180 Phase - Degrees Gain - dB Phase Margin = 53 Degrees 60 VIN = 12 V, VO1 = 3.3 V, IO1 = 4 A 240 Phase Margin = 59 Degrees Phase 60 20 Gain 0 0 -60 -20 -120 -40 100 VIN = 12 V, V(LDO_IN) = VO3 =1.8 V, I(LDO) = 3 A 1K 10K 100K f - Frequency - Hz Figure 44 Phase - Degrees VIN = 12 V, VO3 = 1.8 V -60 -120 1M www.ti.com SLVS426 - MAY 2002 MECHANICAL DATA PT (S-PQFP-G48) PLASTIC QUAD FLATPACK 0,27 0,17 0,50 36 0,08 M 25 37 24 48 13 0,13 NOM 1 12 5,50 TYP 7,20 SQ 6,80 9,20 SQ 8,80 Gage Plane 0,25 1,45 1,35 0,05 MIN Seating Plane 1,60 MAX 0- 7 0,75 0,45 0,10 4040052/ C 11/96 NOTES:A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Falls within JEDEC MS-026 This may also be a thermally enhanced plastic package with leads conected to the die pads. 27 PACKAGE OPTION ADDENDUM www.ti.com 18-Sep-2008 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty TPS5130PT ACTIVE LQFP PT 48 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS5130PTG4 ACTIVE LQFP PT 48 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS5130PTR ACTIVE LQFP PT 48 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS5130PTRG4 ACTIVE LQFP PT 48 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. 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Addendum-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 11-Mar-2008 TAPE AND REEL INFORMATION *All dimensions are nominal Device TPS5130PTR Package Package Pins Type Drawing LQFP PT 48 SPQ Reel Reel Diameter Width (mm) W1 (mm) 1000 330.0 16.4 Pack Materials-Page 1 A0 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 9.6 9.6 1.9 12.0 16.0 Q2 PACKAGE MATERIALS INFORMATION www.ti.com 11-Mar-2008 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS5130PTR LQFP PT 48 1000 346.0 346.0 33.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. 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