SLVS426 − MAY 2002
FEATURES
DThree Independent Step-Down DC/DC
Controllers and One LDO Controller
DInput Voltage Range
− Switcher: 4.5 V ~ 28 V
− LDO: 1.1 V ~ 3.6 V
DOutput Voltage Range
− Switcher: 0.9 V ~ 5.5 V
− LDO: 0.9 V ~ 2.5 V
DSynchronous for High Efficiency
DPrecision Vref (±1.5%)
DPWM Mode Control : Max. 500 kHz Operation
DAuto PWM/SKIP Mode Available
DHigh Speed Error Amplifier
DOver Current Protection With Temperature
Compensation Circuit for Each Channel
DOvervoltage and Undervoltage Protection
DProgrammable Short-Circuit Protection
DPowergood With Programmable Delay Time
D5-V and 3.3-V Linear Regulators
APPLICATIONS
DNotebook PCs, PDAs
DConsumer Game Systems
DDSP Application
DESCRIPTION
The TPS5130 is composed of three independent
synchronous buck regulator controllers (SBRC) and
one low drop-out (LDO) regulator controller. On-chip
high-side and low-side synchronous rectifier drivers are
integrated to drive less expensive N-channel
MOSFETs. The LDO controller can also drive an
external N-channel MOSFET. Since the input current
ripple is minimized by operating 180 degree out of
phase, it allows a smaller input capacitance resulting in
reduced p o w e r s u p p l y c o s t . T h e S B R C o f t h e T P S 5 1 3 0
automatically adjusts from PWM mode to SKIP mode
to maintain high efficiency under light load conditions.
Resistor-less current protection for the synchronous
buck controller and the fixed high-side driver voltage
simplifies the system design and reduces the external
parts count. The LDO controller has a current limit
protection and overshoot protection to suppress output
voltage hump at load transient. To further extend
battery life, the TPS5130 features dead-time control
and very low quiescent current.
See application section of this data sheet for more detailed information.
VIN
Vo1
5 V
Vo3
Vo3
Vo_LDO
TPS5130
OUT3_u OUT1_u
OUT3_d OUT1_d
LL3 LL1
VIN
INV3 INV1
OUT2_u
OUT2_d
LL2
INV2
LDO_IN
LDO_GATE
LDO_CUR
INV_LDO
REG5V_IN
GND
! "#$ ! %#&'" ($) (#"!
" !%$""! %$ *$ $! $+! !#$! !(( ,-)
(#" %"$!!. ($! $"$!!'- "'#($ $!. '' %$$!)
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.
www.ti.com
Copyright 2002, Texas Instruments Incorporated
SLVS426 − MAY 2002
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2
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during
storage or handling to prevent electrostatic damage to the MOS gates.
ORDERING INFORMATION
TAPACKAGED DEVICES
PLASTIC TQFP (PT)(1)
−40°C to 85°C TPS5130PT
(1) The PT package is also available taped and reeled. Add an R suffix to the device type (i.e.,
TPS5130PTR).
PACKAGE DISSIPATION RATINGS
PACKAGE(1) TA ≤ 25°C
POWER RATING DERATING FACTOR
ABOVE TA = 25°CTA = 85°C
POWER RATING
48 pin PT 3210 mW 25.7 mW/°C1670 mW
(1) These devices are mounted on a JEDEC high-k board (2 oz. traces on surface, 2-layer 1 oz. plane
inside). (Assumes the maximum junction temperature is 150°C)
ABSOLUTE MAXIMUM RATINGS
over o p e r a t i n g f ree-air temperature range unless otherwise noted(1)
TPS5130
Supply voltage, (2) VIN −0.3 V to 30 V
(2),
LH1/2/3 −0.3 V to 35 V
(2),
VIN_SENSE12/3, LL1/2/3, STBY_LDO,
(2),
VIN_SENSE12/3, LL1/2/3, STBY_LDO,
STBY_VREF3.3/5, TRIP1/2/3
−0.3 V to 30 V
(2),
STBY_VREF3.3/5, TRIP1/2/3
−0.3 V to 30 V
Input voltage range(2), VI
INV1/2/3, CT, SS_STBY1/2/3,
Input voltage range(2), VI
INV1/2/3, CT, SS_STBY1/2/3,
INV_LDO, LDO_OUT, FLT,
INV_LDO, LDO_OUT, FLT,
PG_DELAY, VREF3.3/5,
−0.3 V to 7 V
PG_DELAY, VREF3.3/5,
LDO_IN, LDO_CUR, PWM_SEL,
−0.3 V to 7 V
LDO_IN, LDO_CUR, PWM_SEL,
REG5V_IN
(2)
OUT1/2/3_u −0.3 V to 35 V
Output voltage range, VO (2)
FB1/2/3, PGOUT, OUT1/2/3_d −0.3 V to 7 V
Output voltage range, V
O
(2)
LDO_GATE −0.3 V to 9 V
REF −0.3 V to 3 V
Operating ambient temperature range, TA−40°C to 85°C
Storage temperature, Tstg −55°C to 150°C
(1) Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to the network ground terminal.
SLVS426 − MAY 2002
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3
RECOMMENDED OPERATING CONDITIONS
MIN NOM MAX UNIT
VIN 4.5 28
Supply voltage LDO_IN 1.1 3.6 V
Supply voltage
REG5V_IN 4.5 5.5
V
OUT1/2/3_u, LH1/2/3 −0.1 33
VIN_SENSE1/2/3 4.5 28
STBY_LDO, LL1/2/3, TRIP, STBY_VREF3.3/5 −0.1 28
Input voltage, V
I
LDO_GATE −0.1 8 V
Input voltage, VI
INV1/2/3, INV_LDO, CT, PWM_SEL, FLT, PG_DELAY, SS_STBY1/2/3 −0.1 6
V
PGOUT, FB1/2/3, OUT1/2/3_d −0.1 5.5
LDO_CUR, LDO_OUT −0.1 3.5
Oscillator frequency, fosc 300 500 kHz
Operating free-air temperature, TA−40 85 °C
ELECTRICAL CHARACTERISTICS
over operating free-air temperature range, V(VIN) = V(VIN_SENSE12) = V(VIN_SENSE3) = 12 V (unless otherwise noted)
Supply Current
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
ICC Supply current TA = 25°C, V(LDO_IN) = 3.6 V,
V(CT) = V(INVx) = V(INV_LDO) = 0 V, V(PWM_SEL) = 0 V 2 3 mA
ICC(STBY) Standby current V(SS_STBYx) = 0 V, V(STBY_LDO) = 0V,
V(STBY_VREF3.3/5) = 5 V 150 250 µA
ICC(S) Shutdown current V(SS_STBYx) = 0 V, V(STBY_LDO) = 0V,
V(STBY_VREF3.3/5) = 0 V 0.001 10 µA
Reference Voltage
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Vref Reference voltage 0.85 V
TA = 25°C, Iref = 50 µA −1.5% 1.5%
V
ref
(tol
)
Reference voltage tolerance TA = 0°C to 85°C, Iref = 50 µA −2% 2%
Vref(tol)
Reference voltage tolerance
TA = −40°C to 85°C, Iref = 50 µA −2.5% 2.5%
Line regulation V(VIN) = 4.5 V to 28 V, Iref = 50 µA 0.05 5 mV
Load regulation Iref = 0.1 µA to 1 mA 0.15 5 mV
5 V Internal Switch
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VT(LH)
Threshold voltage
High
REG5V_IN voltage
4.2 4.8
V
VT(HL)
Threshold voltage
Low
REG5V_IN voltage
4.1 4.7
V
Vhys Hysteresis REG5V_IN voltage 30 200 mV
VREF5 PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VOOutput voltage IO = 0 mA to 50 mA,
V(VIN) = 5.5 V to 28 V, TA = 25°C4.8 5.2 V
Line regulation V(VIN) = 5.5 V to 28 V, IO = 10 mA 20 mV
Load regulation IO = 1 mA to 10 mA, V(VIN) = 5.5 V 40 mV
IOS Short-circuit output current V(VREF5) = 0 V, TA = 25°C 65 mA
VT(LH)
UVLO threshold voltage
High
VREF5 voltage
3.6 4.2
V
VT(HL)
UVLO threshold voltage
Low
VREF5 voltage
3.5 4.1
V
Vhys Hysteresis VREF5 voltage 30 200 mV
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ELECTRICAL CHARACTERISTICS (continued)
over operating free-air temperature range, V(VIN) = V(VIN_SENSE12) = V(VIN_SENSE3) = 12 V (unless otherwise noted)
VREF3.3
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VOOutput voltage IO = 0 mA to 30 mA, V(VIN) = 5.5 V to 28 V,
TA = 25°C3.15 3.30 3.45 V
Line regulation V(VIN) = 5.5 V to 28 V, IO = 10 mA 20 mV
Load regulation IO = 1 mA to 10 mA, V(VIN) = 5.5 V 40 mV
IOS Short circuit output current V(VREF3.3) = 0 V, TA = 25°C −30 mA
Control
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VIH High-level input voltage SS_STBYx, STBY_LDO, PWM_SEL, STBY_VREF3.3/5 2.2 V
VIL Low-level input voltage SS_STBYx, STBY_LDO, PWM_SEL, STBY_VREF3.3/5 0.3 V
Output Voltage Monitor PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
OVP comparator threshold SBRC, LDO 0.91 0.95 0.99 V
UVP comparator threshold SBRC, LDO 0.51 0.55 0.59 V
PG comparator low-level threshold 0.75 0.79 0.81 V
PG comparator high-level threshold 0.88 0.91 0.94 V
PG propagation delay from INVx, INV_LDO to PGOUT (no load at PG_DELA Y)
Powergood H to L 6.5
s
PG propagation delay from INVx, INV_LDO to PGOUT (no load at PG_DELA Y)
Powergood L to H 16 µ
s
I(PG_DELAY) PG_DELA Y source current −1.8 µA
T imer latch current source
UVP protection −1.5 −2.3 −3.1 µA
T imer latch current source
OVP protection −80 −125 −180
Oscillator PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
fosc Oscillation frequency PWM mode, C(CT) = 44 pF, T A = 25°C 300 kHz
VOH
High level output voltage
dc 1 1.1 1.2
V
V
OH
High level output voltage
fosc = 300 kHz 1.17
V
VOL
Low level output voltage
dc 0.4 0.5 0.6
V
V
OL
Low level output voltage
fosc = 300 kHz 0.43
V
Error Amplifier for SBRC
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VIO Input of fset voltage INVx voltage, TA = 25°C 2 10 mV
Open loop voltage gain 50 dB
Unity-gain bandwidth 2.5 MHz
IO(snk) Output sink current V(FBx) = 1 V 0.2 0.7 mA
IO(src) Output source current V(FBx) = 1 V −0.2 −0.9 mA
Duty Control PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Maximum duty control
CH1/3, fosc = 300 kHz, V(INVx) = 0 V 82%
Maximum duty control
CH2, fosc = 300 kHz, V(INVx) = 0 V 97%
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5
ELECTRICAL CHARACTERISTICS (continued)
over operating free-air temperature range, V(VIN) = V(VIN_SENSE12) = V(VIN_SENSE3) = 12 V (unless otherwise noted)
Output Drivers PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
OUT_u sink current V(OUTx_u) – V(LLx) = 3 V 1.2 A
OUT_u source current V(LHx) − V(OUTx_u) = 3 V −1.2 A
OUT_d sink current V(OUTx_d) = 3 V 1.5 A
OUT_d source current V(OUTx_d) = 2 V −1.5 A
LDO_GATE sink current V(LDO_GATE) = 2 V 2 mA
LDO_GATE source current V(LDO_GATE) = 2 V −1.4 mA
I(TRIPx) TRIP current TA = 25°C11 13 15 µA
Soft Start PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
I(SS_STBYx) Soft start current V(SS_STBYx) = 0.7 V −1.6 −2.3 −2.9 µA
Error Amplifier for LDO Controller
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VIO Input of fset voltage V(LDO_IN) = 3.3 V, TA = 25 °C 2 10 mV
Open loop voltage gain V(LDO_IN) = 3.3 V 50 dB
Unity-gain bandwidth V(LDO_IN) = 3.3 V, CL = 2000 pF 1.4 MHz
Current Limit for LDO Controller
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Current limit comparator threshold voltage V(LDO_IN) = 3.3 V 40 50 60 mV
Overshoot Protection for LDO Controller
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
LDO_OUT sink current V(LDO_OUT) = V(LDO_GATE) = 1.5 V 25 mA
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6
PIN ASSIGNMENTS
PT
(TOP VIEW)
13 14 15 16 17 18 19 20 21 22 23 24
25
26
27
28
29
30
31
32
33
34
35
36
48 47 46 45 44 43 42 41 40 39 38 37
1
2
3
4
5
6
7
8
9
10
11
12
INV1
FLT
LH1
OUT1_u
LL1
OUT1_d
OUTGND1
TRIP1
VIN_SENSE12
TRIP2
OUTGND2
OUT2_d
LL2
OUT2_u
LH2
VIN
VREF3.3
VREF5
REG5V_IN
LDO_IN
LDO_CUR
LDO_GATE
LDO_OUT
INV_LDO
FB1
SS_STBY1
INV2
FB2
SS_STBY2
PWM_SEL
CT
GND
REF
STBY_VREF5
STBY_VREF3.3
STBY_LDO
SS_STBY3
FB3
INV3
PGOUT
PG_DELAY
TRIP3
VIN_SENSE3
LH3
OUT3_u
LL3
OUT3_d
OUTGND3
Terminal Functions
TERMINAL
I/O
DESCRIPTION
NAME NO.
I/O
DESCRIPTION
CT 7 I/O External capacitor from CT to GND adjusts frequency of the triangle oscillator .
FB1 1 O Feedback output of SBRC-CH1 error amplifier
FB2 4 O Feedback output of SBRC-CH2 error amplifier
FB3 14 O Feedback output of SBRC-CH3 error amplifier
FLT 47 I/O Fault latch timer pin. An external capacitor connected between FLT and GND sets FLT enable time up.
GND 8 − Signal GND
INV1 48 I Inverting inputs of SBRC-CH1 error amplifier , skip comparator, OVP1/UVP1 comparator and PG comparator
INV2 3 I Inverting inputs of SBRC-CH2 error amplifier, skip comparator, OVP2/UVP2 comparator and PG comparator
INV3 15 I Inverting inputs of SBRC-CH3 error amplifier, skip comparator , OVP3/UVP3 comparator and PG comparator
INV_LDO 25 I Inverting inputs of LDO error amplifier, OVP/UVP comparators and PG comparator.
LDO_CUR 28 I Current sense input of LDO regulator.
LDO_GATE 27 O Gate control output of external MOSFET for LDO regulator
LDO_OUT 26 I/O LDO regulator’s output connection. If output voltage has an overshoot when output current changes high to
low quickly, it absorbs electrical charge from this pin.
LDO_IN 29 I Supply voltage input and current sense input of LDO regulator
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7
Terminal Functions (Continued)
TERMINAL
I/O
DESCRIPTION
NAME NO.
I/O
DESCRIPTION
LH1 46 I/O Bootstrap capacitor connection for SBRC-CH1 high-side gate driver.
LH2 34 I/O Bootstrap capacitor connection for SBRC-CH2 high-side gate driver .
LH3 20 I/O Bootstrap capacitor connection for SBRC-CH3 high-side gate driver .
LL1 44 I/O SBRC-CH1 high-side gate driving return. Connect this pin to the junction of the high-side and low-side
MOSFETs for floating drive configuration. This pin is also an input terminal for current comparator.
LL2 36 I/O SBRC-CH2 high-side gate driving return. Connect this pin to the junction of the high-side and low-side
MOSFETs for floating drive configuration. This pin is also an input terminal for current comparator.
LL3 22 I/O SBRC-CH3 high-side gate driving return. Connect this pin to the junction of the high-side and low-side
MOSFETs for floating drive configuration. This pin is also an input terminal for current comparator.
OUT1_d 43 O Gate drive output for SBRC-CH1 low-side MOSFETs
OUT2_d 37 O Gate drive output for SBRC-CH2 low-side MOSFETs
OUT3_d 23 O Gate drive output for SBRC-CH3 low-side MOSFETs
OUT1_u 45 O Gate drive output for SBRC-CH1 high-side MOSFETs.
OUT2_u 35 O Gate drive output for SBRC-CH2 high-side MOSFETs.
OUT3_u 21 O Gate drive output for SBRC-CH3 high-side MOSFETs.
OUTGND1 42 O Ground for S B R C-CH1 MOSFETs drivers. It is connected to the current limiting comparator’s negative input.
OUTGND2 38 O Ground for SBRC-CH2 MOSFETs drivers. It is connected to the current limiting comparator’s negative input.
OUTGND3 24 O Ground for SBRC-CH3 MOSFETs drivers. It is connected to the current limiting comparator’s negative input.
PGOUT 16 O Powergood open drain output. PG comparators monitor all SBRC’s and LDO’s over voltage and under
voltage. The threshold is ±7%. When one of the output is beyond this condition, powergood output goes low .
PG_DELAY 17 I/O Programmable delay for Powergood. Connect an external capacitor between this pin and GND to specify
time delay.
PWM_SEL 6 I PWM or auto PWM/SKIP mode select.
H : auto PWM/SKIP
L : PWM fixed
REF 9 O 0.85-V reference voltage output. This 0.85-V reference voltage is used to set the output voltage and the
reference for the over and undervoltage protections. This reference voltage is dropped down from the internal
5-V regulator.
REG5V_IN 30 I External 5-V input
SS_STBY1 2 I/O Soft start control and stand by control for SBRC-CH1. Connect an external capacitor between this pin and
GND to specify soft start time.
SS_STBY2 5 I/O Soft start control and stand by control for SBRC-CH2. Connect an external capacitor between this pin and
GND to specify soft start time.
SS_STBY3 13 I/O Soft start control and stand by control for SBRC-CH3. Connect an external capacitor between this pin and
GND to specify soft start time.
STBY_LDO 12 I Standby control input for LDO regulator. LDO regulator can be switched into standby mode by grounding the
STBY_LDO pin.
STBY_VREF3.3 11 IStandby control for 3.3-V linear regulator.
STBY_VREF5 10 I Standby control for 5-V linear regulator.
TRIP1 41 I External resistor connection for SBRC-CH1 output current protection control.
TRIP2 39 I External resistor connection for SBRC-CH2 output current protection control.
TRIP3 18 I External resistor connection for SBRC-CH3 output current protection control.
VIN 33 I Supply voltage input
VIN_SENSE12 40 I SBRC-CH1/2 supply voltage monitor for reference of current limit. Input range is 4.5 V to 28 V.
VIN_SENSE3 19 I SBRC-CH 3 supply voltage monitor for reference of current limit. Input range is 4.5 V to 28 V.
VREF3.3 32 O 3.3-V linear regulator output
VREF5 31 O 5-V linear regulator output.
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8
FUNCTIONAL BLOCK DIAGRAM
3.3 V
REG.
5 V
REG. VREF
0.85 V
Fault
Latch
Timer
TIMER
Oscillator
Phase
Inverter
LH1
OUT1_u
LL1
OUT1_d
OUTGND1
VIN_SENSE12
TRIP1
LH2
OUT2_u
LL2
OUT2_d
OUTGND2
TRIP2
LH3
OUT3_u
LL3
OUT3_d
OUTGND3
VIN_SENSE3
TRIP3
STBY_LDO
LDO_GATE
LDO_CUR
LDO_OUT
LDO_IN
REF
REG5V_IN
VREF5
VREF3.3
STBY_VREF3.3
STBY_VREF5
INV_LDO
FLT
PGOUT
PG_DELAY
PWM_SEL
SS_STBY1
FB1
INV1
CT
SS_STBY2
FB2
INV2
SS_STBY3
FB3
INV3
VIN
0.85 V − 7 %
0.85 V + 7 %
+
−
+
+
+
+
−
−
+
−
−
−
4.5 V LDO
SBRC−CH2
SBRC−CH3
GND
UVLO
SS_STBY
SS_STBY STBY_LDO STBY_LDO
Current Limit
−
+
−
+
−
+
ERROR Amp.
OVP Comp.
UVP Comp.
0.85 V + 12 %
0.85 V − 35 %
0.85 V
LDO Overshoot
Protection
VIN_SENSE
SBRC−CH1
SOFTSTART
/STBY
Current
Protection
Trigger
−
+
−
+
−
+
+
−
+
−
+
−
+
−
+
SKIP Comp.
ERROR Amp.
PWM Comp.
OVP Comp.
UVP Comp.
Current Comp. 1
Current Comp. 2
−(VIN_SENSE−TRIP)
0.85 V + 12 %
0.85 V − 35 %
0.85 V
0.85 V
Duplicate for CH2 and CH3.
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DETAILED DESCRIPTION
PWM OPERATION
The SBRC block has a high-speed error amplifier to regulate the output voltage of the synchronous buck converter. T he
output voltage of the SBRC is fed back to the inverting input (INVx (x=1,2,3)) of the error amplifier. The noninverting input
is internally connected to a 0.85-V precise band gap reference circuit. The unity gain bandwidth of the amplifier is 2.5 MHz.
This decreases the amplifier delay during fast load transients and contributes to a fast response. Loop gain and phase
compensation is programmable by an external C, R network between the FBx and INVx pins. The output signal of the error
amplifier is compared with a triangular wave to achieve the PWM control signal. The oscillation frequency of this triangular
wave sets the switching frequency of the SBRC and is determined by the capacitor connected between the CT and GND
pins. The PWM mode is used for the entire load range if the PWM_SEL pin is set LOW, or used in high output current
condition if auto PWM/SKIP mode is selected by setting the same pin to HIGH.
SKIP MODE OPERATION
The PWM_SEL pin selects either the auto PWM/SKIP mode or fixed PWM mode. If this pin is lower than 0.3-V, the SBRC
operates in the fixed PWM mode. If 2.5 V (min.) or higher is applied, it operates in auto PWM/SKIP mode. In the auto
PWM/SKIP mode, the operation changes from constant frequency PWM mode to an energy-saving SKIP mode
automatically in accordance with load conditions. Using a MOSFET with ultra-low rDS(on) when the auto SKIP function is
implemented is not recommended. The SBRC block has a hysteretic comparator to regulate the output voltage of the
synchronous buck converter during SKIP mode. The delay from the comparator input to the driver output is typically 1.2
µs. In the SKIP mode, the frequency varies with load current and input voltage.
HIGH-SIDE DRIVER
The high-side driver is designed to drive high current and low rDS(on) N-channel MOSFET(s). The current rating of the driver
is 1.2 A at source and sink. When configured as a floating driver, a 5-V bias voltage is delivered from VREF5 pin. The
instantaneous drive current is supplied by the flying capacitor between the LHx and LLx pins since a 5-V power supply does
not usually have low impedance. It is recommended to add a 5 Ω to 10 Ω resistor between the gate of the high-side
MOSFET(s) and the OUTx_u pin to suppress noise. The maximum voltage that can be applied between the LHx and
OUTGNDx pins is 33 V.
When selecting the high current rating MOSFET(s), it is important to pay attention to both gate drive power dissipation and
the rise/fall time against the dead-time between high-side and low-side drivers. The gate drive power is dissipated from
the controller IC and it is proportional to the gate charge at VGS = 5 V, PWM switching frequency, and the numbers of all
MOSFETs used for low-side and high-side switches. This gate drive loss should not exceed the maximum power dissipation
of the device.
LOW-SIDE DRIVER
The low-side driver is designed to drive high current and low rDS(on) N-channel MOSFET(s). The maximum drive voltage
is 5 V from the internal regulator or REG5V_IN pin. The current rating of the driver is typically 1.5 A at source and sink.
Gate resistance is not necessary for the low-side MOSFET for switching noise suppression since it turns on after the
parallel diode is turned on (ZVS). It needs the same dissipation consideration when using high current rating MOSFET(s).
Another issue that needs precaution is the gate threshold voltage. Even though the OUTx_d pin is shorted to the OUTGNDx
pin with low resistance when the low-side MOSFET(s) is OFF, high dv/dt of the LLx pin during turnon of the high-side arm
will generate a voltage peak at the OUTx_d pin through the drain to gate capacitance, Cdg, of the low-side MOSFET(s).
To prevent a short period shoot-through during this switching event, the application designer should select MOSFET(s) with
adequate threshold voltage.
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10
DEAD-TIME
The internally defined dead-time prevents shoot-through-current flowing through the main power MOSFETs during
switching transitions. Typical value of the dead-time is 100 ns.
STANDBY
The SBRC controller, the LDO controller, and the internal regulators can be switched into standby mode separately as
shown in Table 1. The standby mode current, when both controllers and regulators are off, can be as low as 1 nA.
Table 1. Standby Logic
INPUT FUNCTION
STBY_VREF5 SS_STBYx STBY_VREF3.3 STBY_LDO V(REG5V_IN) > 4.5V VREF5 VREF3.3 SBRCx LDO
L L L L False OFF OFF OFF OFF
L(1) L(1) L(1) L(1) True(1) ON(1) OFF(1) OFF(1) OFF(1)
H L L L x ON OFF OFF OFF
L H L L x OFF OFF OFF OFF
H H L L x ON OFF ON OFF
L L H L x ON ON OFF OFF
H L H L x ON ON OFF OFF
L H H L x ON ON OFF OFF
H H H L x ON ON ON OFF
L L L H x ON OFF OFF ON
H L L H x ON OFF OFF ON
L H L H x ON OFF OFF ON
H H L H x ON OFF ON ON
L L H H x ON ON OFF ON
H L H H x ON ON OFF ON
L H H H x ON ON OFF ON
H H H H x ON ON ON ON
(1) This functional mode is not recommended.
x = true or false
SOFT START
Soft start ramp up of the SBRC is controlled by the SS_STBYx pin voltage, which is controlled by an internal current source
and an external capacitor connected between the SS_STBYx and GND pins. When the STBY_VREF5 and/or SS_STBYx
pin voltages are forced to LOW, the SBRCx is disabled. When the STBY_VREF5 pin voltage is set to HIGH and the
SS_STBYx pin floats, the internal current source starts to charge the external capacitor . The output voltage ramps up as
the SS_STBYx pin voltage increases from 0 V to 0.85 V. The soft start time is easily calculated from the supply current and
the capacitance value (see application information). The soft start timing circuit for the LDO is integrated into the device.
The soft start time is fixed and can be as short as 600 µs. This is observed when the LDO is turned on separately from t h e
SBRC. Simultaneous start-up of one of the SBRC and the LDO, is also possible. Tie the LDO input to the SBRCx’s output,
let both the STBY_VREF5 and STBY_LDO voltages rise to the HIGH level, and invoke Soft start on the SS_STBYx pin;
then the LDO’s output follows the ramp of the SBRCx’s output.
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OVER CURRENT PROTECTION
Over current protection (OCP) is achieved by comparing the drain-to-source voltage of the high-side and low-side MOSFET
to a set-point voltage, which is defined by both the internal current source, I(TRIP), and the external resistor connected
between the VIN_SENSEx and the TRIPx pins. I(TRIP) has a typical value of 13 µA at 25°C. When the drain-to-source
voltage exceeds the set-point voltage during low-side conduction, the high-side current comparator becomes active, and
the low-side pulse is extended until this voltage comes back below the threshold. If the set-point voltage is exceeded during
high-side conduction in the following cycle, the current limit circuit terminates the high-side driver pulse. Together this action
has the effect of decreasing the output voltage until the under voltage protection circuit is activated to latch both the
high-side and low-side drivers OFF. In the TPS5130, trip current I(TRIP) has a temperature coefficient of 3400 ppm/°C in
order to compensate for temperature drift of the MOSFET on-resistance.
OCP FOR THE LDO
To achieve the LDO current limit, a sense resistor must be placed in series with the N-channel MOSFET drain, connected
between the LDO_IN and LDO_CUR pins (see reference schematic). If the voltage drop across this sense resistor exceeds
50 mV, the output voltage is reduced to approximately 22% of the nominal value, thus it activates the UVP to start the FLT
latch timer. When the time is up, the LDO_GATE pin is pulled LOW to makes the LDO regulator shut down. Note that all
of the SBRCs are latched OFF at the same time since the LDO and the SBRCs share the same FLT capacitor.
OVER VOLTAGE PROTECTION
For overvoltage protection (OVP), the TPS5130 monitors the INVx and INV_LDO pin voltages. When the INVx or INV_LDO
pin voltage is higher than 0.95 V (0.85 V +12%), the OVP comparator output goes low and the FLT timer starts to charge
an external capacitor connected to FLT pin. After a set time, the FLT circuit latches the high-side MOSFET driver, the
low-side MOSFET drivers, and the LDO. The latched state of each block is summarized in Table 2. The timer source current
for the OVP latch is 125 µA(typ.), and the time-up voltage is 1.185 V (typ.). The OVP timer is designed to be 50 times faster
than the under voltage protection timer described in Table 2.
Table 2. OVP Logic
OVP OCCURRED AT HIGH-SIDE MOSFET DRIVER LOW -SIDE MOSFET DRIVER LDO
SBRC OFF ON OFF
LDO OFF OFF OFF
UNDER VOLTAGE PROTECTION
For under voltage protection (UVP), the TPS5130 monitors the INVx and INV_LDO pin voltages. When the INVx or
INV_LDO pin voltage is lower than 0.55 V (0.85 V - 35 %), the UVP comparator output goes low, and the FLT timer starts
to charge the external capacitor connected to FLT pin. Also, when the current comparator triggers the OCP, the UVP
comparator detects the under voltage output and starts the FLT capacitor charge, too. After a set time, the FLT circuit latches
all of the MOSFET drivers to the OFF state. The timer latch source current for UVP is 2.3 µA (typ.), and the time-up voltage
is also 1.185 V (typ.). The UVP function of the LDO controller is disabled when voltage across the pass transistor is less
than 0.23 V (typ.).
FLT
When a n OVP or UVP comparator output goes low, the FLT circuit starts to charge the FLT capacitor. I f the FLT pin voltage
goes beyond a constant level, the TPS5130 latches the MOSFET drivers. At this time, the state of MOSFET is different
depending o n the OVP alert and the UVP alert (see Table 2). The enable time used to latch the MOSFET drivers is decided
by the value of the FLT capacitor . The charging constant current value depends on whether it is an OVP alert or a UVP
alert as shown in the following equation:
FLT source current (OVP) = FLT source current (UVP) × 50
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UNDER VOLTAGE LOCK OUT (UVLO)
When the output voltage of the internal 5-V regulator or the REG5V_IN voltage decreases below about 4 V, the output
stages o f all the SBRCs and the LDO are turned off. This state is not latched, and the operation recovers immediately after
the input voltage becomes higher than the turnon value again. The typical hysteresis voltage is 100 mV.
UVLO FOR LDO
The LDO_IN voltage is monitored with a hysteretic comparator. When this voltage is less than 1 V, the UVLO circuit disables
the UVP/OVP comparators that monitor the INV_LDO voltage. In case the SBRC overcurrent protection is activated prior
to that of the LDO’s, this protection function may also be observed.
LDO CONTROL
The LDO controller can drive an external N-channel MOSFET. This realizes a fast response as well as an ultralow dropout
voltage regulator. For example, it is easy to configure both a 1.8-V and a 1.5-V high current power supply for core and I/O
of modern digital processors, one from the SBRC and the other from the LDO. The LDO_IN voltage range is from 1.1 V
to 3.6 V, and the output voltage is adjustable from 0.9 V to 2.5 V by an external resistor divider. Gain and phase of the
high-speed error amplifier for this LDO control is internally compensated and is connected to the 0.85-V band gap reference
circuit. The gate driver buffer is supplied by VIN_SENSE voltage. In the relatively high output voltage applications, make
sure that output voltage plus threshold voltage of the pass transistor is less than the minimum VIN. More precisely,
VIN - 0.7 ≥ Vthn + V(LDO_OUT)
where Vthn is the threshold voltage of the Nch MOSFET.
The LDO controller is also equipped with OVP, UVP, overcurrent limit, and overshoot protection functions.
OVERSHOOT PROTECTION
In the event that load current changes from high to low very quickly, the LDO regulator output voltage may start to overshoot.
In order to resist this phenomenon, the LDO controller has an overshoot protection function. If the LDO regulator output
overshoots, the controller draws electrical charge out from the LDO_OUT pin to hold it stable.
POWERGOOD
A single powergood circuit monitors the SBRCx output voltages and the LDO output voltage. The powergood pin is an open
drain output. When the INV or INV_LDO voltage goes beyond ±7% of 0.85 V, the powergood pin is pulled down to the LOW
level. Powergood propagation delay is programmable by controlling rising time using an external capacitor connected to
the PG_DELAY pin. During the soft start period, powergood indicates LOW, in other words power bad.
Table 3. Powergood Logic
SS_STBY1 SS_STBY2 SS_STBY3 STBY_LDO POWERGOOD
LLLL L
H L L L H
L H L L H
H H L L H
L L H L H
H L H L H
L H H L H
H H H L H
H or L H or L H or L H H
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5-V REGULATOR
An internal linear voltage regulator is used for the high-side driver bootstrap. Since the input voltage ranges from 4.5 V to
28 V, this feature offers a fixed bootstrap voltage to simplify the drive design. It is active if the STBY_VREF5 is HIGH and
has a tolerance of 4%. The 5-V regulator is used for powering the low-side driver and the VREF. When this regulator is
disconnected from the MOSFET drivers, it is used only for the source of VREF.
3.3-V REGULATOR
The TPS5130 has a 3.3-V linear regulator. The output is made from the internal 5-V regulator or an external 5 V from the
REG5V_IN pin. The maximum output current of this regulator is limited to 30 mA by an output current limit control. A ceramic
capacitor of 4.7 µF should be connected between the VREF3.3 and GND pins to stabilize the output voltage.
EXTERNAL 5-V INPUT AND 5-V SWITCH
If the internal 5-V switch detects 5-V input from the REG5V_IN pin, the internal 5-V regulator is disconnected from the
MOSFET drivers. The external 5 V is used for both the high-side bootstrap and the low-side driver, thus increasing the
efficiency. When an excess voltage is applied to the REG5V_IN pin, the OVP timer starts to charge the FLT capacitor and
latches all the MOSFET drivers and the LDO at OFF state after a set time.
PHASE INVERTER
The SBRC3 of the TPS5130 operates in the same phase as the internal triangular oscillator output while the SBRC1 and
the SBRC2 operate 180 degrees out of phase. When the SBRC1 and the SBRC3 (or the SBRC2 and the SBRC3) share
the same input power supply, the TPS5130 realizes 180 degrees out of phase operation that reduces input current ripple
and enables the input capacitor value smaller.
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TYPICAL CHARACTERISTICS
Figure 1
1
1.5
2
2.5
3
−50 0 50 100 150
TJ − Junction Temperature − °C
− Supply Current − mA
SUPPLY CURRENT
vs
JUNCTION TEMPERATURE
ICC
V(LDO_IN) = V(LDO_CUR) = 3.6 V,
V(PWM_ESL) = V(FLT) = V(CT) = 0 V
Figure 2
0
50
100
150
200
250
−50 0 50 100 150
TJ − Junction Temperature − °C
− Supply Current (Shutdown) − nA
SUPPLY CURRENT (SHUTDOWN)
vs
JUNCT I O N T E M P E R ATURE
ICC
V(LDO_IN) = V(LDO_CUR) = 3.6 V,
V(INX) = V(INV_LDO) = 0 V
V(SS_STBYx) = 0 V
V(STBY_VREF 3.3/5) = 0 V
V(PWM_SEL) = 0 V
Figure 3
−160
−140
−120
−100
−80
−60
−40
−20
0−50 0 50 100 150
TJ − Junction Temperature − °C
− Source Current − FLT(OVP) −
SOURCE CURRENT FLT(OVP)
vs
JUNCTION TEMPERATURE
IS
V(LDO_IN) = V(LDO_CUR) = 3.3 V,
V(INV_LDO) = 1 V
Aµ
Figure 4
−3
−2.5
−2
−1.5
−1
−0.5
0−50 0 50 100 150
TJ − Junction Temperature − °C
SOURCE CURRENT FLT(UVP)
vs
JUNCTION TEMPERATURE
V(LDO_IN) = V(LDO_CUR) = 3.3 V,
V(INV_LDO) = 5 V
− Source Current − FLT(UVP) − ISAµ
Figure 5
0
5
10
15
20
25
−50 0 50 100 150
TJ − Junction Temperature − °C
Trip Current −
TRIP CURRENT
vs
JUNCTION TEMPERATURE
V(Trip) = V(VIN_SENSE) − 0.1 V
Aµ
Figure 6
0
0.5
1
1.5
2
2.5
3
02468
10
VO − Output Voltage − V
Sink Current (LDO_GATE) − mA
SINK CURRENT (LDO_GATE)
vs
OUTPUT VOLTAGE
V(INV_LDO) = 2 V
V(LDO_IN) = V(LDO_CUR) = 3.3 V
V(VIN_SENSE) = 12 V, unless otherwise noted
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TYPICAL CHARACTERISTICS
Figure 7
−2
−1.5
−1
−0.5
00246810
VO − Output Voltage − V
SOURCE CURRENT (LDO_GATE)
vs
OUTPUT VOLTAGE
Source Current (LDO_GATE) − mA
V(INV_LDO) = 0 V
V(LDO_IN) = V(LDO_CUR) = 3.3 V
Figure 8
935
940
945
950
955
−50 0 50 100 150
TJ − Junction Temperature − °C
Threshold Voltage (OVP) − mV
THRESHOLD VOL TAGE (OVP)
vs
JUNCT I O N T E M P E R ATURE
Figure 9
10
100
1000
0 50 100 150 200 250 300 350
C − Capacitance − pF
Oscillator Frequency − kHz
OSCILLATOR FREQUENCY
vs
CAPACITANCE
TJ = 25°C
Figure 10
70
75
80
85
90
95
100
−50 0 50 100 150
TJ − Junction Temperature − °C
Output Maximum Duty Cycle − %
OUTPUT MAXIMUM DUTY CYCLE
vs
JUNCTION TEMPERATURE
V(LH) = 5 V, C(CT) = 45 pF,
V(PWM_SEL) = V(FLT) = V(LL) = V(INV)
= 0 V
CH2
CH1/3
Figure 11
0.1
1
10
100
1000
10000
100000
10 100 1000 10000
VINV = 0.85 to 1.05 V,
TJ = 25°C
C − Capacitance − pF
− Delay Time FLT (OVP) −
DELAY TIME FLT(OVP)
vs
CAPACITANCE
tdsµ
Figure 12
0.1
1
10
100
1000
10000
100000
10 100 1000 10000
VINV = 0.65 to 0.05 V,
TJ = 25°C
C − Capacitance − pF
− Delay Time FLT (UVP) −
DELAY TIME FLT(UVP)
vs
CAPACITANCE
tdsµ
VVIN_SENSE = 12 V, unless otherwise noted
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TYPICAL CHARACTERISTICS
Figure 13
1
10
100
1000
10000
100000
1 10 100 1000 10000 100000
C − Capacitance − pF
Soft Start Time −
SOFT START TIME
vs
CAPACITANCE
sµ
TJ = 25°C
Figure 14
0
10
20
30
40
50
60
−50 0 50 100 150
TJ − Junction Temperature − °C
Current Limit Threshold Voltage For LDO − mV
CURRENT LIMIT THRESHOLD
VOLTAGE FOR LDO
vs
JUNCT I O N T E M P E R ATURE
V(LDO_IN) = 3.3 V
V(INV_LDO) = 0.5 V
Figure 15
0
0.2
0.4
0.6
0.8
1
1.2
−50 0 50 100 150
TJ − Junction Temperature − °C
LDO UVLO Threshold Voltage − V
LDO UVLO THRESHOLD VOLTAGE
vs
JUNCTION TEMPERATURE
V(INV_LDO) = 1.2 V
VTLH
VTHL
Figure 16
1
10
100
1000
10000
1 10 100 1000 10000
C − Capacitance − pF
Powergood Delay Time −
POWERGOOD DELAY TIME
vs
CAPACITANCE
sµ
VIN = 12 V, TJ = 25°C
V(INV_LDO) = 1 V → 0.85 V
VVIN_SENSE = 12 V, unless otherwise noted
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APPLICATION INFORMATION
The design shown is a reference design for a notebook PC application. An evaluation module (EVM) is available
for customer testing and evaluation.
The following key design procedures aid in the design of the notebook PC power supply using TPS5130.
1
2
3
4
5
6
7
8
9
10
11
12
U01
TPS5130PT
VO3−2
VO3−1
LDO_OUT−2
LDO_OUT−1
GND−2
GND−1
VIN1−2
VIN1−1
VREF5
VREF3.3
VO2−2
VO2−1
VO1−2
VO1−1
C45
C27
Q07A Q07B
R21A
R21B
R21C
R07
C09
C08
C07
C05 C04 R06
R01A
R01B R02
C02
R05
JP03
JP04
1
23
1
23
1
2
3
PWR_GD
13
14
15
16
17
18
19
20
21
22
23
24
STBY_LDO
STBY_VREF3.3
STBY_VREF5
REF
GND
CT
PWM_SEL
SS_STBY2
FB2
INV2
SS_STBY1
FB1
OUTGND3
OUT3_d
LL3
OUT3_u
LH3
VIN_SENSE3
TRIP3
PG_DELAY
PGOUT
INV3
FB3
SS_STBY3
27
26
25
30
29
28
33
32
31
36
35
34
INV_LDO
LDO_OUT
LDO_GATE
LDO_CUR
LDO_VIN
REG5V_IN
VREF5
VREF3.3
VIN
LH2
OUT2_u
LL2
39
38
37
42
41
40
45
44
43
48
47
46
OUT2_d
OUTGND2
TRIP2
VIN_SENSE12
TRIP1
OUTGND1
OUT1_d
LL1
OUT1_u
LH1
FLT
INV1
4
5 − 8
1 − 3 1
2
3
L02
D03
Q03A Q03B
Q04A Q04B
4
5 − 8
1 − 3
45 − 8
1 − 3
4
5 − 8
1 − 3
45 − 8
1 − 3
L01
D02
Q01A Q01B
Q02A Q02B
4
5 − 8
1 − 3
4
5 − 8
1 − 3
4
5 − 8
1 − 3
4
5 − 8
1 − 3
C39C38C37
C32C31
L03
D05
Q05A Q05B
Q06A Q06B
45 − 8
1 − 3
45 − 8
1 − 3
45 − 8
1 − 3
45 − 8
1 − 3 C18C17
C01B
C24
C06 R08
JP05
JP06
1
23
1
23
R03A
R03B R04
C03
1
23
1
23
1
23
LDO_IN
C22
C26
R18
R19
R32
R33R34
Q10
D09C19 C20
C23
C01A
R20
D08C33 C34
D07 C40
2SC4617
R29
R30R31
Q09
2SC4617
R26
R27R28
Q08
2SC4617
D04
R22
D01
R25
C41
C35
C29
C15
R23
R24
C43
C44
C42
R09
R49
R46
R47
C16
C30
Q11
Q12
JP01
JP02
JP11
JP12
R48
C36 Q13
JP07
JP13
C10
R11
R12
C11
R14
R13
R14B
C12
R15
R17
C21 C14
C13
D06
R16
JP10
VIN_SLIT
JP08
C28
Figure 17. EVM Schematic
An optional circuit composed of Q08, Q09, Q10, R26, R27, R28, R29, R30, R31, R32, R33, and R34 can be
used to increase temperature coefficient of the trip current.
OUTPUT VOLTAGE SETPOINT CALCULATION
In the following calculation, assume the output voltage of SBRC1 (VO1), SBRC2 (VO2), SBRC3 (VO3), and LDO
(VO4) are 3.3 V, 5 V, 1.8 V, and 1.5 V respectively. The reference voltage and the voltage divider set the output
voltage. In the TPS5130, the reference voltage is 0.85 V, and the divider is composed of three resistors in the
EVM design that are R01A, R01B, and R05 for the first SBRC output; R03A, R03B, and R07 for the second
SBRC output ; R14A, R14B, and R11 for the third SBRC output ; R18 and R19 for LDO regulator output.
VO+R1 Vref
R2 )Vref or R2 +R1 Vref
VO*Vref
where R1 is the top resistor (kΩ) (R01A + R01B or R03A + R03B or R14A + R14B or R18); R2 is the bottom
resistor (kΩ) (R05 or R07 or R11 or R19); VO is the required output voltage (V); Vref is the reference voltage
(0.85 V in TPS5130). The value for R1 is set as a part of the compensation circuit and the value of R2 may be
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18
calculated to achieve the desired output voltage. In the EVM design, the value of R1 is determined as
R01A = 27 kΩ and R01B = 1.8 kΩ for VO1, R03A = 47 kΩ and R03B = 1.8 kΩ for VO2, R14A = 10 kΩ and
R14B = 1.2 kΩ for VO3, and R18 = 6.8 k + 820 Ω for VO4 considering stability. For VO1:
R05 +(27 k )1.8 k) 0.85
3.3 *0.85 +9.99 kW
Therefore, use 10 kΩ.
In a same manner, R07 = R11 = R19 = 10 kΩ as follows.
R07 +(47 k )1.8 k) 0.85
5*0.85 +10.00 kW
R11 +(10 k )1.2 k) 0.85
1.8 *0.85 +10.02 kW
R19 +(6.8 k )820) 0.85
1.5 *0.85 +9.96 kW
The values of R01B, R03B, R14B and R19 are chosen so that the calculated values of R05, R07, R11, and R19
are standard value resistors and the VO setpoint maintains the highest precision. This is best accomplished by
combining two resistor values. If a standard value resistor can not be applied, use a value for R01A, R03A,
R14A, and R18 that is just slightly less than the desired total. A small resistor value in the range of tens or
hundreds of ohms for R01B, R03B, R14B and R18 can then be added to generate the desired final value.
OUTPUT INDUCTOR SELECTION
The required value for the output filter inductor can be calculated by using the equation below, assuming the
magnitude of the ripple current is 20 % of the maximum output current:
L(out) +VIN *VO
0.2 IO VO
VIN 1
fS
Where L(out) is output filter inductor value (H), VIN is the input voltage (V), IO is the maximum output current
(A), fs is the switching frequency (Hz).
Example : VIN = 8 V; VO = 3.3 V; IO = 4 A; fs = 300 kHz.
Then, L(out) = 8.1 µH.
If faster output response is required for a sudden transition of the load, smaller inductance value is
recommended.
OUTPUT INDUCTOR RIPPLE CURRENT
The output inductor current can affect not only the efficiency, but also the output voltage ripple. The equation
is exhibited below:
I(ripple) +VIN *VO*IO ǒrDS(on) )RLǓ
L(out) VO
VIN 1
fS
where I (ripple) is the peak-to-peak ripple current (A) through the inductor; Io is the output current; rDS(on) is the
on-time resistance of MOSFET (Ω); RL is the inductor dc resistance (Ω). From the equation, it can be seen that
the current ripple can be adjusted by changing the output inductor value.
Example: VIN = 8 V; VO = 3.3 V; IO = 4 A; rDS(on) = 25 mΩ; RL = 10 mΩ; fs = 300 kHz; L(out) = 4 µH.
Then, the ripple current I(ripple) = 1.57 A
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OUTPUT CAPACITOR SELECTION
Selection of the output capacitor is basically dependent on the amount of peak-to-peak ripple voltage allowed
on the output and the ability of the capacitor to dissipate the RMS ripple current. Assuming that the ESR of the
output filter sees the entire inductor ripple current then:
Vpp +I(ripple) R(esr)
And a suitable capacitor must be chosen so that the peak-to-peak output ripple is within the limits allowable
for the application.
OUTPUT CAPACITOR RMS CURRENT
Assuming the inductor ripple current totally goes through the output capacitor to ground, the RMS current in
the output capacitor can be calculated as:
IO(rms) +I(ripple)
12
Ǹ
where I O(rms) is maximum RMS current in the output capacitor (A); I(ripple) is the peak-to-peak inductor ripple
current (A).
Example: I(ripple) = 1.57 A, then, IO(rms) = 0.45 A
INPUT CAPACITOR RMS CURRENT
Since the SBRC3 of the TPS5130 operates 180 degree off phase against the SBRC1 and SBRC2, total RMS
current in the input capacitor is calculated as follows, assuming the input current totally goes into the input
capacitor to the power ground, and ignoring ripple current in the inductor.
When the duty cycle of the SBRC2 (D2) is over 50 %,
II(rms) +(D1 IO12))(D2 IO22))(D3 IO32))(2D1 IO1 IO2) )(2D2 *1) IO2 IO3*IOx2
Ǹ
IOx+(D1 IO1) )(D2 IO2) )(D3 IO3) D2 w0.5 wD1 wD3
II(rms) is the input RMS current in the input capacitor; DX is duty cycles, defined as VO/VI in this case, of the
SBRCx.
When D2 is less than 50%,
II(rms) +(D1 IO12))(D2 IO22))(D3 IO32))(2D1 IO1 IO2) *IOx2
Ǹ
Example: VIN = 12 V, VO1 = 3.3 V, VO2 = 5 V (D2 = 0.42), VO3 = 1.8V, IO1 = IO2 = 4 A, IO3 = 6 A
Then, II(rms) = 3.44 A
On the contrary, if three SBRCs operate in a same phase the RMS current is calculated as follows.
II(rms) +(D1 IO12))(D2 IO22))(D3 IO32))(2D1 IO1 IO2) )(2D3 IO3) ǒIO1)IO2Ǔ*IOx2
Ǹ
Under the same operation condition, II(rms) = 5.13 A
Therefore, 180 degree out of phase operation is effective in reducing input RMS current, and it allows a smaller
input capacitance value. The input capacitors must be chosen so that together they can safely handle the input
ripple current. Depending on the input filtering and the dc input voltage source, not all the ripple current flows
through the input capacitors, but some may be present on the input leads to the EVM.
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SOFT START
The soft start timing can be adjusted by selecting the soft-start capacitor value. The equation is;
C(soft) +2.3 10–6 T(soft)
0.85
where C(soft) is the soft-start capacitor (µF) (C05, C07 and C10 in EVM design):
T(soft) is the start-up time (s).
Example: T(soft) = 5 ms, therefore, C(soft) = 0.0135 µF.
CURRENT PROTECTION
The current limit in TPS5130 is set using an internal current source and an external resistor (R17, R23 and R24).
The current limit protection circuit compares the drain to source voltage of the high-side and low-side
MOSFET(s) with respect to the set-point voltage. If the voltage up exceeds the limit during high-side conduction,
the current limit circuit terminates the high-side driver pulse. If the set point voltage is exceeded during low-side
conduction, the low side pulse is extended through the next cycle. Together this action has the effect of
decreasing the output voltage until the under voltage protection circuit is activated and the fault latch is set and
both the high-side and low-side MOSFET drivers are shut of f. The equation below should be used for calculating
the external resistor value for current protection set point:
R(cl) +
rDS(on) ǒI(trip) )I(ripple)
2Ǔ
13 10–6
where R (cl) is the external current limit resistor (R17, R23 and R24); rDS(on) is the low-side MOSFET(Q02, Q04
and Q06) on-time resistance. I(trip) is the required current limit.
Example: rDS(on) = 25 mΩ, I(trip) = 4 A, I(ripple) = 1.57 A, therefore, R(cl)= 9.2 kΩ.
It should be noted that rDS(on) of a FET is highly dependent on temperature, so to insure full output at maximum
operating temperature, the value of rDS(on) in the above equation should be adjusted. For maximum stability,
it is recommended that the high-side MOSFET(s) has the same, or slightly higher rDS(on)than the low-side
MOSFET(s). If the low-side MOSFET(s) has a higher rDS(on), in certain low duty cycle applications it may be
possible for the device to regulate at an output current higher than that set by the above equation by increasing
the high-side conduction time to compensate for the missed conduction cycle caused by the extension of the
previous low-side pulse.
TIMER-LATCH
The TPS5130 includes fault latch function with a user adjustable timer to latch the MOSFET drivers in case
of a fault condition. When either the OVP or UVP comparator detect a fault condition, the timer starts to charge
FLT capacitor (C42), which is connected with FLT pin. The circuit is designed so that for any value of FLT
capacitor, the undervoltage latch time t(uvplatch) is about 50 times larger than the overvoltage latch time t(ovplatch).
The equations needed to calculate the required value of the FLT capacitor for the desired over and undervoltage
latch delay times are:
C(lat) +2.3 10*6 t(uvplatch)
1.185 and
C(lat) +125 10*6 t(ovplatch)
1.185
where C (lat) is the external capacitor, t (uvplatch) is the time from UVP detection to latch. t(ovplatch) is the time from
OVP detection to latch.
For the EVM, t(uvplatch) = 5 ms and t(ovplatch) = 0.1 ms, so C(lat) = 0.01 µF. If the voltage on the FLT pin reaches
1.185 V, the fault latch is set, and the MOSFET drivers are set as follows:
SLVS426 − MAY 2002
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21
Undervoltage Protection
The undervoltage comparator circuit continually monitors the voltage at the INV and INV_LDO pins. If the
voltage at either pin falls below 65 % of the 0.85 V reference, the timer begins to charge the FLT capacitor. if
the fault condition persists beyond the time t(uvplatch), the fault latch is set and both the high-side and low-side
drivers, and LDO regulator drivers are forced OFF.
Short-Circuit Protection
The short-circuit protection circuitry uses the UVP circuit to latch the MOSFET drivers. When the current limit
circuit limits the output current, then the output voltage goes below the target output voltage and UVP
comparator detects a fault condition as described above.
Overvoltage Protection
The overvoltage comparator circuit continually monitors the voltage at the INV and INV_LDO pins. If the voltage
at either pin rises above 112 % of the 0.85 V reference, the timer begins to charge the FLT capacitor. If the fault
condition persists beyond the time t(ovplatch), the fault latch is set and the high-side drivers are forced OFF, while
the low-side drivers are forced ON, and LDO regulator drivers are forced OFF.
CAUTION:
Do not set the FLT terminal to a lower voltage (or GND) while the device is timing out an OVP or UVP
event. If the FLT terminal is manually set to a lower voltage during this time, output overshoot may
occur. The TPS5130 must be reset by grounding SS_STBYx and STBY_LDO, or dropping down
REG5V_IN.
Disablement of the Protection Function
If it is necessary to inhibit the protection functions of the TPS5130 for troubleshooting or other purposes, the
OCP,OVP, and UVP circuits may be disabled.
DOCP(SBRC): Remove the current limit resistors R17, R23 and R24 to disable the current limit function.
DOCP(LDO): Short−circuit R21 to disable the current limit function.
DOVP, UVP: Grounding the FLT terminal can disable OVP and UVP.
LDO REGULATOR APPLICATION INFORMATION
Output Capacitor Selection
To keep stable operation of the LDO, capacitance of more than 33 µF and R(esr) of more than 30 mΩ are
recommended for the output capacitor.
Power MOSFET Selection
Also, to keep stable operation of LDO, lower input capacitance is recommended for the external power
MOSFET. However, input capacitance that is too small may lead the feedback loop into an unstable region.
In this case, the gate resistor of several hundreds ohms keeps the LDO operation in the stable state.
Current Protection
If excess output current flows through sense resistor (R21) and the voltage drop exceeds 50 mV, the output
voltage is reduced to approximately 22% of the nominal value, thus activates UVP to start the FLT latch timer.
When the set current is 3 A, the value of R21 is 16.7 mΩ.
SLVS426 − MAY 2002
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22
Layout Guidelines
Good power supply results only occur when care is given to proper design and layout. Layout affects noise
pickup and generation and can cause a good design to perform with less than expected results. With a range
of currents from milliamps to tens amps, good power supply layout is much more difficult than most general
PCB designs. The general design should proceed from the switching node to the output, then back to the driver
section and, finally, parallel the low-level components. Below are specific points to consider before the layout
of a TPS5130 design begins.
DA four-layer PCB design is recommended for design using the TPS5130. For the EVM design, the top layer
contains the interconnection to the TPS5130, plus some additional signal traces. Layer2 is fully devoted
to the ground plane. Layer3 has some signal traces. The bottom layer is almost devoted to ANAGND, and
the rest is to other signal trace.
DAll sensitive analog components such as INV, REF, CT, GND, FLT, and SS_STBY should be referenced
to ANAGND.
DIdeally, all of the area directly under the TPS5130 chip should also be ANAGND.
DANAGND and DRVGND should be isolated as much as possible, with a single point connection between
them.
LDO_OUT
LDO_GATE
LDO_CUR
LDO_IN
VIN_SENSE
OUTGND
OUT_d
LL
OUT_u
INV_LDO
FLT
REF
GND
CT
SOFT_START
FB
INV Vox
VIN
Vo_LDO
VoxGND
ANAGND DRVGND
LH
VREF5
TRIP
CTRIP
CBS
CBP CIN
COUT
Figure 18. PCB Diagram
Low-Side MOSFET(s)
DThe source of low-side MOSFET(s) should be referenced to DRVGND, otherwise ANAGND is subject to
the noise of the outputs.
DDRVGND should be connected to the main ground plane close to the source of the low-side MOSFET.
DOUTGND should be placed close to the source of low side MOSFET(s).
DThe Schottky diode anode, the returns for the high frequency bypass capacitor for the MOSFETs, and the
source of the low-side MOSFET(s) traces should be routed as close together as possible.
SLVS426 − MAY 2002
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23
Connections
DConnections from the drivers to the gate of the power MOSFETs should be as short and wide as possible
to reduce stray inductance. This becomes more critical if external gate resistors are not being used. In
addition, a s for the current limit noise issue, use of a gate resistor on the high-side MOSFET(s) considerably
reduces the noise at the LL node, improving the performance of the current limit function.
DThe connection from LL to the power MOSFETs should be as short and wide as possible.
Bypass Capacitor
DThe bypass capacitor for VIN_SENSE should be placed close to the TPS5130.
DThe bulk storage capacitors across VIN should be placed close to the power MOSFETs. High-frequency
bypass capacitors should be placed in parallel with the bulk capacitors and connected close to the drain
of the high-side MOSFET(s) and to the source of the low-side MOSFET(s).
DFor aligning phase between the drain of high-side MOSFET(s) and the trip-pin, and for noise reduction, a
0.1 µF capacitor C(TRIP) should be placed in parallel with the trip resistor.
Bootstrap Capacitor
DThe bootstrap capacitor C(BS) (connected from LH to LL) should be placed close to the TPS5130.
DLH and LL should be routed close to each other to minimize noise coupling to these traces.
DLH and LL should not be routed near the control pin area (ex. INV, FB, REF, etc.).
Output Voltage
DThe output voltage sensing trace should be isolated by either ground plane.
DThe output voltage sensing trace should not be placed under the inductors on same layer.
DThe feedback components should be isolated from output components, such as, MOSFETs, inductors, and
output capacitors. Otherwise the feedback signal line is susceptible to output noise.
DThe resistors for setup output voltage should be referenced to ANAGND.
DThe INV trace should be as short as possible.
Figure 19
0
20
40
60
80
100
0.01 0.1 1 10
VIN = 8 V
VIN = 12 V
VIN = 20 V
IO − Output Current − A
Efficiency (PWM MODE) − %
EFFICIENCY (PWM MODE)
vs
OUTPUT CURRENT
SBRC CH1
External 5 V
VO1 = 3.3 V
Figure 20
0
20
40
60
80
100
0.01 0.1 1 10
VIN = 8 V
VIN = 12 V
VIN = 20 V
IO − Output Current − A
Efficiency (PWM MODE) − %
EFFICIENCY (PWM MODE)
vs
OUTPUT CURRENT
SBRC CH2
External 5 V
VO2 = 5 V
Figure 21
0
20
40
60
80
100
0.01 0.1 1 10
VIN = 8 V
VIN = 12 V
VIN = 20 V
IO − Output Current − A
Efficiency (PWM MODE) − %
EFFICIENCY (PWM MODE)
vs
OUTPUT CURRENT
SBRC CH3
External 5 V
VO3 = 1.8 V
SLVS426 − MAY 2002
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24
Figure 22
0
20
40
60
80
100
0.01 0.1 1 10
VIN = 8 V
VIN = 12 V
VIN = 20 V
IO − Output Current − A
Efficiency (AUTO SKIP MODE) − %
EFFICIENCY (AUTO SKIP MODE)
vs
OUTPUT CURRENT
SBRC CH1
External 5 V
VO1 = 3.3 V
Figure 23
0
20
40
60
80
100
0.01 0.1 1 10
IO − Output Current − A
Efficiency (AUTO SKIP MODE) − %
EFFICIENCY (AUTO SKIP MODE)
vs
OUTPUT CURRENT
SBRC CH2
External 5 V
VO2 = 5 V
VIN = 8 V
VIN = 12 V
VIN = 20 V
Figure 24
0
20
40
60
80
100
0.01 0.1 1 10
IO − Output Current − A
Efficiency (AUTO SKIP MODE) − %
EFFICIENCY (AUTO SKIP MODE)
vs
OUTPUT CURRENT
SBRC CH3
External 5 V
VO3 = 1.8 V
VIN = 8 V
VIN = 12 V
VIN = 20 V
Figure 25
3.260
3.262
3.264
3.266
3.268
3.270
5101520
VI − Input Voltage − V
− Output Voltage − V
SBRC CH1 OUTPUT LINE REGULATION
IO = 4 A
VO
Figure 26
5101520
VI − Input Voltage − V
− Output Voltage − V
SBRC CH2 OUTPUT LINE REGULATIO
N
IO = 4 A
VO
4.994
4.996
4.998
5
5.002
5.004
Figure 27
5101520
VI − Input Voltage − V
− Output Voltage − V
SBRC CH3 OUTPUT LINE REGULATION
IO = 6 A
VO
1.756
1.758
1.760
1.762
1.764
1.766
Figure 28
5101520
VI − Input Voltage − V
− Output Voltage − V
LDO OUTPUT LINE REGULATION
V(LDO_IN = VO3
IO = 3 A
VO
1.454
1.456
1.458
1.460
1.462
1.464
Figure 29
3.260
3.265
3.270
3.275
3.280
3.285
3.290
01234
IO− Output Current − A
− Output Voltage − V
SBRC CH1 OUTPUT LOAD REGULATIO
N
VO
PWM Mode
VIN = 12 V
Figure 30
01234
IO− Output Current − A
− Output Voltage − V
SBRC CH2 OUTPUT LOAD REGULATION
VO
PWM Mode
VIN = 12 V
5
5.005
5.010
5.015
5.020
5.025
5.030
5
SLVS426 − MAY 2002
www.ti.com
25
Figure 31
IO− Output Current − A
− Output Voltage − V
SBRC CH3 OUTPUT LOAD REGULATION
VO
PWM Mode
VIN = 12 V
1.760
1.765
1.770
1.775
1.780
1.785
1.790
0123456
Figure 32
IO− Output Current − A
− Output Voltage − V
LDO OUTPUT LOAD REGULATION
VO
1.450
1.455
1.460
1.465
1.470
1.475
1.480
0123
V(LDO_IN)= VO3
Figure 33
50 mV/div
IO1 = 0 A
2 A
4 A
SBRC CH1 OUTPUT VOLTAGE RIPPLE
VIN = 12 V, VO1 = 3.3 V 1 µs/div
Figure 34
50 mV/div
IO2 = 0 A
2 A
4 A
SBRC CH2 OUTPUT VOLTAGE RIPPLE
VIN = 12 V, VO2 = 5 V 1 µs/div
Figure 35
20 mV/div
IO2 = 0 A
4 A
6 A
SBRC CH3 OUTPUT VOLTAGE RIPPLE
VIN = 12 V, VO3 = 1.8 V 1 µs/div
Figure 36
10 mV/div
IO= 0.3 A
1 A
3 A
LDO OUTPUT VOLTAGE RIPPLE
VIN = 12 V, V(LDO_IN) = VO3 = 1.8 V,
IO3 = 0 A 1 µs/div
Figure 37
SBRC CH1 LOAD TRANSIENT RESPONSE
100 µs/div
VO1
20 mV/div
IO1
2 A/div
4 A
0 A
VIN = 12 V, VO1 = 3.3 V
Figure 38
SBRC CH2 LOAD TRANSIENT RESPONSE
100 µs/div
VO2
20 mV/div
IO2
2 A/div
4 A
0 A
VIN = 12 V, VO2 = 5 V
SLVS426 − MAY 2002
www.ti.com
26
Figure 39
SBRC CH3 LOAD TRANSIENT RESPONSE
100 µs/div
VO3
20 mV/div
IO3
2 A/div
6 A
0 A
VIN = 12 V, VO3 = 1.8 V
Figure 40
LDO LOAD TRANSIENT RESPONSE
100 µs/div
VO
50 mV/div
IO
1 A/div
3 A
30 mA
VIN = 12 V, V(LDO_IN) = VO3 = 1.8 V,
V(LDO) = 1.5 V
Figure 41
−40
−20
0
20
40
60
80
100 1K 10K 100K 1M −120
−60
0
60
120
180
240
Phase Margin = 53 Degrees
Phase
Gain
VIN = 12 V,
VO1 = 3.3 V,
IO1 = 4 A
f − Frequency − Hz
Gain − dB
SBRC CH1 GAIN AND PHASE
Phase − Degrees
Figure 42
−40
−20
0
20
40
60
80
100 1K 10K 100K 1M −120
−60
0
60
120
180
240
Phase Margin = 59 Degrees
Phase
Gain
VIN = 12 V,
VO2 = 5 V,
IO2 = 4 A
f − Frequency − Hz
Gain − dB
SBRC CH2 GAIN AND PHASE
Phase − Degrees
Figure 43
−40
−20
0
20
40
60
80
100 1K 10K 100K 1M −120
−60
0
60
120
180
240
Phase Margin = 37 Degrees
Phase
Gain
VIN = 12 V,
VO3 = 1.8 V,
IO3 = 6 A
f − Frequency − Hz
Gain − dB
SBRC CH3 GAIN AND PHASE
Phase − Degrees
Figure 44
−40
−20
0
20
40
60
80
100 1K 10K 100K 1M −120
−60
0
60
120
180
240
Phase Margin = 74 Degrees
Phase
Gain
VIN = 12 V,
V(LDO_IN) = VO3 =1.8 V,
I(LDO) = 3 A
f − Frequency − Hz
Gain − dB
LDO GAIN AND PHASE
Phase − Degrees
SLVS426 − MAY 2002
www.ti.com
27
MECHANICAL DATA
PT (S-PQFP-G48) PLASTIC QUAD FLATPACK
4040052/C 11/96
0,13 NOM
0,17
0,27
25
24
SQ
12
13
36
37
6,80
7,20
1
48
5,50 TYP
0,25
0,45
0,75
0,05 MIN
SQ
9,20
8,80
1,35
1,45
1,60 MAX
Gage Plane
Seating Plane
0,10
0°−ā7°
0,50 M
0,08
NOTES:A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-026
D. This may also be a thermally enhanced plastic package with leads conected to the die pads.
PACKAGING INFORMATION
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
TPS5130PT ACTIVE LQFP PT 48 250 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS5130PTG4 ACTIVE LQFP PT 48 250 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS5130PTR ACTIVE LQFP PT 48 1000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS5130PTRG4 ACTIVE LQFP PT 48 1000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
www.ti.com 18-Sep-2008
Addendum-Page 1
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0 (mm) B0 (mm) K0 (mm) P1
(mm) W
(mm) Pin1
Quadrant
TPS5130PTR LQFP PT 48 1000 330.0 16.4 9.6 9.6 1.9 12.0 16.0 Q2
PACKAGE MATERIALS INFORMATION
www.ti.com 11-Mar-2008
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TPS5130PTR LQFP PT 48 1000 346.0 346.0 33.0
PACKAGE MATERIALS INFORMATION
www.ti.com 11-Mar-2008
Pack Materials-Page 2
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