Rev. 1.2 4/19 Copyright © 2019 by Silicon Laboratories Si8900/1/2
Si8900/1/2
ISOLATED MONITORING ADC
Features
Applications
Description
The Si8900/1/2 series of isolated monitoring ADCs are useful as linear
signal galvanic isolators, level shifters, and/or ground loop eliminators in
many applications including power-delivery systems and solar inverters.
These devices integrate a 10-bit SAR ADC subsystem, supervisory state
machine and isolated UART (Si8900), I2C/SMbus port (Si8901), or SPI
Port (Si8902) in a single package. Based on Silicon Labs’ proprietary
CMOS isolation technology, ordering options include a choice of 2.5 or
5 kV isolation ratings. All products are safety certified by UL, CSA, and
VDE. The Si8900/1/2 devices offer a typical common-mode transient
immunity performance of 45 kV/µs for robust performance in noisy and
high-voltage environments. Devices in this family are available in 16-pin
SOIC wide-body packages.
Safety Approval
ADC
3 input channels
10-bit resolution
2.5 µs conversion time
Isolated serial I/O port
UART (Si8900)
I2C/SMbus (Si8901)
2 MHz SPI port (Si8902)
Transient immunity:
45 kV/µs (typ)
Temperature range:
–40 to +85 °C
>60-year life at rated working
voltage
CSA component notice 5A
approval
IEC 60950, 62368, 60601
VDE 0884-10
UL1577 recognized
Up to 5 kVrms for 1 minute
I s o l a t e d d a t a ac q u i s i t i o n
AC mains monitor
Solar inverters
Isolated temp/humidity sensing
Switch mode power systems
Telemetry
UL 1577 recognized
Up t o 5 kVrms f o r 1 m i n u t e
CSA component notice 5A
approval
IEC 60950, 62368, 60601
VDE certification conformity
VDE 0884-10
Ordering Information:
See page 27.
Pin Assignments
VDDB
NC
NC
SCL
SDA
NC
VDDB
GNDB
Si8901
VDDA
VREF
RST
AIN0
AIN1
AIN2
RSDA
GNDA
AIN2
VDDB
NC
NC
Rx
Tx
NC
VDDB
GNDB
Si8900
VDDA
VREF
AIN0
AIN1
NC
RST
GNDA
VDDB
NC
SDO
SCLK
SDI
EN
VDDB
GNDB
Si8902
VDDA
RST
NC
VREF
AIN0
AIN1
AIN2
GNDA
Si8900/1/2
Rev. 1.2 2
TABLE OF CONTENTS
Section Page
1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
2. Regulatory Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
3. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
4. ADC Data Transmission Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
4.1. Demand Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
4.2. Burst Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
4.3. Multiple Channel Burst Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
4.4. UART (Si8900) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
4.5. I2C/SMBus (Si8901) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
4.6. SPI Port (Si8902) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
4.7. Master Controller Firmware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
5. Si8900/1/2 Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
6. Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
6.1. Isolated Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
6.2. Device Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
6.3. Application Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
7. Device Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
8. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
9. Package Outline: 16-Pin Wide Body SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
10. Land Pattern: 16-Pin Wide-Body SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
11. Top Marking: 16-Pin Wide Body SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
11.1. Si8900/1/2 Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
11.2. Top Marking Explanation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
Si8900/1/2
Rev. 1.2 3
1. Electrical Specifications
Table 1. Recommended Operating Conditions
Parameter Symbol Condition Min Typ Max Unit
Input Side Supply Voltage VDDA With respect to GNDA 2.7 — 3.6 V
Input Side Supply Curr en t IDDA VDDA = 3.3 V, Si890x active — 10 13.3 mA
VDDA = 3.3 V, Si890x idle — 8.6 11.4
Output Side Supply Voltage VDDB With respect to GNDB 2.7 — 5.5 V
Output Side Supply Current IDDB VDDB = 3.3 V to 5.5 V, Si890x active — 4.4 5.8 mA
VDDB = 3.3 V to 5.5 V, Si890x idle — 3.3 3.9
Operating Temperature TA–40 — +85 °C
Table 2. Electrical Specifications
Parameter Symbol Test Condition Min Typ Max Unit
ADC
Resolution R 10 bits
Integral Nonlinea rit y INL VREF = 2 .4 V — ±0.5 ±1 LSB
Differential Nonlinearity DNL VREF = 2.4 V,
Guaranteed Monotonic —±0.5±1LSB
Offset Error OFS –2 0 +2 LSB
Full Scale Error FSE –2 0 +2 LSB
Offset Tempco TOS —45—ppm/°C
Input Voltage Range VIN 0V
REF V
Sampling Capacitance CIN —5—pF
Input MUX Impedance RMUX —5—k
Power Supply
Rejection PSRR — –70 — dB
Reference Vo ltage VREF Default VREF =V
DDA 0—V
DDA V
VREF Supply Current IVREF —12—µA
ADC Conversion Time tCONV 2.5 µs
Si8900/1/2
4 Rev. 1.2
Reset and Undervoltage Lockout
Power-on RESET
Voltage Thr eshold High VRSTH — — 1.8 V
Power-on RESET
Voltage Threshold Low VRSTL 1.7 — — V
VDDA Power-On Reset Ramp
Time tRAMP Time from VDDA = 0 V
to VDDA > VRST ——1ms
Power-On Reset
Delay Time tPOR tRAMP < 1 ms 0.3 ms
Output Side UVLO Threshold UVLO — 2.3 — V
Output side UVLO
Hysteresis H—100—mV
Digital Inputs
Logic High Level Input Voltage VIH 0.7 x VDDB ——V
Logic Low Level In put Voltage VIL ——0.6V
Logic Input Current IIN VIN = 0 V or VDD –10 +10 µA
Input Capacitance CIN —15—pF
Digital Outputs
Logic High Level Output Voltage VOH VDDB =5V,
IOH =–4mA VDDB – 0.4 4.8 — V
VDDB =3.3V,
IOH =–4mA VDDB – 0.4 3.1 — V
Logic Low Level Output Voltage VOL VDDB = 3.3 to 5 V,
IOL =4mA —0.20.4V
Digital Output Source
Impedance ROUT —50—
Serial Ports
UART Bit Rate 60 — 500 kbps
SMBus/I2C Bit Rate Slave
Address = 1111000x — — 240 kbps
SPI Port Bit Rate Mode 3: CPOL = 1,
CPHA = 1 ——2Mbps
Table 2. Electrical Specifications (Continued)
Parameter Symbol Test Condition Min Typ Max Unit
Si8900/1/2
Rev. 1.2 5
Figure 1. SPI Port Timing Characteristics
SPI Port Timing
EN Falling Edge to SCLK Rising
Edge tSE 80 — — ns
Last Clock Edge to /EN Rising tSD 80 — — ns
EN Falling to SDO Valid tSEZ — — 160 ns
SCLK High Time tCKH 200 — — ns
SCLK Low Time tCKL 200 — — ns
SDI Valid to SCLK Sample Edge tSIS 80 — — ns
SCLK Sample Edge to SDI
Change tSIH 80 — — ns
SCLK Shift Edge to SDO
Change tSOH — — 160 ns
Table 2. Electrical Specifications (Continued)
Parameter Symbol Test Condition Min Typ Max Unit
tSEZ tSOH
tSIS tSIH
tCLKH
tSDZ
SCLK
SDI
SDO
EN
tCKLtSE tSD
Si8900/1/2
6 Rev. 1.2
Figure 2. (WB SOIC-16) Thermal Derating Curve, Dependence of Safety Limiting Values
with Ambient Temperature
Table 3. Thermal Characteristics
Parameter Symbol Test Condition WB SOIC-16 Unit
IC Junction-to-Air Thermal Resistance JA 100 ºC/W
020015010050
500
400
200
100
0
Temperature (ºC)
Safety-Limiting Current (mA)
450
300
370
220
VDDA, VDDB = 2 .70 V
VDDA, VDDB = 3.6 V
VDDA, V DDB = 5.5 V
Si8900/1/2
Rev. 1.2 7
Table 4. Absolute Maximum Ratings
Parameter Symbol Min Typ Max Unit
Storage Temperature TSTG –65 — 150 °C
Ambient Temperature under Bias TA–40 — 85 °C
Input-Side Supply Voltage VDDA –0.5 — 6.0 V
Output-Side Supply Voltage VDDB –0.5 — 6.0 V
Input/Output Voltage VI–0.5 — VDD +0.5 V
Output Current Drive IO—— 10 mA
Lead Solder Temperat ur e (1 0 s) — — 260 °C
Maximum Isolation Voltage — — 6500 VRMS
*Note: Permanent device damage may occur if the absolute maximum ratings are exceeded. Functional operation should be
restricted to conditions as specified in the operational sections of this data sheet. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
Si8900/1/2
8 Rev. 1.2
2. Regulatory Information
The Si8900/1/2 family is certified by Underwriters Laboratories, CSA International, and VDE. Table 5 summarizes
the certification levels supported.
Table 5. Regulatory Information
CSA
The Si89xx is certified under CSA Component Acceptance Notice 5A. For more details, see Master Contract Number 232873.
62368-1: Up to 600 VRMS reinforced insulation working voltage; up to 1000 VRMS basic insulation working voltage.
60950-1: Up to 600 VRMS reinforced insulation working voltage; up to 1000 VRMS basic insulation working voltage.
60601-1: Up to 125 VRMS reinforced insulation working voltage; up to 380 VRMS basic insulation working voltage.
VDE
The Si89xx is certified according to VDE 0884-10. For more details, see File 5006301-4880-0001.
0884-10: Up to 1200 Vpeak for basic insulation working voltage.
60950-1: Up to 600 VRMS reinforced insulation working voltage; up to 1000 VRMS basic insulation working voltage.
UL
The Si89xx is certified under UL1577 component recognition program. For more details, see File E257455.
Rated up to 5000 VRMS isolation voltage for basic protection.
Si8900/1/2
Rev. 1.2 9
3. Functional Description
The Si8900/1/2 (Figure 3) are isolated monitoring ADCs that convert input signals into digital format and transmit
the resulting data through an on-chip isolated serial port to an external master processor (typically a
microcontroller). The Si890x access protocol is simple: The master configures and controls the start of ADC
conversion by writing a configuration register (CNFG_0) Command Byte to th e Si890x. The master th en acquires
ADC conversion data by reading the Si890x serial port. Devices in this series differ only in the ty pe of serial port.
Options include a UART with on-chip baud rate generator that operates at 500 kbps max (Si8900), an SMBus/I2C
port that operates at 240 kbps max (Si8901), and an SPI Port that operates at 2 MHz max (Si8902).
The integrated ADC subsystem consists of a three-channel analog input multiplexer (MUX) followed by a series
gain amplifier (selectable 1x or 0.5x gain) and 10-bit SAR ADC. Serial-port-accessible ADC options allow the user
to select VDDA or a different reference voltage applied to the VREF pin, set the programmable gain amplifier
(PGA), and select the ADC MUX address. The master can configure the Si890x to return ADC data on-demand
(Demand Mode) or continuously (Burst Mode). For more information, see " CNFG_0 Command Byte" on page 20.
The RST pin on the input side resets the state machine. For the Si8901, the RSDA pin connects to an external
pullup resistor to VDDA to allow operation of I2C/SMBus communication.
Si8900/1/2
10 Rev. 1.2
Figure 3. Si8900/1/2 Block Diagrams
VDDA
GNDA
AIN0
AIN1
AIN2
VREF
Si8900
ADCSubsystem
UART
PGAMUX 10‐Bit
ADC
ISOLATION
Tx
Rx
GNDB
VDDB
All
Blocks
RxData
TxData
VREF
StateMachine/
UserRegisters
VDDA
GNDA
AIN0
AIN1
AIN2
VREF
Si8902
ADCSubsystem
SPIPort
PGAMUX 10‐Bit
ADC
ISOLATION
SCK
GNDB
VDDB
All
Blocks
RxData
TxData
VREF
StateMachine/
UserRegisters
SDI
SDO
VDDA
GNDA
AIN0
AIN1
AIN2
VREF
Si8901
ADCSubsystem
SMBus/
I2C
PGAMUX 10‐Bit
ADC
ISOLATION
SDA
SCL
GNDB
VDDB
All
Blocks
RxData
TxData
VREF
StateMachine/
UserRegisters
RSDA
RST
RST
RST
EN
Si8900/1/2
Rev. 1.2 11
4. ADC Data Transmission Modes
The Si890x ADC perfo rms co nver sio ns by exer cisin g the se ria l po rt. Ea ch of the thre e cha nne ls can be in De man d
Mode (MODE=1) or Burst Mode (MODE=0). Upon power cycle or reset, all channels are initialized to Demand
Mode. The CNFG=0 command byte can be used to switch a channel between Demand a nd Burst modes. De mand
Mode ADC conversions are initiated by Demand Mode CNFG=0 commands. Once a channel is in Burst Mode,
ADC conversions are initiated by byte reads of the serial port. An advantage of Burst Mode is the conversion time
of each ADC sample is masked by the time it takes to read data bytes on the serial port. An advantage of Demand
Mode over multiple channels in Burst Mode is the master controller will dictate which ADC channel is sampled
immediately.
4.1. Demand Mode
Figure 4. ADC Demand Mode Operation
C)Si8901DemandModeADCRead
B)Si8900DemandModeADCRead
MastertoSlave
SlavetoMaster
CNFG_0
Command
Byte
tCONV
MasterwritesCNFG _0
CommandBytetoSi 8900Rx
MasterreadsupdatedCNFG _0andADC
DataFromSi8900(Txoutput)
MODE=1
ADC_H ADC_L
CNFG _0
Command
Byte
MastertoSlave
SlavetoMaster
MasterreadsSlaveAddress ,updatedCNFG_0
andADCDatafromSi 8901(SDApin)
MODE=1
ADC_H
tCONV
ADC_L
CNFG_0
Command
Byte
CNFG_0
Command
Byte
CNFG_0
Command
Byte tCONV
D)Si8902DemandModeADCRead
MasterwritesCNFG_0
CommandBytetoSi 8902SDI
MasterreadsupdatedCNFG _0and
ADCDatafromSi 8902SDO
MastertoSlave
SlavetoMaster
MODE=1
ADC_H ADC_L
CNFG_0
Command
Byte
SlaveAddress
MasterwritesSlaveAddressand
CNFG_0CommandBytetoSi 8901SDA
Themastermustwait8µS
(track‐and‐holdtime)before
readingADCdatapacket .
Slave
Address
Si8900/1/2
12 Rev. 1.2
Referring to Figure 4A, a Demand Mode ADC read is initiated when the master writes a Command Byte to the
Si8900. Upon receipt of the Command Byte, the Si8900 updates its CNFG_0 register and triggers the start of an
ADC conversion, at which time the master may immediately begin reading ADC conversion data from the Si8900
UART. The ADC conversion data packet contains an echo of the Command Byte for verification and two-bytes of
ADC conversion data. The Si8901 (Figure 4B) ADC read transaction is identical to that of the Si8900 with the
exception of the added I2C/SMBus Slave Address byte (Si8901 Slave Address is 0xF0). For the slower UART and
I2C, the required tco nv delay is con sumed b y re ading th e echo co mmand byte. Since SPI suppo rt s the fastest dat a
rate, the master controller may need to delay before reading the SPI port. If the SPI read request occurs before
valid data is available, the Si8902 will output 0xFF bytes until valid data is available. The Si8902 Demand Mode
ADC read transaction (Figure 4C) is the same as that of the Si8900, except the master must wait 8 µs after the
transmission of the Command Byte before reading the Si8902 SPI port because byte transmission time is two
times shorter versus the Si8900/01.
4.2. Burst Mode
Figure 5 shows the byte sequence for a channel operating in Burst Mode. A channel is switched from Demand
Mode to Burst Mode by writing a comma nd CNFG_0 byte with MODE=0. Placing a ch annel in Bu rst Mod e neg ates
the need to write subsequent CNFG_0 commands to initiate ADC conversions. At all serial port communication
speeds, the tconv is masked by the data rate of the data byte reads. Like the Demand Mode example, the Si8901
has a Slave Address byte prior to the CNFG_0 Command Byte. When using the Si8901, the master must write the
I2C port address prior to reading the seria l port. The Si89 02 Burst Mode (Figure 5C) is similar to that of the Si8900/
1, except the master must wait 8 µs before reading the first Burst Mode ADC data packet. After reading the first
Burst Mode ADC data packet, the master may read all ADC data packets that follow without delay.
Si8900/1/2
Rev. 1.2 13
Figure 5. ADC Burst Mode Operation
A)Si8900ADCBurstMode(MODE=0)
MastertoSlave
SlavetoMaster
CNFG_0
Command
Byte0
tCONV
MasterwritesCNFG_0
CommandBytetoSi8900Rx
MasterreadsupdatedCNFG_0CommandByteandADCdatafromSi8900Tx
MODE=0
ADC_H
Data
ADC_L
Data
ADC_H
Data
ADC_L
Data
tCONV
CNFG_0
Command
Byte
tCONV
B)Si8901ADCBurstMode(MODE=0)
MastertoSlave
SlavetoMaster
MODE=0tCONV
MasterreadsSlaveAddress,updatedCNFG_0andADCdatafromSi8901SDA
ADC_H
Data
ADC_L
Data
ADC_H
Data
ADC_L
Data
tCONV tCONV
CNFG_0
Command
Byte0
CNFG_0
Command
Byte
MasterwritesSlaveAddress&CNFG_0
CommandBytetoSi8901SDA
SlaveAddress
Read
SlaveAddrress
Write
C)Si8902ADCBurstMode(MODE=0)
MastertoSlave
SlavetoMaster
MasterwritesCNFG_0Command
BytetoSi8902SDI
CNFG_0
Command
Byte
MasterreadsupdatedCNFG_0andADCdatafromSi8902SDO
MODE=0
ADC_H
Data
ADC_L
Data
ADC_H
Data
ADC_L
Data
CNFG_0
Command
Byte
tCONV tCONV
tCONV
Si8900/1/2
14 Rev. 1.2
4.3. Multiple Channel Burst Mode
It is possible to set any channel from Demand to Burst Mode and any Bur st M ode Ch ann el back to Dem and Mod e.
However, CNFG_0 command byte can only write to one channel at a time. To operate two or more channels in
Burst Mode, first set one channel to Burst Mode. This will enable the first Burst Channel operation. The master
controller will then need to set additional channels to Burst Mode by writing another CNFG_0 command byte.
For the Si8901, communication is half duplex. Therefore, the data reads of a previously set burst channel must be
interrupte d by writing a new CNFG_0 command to set the additional channel to Burst Mode.
For the Si8900 and Si8902, communication is full duplex, and a new CFNG_0 command byte can be written at the
same time as reading data from a previously set burst channel. Depending on where the new CNFG_0 command
is received during the burst read, the Si8902 may output data with MX0 = 1 and MX1 = 1 (see “5. Si8900/1/2
Configuration Registers” ), which does not point to a valid channel. Ignore that ADC_H byte and the following
ADC_L byte. This is a temporary artifact of having restarted the burst sequence with an additional burst-enabled
channel. See "4.7. Master Controller Firmware" on page 19.
To parse the data stream for multiple burst mode channels, the master controller must analyze the MX0 and MX1
bits of the ADC_H byte. For each ADC_H byte re ceived, the next ADC_L byt e received is the second part of that
channel's data. The Si890x will cycle through all Burst Mode channels sequentially. For example, if channels 0 and
1 are in Burst Mode, the data read back will have this order: ADC_H (MX1=0, MX0=0), ADC_L, ADC_H (MX1=0,
MX0=1), ADC_L, ADC_H (MX1=0, MX0=0), ADC_L, and so on.
Si8900/1/2
Rev. 1.2 15
4.4. UART (Si8900)
The UART is a two-wire interface (Tx, Rx) and operates as an asynchronous, full-duplex serial port with internal
auto baud rate generator that measures the period of incoming data stream and automatically adjusts the internal
baud rate generator to match. The auto baud rate detection and matching optimizes UART timing for minimum bit
error rate. For more information, see “AN635: Si8900 Automatic Baud Rate Detection”.
There are a total of 10 bits per data byte: One start bit, eight data bits (LSB first), and one stop bit with data
transmitted LSB first as shown in Figure 6. Figure 7A and Figure 7B show master/Si8900 ADC read transactions
for Demand Mode and Burst Mode, respectively.
Figure 6. UART Data Byte
Figure 7. Si8900 ADC Read Operation
D7
D6D5
D4
D3
D2
D1D0
StartBit
MARK
SPACE
BITTIMES
BITSAMPLING
STOPBIT
MastertoSlave
SlavetoMaster
A)Si8900DemandModeADCRead
D0D1D2 D3D4 D5 D6D7 D0D1D2D3D4D5D6D7
STOP
START
START
STO P
D0D1 D2 D3D4 D5 D6D7
STOP
START
S
START
P
CNFG_0WriteCommandByte
B)Si8900BurstModeADCRead
START
STOP
D0D1D2D3 D4D5D6 D7
CNFG_0ReadData
STOP
START STOP
START
PeriodicADCData
CNF G _0ReadData
ADCData
D0 D1D2D3D4D5 D6D7 D0 D1 D2D3D4D5D6D7 D0 D1 D2D3D4D5D6 D7 D0D1D2D3 D4D5D6D7
SP
D0D1D2 D3D4 D5 D6 D7
CNFG_0WriteCommandBy te
STOP
START
STOP
START
STOP
START
D0D1D2D3D4 D5D6 D7
‐
MX1
MODE=1
MX0
PGA
11
VREF
‐
MX1
MODE=0
MX0
PGA
11
VREF
S
S P P S SP
VREF
MX0
PGA
MODE=0
MX1
‐11
D9
0 1
MX0
MX1
D8
D7
D6
D1
D0
00
D5
D4
D3
D2
P S
D9
0 1
MX0
MX1
D8
D7
D6
S P SS P S
D9
0 1
MX0
MX1
D8
D7
D6
D1
D0
00
D5
D4
D3
D2
MX0
PGA
MODE=1
MX1
11
VREF
‐
STO P
START
SP
D1
D0
00
D5
D4
D3
D2
Si8900/1/2
16 Rev. 1.2
4.5. I2C/SMBus (Si8901)
The I2C/SMBus serial port is a two-wire serial bus where data line SDA is bidirectional and clock line SCL is
unidirectional. Reads and writes to this interface by the master are byte-oriented, with the I2C/SMBus master
controlling the serial data rates up to 240 kbps. The SDA and SCL lines must be pulled high through pull-up
resistors of 5 k or less. An Si8901 ADC read transaction beg ins with a START condition (“S” or Repe ated STAR T
condition “SR”), which is defined as a high-to-low transition on SDA while SCL is high (Figure 8). The master
terminates a tran smissio n with a STOP condition (P), defined as a low-to-high transition on SDA while SCL is high.
The data on SDA must remain sta ble during the high peri od of the SCL clock pulse because such changes in either
line will be interpreted as a control command (e.g., S, P SR). SDA and SCL idle in the high state when the bus is
not busy. Acknowledge bits (Figure 9) provide detection of successful data transfers, whereas unsuccessful
transfers con clude wit h a no t-ackn owledge b it (NACK). Both the master and the Si8901 generate ACK and NACK
bits. An ACK bit is generated when the receiving device pulls SDA low before the rising edge of the acknowledged
related (ninth) SCL pulse and maintains it low during the high period of the clock pulse. A NACK bit is generated
when the receiver allows SDA to be pulled high before the rising edge of the acknowledged related SCL pulse and
maintains it high during the high period of the clock pulse. An unsuccessful data transfer occurs if a receiving
device is busy or if a system fault has occurred. In the event of an unsuccessful data transfer, the bus master
attempts communication at a later time. Figure 10A shows the I2C Slave Address Byte and CNFG_0 byte for the
Si8901. Figure 10B and Figure 10C show master/Si8901 ADC read transactions for Demand Mode and Burst
Mode, respectively.
Figure 8. Start and Stop Conditions
Figure 9. Acknowledge Cycle
SDA
SCL
SNotAcknowledge(NACK)
Acknowledge(ACK)
12 9
Si8900/1/2
Rev. 1.2 17
Figure 10. Si8901 ADC Read Operation
MastertoSlave
SlavetoMaster
A)Si8901CNFG_0Write
B)Si8901DemandModeADCRead
Ss6 s5 s4 s3 s2 s1 A1A
START
ACK
ACK
Si8901CNFG_0WriteData
Write
MX0
PGA
P
VREF
STOP
R/W=0
D7D6D5 D4 D3 D2D1D0
MX1
MODE
1
D7D6D5D4D3 D2 D1 D0
ACK
ADCData
STOP
ACK
D7 D6D5D4D3D2D1 D0 D7 D6 D5D4D3D2D1 D0
C)Si8901BurstModeADCRead
Si8901SlaveAddress
s0
ACK
Si8901CNFG_0ReadData
D7 D6 D5 D4 D3D2D1D0
Ss6 s5 s4 s3 s2 s1 A A
START
ACK
ACK
Si8901CNFG_0WriteData
Write
P
STOP
R/W=0
D7 D6 D5 D4 D3D2D1D0
D7 D6 D5 D4D3D2D1D0
Si8901Write
SlaveAddress
s0
START
ACK
ACK
Si8901CNFG_0WriteData
Write
STOP
D7D6 D5 D4 D3D2D1D0
D7 D6 D5 D4D3D2D1D0
Si8901SlaveAddress
STOP
Si8901SlaveAddress=0xF0
START
Read
D7D6D5D4D3 D2 D1 D0
Si8901Read
SlaveAddress
START
ACK
ACK
D7D6 D5D4D3D2D1D0 D7D6D5 D4D3D2D1D0
ACK
Si8901CNFG_0
ReadData
D7D6D5D4D3D2D1D0
Period icADCData
P
START
Read
D7D6D5 D4 D3D2D1D0
Si8901Read
SlaveAddress
‐
1
MX0
PGA
VREF
MX1
MODE= 1
1‐
A A
0 0 0 P
MX1
MX0
D9
D8
A
D7
D6
D5
D4
D3
D2
D1
D0
A 1
MX0
PGA
VREF
MX1
MO D E= 1
1S s6 s5 s4 s3 s2 s1
R/W=1
s0 ‐1
1A
MX0
PGA
VREF
MX1
MODE=0
1A
Ss6 s5 s4 s3 s2 s1
R/W=1
s0 ‐0 0 0
MX1
MX0
D9
D8
A
D7
D6
D5
D4
D3
D2
D1
D0
1A
Ss6 s5 s4 s3 s2 s1 A A P
R/W=0
s0 1
MX0
PGA
VREF
MX1
MODE=0
1‐
ACK
S
START
A
ACK
S
Si8900/1/2
18 Rev. 1.2
4.6. SPI Port (Si8902)
Figure 11. Master Connection to Si8902
Figure 12. Si8902 Data/Clock Relationship
The Serial Peripher al Interface (SPI po rt) is a slave mode, full- duplex, synchron ous, 4-wire ser ial bus that connect s
to the master as shown in Figure 11. The master's clock and data timing must match the Si8902 timing shown
Figure 12 (for more information about clock and data timing, please see the “SPI Port” section of Table 2 on
page 5).
As shown in Figure 13, the Si8902 will update output dat a on SDO with falling SCLK edge and sa mple dat a on SDI
with rising SCLK edge. For idle condition between bytes, EN and SCLK should be held high by the master
controller. Also, during ADC_H and ADC_L byte reads, the master controller must hold SDI high. The master
transmits data from its master-out/slave-in terminal (MOSI) to the Si8902 serial read/write input terminal (SDI). The
Si8902 transmits data to the master from its serial data-out terminal (SDO) to the master-in/slave-out terminal
(MISO), and data transfer ends when the master returns EN to the high state. Figure 13A shows the Si8902
CNFG_0 Command Byte format, while Figures 13B and 13C show Si8902 Demand Mode and Burst Mode ADC
reads.
The Si8902 SDO pin will either drive low or drive high. It does not go into Hi-Z when EN is deasserted. Therefore,
a system with multiple SPI slaves should use separate MISO signals to avoid SPI bus contentions.
MASTER Si8902
MOSI
MISO
SCLK
SDI
SDO
SCLK
EN
76543210
SPIShiftRegister
ReceiveBuffer
BaudRate
Generator
ENorPx.y
76543210
SPIShiftRegister
ReceiveBuffer
MSB Bit6Bit5Bit4Bit3Bit2Bit1Bit0
MSB Bit6Bit5Bit4Bit3Bit2Bit1Bit0
SCLK
SDI
SDO
EN
Si8900/1/2
Rev. 1.2 19
Figure 13. Si8902 ADC Read Operation
4.7. Master Controller Firmware
The user's master contr oller must in clude firmware to m anage th e Si890x Dema nd and Bur st operating modes and
serial port control. For more information on master controller firmware, see “AN637: Si890x Master Controller
Recommendations”, available for download at www.silabs.com/isolation.
MastertoSlave
SlavetoMaster
B)Si8902ADCDemandMode
DemandChannelADCSample
A) Si8902CNFG_0CommandByte
C)Si8902ADCBurstMode
CNFG_0ReadByte
MX0
PGA
VREF
D7D6D5D4D3D2D1D0
MX1
MODE
11 ‐
1
MX1
MX0
D9
D8
D7
D6
MX0
PGA
VREF
MX1
MODE=1
1‐1 0 0
D5
D4
D3
D2
D1
D0
CNFG_0WriteByte
D7D0
MX0
PGA
VREF
MX1
MODE=1
1‐1
0
D7D0 D7D0 D7D0
CNFG_0WriteByte
D7D0
MX0
PGA
VREF
MX1
MODE=0
1‐18µ S
Delay
FisrtBurstChannelADCSampleCNFG_0ReadByte
1
MX1
MX0
D9
D8
D7
D6
MX0
PGA
VREF
MX1
MODE=0
1‐1 0 0
D5
D4
D3
D2
D1
D0
0
NextBurstChannelADCSample
1
MX1
MX0
D9
D8
D7
D6
0 0
D5
D4
D3
D2
D1
D0
0
OptionalCNFG_0WriteBytetoEnable
AnotherBurstChannelortoPlaceanExisting
BurstChannelBacktoDemandMode
D7D0
MX0
PGA
VREF
MX1
MODE=0
1‐1
SDIHighduringIdle SDIHighduringIdle
PeriodicADCData
8µS
Delay
CNFG_0WriteByte
D7D0
MX0
PGA
VREF
MX1
MODE=1
1‐18µS
Delay
AnewCNFG _0WriteByte
and8µSDelayarerequired
tore‐sampleaDemand
ModeChannel
MX0
VREF
MX1
11
D7D0 D7D0 D7D0 D7D0 D7D0
SDIHighduringRead
D7
Si8900/1/2
20 Rev. 1.2
5. Si8900/1/2 Configuration Registers
CNFG_0 Command Byte
BitD7D6D5D4D3D2D1D0
Name 1 1 MX1 MX0 VREF — MODE PGA
Type R/W R/W R/W R/W R/W R/W R/W R/W
Bit Name Function
7:6 1,1 Internal use. These bits are always set to 1.
5:4 MX1, MX0 ADC MUX Address.
ADC MUX address selection is controlled by MX1, MX0 as follows:
3VREFADC Voltage Reference Source
VDD is selected as the refere nce vo ltage when this bit is set to 1. An ext er nally co n-
nected voltage reference generator is selected when this bit is reset to 0.
2 — Not used.
1MODEADC Read Mode
ADC Demand Mode read is enabled when this bit is 1, and Burst Mode is enabled
when this bit is 0. For more information on Demand and Burst mode operation,
please see "4. ADC Data Transmission Modes" on page 11.
0PGAPGA Gain Set
PGA gain is 1 when this bit is set to 1. PGA gain is 0.5 when this bit is reset to 0.
ADC_H Byte
BitD7D6D5D4D3D2D1D0
Name 1 0 MX1 MX0 D9 D8 D7 D6
Type RRRRRRRR
MX1 MX0 Selected ADC MUX Channel
1 1 Not Used
10 AIN2
01 AIN1
00 AIN0
Si8900/1/2
Rev. 1.2 21
Bit Name Function
7:6 1,0 Internal use. These bits are always set to 1,0.
5:4 MX1, MX0 ADC MUX Address
ADC input MUX address for the converted data in ADC_H, ADC_L.
3:0 D9: D6 ADC conversion data bits D9:D6
Most significant 4 bits of ADC conversio n da ta.
ADC_L Byte
BitD7D6D5D4D3D2D1D0
Name 0 D5D4D3D2D1D0 0
Type RRRRRRRR
Bit Name Function
7 0 Internal use. This bit is always set to 0.
6:1 D5:D0 ADC Conversion Data Bits D5:D0
Least significant 6 bits of ADC conversion data.
0 0 Internal use. This bit is always set to 0.
Si8900/1/2
22 Rev. 1.2
6. Applications
6.1. Isolated Outputs
The Si890x serial outputs are internally isolated from the device input side. To ensure safety in the end-user
application, high vo lt age cir cuit s ( i.e., circui t s with >30 VAC) must be physically sep arated from the safe ty extra-low
voltage circuits (i.e., circuits with <30 VAC) by a certain distance (creepage/clearance). If a component straddles
this isolation barrier, it must meet those creepage/clearance requirements and also provide a sufficiently large
high-volt age breakdown protection rating (commonly referr ed to as working volt age pr otection). Tables published in
the component standards (UL1577, VDE 0884-10, CSA 5A) are readily accepted by certification bodies to provide
proof for end-system specifications requirements. Refer to the end-system specification (62368-1, 60950-1, 60601-
1, etc.) require men ts before starting any circ uit design t hat uses galvanic isolation. The nominal output impedance
of a digital output is approximately 50 40%, which is a combination of the on-chip series termination resistor
and channel resist ance of the output driver FET. When driving high-impeda nce term inated PCB traces, ou tput s can
be source terminated to minimize reflection.
The Si890x supply inputs must be bypassed with a parallel combination of 10 µF and 0.1 µF capacitors at VDDA
and VDDB as shown in Figure 14A. The 0.1 µF capacitors should be placed as close to the package as possible.
The Si890x uses the VDDA su pply as its internal ADC voltage refe renc e by defa ult. A precision ex ter nal refer enc e
can be installed as shown in Figure 14A and must be bypassed with a parallel combination of 0.1 µF and 4.7 µF
capacitors. (Note that the CNFG_0 VREF bit must be set to 0 when using the external reference.) The Si890x has
an on-chip power-on-reset circuit (POR) that maintains the device in its reset state until VDDA has stabilized. A
2k
pull-up resistor and 10 nF capacitor on RST is strongly recommended to reduce the possibility of external
noise coupling into the reset input. The capacitor slows the rise of voltage on RST during power up. The delay
ensures a state machine reset s on power up. A st ate machin e reset with power on using the RC on RST will suf fice
for most applications. For the master controller to have access to this pin, a single channel Si8610 digital isolator
can be placed in parallel with the Si890x and connected to the RST input. The Si8901 requires a 5 k pull-up
resistor to VDDA on the RSDA input.
Figure 14. Si890x Installation
Figure 14B shows the required PCB ground configuration, where an 8 mm (min) “keep-out area” is provided to
ensure adequate creepage and clearance distances between the two grounds. PCB metal traces cannot be
present or cross through the ke ep-out area on the PCB top or bottom layer.
Si890x
GNDA GNDB
Si890x
VREF
RST
RSDA
VDDA
GNDA
VDDB
GNDB
2.7Vto3.6V2.7Vto5.5V
8mm
(min) GNDBGNDA
Keep‐outArea
(Nometalinthisarea)
BoardEdge
BoardEdge
AB
OptionalExternalVREF
10µF
VDDA
0.1µF4.7µF
2KO5KO
VDDA
10nF
0.1µF
VREF
Required
forSi8901
0.1µF 10µF
Si8900/1/2
Rev. 1.2 23
6.2. Device Reset
During power-up, the Si890x is held in the reset state by the internal power-on reset signal (POR) until VDDA
settles above VRST. When this condition is met, a delay is initiated that maintains the Si890x in the reset state for
time period tPOR, after which the reset signal is driven high allowing the Si890x to start-up. Note the maximum
allowable VDD ramp time (i.e. time from 0 V to VDDA settled above VRST) is 1 ms. Slower ramp times may cause
the Si890x to be released from reset before VDDA reaches the VRST level.
Figure 15 shows typical VDDA monitor reset timing where the internal reset is driven low (Si890x in reset) when
VDDA falls below VRST (e.g., during a power down or VDDA brownout). The internal reset is released to its high
state when VDDA again settles above VRST. External circuitry can also be used to force a reset event by driving
the external RST input low. A 2 k pull-up resistor on RST is recommended to avoid erroneous reset events from
external noise coupling to the RST input.
Figure 15. Si890x Power-on and Monitor Reset
VDDA
Monitor
Reset
Power‐OnReset
tPOR
VRSTH
V
DDA
VDDA(min)
VDDA
VRSTL
Internal
RESET
Si8900/1/2
24 Rev. 1.2
6.3. Application Example
Figure 16 shows the Si8900 operating as a single-phase ac line voltage and current monitor. The VDDA dc bias
circuit uses a low-cost 3.3 V linear regulator referenced to the neutral (white wire). The ac current is measured on
ADC input AIN0. The ac line voltage is scaled by resistors R17 and R18 and level-shifted by the 1.5 V VREF. AC
line current is measured using differential amplifier U1 connected across shunt resistor R1. Data is transferred to
the external controller or processor via the isolated UART.
Figure 16. AC Line Monitor Application Example
U1
LowCost
DualOpAmp
R1
C1
U2
3.3V
LDO
C4 C5
Si8900
AIN0
VDDA
GNDA
AIN1
WHITE
BLACK
D1
TX
RX
VDDB
GNDB
External
MasterController
OutputSide
BiasSupply
C2
1.5V
R2 R3
R6
R5
R7
R8
R9
1.5V
R11
C3
1.5V
R12
R13 R14
R15
R4
Single‐Phase
ACLine
R10
R17
R18
Si8900/1/2
Rev. 1.2 25
7. Device Pin Assignments
Figure 17. Si8900/1/2 Pinout (SOIC-16 WB)
Table 6. Si8900/1/2 Pin Assignments
Pin Si8900
Pin Si8901
Pin Si8902
Pin Description
1 VDDA Input side VDD bias voltage (typically 3.3 V)
2VREFRST
Si8900/1: External voltage reference input.
Si8902: Active low reset.
3 AI N0 AIN0 NC Si8900: ADC analog inpu t ch an ne l 0.
Si8901: ADC analog inpu t ch anne l 0.
Si8902: No connection
4 AIN1 AIN1 VREF Si8900: ADC analog input channel 1.
Si8901: ADC analog inpu t ch anne l 1.
Si8902: External VREF in.
5 AIN2 AIN2 AIN0 Si8900: ADC analog input channel 2.
Si8901: ADC analog inpu t ch anne l 2.
Si8902: ADC analog inpu t ch anne l 0.
6NCRST
AIN1 Si8900: No Connection.
Si8901: Active low reset.
Si8902: ADC analog inpu t ch anne l 1.
7RST
RSDA AIN2 Si8900: Active low reset.
Si8901: RSDA bias resistor (typically 5 k).
Si8902: ADC analog inpu t ch anne l 2.
8 GNDA Input side ground
9 GNDB Output side ground
10 VDDB Output side VDD bias voltage (2.7 V to 5.5 V )
11 NC EN Si8900/1: No connection. Si8902: SPI Port Enable.
12 Tx SDA SDI Si8900: UART unidirectional transmit output.
Si8901: I2C bidirectional data input/output.
Si8902: SPI port serial data in.
AIN2
VDDB
NC
NC
Rx
Tx
NC
VDDB
GNDB
Si8900
VDDA
VREF
AIN0
AIN1
NC
RST
GNDA
VDDB
NC
NC
SCL
SDA
NC
VDDB
GNDB
Si8901
VDDA
VREF
RST
AIN0
AIN1
AIN2
RSDA
GNDA
VDDB
NC
SDO
SCLK
SDI
EN
VDDB
GNDB
Si8902
VDDA
RST
NC
VREF
AIN0
AIN1
AIN2
GNDA
Si8900/1/2
26 Rev. 1.2
13 Rx SCL SCLK Si8900: UART unidirectional receive inpu t.
Si8901: I2C port unidirectional serial clock input.
Si8902: SPI port unidirectional serial clock input.
14 NC SDO Si8900/1: No connection.
Si8902: SPI port Serial data out (SDO)
15 NC No connection
16 VDDB Si8900/1/2: Output side VDD bias voltage (2.7 V to 5.5 V).
Table 6. Si8900/1/2 Pin Assignments (Continued)
Pin Si8900
Pin Si8901
Pin Si8902
Pin Description
Si8900/1/2
Rev. 1.2 27
8. Ordering Guide
Table 7. Product Ordering Information1,2
Part Number (OPN) Serial Port Package Isolation Rating Temp Range
Si8900B-A01-GS UART WB SOIC 2.5 kV –40 to +85 °C
Si8900D-A01-GS UART WB SOIC 5.0 kV –40 to +85 °C
Si8901B-A02-GS I2C/SMBus WB SOIC 2.5 kV –40 to +85 °C
Si8901D-A02-GS I2C/SMBus WB SOIC 5.0 kV –40 to +85 °C
Si8902B-A01-GS SPI Port WB SOIC 2.5 kV –40 to +85 °C
Si8902D-A01-GS SPI Port WB SOIC 5.0 kV –40 to +85 °C
Notes:
1. Add an “R” suffix to the part number to specify the tape and reel option. Example: “Si8900AB-A-ISR”.
2. All packages are RoHS-compliant.
Si8900/1/2
28 Rev. 1.2
9. Package Outline: 16-Pin Wide Body SOIC
Figure 18 illustrates the package details for the Si8900/1/2 Digital Isolator. Table 8 lists the values for the
dimensions shown in the illustration.
Figure 18. 16-Pin Wide Body SOIC
Si8900/1/2
29 Rev. 1.2
Table 8. Package Diagram Dimensions
Symbol
Millimeters
Min Max
A — 2.65
A1 0.10 0.30
A2 2.05 —
b 0.31 0.51
c 0.20 0.33
D 10.30 BSC
E 10.30 BSC
E1 7.50 BSC
e1.27 BSC
L 0.40 1.27
h 0.25 0.75
θ0° 8°
aaa — 0.10
bbb — 0.33
ccc — 0.10
ddd — 0.25
eee — 0.10
fff — 0.20
Notes:
1. All dimensions shown are in millimeters (mm) unless otherwise
noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. This drawing conforms to JEDEC Outline MS-013, Variation AA.
4. Recommended reflow profile per JEDEC J-STD-020C specification
for small body, lead-free components.
Si8900/1/2
30 Rev. 1.2
10. Land Pattern: 16-Pin Wide-Body SOIC
Figure 19 illustrates the rec ommended land pattern details for the Si8900/1/2 in a 16-pin wide-body SOIC. Table 9
lists the values for the dimensions shown in the illustration.
Figure 19. 16-Pin SOIC Land Pattern
Table 9. 16-Pin Wide Body SOIC Land Pattern Dimensions
Dimension Feature (mm)
C1 Pad Column Spacing 9.40
E Pad Row Pitch 1.27
X1 Pad Width 0.60
Y1 Pad Length 1.90
Notes:
1. This Land Pattern Design is based on IPC-7351 pattern SOIC127P1032X265-16AN
for Density Level B (Median Land Protrusion).
2. All feature sizes shown are at Maximum Material Condition (MMC) and a card
fabrication tolerance of 0.05 mm is assumed.
Si8900/1/2
Rev. 1.2 31
11. Top Marking: 16-Pin Wide Body SOIC
11.1. Si8900/1/2 Top Marking
11.2. Top Marking Explanation
Line 1 Marking:
Base Part Number
Ordering Options
(See Ordering Gui de fo r more
information).
Si890 = Isolator product series
X = Serial Port
0=UART
1=I
2C
2 = SPI
Y = Insulation rating
B = 2.5 kV; D = 5.0 kV
Line 2 Marking:
YY = Year
WW = Workweek Assigned by assembly subcontractor. Corresponds to the
year and workweek of the mold date.
RTTTTT = Mfg Code Manufacturing code fro m assembly house
“R” indicates revision
Line 3 Marking:
Circle = 1.7 mm Diameter
(Center-Justified) “e4” Pb-Free Symbol
Country of Origin ISO Code
Abbreviation TW = Taiwan
Si890XY
YYWWRTTTTT
TW
e4
Si8900/1/2
32 Rev. 1.2
DOCUMENT CHANGE LIST
Revision 0.5 to Revision 1.0
No changes.
Revision 1.0 to Revision 1.1
Removed “pending” throughout.
Changed AN638 reference to AN637.
Updated "11. Top Marking: 16-Pin Wide Body SOIC" on page 31.
Revision 1.1 to Revision 1.2
April, 2019
Table 1, Changed GND1 to GNDA and GND2 to GNDB.
Table 2, tconv changed from 2 µs to 2.5 µs.
Table 2, Digital Outputs, changed min for Voh with VDDB=3.3 V to 3.1 V.
Table 2, Digital Outputs, added typical for Voh with VDDB=3.3 V to 3.1 V.
Table 2, Digital Output s, cha nged specifica t ion name Dig ital Output Series Impedance to Digital Output Source
Resistance.
Table 2, Digital Outputs, changed typical source resistance from 85 to 50 typical.
Table 2, Serial Ports, changed maximum UART Bit Rate from 234 kbps to 500 kbps.
Table 2, Serial Ports, changed specification name SPI port to SPI Bit Rate.
Table 2, Serial Ports, added test condition for SPI Port, Mode 3: CPOL=1, CPHA=1.
Table 2, Serial Ports, changed maximum SPI Bit Rate from 2 mbps to 2.5 mbps.
Table 3, Removed data from NB SOIC 16.
Figure 2, Changed VDD1 and VDD2 to VDDA and VDDB.
Table 5, Updated ce rtification nomenclature for CSA from 61010-1 to 62368-1, up to 1000 VRMS basic
insulation working voltage.
Table 5, Updated certification nomenclature for VDE from IEC 60747-5-2 to VDE 0884- 10.
Removed Figure 3, NB SOIC 16 derating curve.
Function Description, removed ADC option of internal voltage reference.
Function Description, described RST and RSDA pin functions.
Figure 4, Updated Si8902 GND pin names.
ADC Data Transmission Modes, Updated description of Demand and Burst Modes.
Figure 5, Showed tconv starting at the end of CNFG_0 byte for Si8901 Demand Mode.
UART (Si8900), Changed name of AN635 from AC Line Monitoring to Si8900 Automatic Band Rate Detection.
Figure 8A, Showed proper span of ADC data.
Figure 11B and 11C, Added ACK bit between slave address and echo CNFG_0 byte.
Figure 12, Remove d EN signal from controlling SDO driver circuit.
SPI Port (Si8902), Add e d requ ire m en t of SDI be in g he ld hig h duri ng byte rea d s.
SPI Port (Si8902), SDO does not enter Hi-Z state with EN function.
Si8900/1/2 Configuration Registers, rem oved default setting from registers.
Applications, Isolated Outputs, recommend a 10 nF capacitor from RST to GNDA for reliable reset on power
cycle.
Table 7, updated OPN for Si8901 from re vision A01 to A02.
Table 7, removed Note 3.
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