RT8271
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DS8271-02 March 2011 www.richtek.com
Ordering Information
Pin Configurations
(TOP VIEW)
MSOP-10 (Exposed Pad)
Note :
Richtek products are :
` RoHS compliant and compatible with the current require-
ments of IPC/JEDEC J-STD-020.
` Suitable for use in SnPb or Pb-free soldering processes.
2A, 24V, 1.2MHz Step-Down Converter
Applications
zDistributive Power Systems
zBattery Charger
zDSL Modems
zPre-regulator for Linear Regulators
Marking Information
For marking information, contact our sales representative
directly or through a Richtek distributor located in your
area, otherwise visit our website for detail.
General Description
The RT8271 is a high voltage buck converter that can
support the input voltage range from 4.75V to 24V a nd the
output current ca n be up to 2A. Current Mode operation
provides fast transient response and eases loop
stabilization. The RT8271 also provides adjustable soft-
start to be a flexible solution for customers.
The chip provides protection functions such a s cycle-by-
cycle current limiting and thermal shutdown protection.
In shutdown mode, the regulator draws 22μA of supply
current. The RT8271 is available in the SOP-8 and
MSOP-10 (Exposed Pad) surface mount package.
Features
zz
zz
zWide Operating Input Range : 4.75V to 24V
zz
zz
zAdjustable Output Voltage Range : 0.92V to 16V
zz
zz
zOutput Current up to 2A
zz
zz
z22μμ
μμ
μA Low Shutdown Current
zz
zz
zPower MOSFET : 0.18ΩΩ
ΩΩ
Ω
zz
zz
zHigh Efficiency up to 92%
zz
zz
z1.2MHz Fixed Switching Frequency
zz
zz
zSta ble with Low ESR Output Ceramic Capacitors
zz
zz
zProgrammable Soft-Start
zz
zz
zThermal Shutdown Protection
zz
zz
zCycle-By-Cycle Over Current Protection
zz
zz
zRoHS Compliant and Halogen Free
SS
FB
NC
VIN
NC EN
COMP
SW GND
BOOT
56
7
8
4
3
210
9
GND
11
BOOT
VIN
SW
GND
SS
EN
FB
COMP
2
3
45
6
7
8
SOP-8
Package T y pe
S : SOP-8
FP : MSOP-10 (Exposed Pad)
RT8271
Lead Plating System
G : Green (Halogen Free and Pb Free)
RT8271
2DS8271-02 March 2011www.richtek.com
VOUT (V) R1 (kΩ) R2 (kΩ) RC (kΩ) CC (nF) L (μH) COUT (μF)
15 154 10 68 0.56 22 22
10 100 10 49.9 0.82 15 22
8 76.8 10 49.9 1 10 22
5 44.2 10 33 1.2 6.8 22
3.3 25.5 10 22 1.5 4.7 22
2.5 16.9 10 15 1.5 4.7 22
1.8 9.53 10 12 1.5 2.2 22
1.2 3 10 12 1.5 2.2 22
Table 1. Recommended Component Selection
Function Block Diagram
Typical Application Circuit
VIN
EN
GND
BOOT
FB
SW
L1
4.7µH
CBOOT
10nF
COUT
22µF/6.3V
R1
16.9k
R2
10k
VOUT
2.5V
CIN
10µF/25V
Chip Enable
VIN
4.75V to 24V RT8271
D1
B230A
SS
CSS
10nF COMP
CC
1.5nF RC
15k
CP
NC
VA
+
-
+
-
+
-
UV
Comparator
Oscillator
1.2MHz/440kHz
Foldback
Control
0.5V
Internal
Regulator
+
-
1V
1µA
Shutdown
Comparator
Current Sense
Amplifier
BOOT
VIN
GND
SW
FB
EN
COMP
3V
10k VA VCC
VCC Slope Comp
Current
Comparator
SS
10µA
VCC
+
-EA
0.92V
Gm = 920µA/V
+
Logic
RT8271
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DS8271-02 March 2011 www.richtek.com
Functional Pin Description
Pin No.
PMSOP-10 SOP-8
Pin Name Pin Function
1, 3 -- NC No In terna l Con nection.
2 1 BOOT
High Side Gate Drive Boost Input. BOOT supplies the drive for the
high side N-MOSFET switch. Connect a 10nF or greater capacitor
from SW to BOOT to power the high side switch.
4 2 VIN
Power Input. VIN supplies the power to the IC, as well as the
step-down converter switches. Bypass VIN to GND with a suitable
la rge capacitor to elim inate noise on the input to the IC.
5 3 SW
Power Switching Output. SW is the switching node that supplies
power to the output. Connect the output LC filter from SW to the
output load. Note that a capacitor is required from SW to BOOT to
power the high side switch.
6,
11 (Exposed Pad ) 4 GND Ground. The exposed pad must be soldered to a large PCB and
connected to GND for maximum power dissipation.
7 5 FB
Feedback Input. FB senses the output voltage to regulate said
voltage. The feedback refer ence voltage is 0.92V typica lly.
8 6 COMP
Compensation Node. COMP is used to compensate the regulation
control loop. Connect a series RC network from COMP to GND to
compensate the regulation control loop. In some cases, an additional
capacitor fro m COMP to GND is r equ ired.
9 7 EN
Enable Input. EN is a digital input that turns the regulator on or off.
Drive EN higher than 1.4V to turn on the regulator, lower than 0.4V to
turn it off. If the EN pin is open, it will be pulled to high by internal
circuit.
10 8 SS
Soft-Start Control Input. SS c ontrol s the soft start period. Connect a
capacitor from SS to GND to set the soft-start period. A 10nF
capacitor sets the soft-start period to 1ms.
RT8271
4DS8271-02 March 2011www.richtek.com
Electrical Characteristics
Parameter Symbol Test Conditions Min Typ Max Unit
Feedback Reference Voltage VFB 4.75V ≤ VIN ≤ 24V 0.902 0.92 0.938 V
High Side Switch-On Resistance RDS(ON)1 -- 0.18 -- Ω
Low Side Switch- On Resistance RDS(ON)2 -- 10 -- Ω
Switch Leakage VEN = 0 V, VSW = 0V -- -- 10 μA
Cu rrent Limit ILIM Duty = 75%; VBOOT−SW = 4.8V -- 3 -- A
Curren t Sen se Transconductance GCS Output Current to VCOMP -- 2.5 -- A/V
Error Amplifier Tanscond uctance Gm ΔIC = ±10μA 620 920 1220 μA/V
Oscillator Fr equency fSW -- 1.2 -- MHz
S hor t Cir cuit Oscillation Fr eque ncy VFB = 0V -- 440 -- kHz
Maximum Duty Cycle DMAX V
FB = 0.8V -- 75 -- %
Minimu m On-T i me tON -- 90 -- ns
Under Voltage Lockout Threshold
Rising 3.8 4.2 4.5 V
Under Voltage Lockout Threshold
Hysteresis -- 250 -- mV
(VIN = 12V, TA = 25°C unless otherwise specified)
Absolute Maximum Ratings (Note 1)
zSupply Voltage, VIN -----------------------------------------------------------------------------------------−0.3V to 26V
zSwitching Voltage, SW -------------------------------------------------------------------------------------−0.3V to (VIN + 0.3V)
zBOOT V oltage ------------------------------------------------------------------------------------------------(VSW − 0.3V) to (VSW + 6V)
zThe Other Pins Voltage-------------------------------------------------------------------------------------−0.3V to 6V
zPower Dissipation, PD @ TA = 25°C
SOP-8 ----------------------------------------------------------------------------------------------------------0.833W
MSOP-10 (Exposed Pad)----------------------------------------------------------------------------------1.163W
zPackage Thermal Resistance (Note 2)
SOP-8, θJA ----------------------------------------------------------------------------------------------------120°C/W
MSOP-10 (Exposed Pad), θJA ----------------------------------------------------------------------------86°C/W
MSOP-10 (Exposed Pad), θJC ----------------------------------------------------------------------------30°C/W
zJunction T emperature ---------------------------------------------------------------------------------------150°C
zLead T emperature (Soldering, 10 sec.) -----------------------------------------------------------------260°C
zStorage T emperature Range -------------------------------------------------------------------------------−65°C to 150°C
zESD Susceptibility (Note 3)
HBM (Human Body Mode) ---------------------------------------------------------------------------------2kV
MM (Ma chine Mode) ----------------------------------------------------------------------------------------200V
Recommended Operating Conditions (Note 4)
zSupply Voltage, VIN -----------------------------------------------------------------------------------------4.75V to 24V
zEnable V oltage, VEN -----------------------------------------------------------------------------------------0V to 5.5V
zJunction T emperature Range ------------------------------------------------------------------------------−40°C to 125°C
zAmbient T emperature Range ------------------------------------------------------------------------------−40°C to 85°C
To be continued
RT8271
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DS8271-02 March 2011 www.richtek.com
Note 1. Stresses listed as the above "Absolute Maximum Ratings" may cause permanent damage to the device. These are for
stress ratings. Functional operation of the device at these or any other conditions beyond those indicated in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended
periods may remain possibility to affect device reliability.
Note 2. θJA is measured in the natural convection at TA = 25 °C on a high effective thermal conductivity four layers test board of
JEDEC 51-7 thermal measure ment standard. The case point of θJC is on the expose pad for MSOP-10 (Exposed Pad)
package.
Note 3. Devices are ESD sensitive. Handling precaution is recommended.
Note 4. The device is not guaranteed to function outside its operating conditions.
Parameter Symbol Test Conditions Min Typ Max Unit
Logic High 1.4 -- 5.5
EN Input Voltage Logic Low -- -- 0.4 V
E nable Pull Up Curren t VEN = 0V -- 1 -- μA
Shutdown Current ISHDN V
EN = 0V -- 22 3 6 μA
Quiescent Current IQ V
EN = 2V, VFB = 1V -- 0.6 1 mA
Soft -Star t Period CSS = 10nF -- 1 -- ms
Thermal Shutdown TSD -- 150 -- °C
RT8271
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Efficiency vs. Load Current
0
10
20
30
40
50
60
70
80
90
100
0 0.25 0.5 0.75 1 1.25 1.5 1.75 2
Load Current (A)
Efficienc y (%)
VIN = 12V
VOUT = 2.5V
VOUT = 3.3V
Typical Operating Characteristics
Curre n t Limit vs. Dut y Ratio
2.6
2.8
3.0
3.2
3.4
3.6
3.8
4.0
0 102030405060708090
Duty Ratio (%)
Current Limi t (A)
Reference Voltage v s. Temperature
0.900
0.905
0.910
0.915
0.920
0.925
0.930
-50 -25 0 25 50 75 100 125
Temperature (°C)
Refer ence Volt age ( V )
VIN = 12V, IOUT = 0A
Output Voltage vs. Load Current
2.516
2.518
2.520
2.522
2.524
2.526
2.528
0 0.25 0.5 0.75 1 1.25 1.5 1.75 2
Load Current (A)
Output Voltage (V)
VIN = 12V
Quiescent Current vs. Temperature
0.50
0.55
0.60
0.65
0.70
0.75
0.80
-50 -25 0 25 50 75 100 125
Temperature (°C)
Qu iescent Current (mA
)
VIN = 12V
Shutdown Current vs. Input Voltage
16
17
18
19
20
21
22
3 6 9 1215182124
Input Vo lt age (V)
Shutdown Curr ent (µA) 1
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Output Ripple
Time (1μs/Div)
IL
(1A/Div)
VOUT
(5mV/Div)
VIN = 12V
VOUT = 2.5V
IOUT = 2A
VSW
(10V/Div)
Output Voltage vs. Input Voltage
2.517
2.519
2.521
2.523
2.525
2.527
2.529
4 6.5 9 11.51416.51921.524
In put Vo l ta g e (V)
Output Voltage (V)
IOUT = 1A
Switching Frequency vs. Input Voltage
1.05
1.10
1.15
1.20
1.25
1.30
1.35
3 6 9 1215182124
Input Vo ltage (V)
Swit ching Fr equ enc y (MHz ) 1
VOUT = 2.5V, IOUT = 0.3A
Switching Frequency vs. Temperature
1.00
1.05
1.10
1.15
1.20
1.25
1.30
-50-250 255075100125
Tem pera tu re ( °C)
Sw i tching Frequency (MHz) 1
VIN = 12V, VOUT = 2.5V, IOUT = 0.3A
Load Transient Response
Time (100μs/Div)
IOUT
(1A/Div)
VOUT
(50mV/Div)
VIN = 12V, VOUT = 2.5V
IOUT = 0A to 2A
Load Transient Response
Time (100μs/Div)
IOUT
(1A/Div)
VOUT
(50mV/Div)
VIN = 12V, VOUT = 2.5V
IOUT = 1A to 2A
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Power On from EN Pin
Time (250μs/Div)
IIN
(500mA/Div) VIN = 12V
VOUT = 2.5V
IOUT = 2A
VOUT
(1V/Div)
VEN
(5V/Div)
Power Off from EN Pin
Time (100μs/Div)
IIN
(500mA/Div)
VOUT
(1V/Div)
VEN
(5V/Div)
VIN = 12V, VOUT = 2.5V, IOUT = 2A
RT8271
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DS8271-02 March 2011 www.richtek.com
Application Information
The RT8271 is an asynchronous high voltage buck
converter that can support the input voltage range from
4.75V to 24V a nd the output current ca n be up to 2A.
Output Voltage Setting
The resistive divider allows the FB pin to sense the output
voltage a s shown in Figure 1.
Figure 1. Output Voltage Setting
The output voltage is set by a n external resistive divider
a ccording to the following equation :
⎛⎞
+
⎜⎟
⎝⎠
OUT FB R1
V = V1
R2
Where VFB is the feedba ck reference voltage (0.92V typ.).
External Bootstrap Diode
Connect a 10nF low ESR cera mic ca pacitor between the
BOOT pin and SW pin. This capacitor provides the gate
driver voltage for the high side MOSFET.
It is recommended to add an external bootstrap diode
between a n external 5V a nd the BOOT pin for ef ficiency
improvement when input voltage is lower than 5.5V or duty
ratio is higher than 65%. The bootstrap diode can be a
low cost one such a s 1N4148 or BAT54.
The external 5V can be a 5V fixed input from system or a
5V output of the RT8271.
Figure 2. External Bootstra p Diode
Soft-Start
The RT8271 contains an external soft-start clamp that
gradually raises the output voltage. The soft-start timming
can be progra med by the external ca pacitor between SS
pin and GND. The chip provides a 10μA charge current for
the external ca pa citor . If 10nF ca pacitor is used to set the
soft-start a nd it’s period will be 1ms (typ.).
Inductor Selection
The inductor value and operating frequency determine the
ripple current according to a specific input and output
voltage. The ripple current ΔIL increases with higher VIN
and decrea ses with higher inducta nce.
OUT OUT
LIN
VV
I = 1
fL V
⎡⎤⎡ ⎤
Δ×−
⎢⎥⎢ ⎥
×
⎣⎦⎣ ⎦
Having a lower ripple current reduces not only the ESR
losses in the output ca pa citors but also the output voltage
ripple. High frequency with small ripple current can achieve
highest efficiency operation. However , it requires a large
inductor to a chieve this goal.
For the ripple current selection, the value of ΔIL = 0.2(IMAX)
will be a rea sonable starting point. The largest ripple current
occurs at the highest VIN. To guarantee that the ripple
current stays below the specified maximum, the inductor
value should be chosen according to the following
equation :
OUT OUT
L(MAX) IN(MAX)
VV
L = 1
fI V
⎡⎤⎡ ⎤
×−
⎢⎥⎢ ⎥
×Δ
⎣⎦⎣ ⎦
Inductor Core Selection
The inductor type must be selected once the value for L
is known. Generally speaking, high efficiency converters
can not aff ord the core loss f ound in low cost powdered
iron cores. So, the more expensive ferrite or
mollypermalloy cores will be a better choice.
The selected inductance rather than the core size for a
fixed inductor value is the key for a ctual core loss. As the
inductance increa ses, core losses decrease. Unfortunately ,
increase of the inductance requires more turns of wire
a nd therefore the copper losses will increa se.
Ferrite designs are preferred at high switching frequency
due to the characteristics of very low core losses. So,
design goals can focus on the reduction of copper loss
and the saturation prevention.
RT8271
GND
FB
R1
R2
VOUT
SW
BOOT
5V
RT8271 10nF
RT8271
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Ferrite core material saturates “hard”, which means that
inductance collapses abruptly when the peak design
current is exceeded. The previous situation results in a n
abrupt increa se in inductor ripple current and consequent
output voltage ripple.
Do not allow the core to saturate!
Different core materials and sha pes will cha nge the size/
current and price/current relationship of a n inductor .
T oroid or shielded pot cores in ferrite or permalloy materials
are small and do not radiate energy. However, they are
usually more expensive than the similar powdered iron
inductors. The rule for inductor choice mainly depends
on the price vs. size requirement a nd a ny ra diated f ield/
EMI requirements.
Diode Selection
When the power switch turns off, the path for the current
is through the diode connected between the switch output
and ground. This forward biased diode must have a
minimum voltage drop a nd recovery times. Schottky diode
is recommended and it should be able to handle those
current. The reverse voltage rating of the diode should be
greater than the maximum input voltage, a nd current rating
should be greater than the maximum load current. For
more detail plea se refer to Table 4.
CIN and COUT Selection
The input capacitance, CIN, is needed to filter the
tra pezoidal current at the source of the high side MOSFET .
To prevent large ripple current, a low ESR input ca pacitor
sized for the maximum RMS current should be used. The
RMS current is given by :
This formula has a maximum at VIN = 2VOUT, where
IRMS = IOUT/2. This simple worst-case condition is
commonly used for design because even significant
deviations do not offer much relief.
Choose a capacitor rated at a higher temperature than
required. Several capacitors may also be paralleled to
meet size or height requirements in the design.
For the input ca pacitor , a 10μF low ESR cera mic capacitor
is recommended. For the recommended ca pacitor, plea se
refer to table 3 for more detail.
The selection of COUT is determined by the required ESR
to minimize voltage ripple.
Moreover, the amount of bulk capacitance is also a key
for COUT selection to ensure that the control loop is stable.
Loop stability can be checked by viewing the load transient
respon se as described in a later section.
The output ripple, ΔVOUT , is determined by :
The output ripple will be highest at the maximum input
voltage since ΔIL increases with input voltage. Multiple
ca pa citors pla ced in parallel may be needed to meet the
ESR and RMS current handling requirement. Dry tantalum,
special polymer, aluminum electrolytic and ceramic
capacitors are all available in surface mount packages.
Special polymer capacitors offer very low ESR value.
However, it provides lower capacitance density than other
types. Although Tantalum capacitors have the highest
ca pa citance density , it is i mportant to only use type s that
pass the surge test for use in switching power supplie s.
Aluminum electrolytic ca pacitors have significantly higher
ESR. However, it can be used in cost-sensitive a pplications
for ripple current rating and long term reliability
considerations. Ceramic capacitors have excellent low
ESR characteristics but can have a high voltage coefficient
a nd audible piezoelectric ef fects. The high Q of ceramic
ca pacitors with tra ce inductance can also lead to significant
ringing.
Higher values, lower cost ceramic capacitors are now
becoming available in smaller ca se sizes. Their high ripple
current, high voltage rating and low ESR make them ideal
for switching regulator applications. However , care must
be taken when these capacitors are used at input and
output. When a ceramic capacitor is used at the input
and the power is supplied by a wall ada pter through long
wires, a loa d step at the output ca n induce ringing at the
input, VIN. At best, this ringing can couple to the output
and be mistaken as loop instability. At worst, a sudden
inrush of current through the long wires can potentially
cause a voltage spike at VIN large enough to da mage the
part.
OUT IN
RMS OUT(MAX) IN OUT
VV
I = I 1
VV
−
OUT L OUT
1
VIESR
8fC
⎡⎤
Δ≤Δ +
⎢⎥
⎣⎦
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Checking T ransient Re sponse
The regulator loop response ca n be checked by looking
at the load transient response. Switching regulators ta ke
several cycles to respond to a step in load current. When
a load step occurs, VOUT immedi ately shifts by an a mount
equal to ΔILOAD (ESR) also begins to charge or discharge
COUT generating a feedback error signal for the regulator
to return VOUT to its steady-state value. During this recovery
time, VOUT can be monitored for overshoot or ringing that
would indicate a stability problem.
Thermal Considerations
The maximum power dissipation depends on the thermal
resistance of IC package, PCB layout, the rate of
surroundings airflow and temperature difference between
junction to a mbient. The maximum power dissipation can
be calculated by following formula :
PD(MAX) = ( T J(MAX) - TA ) / θJA
Where TJ(MAX) is the maximum operation junction
temperature, TA is the a mbient temperature and the θJA is
the junction to a mbient thermal re sistance.
For recommended operating conditions specification of
RT8271, the maximum junction temperature is 125°C. The
junction to ambient thermal resista nce θJA f or MSOP-10
(Exposed Pad) package is 86°C/W and for SOP-8 is
120°C/W on the standard JEDEC 51-7 four-layers thermal
test board. The maximum power dissipation at TA = 25°C
can be calculated by following f ormula :
PD(MAX) = (125°C − 25°C) / (86°C/W) = 1.163W for
MSOP-10 (Exposed Pad)
PD(MAX) = (125°C − 25°C) / (120°C/W) = 0.833W for
SOP-8
The maximum power dissipation depends on operating
ambient temperature for fixed TJ(MAX) and thermal
resistance θJA. For RT8271 packages, the Figure 3 of
derating curves allows the designer to see the effect of
rising ambient temperature on the maximum power
dissipation allowed.
Layout Consideration
Follow the PCB layout guidelines for optimal performance
of the RT8271.
`Keep the tra ces of the main current paths a s short a nd
wide a s possible.
`Put the input ca pa citor as close a s possible to the device
pins (VIN and GND).
`LX node is with high frequency voltage swing and should
be kept at small area. Keep sensitive components away
from the LX node to prevent stray ca pacitive noise pick-
up.
`Pla ce the feedback components to the FB pin a s close
as possible.
`The GND a nd Exposed Pa d should be connected to a
strong ground plane for heat sinking and noise protection.
Figure 3. Derating Curves for RT8271 Packages
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
1.1
1.2
0255075100125
Ambient Tem pera tu re ( °C )
Power Di ssi pation (W )
Four Layer PCB
MSOP-10 (Exposed Pad)SOP-8
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Figure 4. PCB Layout Guide for MSOP-10 (Exposed Pad)
VIN
VOUT
GND
CIN
CB
SS
BOOT
VIN
GND
SW FB
EN
COMP
GND
CS
CP
CC
RC
SW
D1
VOUT
COUT L1
Input capacitor must
be placed as close
to the IC as pos sible.
The output capacitor
must be placed near
the RT8271. SW should be connected to inductor by
wide and short trace. Keep sensitive
components away from this trace.
The resistor divider must be connected
as close to the device as possible.
The parallel distance between
COM P and FB traces must be
as short as possible .
2
3
45
6
7
8
Figure 5. PCB Layout Guide for SOP-8
SS
FB
NC
VIN
NC EN
COMP
SW GND
BOOT
56
7
8
4
3
210
9
GND
11
CSS
VOUT
R1
R2
RC
CC
CP
SW
CBOOT
CIN D1
COUT L1
VOUT
GND
Input capacitor must
be placed as close
to the IC as possible. SW should be connected to inductor by
wide and short trace. K eep sensitive
components away from this trace.
The feedback components
must be connected as close
to the device as possible .
VIN
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Table 3. Suggested Capacitors for CIN and COUT
Component Suppli er Series Dimension s (mm)
TDK SLF 12555T 12.5 x 12.5 x 5.5
TAIYO YUDEN NR8040 8 x 8 x 4
TDK SLF12565T 12.5 x 2.5 x 6.5
Table 2. Sugge sted Inductors for Typical Application Circuit
Component Supplier Series VRRM (V) IOUT (A) Package
DIODES B330A 30 3 SMA
DIODES B220A 20 2 SMA
PANJIT SK22 20 2 DO-214AA
PANJIT SK23 30 2 DO-214AA
Table 4. Suggested Diode
Location Component Supplier Part No. Capacitance (μF) Case Size
CIN MURATA GRM31CR61E106K 10 1206
CIN TDK C3225X5R1E106K 10 1206
CIN TAI YO YUDEN TMK316BJ106ML 10 1206
COUT MURATA GRM32ER61E226M 22 1210
COUT MURATA GRM21BR60J226M 22 0805
COUT TDK C3225X5R0J226M 22 1210
COUT TAIYO YUDEN EMK325BJ226MM 22 1210
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A
B
J
F
H
M
C
D
I
8-Lead SOP Plastic Package
Dimension s In Millimeters Dimension s In Inch es
Symbol Min Max Min Max
A 4.801 5.004 0.189 0.197
B 3.810 3.988 0.150 0.157
C 1.346 1.753 0.053 0.069
D 0.330 0.508 0.013 0.020
F 1.194 1.346 0.047 0.053
H 0.170 0.254 0.007 0.010
I 0.050 0.254 0.002 0.010
J 5.791 6.200 0.228 0.244
M 0.400 1.270 0.016 0.050
Outline Dimension
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DS8271-02 March 2011 www.richtek.com
Information that is provided by Richtek Technology Corporation is believed to be accurate and reliable. Richtek reserves the right to make any change in circuit
design, specification or other related things if necessary without notice at any time. No third party intellectual property infringement of the applications should be
guaranteed by users when integrating Richtek products into any application. No legal responsibility for any said applications is assumed by Richtek.
Richtek Technology Corporation
Headquarter
5F, No. 20, Taiyuen Street, Chupei City
Hsinchu, Taiwan, R.O.C.
Tel: (8863)5526789 Fax: (8863)5526611
Richtek Technology Corporation
Taipei Office (Marketing)
5F, No. 95, Minchiuan Road, Hsintien City
Taipei County, Taiwan, R.O.C.
Tel: (8862)86672399 Fax: (8862)86672377
Email: marketing@richtek.com
L
A2
A
b
A1
D
E1
E
e
EXPOSED THERMAL PAD
(Bottom of Package)
U
V
10-Lead MSOP (Exposed Pad) Plastic Package
Dimensions In Millimeters Dimensions In Inches
Symbol Min Max Min Max
A 0.810 1.100 0.032 0.043
A1 0.000 0.100 0.000 0.004
A2 0.750 0.950 0.030 0.037
b 0.170 0.270 0.007 0.011
D 2.900 3.100 0.114 0.122
e 0.500 0.020
E 4.800 5.000 0.189 0.197
E1 2.900 3.100 0.114 0.122
L 0.400 0.800
0.016 0.031
U 1.300 1.700
0.051 0.067
V 1.500 1.900
0.059 0.075
