IRFR2905Z
IRFU2905Z
HEXFET® Power MOSFET
VDSS = 55V
RDS(on) = 14.5mΩ
ID = 42A
11/24/03
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AUTOMOTIVE MOSFET
PD - 95811
Specifically designed for Automotive applications, this HEXFET®
Power MOSFET utilizes the latest processing techniques to
achieve extremely low on-resistance per silicon area. Additional
features of this design are a 175°C junction operating tempera-
ture, fast switching speed and improved repetitive avalanche
rating . These features combine to make this design an extremely
efficient and reliable device for use in Automotive applications and
a wide variety of other applications.
S
D
G
Description
●Advanced Process Technology
●Ultra Low On-Resistance
●175°C Operating Temperature
●Fast Switching
●Repetitive Avalanche Allowed up to Tjmax
Features
D-Pak
IRFR2905Z I-Pak
IRFU2905Z
HEXFET® is a registered trademark of International Rectifier.
Absolute Maximum Ratings
Parameter Units
ID @ TC = 25 °C Cont inuous Dr ain C urrent , VGS @ 10V (Silicon Limited)
ID @ TC = 10 0°C Cont inuous Dr ain C urrent , VGS @ 10V A
ID @ TC = 25 °C Cont inuous Dr ain C urrent , VGS @ 10V (Package Limited)
IDM
P
u
l
se
d
D
ra
i
n
C
urrent
c
PD @TC = 25°C Power Dissipati on W
Li ne ar Der ating Factor W/ °C
VGS Gate- to- Sou r c e V o ltage V
EAS (Thermally limi ted)
Si
n
gl
e
P
u
l
se
A
va
l
anc
h
e
E
ner
gy
d
mJ
EAS (Tested )
Si
n
gl
e
P
u
l
se
A
va
l
anc
h
e
E
ner
gy
T
este
d
V
a
l
ue
h
IAR
A
va
l
anc
h
e
C
urrent
c
A
EAR
R
epet
i
t
i
ve
A
va
l
anc
h
e
E
ner
gy
g
mJ
TJ Ope r ating Jun ction and
TSTG Storage Te m perat ure Range °C
Soldering Temperature, for 10 seconds
Mo unting Tor que, 6-32 or M3 screw
Thermal Resistance Parameter Typ. Max. Units
RθJC
J
unct
i
on-to-
C
ase
j
––– 1.38
RθJA
unct
on-to-
m
ent
mount
ij
––– 40 °C/W
RθJA
J
unct
i
on-to-
A
m
bi
ent
j
––– 110
82
55
See Fig.12 a, 12b, 15 , 16
110
0.72
± 20
Max.
59
42
240
42
-5 5 to + 175
300 ( 1.6m m f r o m ca se )
10 lbf
y
in (1.1N
y
m)
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S
D
G
Electrical Characteristics @ TJ = 25°C (unless otherwise specified)
Parameter Min. Typ. Max. Units
V(BR)DSS Drain-to-Source Br eakdow n Vol tage 55 ––– ––– V
∆V(BR)DSS
/
∆TJ B reak dow n Voltage Tem p. Co eff i c i e nt ––– 0. 053 ––– V /°C
RDS(on) Static D r ain-to-Source On-Resistan c e ––– 11.1 14.5 mΩ
VGS(th) Gate Threshold Voltage 2.0 ––– 4.0 V
gf s F orw a r d Trans co nduc tance 20 ––– ––– S
IDSS Drain-to-Source Leakage Current ––– ––– 20 µA
––– ––– 250
IGSS Gate-to-Source Forward Leakage ––– ––– 200 nA
Gate-to-S ource Reverse Leakage ––– ––– -200
QgTotal Gate Charge ––– 29 44
Qgs Gate-to-Source Charge ––– 7.7 ––– nC
Qgd Ga t e - to- Dr ain ( " M ill e r " ) Ch ar g e ––– 12 –––
RGGat e In put Resistance ––– 1.3 ––– Ωf = 1MHz, open drain
td(on) Tur n - O n Delay Tim e ––– 14 –––
trRise Time –––66–––
td(off) Turn-Off Delay Time ––– 3 1 ––– ns
tfFall Time –––35–––
LDInte rnal Drain Indu ctance ––– 4 .5 ––– Between lead,
nH 6mm (0.25in.)
LSInte r nal Sour ce Ind uctance ––– 7.5 ––– f rom package
and center of die contact
Ciss In put Capaci tance ––– 1380 –––
Coss O utput Cap acitance ––– 240 –––
Crss Reverse Tr ansfer C apacita nce ––– 120 ––– pF
Coss O utput Cap acitance ––– 820 –––
Coss O utput Cap acitance ––– 190 –––
Coss eff . Effe cti ve Output Capacitance ––– 300 –––
Source-Drain Ratin
g
s and Characteristics
Paramet e r Min . Typ . M a x . Un its
ISCo nti n uous S o ur c e Cu r rent ––– – –– 36
(Body Diode) A
ISM Pulsed Source Current ––– ––– 240
(Body Diode)
c
VSD Diode Forward Voltage ––– ––– 1.3 V
trr Reve r se Recovery Time ––– 23 3 5 ns
Qrr Reverse Reco ver y Charge ––– 16 24 nC
ton Forward Turn-On Time Intrinsic turn-on time is neg ligible (turn-on is domina ted by LS+LD)
VGS = 0 V, VDS = 1.0V, ƒ = 1.0MHz
VGS = 0 V, VDS = 44V, ƒ = 1. 0M Hz
VGS = 0V, VDS = 0V to 44 V
f
VGS = 10V
e
VDD = 28V
ID = 36A
RG = 15 Ω
TJ = 25°C, IS = 36A, VGS = 0V
e
TJ = 25°C, IF = 36 A, VDD = 28V
di /dt = 100A/ µ s
e
Conditions
VGS = 0V, ID = 25 0µA
Refe ren c e to 25°C, ID = 1mA
VGS = 10V, ID = 36A
e
VDS = VGS, ID = 250µ A
VDS = 55V , V GS = 0V
VDS = 55V , V GS = 0V , TJ = 12 5°C
MOSFET symbol
showing the
integra l revers e
p-n junction diod e.
VDS = 25V , I D = 36A
ID = 36A
VDS = 44V
Conditions
VGS = 10V
e
VGS = 0V
VDS = 25V
ƒ = 1. 0M H z
VGS = 20V
VGS = -20V
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Fig 2. Typical Output CharacteristicsFig 1. Typical Output Characteristics
Fig 3. Typical Transfer Characteristics Fig 4. Typical Forward Transconductance
Vs. Drain Current
0.1 110 100
VDS, Drain- to-Sour ce Voltage (V)
0.1
1
10
100
1000
ID, Drain-to-Source Current (A)
≤ 60µs PU LSE WIDTH
Tj = 25° C
4.5V
VGS
TOP 15V
10V
8.0V
7.0V
6.0V
5.5V
5.0V
BOTTOM 4.5V
0 1 10 100
0.1 110 100
VDS, Dr ain-to-Source V oltage (V)
1
10
100
1000
ID, Drain-to-Source Current (A)
≤ 60µs PU LSE WIDTH
Tj = 175° C
4.5V
VGS
TOP 15V
10V
8.0V
7.0V
6.0V
5.5V
5.0V
BOTTOM 4.5V
4.0 5.0 6.0 7.0 8.0 9.0 10.0
VGS, Gate-t o-Source V oltage (V)
1.0
10.0
100.0
1000.0
ID, Drain-to-Source Current (Α)
VDS = 25V
≤ 60µs PULSE WIDT H
TJ = 25° C
TJ = 175° C
0 1020304050
ID, Drain-to- Source Current (A )
0
10
20
30
40
50
Gfs, Forward Transconductance (S)
TJ = 25° C
TJ = 175° C
VDS = 15V
380µs PU LSE WIDTH
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Fig 8. Maximum Safe Operating Area
Fig 6. Typical Gate Charge Vs.
Gate-to-Source Voltage
Fig 5. Typical Capacitance Vs.
Drain-to-Source Voltage
Fig 7. Typical Source-Drain Diode
Forward Voltage
110 100
VDS, Dr ain-to-Source V oltage (V)
0
400
800
1200
1600
2000
2400
C, Capacitance (pF)
Coss
Crss
Ciss
VGS = 0V, f = 1 MHZ
Ciss = Cgs + Cgd, Cds SHORTED
Crss = Cgd
Coss = Cds + Cgd
0 1020304050
QG Total Gate Charge (nC)
0
4
8
12
16
20
VGS, Gate-to-Source Voltage (V)
VDS= 44V
VDS= 28V
VDS= 11V
ID= 36A
FOR TEST CIRCUIT
SEE FIGURE 13
0.2 0.6 1.0 1.4 1.8 2.2
VSD, Source-toDr ain Voltage (V)
0.1
1.0
10.0
100.0
1000.0
ISD, Reverse Drain Current (A)
TJ = 25° C
TJ = 175° C
VGS = 0V
1 10 100 1000
VDS , Dr ain-toSource Voltage (V )
0.1
1
10
100
1000
ID, Drain-to-Source Current (A)
Tc = 25°C
Tj = 175° C
Single Pulse
1msec
10msec
OPERATION IN THIS AREA
LIMITED BY RDS(on)
100µsec
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Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case
Fig 9. Maximum Drain Current Vs.
Case Temperature Fig 10. Normalized On-Resistance
Vs. Temperature
25 50 75 100 125 150 175
TC , Case Temperature (°C )
0
10
20
30
40
50
60
70
ID , Drain Current (A)
LIMITED BY PACKAGE
-60 -40 -20 020 40 60 80 100 120 140 160 180
TJ , Junction Temperature (° C)
0.5
1.0
1.5
2.0
RDS(on) , Drain-to-Source On Resistance
(Normalized)
ID = 36A
VGS = 10V
1E-006 1E-005 0.0001 0.001 0.01 0.1
t1 , Rectangular Pul s e Durati on (sec)
0.001
0.01
0.1
1
10
Thermal Response ( Z thJC )
0.20
0.10
D = 0.50
0.02
0.01
0.05
SINGLE PULSE
( THERMAL RESPONSE ) Notes:
1. Duty Factor D = t1/t2
2. Peak Tj = P dm x Zthjc + Tc
Ri (°C/W) τi (sec)
0.3962 0.00012
0.5693 0.00045
0.4129 0.0015
τJ
τJ
τ1
τ1τ2
τ2τ3
τ3
R1
R1R2
R2R3
R3
τ
τC
Ci i/Ri
Ci= τi/Ri
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Q
G
Q
GS
Q
GD
V
G
Charge
D.U.T. V
DS
I
D
I
G
3mA
V
GS
.3µF
50KΩ
.2µF
12V
Current Regulator
Same Type as D.U.T.
Current Sampling Resistors
+
-
10 V
Fig 13b. Gate Charge Test Circuit
Fig 13a. Basic Gate Charge Waveform
Fig 12c. Maximum Avalanche Energy
Vs. Drain Current
Fig 12b. Unclamped Inductive Waveforms
Fig 12a. Unclamped Inductive Test Circuit
tp
V
(BR)DSS
I
AS
Fig 14. Threshold Voltage Vs. Temperature
R
G
I
AS
0.01
Ω
t
p
D.U.T
L
VDS
+
-V
DD
DRIVER
A
15V
20V
VGS
25 50 75 100 125 150 175
Starting TJ, Junct ion Temper ature (° C)
0
40
80
120
160
200
240
EAS, Single Pulse Avalanche Energy (mJ)
ID
TOP 36A
8.6A
BOTTOM 4.8A
-75 -50 -25 025 50 75 100 125 150 175
TJ , Temperature ( ° C )
2.0
2.5
3.0
3.5
4.0
4.5
VGS(th) Gate threshold Voltage (V)
ID = 250µA
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Fig 15. Typical Avalanche Current Vs.Pulsewidth
Fig 16. Maximum Avalanche Energy
Vs. Temperature
Notes on Repetitive Avalanche Curves , Figures 15, 16:
(For further info, see AN-1005 at www.irf.com)
1. Avalanche failures assumption:
Purely a thermal phenomenon and failure occurs at a
temperature far in excess of T jmax. This is validated for
every part type.
2. Safe operation in Avalanche is allowed as long asTjmax is
not exceeded.
3. Equation below based on circuit and waveforms shown in
Figures 12a, 12b.
4. PD (ave) = Average power dissipation per single
avalanche pulse.
5. BV = Rated breakdown voltage (1.3 factor accounts for
voltage increase during avalanche).
6. Iav = Allowable avalanche current.
7. ∆T = Allowable rise in junction temperature, not to exceed
Tjmax (assumed as 25°C in Figure 15, 16).
tav = Average time in avalanche.
D = Duty cycle in avalanche = tav ·f
ZthJC(D, tav) = Transient thermal resistance, see figure 11)
PD (ave) = 1/2 ( 1.3·BV·Iav) = DT/ ZthJC
Iav = 2DT/ [1.3· BV·Zth]
EAS (AR) = PD (ave)·tav
1.0E-06 1.0E-05 1.0E-04 1.0E-03 1.0E-02 1.0E-01
tav (sec)
0.1
1
10
100
1000
Avalanche Current (A)
0.05
Dut y Cycle = Single Pulse
0.10
Allowed avalanche Current vs
avalanche pulsewidth, tav
assuming ∆Tj = 25°C due to
avalanche losses. Note: In no
case should Tj be allowed to
exceed Tjmax
0.01
25 50 75 100 125 150 175
Starting TJ , Junction Temperature (°C )
0
10
20
30
40
50
60
EAR , Avalanche Energy (mJ)
TOP Single Pulse
BOTTOM 1% Duty Cycle
ID = 36A
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Fig 17. Peak Diode Recovery dv/dt Test Circuit for N-Channel
HEXFET® Power MOSFETs
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
P.W. Period
di/dt
Diode Recovery
dv/dt
Ripple ≤5%
Body Diode Forward Drop
Re-Applied
Voltage
Reverse
Recovery
Current Body Diode Forward
Current
VGS=10V
VDD
ISD
Driver Gate Drive
D.U.T. ISD Waveform
D.U.T. VDS Waveform
Inductor Curent
D = P.W.
Period
* VGS = 5V for Logic Level Devices
*
+
-
+
+
+
-
-
-
RGVDD
• dv/dt controlled by RG
• Driver same type as D.U.T.
• ISD controlled by Duty Factor "D"
• D.U.T. - Device Under Test
D.U.T
VDS
90%
10%
VGS t
d(on)
t
r
t
d(off)
t
f
VDS
Pulse Width ≤ 1 µs
Duty Factor ≤ 0.1 %
RD
VGS
RG
D.U.T.
10V
+
-
VDD
Fig 18a. Switching Time Test Circuit
Fig 18b. Switching Time Waveforms
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D-Pak (TO-252AA) Package Outline
Dimensions are shown in millimeters (inches)
D-Pak (TO-252AA) Part Marking Information
6.73 (.265)
6.35 (.250)
- A -
4
1 2 3
6.22 (.245)
5.97 (.235)
- B -
3X 0.89 (.035)
0.64 (.025)
0.25 (.010) M A M B
4. 57 (.180 )
2.28 (.090)
2X 1.14 (.045)
0.76 (.030)
1. 52 (.060 )
1. 15 (.045 )
1.02 (.040)
1.64 (.025)
5.46 (.215)
5.21 (.205) 1.27 (.050)
0.88 (.035)
2.38 (.094)
2.19 (.086) 1.14 (.045)
0.89 (.035)
0.58 (.023)
0.46 (.018)
6.45 (.245)
5.68 (.224)
0.51 (.020)
MIN.
0. 58 (.023 )
0. 46 (.018 )
LEAD ASSIGNMENTS
1 - GATE
2 - DRAIN
3 - SOURCE
4 - DRAIN
10.42 (.410)
9.40 (.370)
NOTES:
1 DIMENSI ONING & TOLERANCING PER ANSI Y14.5M, 1982.
2 CONTROL LIN G DI MENSIO N : I NCH.
3 CONFORMS TO JEDEC OUTLINE TO-252AA.
4 DIM ENSI O NS SHOWN ARE BEFORE SOLDER DI P,
SOLDER DIP MAX. +0.16 (.006).
EXAMPLE:
LOT CODE 9U1P
T HIS IS AN IRFR120
WITH ASSEMBLY
WE E K = 16
DAT E CODE
YEAR = 0
LOGO
RECTIFIER
INT E RNAT IONAL
AS S E MB L Y
LOT CODE
016
IRFU120
9U 1P
Notes: T his part marking information applies to devices produced before 02/26/2001
INT E RNAT IONAL
LOGO
RECTIFIER
3412
IRFU120
916A
LOT CODE
AS S E MB L Y
EXAMPLE:
WITH ASSEMBLY
T HIS IS AN IRFR120
YE AR 9 = 1999
DAT E CODE
LINE A
WE E K 16
IN THE ASSEMBLY LINE "A"
ASSEMBLE D ON WW 16, 1999
L OT CODE 1234
PART NUMBER
Notes: T his part marking information applies to devices produced after 02/26/2001
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I-Pak (TO-251AA) Package Outline
Dimensions are shown in millimeters (inches)
I-Pak (TO-251AA) Part Marking Information
6.73 (.265)
6.35 (.250)
- A -
6.22 (.245)
5.97 (.235)
- B -
3X 0.89 (.035)
0.64 (.025)
0.25 (.010) M A M B
2.28 (.0 90)
1.14 (.045)
0.76 (.030)
5.46 ( .215)
5.21 ( .205) 1.27 (.050)
0.88 (.035)
2.38 (.094)
2.19 (.086)
1.14 (.045)
0.89 (.035)
0.58 (.023)
0.46 (.018) LEAD ASSIGNMENTS
1 - GATE
2 - DRAIN
3 - SO URCE
4 - DRAIN
NOTES:
1 DI ME NS IONING & TO LE RA NCING PER ANSI Y14.5 M, 1982 .
2 CON TRO LL ING DI MENSI O N : I NCH.
3 CONFORMS TO JEDEC OUTLINE TO-252AA.
4 DIMENSIONS SHOWN ARE BEFORE SOLDER DIP,
SOLDER DIP MAX. +0.16 (.006).
9.65 (.380)
8.89 (.350)
2X
3X
2.28 (.090)
1.91 (.075)
1.52 (.060)
1.15 (.045)
4
1 2 3
6.45 ( .245)
5.68 ( .224)
0.58 (.023)
0.46 (.018)
WE E K = 16
DAT E CODE
YE AR = 0
Notes : T his part marking information applies to devices produced before 02/26/2001
EXAMPLE:
LOT CODE 9U1P
THIS IS AN IRFR120
WIT H AS S E MB L Y
ASSEMBLY
INTERNATIONAL
RE CT IF IER
LOGO
LOT CODE
IRFU120
9U 1P
016
INTERNATIONAL
LOGO
RECTIFIER
LOT CODE
AS S E MB L Y
EXAMPLE:
WIT H AS S E MB L Y
THIS IS AN IRFR120
YEAR 9 = 1999
DAT E CODE
LINE A
WE E K 19
IN THE ASSEMBLY LINE "A"
AS S E MB L E D ON WW 19, 1999
LOT CODE 5678
PART NUMBER
Notes : T his part marking information applies to devices produced after 02/26/2001
56
IRFU120
919A
78
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Data and specifications subject to change without notice.
This product has been designed and qualified for the Automotive [Q101] market.
Qualification Standards can be found on IR’s Web site.
D-Pak (TO-252AA) Tape & Reel Information
Dimensions are shown in millimeters (inches)
TR
16.3 ( .641 )
15.7 ( .619 )
8.1 ( .318 )
7.9 ( .312 )
12.1 ( .476 )
11.9 ( .469 ) FEED DIRECTION FEED DIRE CTION
16.3 ( .641 )
15.7 ( .619 )
TRR TRL
NOTES :
1. CO NTRO LLIN G DIMENSION : MILL IMETER.
2. ALL D IMENSION S ARE SHOW N IN MILLIMET ERS ( INCHES ).
3. OUTLINE CONFORMS TO EIA-481 & EIA-541.
NOTES :
1. OUTLINE CONFORMS TO EIA-481.
16 mm
13 INCH
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information.11/03
Repetitive rating; pulse width limited by
max. junction temperature. (See fig. 11).
Limited by TJmax, starting TJ = 25°C, L = 0.08mH
RG = 25Ω, IAS = 36A, VGS =10V. Part not
recommended for use above this value.
Pulse width ≤ 1.0ms; duty cycle ≤ 2%.
Notes:
Coss eff. is a fixed capacitance that gives the same charging time
as Coss while VDS is rising from 0 to 80% VDSS .
Limited by T Jmax , see Fig.12a, 12b, 15, 16 for typical repetitive
avalanche performance.
This value determined from sample failure population. 100%
tested to this value in production.
When mounted on 1" square PCB (FR-4 or G-10 Material) .
For recommended footprint and soldering techniques refer to
application note #AN-994
Rθ is measured at TJ approximately 90°C
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Note: For the most current drawings please refer to the IR website at:
http://www.irf.com/package/
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