74AVC1T45GW-Q100 - NXP - Datasheet.Directory

1. General description

The 74AVC1T45-Q100 is a single bit, dual supply transceiver with 3-state output that

enables bidirectional level translation. It features two 1-bit input-output ports (A and B), a

direction cont ro l input (DIR) and dual supply pins (V CC(A) and VCC(B)). Both VCC(A) and

VCC(B) can be supplied at any voltage between 0.8 V and 3.6 V. This feature makes the

device suitable for translating between any of the low voltage nodes (0.8 V, 1.2 V, 1.5 V,

1.8 V, 2.5 V and 3.3 V). Pins A and DIR ar e re fe renced to VCC(A) and pin B is referenced

to VCC(B). A HIGH on DIR allows transmission from A to B and a LOW on DIR allows

transmission from B to A.

The device is fully specified for partial power-down applications using IOFF. The IOFF

circuitry disables the output, preventing any damaging backflow current through the

device when it is powered down. In suspend mod e when either VCC(A) or VCC(B) are at

GND level, both A and B are in the high-impedance OFF-st ate.

This product has been qualified to the Automotive Electronics Council (AEC) standard

Q100 (Grade 1) and is suitable for use in automotive applications.

2. Features and benefits

Automotive product qualification in accordance with AEC-Q100 (Grade 1)

Specified from 40 C to +85 C and from 40 C to +125 C

Wide supply voltage range:

VCC(A): 0.8 V to 3.6 V

VCC(B): 0.8 V to 3.6 V

High noise immunity

Complies with JEDEC standards:

JESD8-12 (0.8 V to 1.3 V)

JESD8-11 (0.9 V to 1.65 V)

JESD8-7 (1.2 V to 1.95 V )

JESD8-5 (1.8 V to 2.7 V)

JESD8-B (2.7 V to 3.6 V)

ESD protection:

MIL-STD-883, method 3015 Class 3B exceeds 8000 V

HBM JESD22-A114E Class 3B exceeds 8000 V

MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 )

Maximum data rates:

500 Mbit/s (1.8 V to 3.3 V translation)

320 Mbit/s (< 1.8 V to 3.3 V translation)

74AVC1T45-Q100

Dual-supply voltage level translator/transceiver; 3-state

Rev. 2 — 8 April 2013 Product data sheet

Product data sheet Rev. 2 — 8 April 2013 2 of 20

NXP Semiconductors 74AVC1T45-Q100

Dual-supply voltage level translator/transceiver; 3-state

320 Mbit/s (translate to 2.5 V or 1.8 V)

280 Mbit/s (translate to 1.5 V)

240 Mbit/s (translate to 1.2 V)

Suspend mode

Latch-up pe rform a nc e exceeds 100 mA per JESD 78 Clas s II

Inputs accept voltages up to 3.6 V

Low noise overshoot and undershoot < 10 % of VCC

IOFF circuitry provides partial Power-down mode operation

3. Ordering information

4. Marking

[1] The pin 1 indicator is located on the lower left corner of the device, below the marking code.

5. Functional diagram

Table 1. Ordering information

Type number Package

Tempe rature range Name Description Version

74AVC1T45GW-Q100 40 Cto+125C SC-88 plastic surface-mounted package; 6 leads SOT363

Table 2. Marking

Type number Marking code[1]

74AVC1T45GW-Q100 B5

Fig 1. Logic symbol Fig 2. Logic diagra m

001aag885

VCC(B)

VCC(A)

DIR

001aag886

VCC(B)

VCC(A)

DIR

Product data sheet Rev. 2 — 8 April 2013 3 of 20

NXP Semiconductors 74AVC1T45-Q100

Dual-supply voltage level translator/transceiver; 3-state

6. Pinning information

6.1 Pinning

6.2 Pin description

7. Functional description

[1] H = HIGH voltage level; L = LOW voltage level; X = don’t care; Z = high-impedance OFF-state.

[2] The input circuit of the data I/O is always active.

[3] The DIR input circuit is referenced to VCC(A).

[4] When either VCC(A) or VCC(B) is at GND level, the device goes into suspend mode.

Fig 3. Pin configuration SOT363

$9&74

&&$

&&%













DDD

Table 3. Pin description

Symbol Pin Description

VCC(A) 1 supply voltage port A and DIR

GND 2 ground (0 V)

A 3 data input or output

B 4 data input or output

DIR 5 direction control

VCC(B) 6 supply voltage port B

Table 4. Function table[1]

Supply voltage Input Input/output[2]

VCC(A), VCC(B) DIR[3] A B

0.8 V to 3.6 V L A = B input

0.8 V to 3.6 V H input B = A

GND[4] XZZ

Product data sheet Rev. 2 — 8 April 2013 4 of 20

NXP Semiconductors 74AVC1T45-Q100

Dual-supply voltage level translator/transceiver; 3-state

8. Limiting values

[1] The minimum input voltage ratings and output voltage ratings may be exceeded if the input and output current ratings are observed.

[2] VCCO is the supply voltage associated with the output port.

[3] VCCO + 0.5 V should not exceed 4.6 V.

[4] For SC-88 packages: above 87.5 C the value of Ptot derates linearly with 4.0 mW/K.

9. Recommended operating conditions

[1] VCCO is the supply voltage associated with the output port.

[2] VCCI is the supply voltage associated with the input port.

Table 5. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).

Symbol Parameter Conditions Min Max Unit

VCC(A) supply voltage A 0.5 +4.6 V

VCC(B) supply voltage B 0.5 +4.6 V

IIK input clamping current VI<0V 50 - mA

VIinput voltage [1] 0.5 +4.6 V

IOK output clamping current VO<0V 50 - mA

VOoutput voltage Active mode [1][2][3] 0.5 VCCO +0.5 V

Suspend or 3-state mode [1] 0.5 +4.6 V

IOoutput current VO=0VtoV

CCO -50 mA

ICC supply current ICC(A) or ICC(B) -100mA

IGND ground current 100 - mA

Tstg storage temperature 65 +150 C

Ptot total power dissipation Tamb =40 C to +125 C[4] -250mW

Table 6. Recommended operating con ditions

Symbol Parameter Conditions Min Max Unit

VCC(A) supply voltage A 0.8 3.6 V

VCC(B) supply voltage B 0.8 3.6 V

VIinput voltage 0 3.6 V

VOoutput voltage Active mode [1] 0V

CCO V

Suspend or 3-state mode 0 3.6 V

Tamb ambient temperature 40 +125 C

t/V input transition rise and fall rate VCCI = 0.8 V to 3.6 V [2] -5ns/V

Product data sheet Rev. 2 — 8 April 2013 5 of 20

NXP Semiconductors 74AVC1T45-Q100

Dual-supply voltage level translator/transceiver; 3-state

10. Static characteristics

[1] VCCO is the supply voltage associated with the output port.

[2] VCCI is the supply voltage associated with the data input port.

[3] For I/O ports, the parameter IOZ includes the input leakage current.

Table 7. Typical static characteristics at Tamb = 25 C[1][2]

At recommended operating conditions; voltages are referenced to GND (ground = 0 V).

Symbol Parameter Conditions Min Typ Max Unit

VOH HIGH-level output voltage VI = VIH or VIL

IO=1.5 mA; VCC(A) =V

CC(B) = 0.8 V - 0.69 - V

VOL LOW-level output voltage VI = VIH or VIL

IO = 1.5 mA; VCC(A) =V

CC(B) = 0.8 V - 0.07 - V

IIinput leakage current DIR input; VI = 0 V or 3.6 V;

VCC(A) =V

CC(B) = 0.8 V to 3.6 V -0.025 0.25 A

IOZ OFF-state output current A or B port; VO=0 Vor V

CCO;

VCC(A) =V

CC(B) = 0.8 V to 3.6 V [3] -0.5 2.5 A

IOFF power-off leakage current A port; VI or VO = 0 V to 3.6 V;

VCC(A) =0V;V

CC(B) = 0.8 V to 3.6 V -0.1 1A

B port; VI or VO = 0 V to 3.6 V;

VCC(B) =0V;V

CC(A) = 0.8 V to 3.6 V -0.1 1A

CIinput capacitance DIR input; VI= 0 V or 3.3 V;

VCC(A) =V

CC(B) =3.3V -1.0-pF

CI/O input/output capacitance A and B port; Suspend mod e;

VO=V

CCO or GND; VCC(A) =V

CC(B) =3.3V -4.0-pF

Table 8. Static characteristics [1][2]

At recommended operating conditions; voltages are referenced to GND (ground = 0 V).

Symbol Parameter Conditions 40 C to +85 C40 C to +125 CUnit

Min Max Min Max

VIH HIGH-level

input voltage data input

VCCI = 0.8 V 0.70VCCI - 0.70VCCI -V

VCCI = 1.1 V to 1.95 V 0.65VCCI - 0.65VCCI -V

VCCI = 2.3 V to 2.7 V 1.6 - 1.6 - V

VCCI = 3.0 V to 3.6 V 2 - 2 - V

DIR input

VCC(A) = 0.8 V 0.70VCC(A) -0.70V

CC(A) -V

VCC(A) = 1.1 V to 1.95 V 0.65VCC(A) -0.65V

CC(A) -V

VCC(A) = 2.3 V to 2.7 V 1.6 - 1.6 - V

VCC(A) = 3.0 V to 3.6 V 2 - 2 - V

Product data sheet Rev. 2 — 8 April 2013 6 of 20

NXP Semiconductors 74AVC1T45-Q100

Dual-supply voltage level translator/transceiver; 3-state

VIL LOW-level

input voltage data input

VCCI = 0.8 V - 0.30VCCI - 0.30VCCI V

VCCI = 1.1 V to 1.95 V - 0.3 5VCCI - 0.35VCCI V

VCCI = 2.3 V to 2.7 V - 0.7 - 0.7 V

VCCI = 3.0 V to 3.6 V - 0.9 - 0.9 V

DIR input

VCC(A) = 0.8 V - 0.30VCC(A) - 0.30VCC(A) V

VCC(A) = 1.1 V to 1.95 V - 0.35VCC(A) - 0.35VCC(A) V

VCC(A) = 2.3 V to 2.7 V - 0.7 - 0.7 V

VCC(A) = 3.0 V to 3.6 V - 0.9 - 0.9 V

VOH HIGH-level

output voltage VI = VIH or VIL

IO=100 A;

VCC(A) =V

CC(B) = 0.8 V to 3.6 V VCCO  0.1 - VCCO  0.1 - V

IO = 3mA;

VCC(A) =V

CC(B) =1.1V 0.85 - 0.85 - V

IO = 6mA;

VCC(A) =V

CC(B) =1.4V 1.05 - 1.05 - V

IO = 8mA;

VCC(A) =V

CC(B) =1.65V 1.2 - 1.2 - V

IO = 9mA;

VCC(A) =V

CC(B) =2.3V 1.75 - 1.75 - V

IO = 12 mA;

VCC(A) =V

CC(B) =3.0V 2.3 - 2.3 - V

VOL LOW-level

output voltage VI = VIH or VIL

IO = 100 A;

VCC(A) =V

CC(B) = 0.8 V to 3.6 V -0.1-0.1V

IO = 3 mA; VCC(A) =V

CC(B) = 1.1 V - 0.25 - 0.25 V

IO = 6 mA; VCC(A) =V

CC(B) = 1.4 V - 0.35 - 0.35 V

IO = 8 mA;

VCC(A) =V

CC(B) =1.65V - 0.45 - 0.45 V

IO = 9 mA; VCC(A) =V

CC(B) = 2.3 V - 0.55 - 0.55 V

IO = 12 mA;

VCC(A) =V

CC(B) =3.0V -0.7-0.7V

IIinput leakage

current DIR input; VI = 0 V or 3.6 V;

VCC(A) =V

CC(B) = 0.8 V to 3.6 V -1-1.5 A

IOZ OFF-state

output current A or B port; VO=0 Vor V

CCO;

VCC(A) =V

CC(B) =3.6V [3] -5-7.5 A

IOFF power-off

leakage

current

A port; VI or VO = 0 V to 3.6 V;

VCC(A) =0V; V

CC(B) = 0.8 V to 3.6 V -5-35 A

B port; VI or VO = 0 V to 3.6 V;

VCC(B) =0V; V

CC(A) = 0.8 V to 3.6 V -5-35 A

Table 8. Static characteristics …continued[1][2]

At recommended operating conditions; voltages are referenced to GND (ground = 0 V).

Symbol Parameter Conditions 40 C to +85 C40 C to +125 CUnit

Min Max Min Max

Product data sheet Rev. 2 — 8 April 2013 7 of 20

NXP Semiconductors 74AVC1T45-Q100

Dual-supply voltage level translator/transceiver; 3-state

[1] VCCO is the supply voltage associated with the output port.

[2] VCCI is the supply voltage associated with the data input port.

[3] For I/O ports, the parameter IOZ includes the input leakage current.

ICC supply current A port; VI = 0 V or VCCI; IO = 0 A

VCC(A) = 0.8 V to 3.6 V;

VCC(B) = 0.8 V to 3.6 V -8-12A

VCC(A) = 3.6 V; VCC(B) = 0 V - 8 - 12 A

VCC(A) = 0 V; VCC(B) = 3.6 V 2-8-A

B port; VI = 0 V or VCCI; IO = 0 A

VCC(A) = 0.8 V to 3.6 V;

VCC(B) = 0.8 V to 3.6 V -8-12A

VCC(A) = 3.6 V; VCC(B) = 0 V 2-8-A

VCC(A) = 0 V; VCC(B) = 3.6 V - 8 - 12 A

A plus B port (ICC(A) + ICC(B));

IO=0A; V

I=0 Vor V

CCI;

VCC(A) = 0.8 V to 3.6 V;

VCC(B) = 0.8 V to 3.6 V

-16-24A

Table 8. Static characteristics …continued[1][2]

At recommended operating conditions; voltages are referenced to GND (ground = 0 V).

Symbol Parameter Conditions 40 C to +85 C40 C to +125 CUnit

Min Max Min Max

Product data sheet Rev. 2 — 8 April 2013 8 of 20

NXP Semiconductors 74AVC1T45-Q100

Dual-supply voltage level translator/transceiver; 3-state

11. Dynamic characteristics

[1] tpd is the same as tPLH and tPHL; tdis is the same as tPLZ and tPHZ; ten is the same as tPZL and tPZH.

ten is a calculated value using the formula shown in Section 13.4 “Enable times”

[1] tpd is the same as tPLH and tPHL; tdis is the same as tPLZ and tPHZ; ten is the same as tPZL and tPZH.

ten is a calculated value using the formula shown in Section 13.4 “Enable times”

[1] CPD is used to determine the dynamic power dissipation (PD in W).

PD=C

PD VCC2fiN+(CLVCC2fo) where:

fi= input frequency in MHz;

fo= output frequency in MHz;

CL= load capacitance in pF;

VCC = supply voltage in V;

N = number of inputs switching;

(CLVCC2fo) = sum of the outputs.

[2] fi = 10 MHz; VI=GNDtoV

CC; tr = tf = 1 ns; CL = 0 pF; RL =  .

Table 9. Typical dynamic characteristics at VCC(A) = 0.8 V and Tamb = 25 C [1]

Vo ltages are referenced to GND (ground = 0 V); for test circuit see Figure 6; for wave forms see Figure 4 and Figure 5

Symbol Parameter Conditions VCC(B) Unit

0.8 V 1.2 V 1.5 V 1.8 V 2.5 V 3.3 V

tpd propagation delay A to B 15.5 8.1 7.6 7.7 8.4 9.2 ns

B to A 15.5 12.7 12.3 12.2 12.0 11.8 ns

tdis disable time DIR to A 12.2 12.2 12.2 12.2 12.2 12.2 ns

DIR to B 11.7 7.9 7.6 8.2 8.7 10.2 ns

ten enable time DIR to A 27.2 20.6 19.9 20.4 20.7 22.0 ns

DIR to B 27.7 20.3 19.8 19.9 20.6 21.4 ns

Table 10. Typical dynamic characteristics at VCC(B) = 0.8 V and Tamb = 25 C [1]

Vo ltages are referenced to GND (ground = 0 V); for test circuit see Figure 6; for wave forms see Figure 4 and Figure 5

Symbol Parameter Conditions VCC(A) Unit

0.8 V 1.2 V 1.5 V 1.8 V 2.5 V 3.3 V

tpd propagation delay A to B 15.5 12.7 12.3 12.2 12.0 11.8 ns

B to A 15.5 8.1 7.6 7.7 8.4 9.2 ns

tdis disable time DIR to A 12.2 4.9 3.8 3.7 2.8 3.4 ns

DIR to B 11.7 9.2 9.0 8.8 8.7 8.6 ns

ten enable time DIR to A 27.2 17.3 16.6 16.5 17.1 17.8 ns

DIR to B 27.7 17.6 16.1 15.9 14.8 15.2 ns

Table 11. Typica l power dissipation capacitance at VCC(A) = VCC(B) and Tamb = 25 C [1][2]

Vo ltages are referenced to GND (ground = 0 V).

Symbol Parameter Conditions VCC(A) and VCC(B) Unit

0.8 V 1.2 V 1.5 V 1.8 V 2.5 V 3.3 V

CPD power dissipation

capacitance A port: (direction A to B);

B port: (direction B to A) 122222pF

A port: (direction B to A);

B port: (direction A to B) 91111121417pF

Product data sheet Rev. 2 — 8 April 2013 9 of 20

NXP Semiconductors 74AVC1T45-Q100

Dual-supply voltage level translator/transceiver; 3-state

[1] tpd is the same as tPLH and tPHL; tdis is the same as tPLZ and tPHZ; ten is the same as tPZL and tPZH.

ten is a calculated value using the formula shown in Section 13.4 “Enable times”

Table 12 . Dynamic characteristics for temperature ran ge 40 C to +85 C [1]

Vo ltages are referenced to GND (ground = 0 V); for test circuit see Figure 6; for wave forms see Figure 4 and Figure 5.

Symbol Parameter Conditions VCC(B) Unit

1.2 V  0.1 V 1.5 V  0.1 V 1.8 V  0.15 V 2.5 V  0.2 V 3.3 V  0.3 V

Min Max Min Max Min Max Min Max Min Max

VCC(A) = 1.1 V to 1.3 V

tpd propagation

delay A to B 1.0 9.0 0.7 6.8 0.6 6.1 0.5 5.7 0.5 6.1 ns

B to A 1.0 9.0 0.8 8.0 0.7 7.7 0.6 7.2 0.5 7.1 ns

tdis disable time DIR to A 2.2 8.8 2.2 8.8 2.2 8.8 2.2 8.8 2.2 8.8 ns

DIR to B 2.2 8.4 1.8 6.7 2.0 6.9 1.7 6.2 2.4 7.2 ns

ten enable time DIR to A - 17.4 - 14.7 - 14.6 - 13.4 - 14.3 ns

DIR to B - 17.8 - 15.6 - 14.9 - 14.5 - 14.9 ns

VCC(A) = 1.4 V to 1.6 V

tpd propagation

delay A to B 1.0 8.0 0.7 5.4 0.6 4.6 0.5 3.7 0.5 3.5 ns

B to A 1.0 6.8 0.8 5.4 0.7 5.1 0.6 4.7 0.5 4.5 ns

tdis disable time DIR to A 1.6 6.3 1.6 6.3 1.6 6.3 1.6 6.3 1.6 6.3 ns

DIR to B 2.0 7.6 1.8 5.9 1.6 6.0 1.2 4.8 1.7 5.5 ns

ten enable time DIR to A - 14.4 - 11.3 - 11.1 - 9.5 - 10.0 ns

DIRtoB -14.3-11.7-10.9-10.0- 9.8ns

VCC(A) = 1.65 V to 1.95 V

tpd propagation

delay A to B 1.0 7.7 0.6 5.1 0.5 4.3 0.5 3.4 0.5 3.1 ns

B to A 1.0 6.1 0.7 4.6 0.5 4.4 0.5 3.9 0.5 3.7 ns

tdis disable time DIR to A 1.6 5.5 1.6 5.5 1.6 5.5 1.6 5.5 1.6 5.5 ns

DIR to B 1.8 7.7 1.8 5.7 1.4 5.8 1.0 4.5 1.5 5.2 ns

ten enable time DIR to A - 13.8 - 10.3 - 10.2 - 8.4 - 8.9 ns

DIR to B - 13.2 - 10.6 - 9.8 - 8.9 - 8.6 ns

VCC(A) = 2.3V to 2.7V

tpd propagation

delay A to B 1.0 7.2 0.5 4.7 0.5 3.9 0.5 3.0 0.5 2.6 ns

B to A 1.0 5.7 0.6 3.8 0.5 3.4 0.5 3.0 0.5 2.8 ns

tdis disable time DIR to A 1.5 4.2 1.5 4.2 1.5 4.2 1.5 4.2 1.5 4.2 ns

DIR to B 1.7 7.3 2.0 5.2 1.5 5.1 0.6 4.2 1.1 4.8 ns

ten enable time DIR to A - 13.0 - 9.0 - 8.5 - 7.2 - 7.6 ns

DIR to B - 11.4 - 8.9 - 8.1 - 7.2 - 6.8 ns

VCC(A) = 3.0V to 3.6V

tpd propagation

delay A to B 1.0 7.1 0.5 4.5 0.5 3.7 0.5 2.8 0.5 2.4 ns

B to A 1.0 6.1 0.6 3.6 0.5 3.1 0.5 2.6 0.5 2.4 ns

tdis disable time DIR to A 1.5 4.7 1.5 4.7 1.5 4.7 1.5 4.7 1.5 4.7 ns

DIR to B 1.7 7.2 0.7 5.5 0.6 5.5 0.7 4.1 1.7 4.7 ns

ten enable time DIR to A - 13.3 - 9.1 - 8.6 - 6.7 - 7.1 ns

DIR to B - 11.8 - 9.2 - 8.4 - 7.5 - 7.1 ns

Product data sheet Rev. 2 — 8 April 2013 10 of 20

NXP Semiconductors 74AVC1T45-Q100

Dual-supply voltage level translator/transceiver; 3-state

[1] tpd is the same as tPLH and tPHL; tdis is the same as tPLZ and tPHZ; ten is the same as tPZL and tPZH.

ten is a calculated value using the formula shown in Section 13.4 “Enable times”

Table 13 . Dynamic characteristics for temperature ran ge 40 C to +125 C [1]

Vo ltages are referenced to GND (ground = 0 V); for test circuit see Figure 6; for wave forms see Figure 4 and Figure 5

Symbol Parameter Conditions VCC(B) Unit

1.2 V  0.1 V 1.5 V  0.1 V 1.8 V  0.15 V 2.5 V  0.2 V 3.3 V  0.3 V

Min Max Min Max Min Max Min Max Min Max

VCC(A) = 1.1 V to 1.3 V

tpd propagation

delay A to B 1.0 9.9 0.7 7.5 0.6 6.8 0.5 6.3 0.5 6.8 ns

B to A 1.0 9.9 0.8 8.8 0.7 8.5 0.6 8.0 0.5 7.9 ns

tdis disable time DIR to A 2.2 9.7 2.2 9.7 2.2 9.7 2.2 9.7 2.2 9.7 ns

DIR to B 2.2 9.2 1.8 7.4 2.0 7.6 1.7 6.9 2.4 8.0 ns

ten enable time DIR to A - 19.1 - 16 .2 - 16.1 - 14.9 - 15.9 ns

DIR to B - 19.6 - 17.2 - 16.5 - 16.0 - 16.5 ns

VCC(A) = 1.4 V to 1.6 V

tpd propagation

delay A to B 1.0 8.8 0.7 6.0 0.6 5.1 0.5 4.1 0.5 3.9 ns

B to A 1.0 7.5 0.8 6.0 0.7 5.7 0.6 5.2 0.5 5.0 ns

tdis disable time DIR to A 1.6 7.0 1.6 7.0 1.6 7.0 1.6 7.0 1.6 7.0 ns

DIR to B 2.0 8.3 1.8 6.5 1.6 6.6 1.2 5.3 1.7 6.1 ns

ten enable time DIR to A - 15.8 - 12 .5 - 1 2.3 - 10.5 - 11.1 ns

DIR to B - 15.8 - 13.0 - 12.1 - 11.1 - 10.9 ns

VCC(A) = 1.65 V to 1.95 V

tpd propagation

delay A to B 1.0 8.5 0.6 5.7 0.5 4.8 0.5 3.8 0.5 3.5 ns

B to A 1.0 6.8 0.7 5.1 0.5 4.9 0.5 4.3 0.5 4.1 ns

tdis disable time DIR to A 1.6 6.1 1.6 6.1 1.6 6.1 1.6 6.1 1.6 6.1 ns

DIR to B 1.8 8.5 1.8 6.3 1.4 6.4 1.0 5.0 1.5 5.8 ns

ten enable time DIR to A - 15.3 - 11.4 - 11.3 - 9.3 - 9.9 ns

DIR to B - 14.6 - 11.8 - 10.9 - 9.9 - 9.6 ns

VCC(A) = 2.3V to 2.7V

tpd propagation

delay A to B 1.0 8.0 0.5 5.2 0.5 4.3 0.5 3.3 0.5 2.9 ns

B to A 1.0 6.3 0.6 4.2 0.5 3.8 0.5 3.3 0.5 3.1 ns

tdis disable time DIR to A 1.5 4.7 1.5 4.7 1.5 4.7 1.5 4.7 1.5 4.7 ns

DIR to B 1.7 8.0 2.0 5.8 1.5 5.7 0.6 4.7 1.1 5.3 ns

ten enable time DIR to A - 14.3 - 10.0 - 9.5 - 8.0 - 8.4 ns

DIR to B - 12.7 - 9.9 - 9.0 - 8.0 - 7.6 ns

VCC(A) = 3.0V to 3.6V

tpd propagation

delay A to B 1.0 7.9 0.5 5.0 0.5 4.1 0.5 3.1 0.5 2.7 ns

B to A 1.0 6.8 0.6 4.0 0.5 3.5 0.5 2.9 0.5 2.7 ns

tdis disable time DIR to A 1.5 5.2 1.5 5.2 1.5 5.2 1.5 5.2 1.5 5.2 ns

DIR to B 1.7 7.9 0.7 6.1 0.6 6.1 0.7 4.6 1.7 5.2 ns

ten enable time DIR to A - 14.7 - 10.1 - 9.6 - 7.5 - 7.9 ns

DIR to B - 13.1 - 10.2 - 9.3 - 8.3 - 7.9 ns

Product data sheet Rev. 2 — 8 April 2013 11 of 20

NXP Semiconductors 74AVC1T45-Q100

Dual-supply voltage level translator/transceiver; 3-state

12. Waveforms

[1] VCCI is the supply voltage associated with the data input port.

[2] VCCO is the supply voltage associated with the output port.

Measurement points are given in Table 14.

VOL and VOH are typical output voltage levels that occur with the output load.

Fig 4. The data input (A, B) to output (B, A) propagation delay times

001aae967

A, B input

B, A output

tPLH

tPHL

GND

VOH

VOL

Measurement points are given in Table 14.

VOL and VOH are typical output voltage levels that occur with the output load.

Fig 5. Enable and disable times

001aae968

PZL

PZH

PHZ

PLZ

GND

CCO

outputs

disabled outputs

enabled

outputs

enabled

output

LOW-to-OFF

OFF-to-LOW

output

HIGH-to-OFF

OFF-to-HIGH

DIR input

Table 14 . Measurement points

Supply voltage Input[1] Output[2]

VCC(A), VCC(B) VMVMVXVY

1.1 V to 1.6 V 0.5VCCI 0.5VCCO VOL +0.1V V

OH 0.1 V

1.65 V to 2.7 V 0.5VCCI 0.5VCCO VOL +0.15V V

OH 0.15 V

3.0 V to 3.6 V 0.5VCCI 0.5VCCO VOL +0.3V V

OH 0.3 V

Product data sheet Rev. 2 — 8 April 2013 12 of 20

NXP Semiconductors 74AVC1T45-Q100

Dual-supply voltage level translator/transceiver; 3-state

[1] VCCI is the supply voltage associated with the data input port.

[2] dV/dt  1.0 V/ns

[3] VCCO is the supply voltage associated with the output port.

Test data is given in Table 15.

RL = Load resistance.

CL = Load capacitance including jig and probe capacitance.

RT = Termination resistance.

VEXT = External voltage for measuring switching times.

Fig 6. Test circuit for measuring switching times

10 %

90 %

0 V

negative

pulse

positive

pulse

0 V

90 %

10 %

001aae331

EXT

DUT

Table 15 . Test da ta

Supply voltage Input Load VEXT

VCC(A), VCC(B) VI[1] t/V[2] CLRLtPLH, tPHL tPZH, tPHZ tPZL, tPLZ[3]

1.1 V to 1.6 V VCCI 1.0ns/V 15pF 2kopen GND 2VCCO

1.65 V to 2.7 V VCCI  1.0ns/V 15pF 2kopen GND 2VCCO

3.0 V to 3.6 V VCCI  1.0ns/V 15pF 2kopen GND 2VCCO

Product data sheet Rev. 2 — 8 April 2013 13 of 20

NXP Semiconductors 74AVC1T45-Q100

Dual-supply voltage level translator/transceiver; 3-state

13. Application information

13.1 Unidirectional logic level-shifting application

The circuit given in Figure 7 is an example of the 74AVC1T45-Q100 being used in a

unidirectional logic level-shifting application.

Fig 7. Unidirectional logic level-shifting application

Table 16. Description unidirection al lo gic level-shifting application

Pin Name Function Description

CC(A) VCC1 supply voltage of system-1 (0.8 V to 3.6 V)

2 GND GND device GND

3 A OUT output level depends on VCC1 voltage

4 DIR DIR the GND (LOW level) determines B port to A port direction

5 B IN input threshold value depends on VCC2 voltage

CC(B) VCC2 supply voltage of system-2 (0.8 V to 3.6 V)

$9&74



&&$



*1'









&&%

',5

V\VWHP

V\V

WHP

&&

DDD

&&

Product data sheet Rev. 2 — 8 April 2013 14 of 20

NXP Semiconductors 74AVC1T45-Q100

Dual-supply voltage level translator/transceiver; 3-state

13.2 Bidirectional logic level-shifting application

Figure 8 shows the 74AVC1T45-Q100 being used in a bidirectional logic level-shifting

application. Sinc e th e de vice does no t ha ve an output enable pin, take precautions to

avoid bus contention between system-1 and system-2 when changing directions.

Table 17 gives a sequence that illustrates data transmission from system-1 to system-2

and then from system-2 to system-1.

[1] H = HIGH voltage level;

L = LOW voltage level;

Z = high-impedance OFF-state.

Fig 8. Bidirectional logic level-shifting application

Tabl e 17. Description bidirectional logic level-shifting applicat ion[1]

State DIR CTRL I/O-1 I/O-2 Description

1 H output input system-1 data to system-2

2 H Z Z system-2 is getting ready to send data to system-1.

I/O-1 and I/O-2 are disabled. The bus-line state

depends on bus hold.

3 L Z Z DIR bit is set LOW. I/O-1 and I/O-2 are still disabled.

The bus-line state depends on bus hold.

4 L input output system-2 data to system-1

',5&75/

,2 ,2

$9&74



9&&$

9&&



*1'









9&&%

',5

38//83'2:1

V\VWHP V\VWHP

38//83'2:1

DDD

9&&

Product data sheet Rev. 2 — 8 April 2013 15 of 20

NXP Semiconductors 74AVC1T45-Q100

Dual-supply voltage level translator/transceiver; 3-state

13.3 Power-up considerations

The device is designed such that no special power-up sequence is required other than

GND being applied first.

13.4 Enable times

Calculate the enable times for the 74AVC1T45-Q100 using the following formulas:

•ten (DIR to A) = tdis (DIR to B) + tpd (B to A)

•ten (DIR to B) = tdis (DIR to A) + tpd (A to B)

In a bidirectional application, these enable times provide the maximum delay from the

time the DIR bit is switched until an output is expected. For example, if the

74AVC1T45-Q100 initially transmits from A to B, the DIR bit is switched and the B port of

the device must be disabled before presenting it with an input. After the B port has been

disabled, an input signal applied to it appears on the corresponding A port after the

specified propagation delay.

Table 18. Typical total supply current (ICC(A) + ICC(B))

VCC(A) VCC(B) Unit

0 V 0.8 V 1.2 V 1.5 V 1.8 V 2.5 V 3.3 V

0 V 0 0.1 0.1 0.1 0.1 0.1 0.1 A

0.8 V 0.1 0.1 0.1 0.1 0.1 0.7 2.3 A

1.2 V 0.1 0.1 0.1 0.1 0.1 0.3 1.4 A

1.5 V 0.1 0.1 0.1 0.1 0.1 0.1 0.9 A

1.8 V 0.1 0.1 0.1 0.1 0.1 0.1 0.5 A

2.5 V 0.1 0.7 0.3 0.1 0.1 0.1 0.1 A

3.3 V 0.1 2.3 1.4 0.9 0.5 0.1 0.1 A

Product data sheet Rev. 2 — 8 April 2013 16 of 20

NXP Semiconductors 74AVC1T45-Q100

Dual-supply voltage level translator/transceiver; 3-state

14. Package outline

Fig 9. Package outline SOT3 63 (SC-88 )

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

SOT363 SC-88

wBM

pin 1

index A

detail X

vMA

0 1 2 mm

scale

132

456

Plastic surface-mounted package; 6 leads SOT363

UNIT A1

max bpcDEe1HELpQywv

mm 0.1 0.30

0.20 2.2

1.8

0.25

0.10 1.35

1.15 0.65

1.3 2.2

2.0 0.2 0.10.2

DIMENSIONS (mm are the original dimensions)

0.45

0.15 0.25

0.15

1.1

0.8

04-11-08

06-03-16

Product data sheet Rev. 2 — 8 April 2013 17 of 20

NXP Semiconductors 74AVC1T45-Q100

Dual-supply voltage level translator/transceiver; 3-state

15. Abbreviations

16. Revision history

Table 19. Abbreviations

Acronym Description

CDM Charged Device Mo del

CMOS Complementary Metal Oxide Semiconductor

DUT Device Under Test

ESD ElectroStatic Discharge

HBM Human Body Model

MM Machine Model

MIL Military

Table 20. Revision history

Document ID Release date Data sheet status Change notice Supersedes

74AVC1T45_Q100 v.2 20130408 Product data sheet - 74AVC1T45 _Q100 v.1

Modifications: •Type number 74AVC1T45GM-Q100 has been removed.

74AVC1T45_Q100 v.1 20120820 Product data sheet - -

Product data sheet Rev. 2 — 8 April 2013 18 of 20

NXP Semiconductors 74AVC1T45-Q100

Dual-supply voltage level translator/transceiver; 3-state

17. Legal information

17.1 Data sheet status

[1] Please consult the most recently issued document before initiating or completing a design.

[2] The term ‘short data sheet’ is explained in section “Definitions”.

[3] The product status of de vice(s) descr ibed in th is docume nt may have cha nged since this docume nt was publis hed and ma y dif fer in case of multiple devices. The latest product status

information is available on the Internet at URL http://www.nxp.com.

17.2 Definitions

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modifications or additions. NXP Semiconductors does not give any

representations or warranties as to the accuracy or completeness of

information included herein and shall have no liab ility for the consequences of

use of such information.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and tit le. A short data sh eet is intended

for quick reference only and shou ld not be rel ied u pon to cont ain det ailed and

full information. For detailed and full information see the relevant full data

sheet, which is available on request via the local NXP Semiconductors sales

office. In case of any inconsistency or conf lict with the short data sheet, the

full data sheet shall pre vail.

Product specification — The information and data provided in a Product

data sheet shall define the specification of the product as agr eed between

NXP Semiconductors and its customer, unless NXP Semiconductors and

customer have explicitly agreed otherwise in writing. In no event however,

shall an agreement be valid in which the NXP Semiconductors product is

deemed to off er functions and qualities beyon d those described in the

Product data sheet.

17.3 Disclaimers

Limited warr a nty and liability — Information in this document is believed to

be accurate and reliable. However, NXP Semiconductors does not give any

representations or warranties, expressed or implied, as to the accuracy or

completeness of such information and shall have no liability for the

consequences of use of such information. NXP Se miconductors takes no

responsibility for the content in this document if provided by an inf ormation

source outside of NXP Semiconductors.

In no event shall NXP Semiconductors be liable for any indirect, incidenta l ,

punitive, special or consequ ential damages (including - wit hout limitatio n - lost

profits, lost savings, business interruption, costs related to the removal or

replacement of any products or rework charges) whether or not such

damages are based on tort (including negligence), warranty, breach of

contract or any other legal theory.

Notwithstanding any damages that customer might incur for any reason

whatsoever, NXP Semiconductors’ ag gregate and cumulative l iability toward s

customer for the products described herein shall be limited in accordance

with the Terms and conditions of commercial sale of NXP Semiconductors.

Right to make changes — NXP Semiconductors reserves the right to make

changes to information published in this document, including without

limitation specifications and product descripti ons, at any time and without

notice. This document supersedes and replaces all informa tion supplied prior

to the publication hereof .

Suitability for use in automotive applications — T his NXP

Semiconductors product has been qualified for use in automotive

applications. Unless ot herwise agreed in writing, t he product is not designed,

authorized or warranted to be suitable for use in life support, life-critical or

safety-critical systems or equipment, nor in applications where failure or

malfunction of an NXP Semiconductors product can reasonably be expected

to result in perso nal injury, death or severe property or environmental

damage. NXP Semiconductors and its suppliers accept no liability for

inclusion and/or use of NXP Semiconducto rs products in such equipment or

applications an d ther efo re su ch inclusi on a nd/or use is at the cu stome r's own

risk.

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. NXP Semiconductors makes no

representation or warranty tha t such application s will be suitable for the

specified use without further testing or modification.

Customers are responsible for the design and ope ration of their applications

and products using NXP Semiconductors product s, and NXP Semiconductors

accepts no liability for any assistance with applications or customer product

design. It is customer’s sole responsibility to determine whether the NXP

Semiconductors product is suit able and fit for the custome r’s applications and

products planned, as well as fo r the planned application and use of

customer’s third party customer(s). Customers should provide appropriate

design and operating safeguards to minimize the risks associate d with t heir

applications and products.

NXP Semiconductors does not accept any liabil ity related to any default,

damage, costs or problem which is based on any weakness or default in the

customer’s applications or products, or the application or use by customer’s

third party customer(s). Customer is responsible for doing all necessary

testing for th e customer’s applications and pro ducts using NXP

Semiconductors products in order to avoid a default of the applications and

the products or of the application or use by customer’s third party

customer(s). NXP does not accept any liability in this respect.

Limiting values — Stress above one or more limiting values (as defined in

the Absolute Maximum Ratings System of IEC 60134) will cause permanent

damage to the device. Limiting values are stress rating s only and (proper)

operation of the device at these or any other conditions above those given in

the Recommended operating conditions section (if present) or the

Characteristics sections of this document is not warranted. Constant or

repeated exposure to limiting values will permanent ly and irreversibly affect

the quality and reliability of the device.

Terms and conditions of commercial sale — NXP Semiconductors

products are sold subject to the general terms and conditions of commercial

sale, as published at http://www.nxp.com/profile/terms, unless otherwise

agreed in a valid written individua l agreement. In case an individual

agreement is concluded only the ter ms and conditions of the respective

agreement shall apply. NXP Semiconductors hereby expressly object s to

applying the customer’s general terms and conditions with regard to the

purchase of NXP Semiconductors products by customer.

Document status[1][2] Product status[3] Definition

Objective [short] data sheet Development This document contains data from the objective specificati on for product development.

Preliminary [short] dat a sheet Qualification This document contains data from the preliminary specificat ion.

Product [short] dat a sheet Production This document contains the product specification.

Product data sheet Rev. 2 — 8 April 2013 19 of 20

NXP Semiconductors 74AVC1T45-Q100

Dual-supply voltage level translator/transceiver; 3-state

No offer to sell or license — Nothing in this document may be interpret ed or

construed as an of fer to sell product s that is op en for accept ance or the grant ,

conveyance or implication of any license under any copyrights, patents or

other industrial or intellectual property rights.

Export control — This document as well as the item(s) described herein

may be subject to export control regulations. Export might require a prior

authorization from competent authorities.

Translations — A non-English (translated) version of a document is for

reference only. The English version shall prevail in case of any discrepancy

between the translated and English versions.

17.4 Trademarks

Notice: All referenced b rands, produc t names, service names and trademarks

are the property of their respect i ve ow ners.

18. Contact information

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an em ail to: salesaddresses@nxp.com

NXP Semiconductors 74AVC1T45-Q100

Dual-supply voltage level translator/transceiver; 3-state

For more information, please visit: http://www.nxp.co m

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 8 April 2013

Document identifier : 74AVC1T45_Q100

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section ‘Legal information’.

19. Contents

1 General description. . . . . . . . . . . . . . . . . . . . . . 1

2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1

3 Ordering information. . . . . . . . . . . . . . . . . . . . . 2

4 Marking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

5 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2

6 Pinning information. . . . . . . . . . . . . . . . . . . . . . 3

6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3

7 Functional description . . . . . . . . . . . . . . . . . . . 3

8 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4

9 Recommended operating conditions. . . . . . . . 4

10 Static characteristics. . . . . . . . . . . . . . . . . . . . . 5

11 Dynamic characteristics . . . . . . . . . . . . . . . . . . 8

12 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

13 Application information. . . . . . . . . . . . . . . . . . 13

13.1 Unidirectional logic level-shifting application . 13

13.2 Bidirectional logic level-shifting application. . . 14

13.3 Power-up considerations . . . . . . . . . . . . . . . . 15

13.4 Enable times. . . . . . . . . . . . . . . . . . . . . . . . . . 15

14 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 16

15 Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 17

16 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 17

17 Legal information. . . . . . . . . . . . . . . . . . . . . . . 18

17.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 18

17.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

17.3 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 18

17.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 19

18 Contact information. . . . . . . . . . . . . . . . . . . . . 19

19 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20