Mixed Signal ISP Flash MCU Fa mily
C8051F060/1/2/3/4/5/6/7
Preliminary Rev. 1.2 7/04 Copyright © 2004 by Silicon Labo rato ries C8051F060/1/2/3/4/5/6/7
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
Analog Peripherals
-Two 16-Bit SAR ADCs
•16-bit resolution
•±0.75 LSB INL, guaranteed no missing codes
•Programmable throughput up to 1 Msps
•Operate as two single-ended or one differential con-
verter
•Direct memory access; data stored in RAM without
software overhead
•Data-dependent windowed interrupt generator
-10-bit SAR ADC (C8051F060/1/2/3)
•Programmable throughput up to 200 ksps
•8 external inputs, single-ended or differential
•Built-in temperature sensor
-Two 12-bit DACs (C8051F060/1/2/3)
•Can synchronize outputs to timers for jitter-free wave-
form generation
-Three Analog Comparators
•Programmable hysteresis/response time
-Voltage Refer e nc e
-Precision VDD Monitor/Brown-Out Detector
On-Chip JTAG Debug & Boundary Scan
-On-chip debug circuitry facilitates full-speed, non-
intrusive in-circuit/in-system debugging
-Provides breakpoints, single-stepping, watchpoints,
stack monitor; inspect/modify memory and registers
-Superior performance to emulation systems using
ICE-chips, target pods, and sockets
-IEEE1149.1 compliant boundary scan
-Complete development kit
High Speed 8051 C Core
-Pipelined instruction architecture; executes 70% of
instruction set in 1 or 2 system clocks
-Up to 25 MIPS throughput with 25 MHz clock
-Flexible Interrupt sources
Memory
-4352 Bytes internal data RAM (4 k + 256)
-64 kB (C8051F060/1/2/3/4/5), 32 kB (C8051F066/7)
Flash; In-system programmable in 512-byte sectors
-External 64 kB data memory interface with multi-
plexed and non-multiplexed modes (C8051F060/2/
4/6)
Digital Peripherals
-59 general purpose I/O pins (C8051F060/2/4/6)
-24 general purpose I/O pins (C8051F061/3/5/7)
-Bosch Controller Area Network (CAN 2.0B -
C8051F060/1/2/3)
-Hardware SMBus™ (I2C™ Compatible), SPI™, and
two UART serial ports available concurrently
-Programmable 16-bit counter/timer array with
6 capture/compare modules
-5 gen eral purpose 16-bit counter/timers
-Dedicated watchdog timer; bi-directional reset pin
Clock Sources
-Internal calibrated precision oscillator: 24.5 MHz
-External oscillator: Crystal, RC, C, or clock
Supply Voltage .................. .... ... . 2. 7 to 3.6 V
-Multiple power saving sleep and shutdown modes
100-Pin and 64-Pin TQFP Packages Available
Temperature Range: -40 to +85 °C
JTAG
64/ 32 kB
ISP FLASH 4352 B
SRAM SANITY
CONTROL
16-bit
1 Msps
ADC
CLOCK
CIRCUIT
TEMP
SENSOR
ANALOG PERIPHERALS Port 0
Port 1
Port 2
CROSSBAR
DIGITAL I/O
HIGH-SPEED CONTROLLER CORE
DEBUG
CIRCUITRY
22
INTERRUPTS
8051 CPU
(25MIPS)
10-bit
200ksps
ADC
Port 4
Port 5
Port 6
Port 7
External Memory
Interface
100 pin Only
UART0
SMBus
SPI Bus
PCA
Timer 0
Timer 1
Timer 2
Timer 3
Timer 4
UART1
CAN 2. 0 B
C8051F060/1/2/3
AMUX
VREF
DMA
Interface
16-bit
1 Msps
ADC
12-Bit
DAC
VOLTAGE
COMPARATOR
S
12-Bit
DAC
Port 3
+
-
+
-
+
-
C8051 F060/1/2/3 Only
C8051F060/1/2/3/4/5/6/7
2 Rev. 1.2
C8051F060/1/2/3/4/5/6/7
Rev. 1.2 3
Table of Contents
1. System Overview.................................................................................................... 19
1.1. CIP-51™ Microcontroller Core.......................................................................... 25
1.1.1. Fully 8051 Compatible.............................................................................. 25
1.1.2. Improved Throughput............................................................................... 25
1.1.3. Additional Features .................................................................................. 26
1.2. On-Chip Memory............................................................................................... 27
1.3. JTAG Debug and Boundary Scan..................................................................... 28
1.4. Programmable Digital I/O and Crossbar........................................................... 29
1.5. Programmable Counter Array........................................................................... 30
1.6. Controller Area Network.................................................................................... 31
1.7. Serial Ports ....................................................................................................... 32
1.8. 16-Bit Analog to Digital Converters................................................................... 33
1.9. 10-Bit Analog to Digital Converter..................................................................... 34
1.10.12-bit Digital to Analog Converters................................................................... 35
1.11.Analog Comparators......................................................................................... 36
2. Absolute Maximum Ratings .................................................................................. 37
3. Global DC Electrical Characteristics.................................................................... 38
4. Pinout and Package Definitions............................................................................ 39
5. 16-Bit ADCs (ADC0 and ADC1) ............................................................................. 51
5.1. Single-Ended or Differential Operation............................................................. 52
5.1.1. Pseudo-Differential Inputs........................................................................ 52
5.2. Voltage Reference............................................................................................ 53
5.3. ADC Modes of Operation.................................................................................. 54
5.3.1. Starting a Conversion............................................................................... 54
5.3.2. Tracking Modes........................................................................................ 54
5.3.3. Settling Time Requirements..................................................................... 56
5.4. Calibration......................................................................................................... 66
5.5. ADC0 Programmable Window Detector ........................................................... 69
6. Direct Memory Access Interface (DMA0) ............................................................. 75
6.1. Writing to the Instruction Buffer......................................................................... 75
6.2. DMA0 Instruction Format.................................................................................. 76
6.3. XRAM Addressing and Setup........................................................................... 76
6.4. Instruction Execution in Mode 0. ....................................................................... 77
6.5. Instruction Execution in Mode 1. ....................................................................... 78
6.6. Interrupt Sources .............................................................................................. 79
6.7. Data Buffer Overflow Warnings and Errors....................................................... 79
7. 10-Bit ADC (ADC2, C8051F060/1/2/3).................................................................... 87
7.1. Analog Multiplexer ............................................................................................ 88
7.2. Modes of Operation .......................................................................................... 89
7.2.1. Starting a Conversion............................................................................... 89
7.2.2. Tracking Modes........................................................................................ 90
7.2.3. Settling Time Requirements..................................................................... 91
C8051F060/1/2/3/4/5/6/7
4 Rev. 1.2
7.3. Programmable Window Detector...................................................................... 97
7.3.1. Window Detector In Single-Ended Mode ................................................. 99
7.3.2. Window Detector In Differential Mode.................................................... 100
8. DACs, 12-Bit Voltage Mode (DAC0 and DAC1, C8051F060/1/2/3) .................... 103
8.1. DAC Output Scheduling.................................................................................. 104
8.1.1. Update Output On-Demand ................................................................... 104
8.1.2. Update Output Based on Timer Overflow .............................................. 104
8.2. DAC Output Scaling/Justification.................................................................... 104
9. Voltage Reference 2 (C8051F060/2).................................................................... 111
10.Voltage Reference 2 (C8051F061/3) ................................................................... 113
11.Voltage Reference 2 (C8051F064/5/6/7).............................................................. 115
12.Comparators......................................................................................................... 117
12.1.Comparator Inputs.......................................................................................... 119
13.CIP-51 Microcontroller......................................................................................... 123
13.1.Instruction Set................................................................................................. 125
13.1.1.Instruction and CPU Timing................................................................... 125
13.1.2.MOVX Instruction and Program Memory............................................... 125
13.2.Memory Organization..................................................................................... 130
13.2.1.Program Memory ................................................................................... 130
13.2.2.Data Memory.......................................................................................... 131
13.2.3.General Purpose Registers.................................................................... 131
13.2.4.Bit Addressable Locations...................................................................... 131
13.2.5.Stack ..................................................................................................... 131
13.2.6.Special Function Registers .................................................................... 132
13.2.6.1.SFR Paging ................................................................................... 132
13.2.6.2.Interrupts and SFR Paging............................................................ 132
13.2.6.3.SFR Page Stack Example............................................................. 134
13.2.7.Register Descriptions............................................................................. 148
13.3.Interrupt Handler............................................................................................. 151
13.3.1.MCU Interrupt Sources and Vectors...................................................... 151
13.3.2.External Interrupts.................................................................................. 151
13.3.3.Interrupt Priorities................................................................................... 153
13.3.4.Interrupt Latency.................................................................................... 153
13.3.5.Interrupt Register Descriptions............................................................... 154
13.4.Power Management Modes............................................................................ 160
13.4.1.Idle Mode ............................................................................................... 160
13.4.2.Stop Mode.............................................................................................. 161
14.Reset Sources....................................................................................................... 163
14.1.Power-on Reset.............................................................................................. 164
14.2.Power-fail Reset............................................................................................. 164
14.3.External Reset................................................................................................ 164
14.4.Missing Clock Detector Reset ........................................................................ 165
14.5.Comparator0 Reset........................................................................................ 165
14.6.External CNVSTR2 Pin Reset........................................................................ 165
14.7.Watchdog Timer Reset................................................................................... 165
C8051F060/1/2/3/4/5/6/7
Rev. 1.2 5
14.7.1.Enable/Reset WDT ................................................................................ 166
14.7.2.Disable WDT.......................................................................................... 166
14.7.3.Disable WDT Lockout ............................................................................ 166
14.7.4.Setting WDT Interval.............................................................................. 166
15.Oscillators............................................................................................................. 171
15.1.Programmable Internal Oscillator................................................................... 171
15.2.External Oscillator Drive Circuit...................................................................... 173
15.3.System Clock Selection.................................................................................. 173
15.4.External Crystal Example............................................................................... 175
15.5.External RC Example..................................................................................... 175
15.6.External Capacitor Example........................................................................... 175
16.Flash Memory ....................................................................................................... 177
16.1.Programming The Flash Memory................................................................... 177
16.2.Non-volatile Data Storage .............................................................................. 178
16.3.Security Options............................................................................................. 179
16.3.1.Summary of Flash Security Options....................................................... 183
17.External Data Memory Interface and On-Chip XRAM ........................................ 187
17.1.Accessing XRAM............................................................................................ 187
17.1.1.16-Bit MOVX Example........................................................................... 187
17.1.2.8-Bit MOVX Example............................................................................. 187
17.2.Configuring the External Memory Interface.................................................... 188
17.3.Port Selection and Configuration.................................................................... 188
17.4.Multiplexed and Non-multiplexed Selection.................................................... 190
17.4.1.Multiplexed Configuration....................................................................... 190
17.4.2.Non-multiplexed Configuration............................................................... 191
17.5.Memory Mode Selection................................................................................. 192
17.5.1.Internal XRAM Only ............................................................................... 192
17.5.2.Split Mode without Bank Select.............................................................. 192
17.5.3.Split Mode with Bank Select................................................................... 193
17.5.4.External Only.......................................................................................... 193
17.6.Timing .......................................................................................................... 194
17.6.1.Non-multiplexed Mode........................................................................... 196
17.6.1.1.16-bit MOVX: EMI0CF[4:2] = ‘101’, ‘110’, or ‘111’......................... 196
17.6.1.2.8-bit MOVX without Bank Select: EMI0CF[4:2] = ‘101’ or ‘111’..... 197
17.6.1.3.8-bit MOVX with Bank Select: EMI0CF[4:2] = ‘110’....................... 198
17.6.2.Multiplexed Mode................................................................................... 199
17.6.2.1.16-bit MOVX: EMI0CF[4:2] = ‘001’, ‘010’, or ‘011’......................... 199
17.6.2.2.8-bit MOVX without Bank Select: EMI0CF[4:2] = ‘001’ or ‘011’..... 200
17.6.2.3.8-bit MOVX with Bank Select: EMI0CF[4:2] = ‘010’....................... 201
18.Port Input/Output.................................................................................................. 203
18.1.Ports 0 through 3 and the Priority Crossbar Decoder..................................... 205
18.1.1.Crossbar Pin Assignment and Allocation............................................... 205
18.1.2.Configuring the Output Modes of the Port Pins...................................... 206
18.1.3.Configuring Port Pins as Digital Inputs................................................... 207
18.1.4.Weak Pull-ups........................................................................................ 207
C8051F060/1/2/3/4/5/6/7
6 Rev. 1.2
18.1.5.Configuring Port 1 and 2 pins as Analog Inputs..................................... 207
18.1.6.Crossbar Pin Assignment Example........................................................ 208
18.2.Ports 4 through 7 (C8051F060/2/4/6 only)..................................................... 219
18.2.1.Configuring Ports which are not Pinned Out.......................................... 219
18.2.2.Configuring the Output Modes of the Port Pins...................................... 219
18.2.3.Configuring Port Pins as Digital Inputs................................................... 219
18.2.4.Weak Pull-ups........................................................................................ 219
18.2.5.External Memory Interface..................................................................... 220
19.Controller Area Network (CAN0, C8051F060/1/2/3)........................................... 225
19.1.Bosch CAN Controller Operation.................................................................... 227
19.2.CAN Registers................................................................................................ 228
19.2.1.CAN Controller Protocol Registers......................................................... 228
19.2.2.Message Object Interface Registers...................................................... 228
19.2.3.Message Handler Registers................................................................... 228
19.2.4.CIP-51 MCU Special Function Registers............................................... 229
19.2.5.Using CAN0ADR, CAN0DATH, and CANDATL To Access CAN Registers
229 19.2.6.CAN0ADR Autoin crement Feature ........................................................ 229
20.System Management BUS / I2C BUS (SMBUS0)................................................ 235
20.1.Supporting Documents................................................................................... 236
20.2.SMBus Protocol.............................................................................................. 236
20.2.1.Arbitration............................................................................................... 237
20.2.2.Clock Low Extension.............................................................................. 237
20.2.3.SCL Low Timeout................................................................................... 237
20.2.4.SCL High (SMBus Free) Timeout .......................................................... 237
20.3.SMBus Transfer Modes.................................................................................. 238
20.3.1.Master Transmitter Mode....................................................................... 238
20.3.2.Master Receiver Mode........................................................................... 238
20.3.3.Slave Transmitter Mode......................................................................... 239
20.3.4.Slave Receiver Mode............................................................................. 239
20.4.SMBus Special Function Registers................................................................ 241
20.4.1.Control Register..................................................................................... 241
20.4.2.Clock Rate Register............................................................................... 244
20.4.3.Data Register......................................................................................... 245
20.4.4.Address Register.................................................................................... 245
20.4.5.Status Register....................................................................................... 246
21.Enhanced Serial Peripheral Interface (SPI0)...................................................... 251
21.1.Signal Descriptions......................................................................................... 252
21.1.1.Master Out, Slave In (MOSI).................................................................. 252
21.1.2.Master In, Slave Out (MISO).................................................................. 252
21.1.3.Serial Clock (SCK)................................................................................. 252
21.1.4.Slave Select (NSS) ................................................................................ 252
21.2.SPI0 Master Mode Operation......................................................................... 253
21.3.SPI0 Slave Mode Operation........................................................................... 255
21.4.SPI0 Interrupt Sources................................................................................... 255
C8051F060/1/2/3/4/5/6/7
Rev. 1.2 7
21.5.Serial Clock Timing......................................................................................... 256
21.6.SPI Special Function Registers...................................................................... 258
22.UART0.................................................................................................................... 265
22.1.UART0 Operational Modes ............................................................................ 266
22.1.1.Mode 0: Synchronous Mode.................................................................. 266
22.1.2.Mode 1: 8-Bit UART, Variable Baud Rate.............................................. 267
22.1.3.Mode 2: 9-Bit UART, Fixed Baud Rate.................................................. 269
22.1.4.Mode 3: 9-Bit UART, Variable Baud Rate.............................................. 270
22.2.Multiprocessor Communications .................................................................... 271
22.2.1.Configuration of a Masked Address....................................................... 271
22.2.2.Broadcast Addressing............................................................................ 271
22.3.Frame and Transmission Error Detection....................................................... 272
23.UART1.................................................................................................................... 277
23.1.Enhanced Baud Rate Generation................................................................... 278
23.2.Operational Modes......................................................................................... 279
23.2.1.8-Bit UART............................................................................................. 279
23.2.2.9-Bit UART............................................................................................. 280
23.3.Multiprocessor Communications .................................................................... 281
24.Timers.................................................................................................................... 287
24.1.Timer 0 and Timer 1....................................................................................... 287
24.1.1.Mode 0: 13-bit Counter/Timer................................................................ 287
24.1.2.Mode 1: 16-bit Counter/Timer................................................................ 289
24.1.3.Mode 2: 8-bit Counter/Timer with Auto-Reload...................................... 289
24.1.4.Mode 3: Two 8-bit Counter/Timers (Timer 0 Only)................................. 290
24.2.Timer 2, Timer 3, and Timer 4........................................................................ 295
24.2.1.Configuring Timer 2, 3, and 4 to Count Down........................................ 295
24.2.2.Capture Mode ........................................................................................ 296
24.2.3.Auto-Reload Mode................................................................................. 297
24.2.4.Toggle Output Mode .............................................................................. 298
25.Programmable Counter Array............................................................................. 303
25.1.PCA Counter/Timer........................................................................................ 304
25.2.Capture/Compare Modules ............................................................................ 305
25.2.1.Edge-triggered Capture Mode................................................................ 306
25.2.2.Software Timer (Compare) Mode........................................................... 307
25.2.3.High Speed Output Mode....................................................................... 308
25.2.4.Frequency Output Mode ........................................................................ 309
25.2.5.8-Bit Pulse Width Modulator Mode......................................................... 310
25.2.6.16-Bit Pulse Width Modulator Mode....................................................... 311
25.3.Register Descriptions for PCA0...................................................................... 312
26.JTAG (IEEE 1149.1) .............................................................................................. 317
26.1.Boundary Scan............................................................................................... 318
26.1.1.EXTEST Instruction................................................................................ 321
26.1.2.SAMPLE Instruction............................................................................... 321
26.1.3.BYPASS Instruction............................................................................... 321
26.1.4.IDCODE Instruction................................................................................ 321
C8051F060/1/2/3/4/5/6/7
8 Rev. 1.2
26.2.Flash Programming Commands..................................................................... 322
26.3.Debug Support ............................................................................................... 325
27.Document Change List ........................................................................................ 327
27.1.Revision 1.1 to Revision 1.2........................................................................... 327
C8051F060/1/2/3/4/5/6/7
Rev. 1.2 9
List of Figures
1. System Overview.................................................................................................... 19
Figure 1.1. C8051F060 / C8051F062 Block Diagram.............................................. 21
Figure 1.2. C8051F061 / C8051F063 Block Diagram.............................................. 22
Figure 1.3. C8051F064 / C8051F066 Block Diagram.............................................. 23
Figure 1.4. C8051F065 / C8051F067 Block Diagram.............................................. 24
Figure 1.5. Comparison of Peak MCU Execution Speeds ....................................... 25
Figure 1.6. On-Board Clock and Reset.................................................................... 26
Figure 1.7. On-Chip Memory Map. ........................................................................... 27
Figure 1.8. Development/In-System Debug Diagram............................................... 28
Figure 1.9. Digital Crossbar Diagram....................................................................... 29
Figure 1.10. PCA Block Diagram.............................................................................. 30
Figure 1.11. CAN Controller Overview..................................................................... 31
Figure 1.12. 16-Bit ADC Block Diagram................................................................... 33
Figure 1.13. 10-Bit ADC Diagram............................................................................. 34
Figure 1.14. DAC System Block Diagram ................................................................ 35
Figure 1.15. Comparator Block Diagram.................................................................. 36
2. Absolute Maximum Ratings .................................................................................. 37
3. Global DC Electrical Characteristics.................................................................... 38
4. Pinout and Package Definitions............................................................................ 39
Figure 4.1. C8051F060 / C8051F062 Pinout Diagram (TQFP-100)......................... 45
Figure 4.2. C8051F064 / C8051F066 Pinout Diagram (TQFP-100)......................... 46
Figure 4.3. TQFP-100 Package Drawing................................................................. 47
Figure 4.4. C8051F061 / C8051F063 Pinout Diagram (TQFP-64)........................... 48
Figure 4.5. C8051F065 / C8051F067 Pinout Diagram (TQFP-64)........................... 49
Figure 4.6. TQFP-64 Package Drawing................................................................... 50
5. 16-Bit ADCs (ADC0 and ADC1) ............................................................................. 51
Figure 5.1. 16-Bit ADC0 and ADC1 Control Path Diagram...................................... 51
Figure 5.2. 16-bit ADC0 and ADC1 Data Path Diagram .......................................... 52
Figure 5.3. Voltage Reference Block Diagram......................................................... 53
Figure 5.4. ADC Track and Conversion Example Timing......................................... 55
Figure 5.5. ADC0 and ADC1 Equivalent Input Circuits............................................ 56
Figure 5.6. AMX0SL: AMUX Configuration Register................................................ 57
Figure 5.7. ADC0CF: ADC0 Configuration Register ................................................ 58
Figure 5.8. ADC1CF: ADC1 Configuration Register ................................................ 59
Figure 5.9. ADC0CN: ADC0 Control Register.......................................................... 60
Figure 5.10. ADC1CN: ADC1 Control Register........................................................ 61
Figure 5.11. REF0CN: Reference Control Register 0 .............................................. 62
Figure 5.12. REF1CN: Reference Control Register 1 .............................................. 62
Figure 5.13. ADC0H: ADC0 Data Word MSB Register............................................ 63
Figure 5.14. ADC0L: ADC0 Data Word LSB Register.............................................. 63
Figure 5.15. ADC0 Data Word Example................................................................... 64
Figure 5.16. ADC1H: ADC1 Data Word MSB Register............................................ 65
C8051F060/1/2/3/4/5/6/7
10 Rev. 1.2
Figure 5.17. ADC1L: ADC1 Data Word LSB Register.............................................. 65
Figure 5.18. ADC1 Data Word Example................................................................... 65
Figure 5.19. Calibration Coefficient Locations.......................................................... 66
Figure 5.20. Offset and Gain Register Mapping....................................................... 67
Figure 5.21. Offset and Gain Calibration Block Diagram.......................................... 67
Figure 5.22. ADC0CPT: ADC Calibration Pointer Register...................................... 68
Figure 5.23. ADC0CCF: ADC Calibration Coefficient Register................................ 68
Figure 5.24. ADC0GTH: ADC0 Greater-Than Data High Byte Register .................. 69
Figure 5.25. ADC0GTL: ADC0 Greater-Than Data Low Byte Register.................... 69
Figure 5.26. ADC0LTH: ADC0 Less-Than Data High Byte Register........................ 70
Figure 5.27. ADC0LTL: ADC0 Less-Than Data Low Byte Register......................... 70
Figure 5.28. 16-Bit ADC0 Window Interrupt Example: Single-Ended Data.............. 71
Figure 5.29. 16-Bit ADC0 Window Interrupt Example: Differential Data .................. 72
6. Direct Memory Access Interface (DMA0) ............................................................. 75
Figure 6.1. DMA0 Block Diagram............................................................................. 75
Figure 6.2. DMA Mode 0 Operation ......................................................................... 77
Figure 6.3. DMA Mode 1 Operation ......................................................................... 78
Figure 6.4. DMA0CN: DMA0 Control Register......................................................... 80
Figure 6.5. DMA0CF: DMA0 Configuration Register................................................ 81
Figure 6.6. DMA0IPT: DMA0 Instruction Write Address Register............................ 82
Figure 6.7. DMA0IDT: DMA0 Instruction Write Data Register ................................. 82
Figure 6.8. DMA0BND: DMA0 Instruction Boundary Register................................. 83
Figure 6.9. DMA0ISW: DMA0 Instruction Status Register....................................... 83
Figure 6.10. DMA0DAH: DMA0 Data Address Beginning MSB Register................. 84
Figure 6.11. DMA0DAL: DMA0 Data Address Beginning LSB Register .................. 84
Figure 6.12. DMA0DSH: DMA0 Data Address Pointer MSB Register ..................... 84
Figure 6.13. DMA0DSL: DMA0 Data Address Pointer LSB Register....................... 84
Figure 6.14. DMA0CTH: DMA0 Repeat Counter Limit MSB Register...................... 85
Figure 6.15. DMA0CTL: DMA0 Repeat Counter Limit LSB Register ....................... 85
Figure 6.16. DMA0CSH: DMA0 Repeat Counter MSB Register.............................. 85
Figure 6.17. DMA0CSL: DMA0 Repeat Counter LSB Register................................ 85
7. 10-Bit ADC (ADC2, C8051F060/1/2/3).................................................................... 87
Figure 7.1. ADC2 Functional Block Diagram............................................................ 87
Figure 7.2. Temperature Sensor Transfer Function................................................. 89
Figure 7.3. 10-Bit ADC Track and Conversion Example Timing.............................. 90
Figure 7.4. ADC2 Equivalent Input Circuits.............................................................. 91
Figure 7.5. AMX2CF: AMUX2 Configuration Register ............................................. 92
Figure 7.6. AMX2SL: AMUX2 Channel Select Register........................................... 93
Figure 7.7. ADC2CF: ADC2 Configuration Register ................................................ 94
Figure 7.8. ADC2H: ADC2 Data Word MSB Register.............................................. 95
Figure 7.9. ADC2L: ADC2 Data Word LSB Register................................................ 95
Figure 7.10. ADC2CN: ADC2 Control Register........................................................ 96
Figure 7.11. ADC2GTH: ADC2 Greater-Than Data High Byte Register .................. 97
Figure 7.12. ADC2GTL: ADC2 Greater-Than Data Low Byte Register.................... 97
Figure 7.13. ADC2LTH: ADC2 Less-Than Data High Byte Register........................ 98
C8051F060/1/2/3/4/5/6/7
Rev. 1.2 11
Figure 7.14. ADC2LTL: ADC2 Less-Than Data Low Byte Register......................... 98
Figure 7.15. ADC Window Compare Example: Right-Justified Single-Ended Data. 99
Figure 7.16. ADC Window Compare Example: Left-Justified Single-Ended Data.... 99
Figure 7.17. ADC Window Compare Example: Right-Justified Differential Data.... 100
Figure 7.18. ADC Window Compare Example: Left-Justified Differential Data...... 100
8. DACs, 12-Bit Voltage Mode (DAC0 and DAC1, C8051F060/1/2/3) .................... 103
Figure 8.1. DAC Functional Block Diagram............................................................ 103
Figure 8.2. DAC0H: DAC0 High Byte Register ...................................................... 105
Figure 8.3. DAC0L: DAC0 Low Byte Register........................................................ 105
Figure 8.4. DAC0CN: DAC0 Control Register........................................................ 106
Figure 8.5. DAC1H: DAC1 High Byte Register ...................................................... 107
Figure 8.6. DAC1L: DAC1 Low Byte Register........................................................ 107
Figure 8.7. DAC1CN: DAC1 Control Register........................................................ 108
9. Voltage Reference 2 (C8051F060/2).................................................................... 111
Figure 9.1. Voltage Reference Functional Block Diagram ..................................... 111
Figure 9.2. REF2CN: Reference Control Register 2.............................................. 112
10.Voltage Reference 2 (C8051F061/3) ................................................................... 113
Figure 10.1. Voltage Reference Functional Block Diagram.................................... 113
Figure 10.2. REF2CN: Reference Control Register 2 ............................................ 114
11.Voltage Reference 2 (C8051F064/5/6/7).............................................................. 115
Figure 11.1. Voltage Reference Functional Block Diagram.................................... 115
Figure 11.2. REF2CN: Reference Control Register 2 ............................................ 116
12.Comparators......................................................................................................... 117
Figure 12.1. Comparator Functional Block Diagram .............................................. 117
Figure 12.2. Comparator Hysteresis Plot ............................................................... 118
Figure 12.3. CPTnCN: Comparator 0, 1, and 2 Control Register........................... 120
Figure 12.4. CPTnMD: Comparator Mode Selection Register ............................... 121
13.CIP-51 Microcontroller......................................................................................... 123
Figure 13.1. CIP-51 Block Diagram....................................................................... 124
Figure 13.2. Memory Map ...................................................................................... 130
Figure 13.3. SFR Page Stack................................................................................. 133
Figure 13.4. SFR Page Stack While Using SFR Page 0x0F To Access Port 5...... 134
Figure 13.5. SFR Page Stack After ADC2 Window Comparator Interrupt Occurs. 135
Figure 13.6. SFR Page Stack Upon PCA Interrupt Occurring During an ADC2 ISR....
136
Figure 13.7. SFR Page Stack Upon Return From PCA Interrupt........................... 137
Figure 13.8. SFR Page Stack Upon Return From ADC2 Window Interrupt........... 138
Figure 13.9. SFRPGCN: SFR Page Control Register............................................ 139
Figure 13.10. SFRPAGE: SFR Page Register....................................................... 139
Figure 13.11. SFRNEXT: SFR Next Register......................................................... 140
Figure 13.12. SFRLAST: SFR Last Register.......................................................... 140
Figure 13.13. SP: Stack Pointer............................................................................. 148
Figure 13.14. DPL: Data Pointer Low Byte............................................................. 148
Figure 13.15. DPH: Data Pointer High Byte........................................................... 148
Figure 13.16. PSW: Program Status Word............................................................. 149
C8051F060/1/2/3/4/5/6/7
12 Rev. 1.2
Figure 13.17. ACC: Accumulator............................................................................ 150
Figure 13.18. B: B Register.................................................................................... 150
Figure 13.19. IE: Interrupt Enable .......................................................................... 154
Figure 13.20. IP: Interrupt Priority .......................................................................... 155
Figure 13.21. EIE1: Extended Interrupt Enable 1................................................... 156
Figure 13.22. EIE2: Extended Interrupt Enable 2................................................... 157
Figure 13.23. EIP1: Extended Interrupt Priority 1................................................... 158
Figure 13.24. EIP2: Extended Interrupt Priority 2................................................... 159
Figure 13.25. PCON: Power Control...................................................................... 161
14.Reset Sources....................................................................................................... 163
Figure 14.1. Reset Sources.................................................................................... 163
Figure 14.2. Reset Timing...................................................................................... 164
Figure 14.3. WDTCN: Watchdog Timer Control Register....................................... 167
Figure 14.4. RSTSRC: Reset Source Register ...................................................... 168
15.Oscillators............................................................................................................. 171
Figure 15.1. Oscillator Diagram.............................................................................. 171
Figure 15.2. OSCICL: Internal Oscillator Calibration Register ............................... 172
Figure 15.3. OSCICN: Internal Oscillator Control Register .................................... 172
Figure 15.4. CLKSEL: Oscillator Clock Selection Register .................................... 173
Figure 15.5. OSCXCN: External Oscillator Control Register.................................. 174
16.Flash Memory ....................................................................................................... 177
Figure 16.1. C8051F060/1/2/3/4/5 Flash Program Memory Map and Security Bytes..
180
Figure 16.2. C8051F066/7 Flash Program Memory Map and Security Bytes........ 181
Figure 16.3. FLACL: Flash Access Limit................................................................ 182
Figure 16.4. FLSCL: Flash Memory Control........................................................... 184
Figure 16.5. PSCTL: Program Store Read/Write Control....................................... 185
17.External Data Memory Interface and On-Chip XRAM ........................................ 187
Figure 17.1. EMI0CN: External Memory Interface Control..................................... 189
Figure 17.2. EMI0CF: External Memory Configuration........................................... 189
Figure 17.3. Multiplexed Configuration Example.................................................... 190
Figure 17.4. Non-multiplexed Configuration Example............................................ 191
Figure 17.5. EMIF Operating Modes...................................................................... 192
Figure 17.6. EMI0TC: External Memory Timing Control......................................... 194
Figure 17.7. Non-multiplexed 16-bit MOVX Timing................................................ 196
Figure 17.8. Non-multiplexed 8-bit MOVX without Bank Select Timing ................. 197
Figure 17.9. Non-multiplexed 8-bit MOVX with Bank Select Timing ...................... 198
Figure 17.10. Multiplexed 16-bit MOVX Timing...................................................... 199
Figure 17.11. Multiplexed 8-bit MOVX without Bank Select Timing....................... 200
Figure 17.12. Multiplexed 8-bit MOVX with Bank Select Timing............................ 201
18.Port Input/Output.................................................................................................. 203
Figure 18.1. Port I/O Cell Block Diagram ............................................................... 203
Figure 18.2. Port I/O Functional Block Diagram..................................................... 204
Figure 18.3. Priority Crossbar Decode Table......................................................... 205
Figure 18.4. Crossbar Example:............................................................................. 209
C8051F060/1/2/3/4/5/6/7
Rev. 1.2 13
Figure 18.5. XBR0: Port I/O Crossbar Register 0................................................... 210
Figure 18.6. XBR1: Port I/O Crossbar Register 1................................................... 211
Figure 18.7. XBR2: Port I/O Crossbar Register 2................................................... 212
Figure 18.8. XBR3: Port I/O Crossbar Register 3................................................... 213
Figure 18.9. P0: Port0 Data Register ..................................................................... 214
Figure 18.10. P0MDOUT: Port0 Output Mode Register......................................... 214
Figure 18.11. P1: Port1 Data Register ................................................................... 215
Figure 18.12. P1MDIN: Port1 Input Mode Register................................................ 215
Figure 18.13. P1MDOUT: Port1 Output Mode Register......................................... 216
Figure 18.14. P2: Port2 Data Register ................................................................... 216
Figure 18.15. P2MDIN: Port2 Input Mode Register................................................ 217
Figure 18.16. P2MDOUT: Port2 Output Mode Register......................................... 217
Figure 18.17. P3: Port3 Data Register ................................................................... 218
Figure 18.18. P3MDOUT: Port3 Output Mode Register......................................... 218
Figure 18.19. P4: Port4 Data Register ................................................................... 221
Figure 18.20. P4MDOUT: Port4 Output Mode Register......................................... 221
Figure 18.21. P5: Port5 Data Register ................................................................... 222
Figure 18.22. P5MDOUT: Port5 Output Mode Register......................................... 222
Figure 18.23. P6: Port6 Data Register ................................................................... 223
Figure 18.24. P6MDOUT: Port6 Output Mode Register......................................... 223
Figure 18.25. P7: Port7 Data Register ................................................................... 224
Figure 18.26. P7MDOUT: Port7 Output Mode Register......................................... 224
19.Controller Area Network (CAN0, C8051F060/1/2/3)........................................... 225
Figure 19.1. CAN Controller Diagram..................................................................... 226
Figure 19.2. Typical CAN Bus Configuration.......................................................... 226
Figure 19.3. CAN0DATH: CAN Data Access Register High Byte.......................... 231
Figure 19.4. CAN0DATL: CAN Data Access Register Low Byte............................ 231
Figure 19.5. CAN0ADR: CAN Address Index Register.......................................... 232
Figure 19.6. CAN0CN: CAN Control Register........................................................ 232
Figure 19.7. CAN0TST: CAN Test Register........................................................... 233
Figure 19.8. CAN0STA: CAN Status Register........................................................ 233
20.System Management BUS / I2C BUS (SMBUS0)................................................ 235
Figure 20.1. SMBus0 Block Diagram ..................................................................... 235
Figure 20.2. Typical SMBus Configuration............................................................. 236
Figure 20.3. SMBus Transaction............................................................................ 237
Figure 20.4. Typical Master Transmitter Sequence................................................ 238
Figure 20.5. Typical Master Receiver Sequence.................................................... 238
Figure 20.6. Typical Slave Transmitter Sequence.................................................. 239
Figure 20.7. Typical Slave Receiver Sequence...................................................... 240
Figure 20.8. SMB0CN: SMBus0 Control Register.................................................. 243
Figure 20.9. SMB0CR: SMBus0 Clock Rate Register............................................ 244
Figure 20.10. SMB0DAT: SMBus0 Data Register.................................................. 245
Figure 20.11. SMB0ADR: SMBus0 Address Register............................................ 246
Figure 20.12. SMB0STA: SMBus0 Status Register ............................................... 247
21.Enhanced Serial Peripheral Interface (SPI0)...................................................... 251
C8051F060/1/2/3/4/5/6/7
14 Rev. 1.2
Figure 21.1. SPI Block Diagram............................................................................. 251
Figure 21.2. Multiple-Master Mode Connection Diagram....................................... 254
Figure 21.3. 3-Wire Single Master and 3-Wire Single Slave Mode Connection Diagram
254
Figure 21.4. 4-Wire Single Master Mode and 4-Wire Slave Mode Connection Diagram
254
Figure 21.5. Master Mode Data/Clock Timing........................................................ 256
Figure 21.6. Slave Mode Data/Clock Timing (CKPHA = 0).................................... 257
Figure 21.7. Slave Mode Data/Clock Timing (CKPHA = 1).................................... 257
Figure 21.8. SPI0CFG: SPI0 Configuration Register ............................................. 258
Figure 21.9. SPI0CN: SPI0 Control Register.......................................................... 259
Figure 21.10. SPI0CKR: SPI0 Clock Rate Register............................................... 260
Figure 21.11. SPI0DAT: SPI0 Data Register.......................................................... 261
Figure 21.12. SPI Master Timing (C KPHA = 0)...................................................... 262
Figure 21.13. SPI Master Timing (C KPHA = 1)...................................................... 262
Figure 21.14. SPI Slave Timing (CKPHA = 0)......... ............................................... 263
Figure 21.15. SPI Slave Timing (CKPHA = 1)......... ............................................... 263
22.UART0.................................................................................................................... 265
Figure 22.1. UART0 Block Diagram....................................................................... 265
Figure 22.2. UART0 Mode 0 Timing Diagram........................................................ 267
Figure 22.3. UART0 Mode 0 Interconnect.............................................................. 267
Figure 22.4. UART0 Mode 1 Timing Diagram........................................................ 267
Figure 22.5. UART0 Modes 2 and 3 Timing Diagram ............................................ 269
Figure 22.6. UART0 Modes 1, 2, and 3 Interconnect Diagram .............................. 270
Figure 22.7. UART Multi-Processor Mode Interconnect Diagram.......................... 272
Figure 22.8. SCON0: UART0 Control Register...................................................... 274
Figure 22.9. SSTA0: UART0 Status and Clock Selection Register........................ 275
Figure 22.10. SBUF0: UART0 Data Buffer Register .............................................. 276
Figure 22.11. SADDR0: UART0 Slave Address Register ...................................... 276
Figure 22.12. SADEN0: UART0 Slave Address Enable Register .......................... 276
23.UART1.................................................................................................................... 277
Figure 23.1. UART1 Block Diagram....................................................................... 277
Figure 23.2. UART1 Baud Rate Logic.................................................................... 278
Figure 23.3. UART Interconnect Diagram.............................................................. 279
Figure 23.4. 8-Bit UART Timing Diagram............................................................... 279
Figure 23.5. 9-Bit UART Timing Diagram............................................................... 280
Figure 23.6. UART Multi-Processor Mode Interconnect Diagram.......................... 281
Figure 23.7. SCON1: Serial Port 1 Control Register.............................................. 282
Figure 23.8. SBUF1: Serial (UART1) Port Data Buffe r Register............................ 283
24.Timers.................................................................................................................... 287
Figure 24.1. T0 Mode 0 Block Diagram.................................................................. 288
Figure 24.2. T0 Mode 2 Block Diagram.................................................................. 289
Figure 24.3. T0 Mode 3 Block Diagram.................................................................. 290
Figure 24.4. TCON: Timer Control Register........................................................... 291
Figure 24.5. TMOD: Timer Mode Register............................................................. 292
C8051F060/1/2/3/4/5/6/7
Rev. 1.2 15
Figure 24.6. CKCON: Clock Control Register ........................................................ 293
Figure 24.7. TL0: Timer 0 Low Byte....................................................................... 294
Figure 24.8. TL1: Timer 1 Low Byte....................................................................... 294
Figure 24.9. TH0: Timer 0 High Byte...................................................................... 294
Figure 24.10. TH1: Timer 1 High Byte.................................................................... 294
Figure 24.11. T2, 3, and 4 Capture Mode Block Diagram...................................... 296
Figure 24.12. T2, 3, and 4 Auto-reload Mode Block Diagram................................ 297
Figure 24.13. TMRnCN: Timer 2, 3, and 4 Control Registers ................................ 299
Figure 24.14. TMRnCF: Timer 2, 3, and 4 Configuration Registers....................... 300
Figure 24.15. RCAPnL: Timer 2, 3, and 4 Capture Register Low Byte.................. 301
Figure 24.16. RCAPnH: Timer 2, 3, and 4 Capture Register High Byte................. 301
Figure 24.17. TMRnL: Timer 2, 3, and 4 Low Byte................................................. 301
Figure 24.18. TMRnH: Timer 2, 3, and 4 High Byte............................................... 302
25.Programmable Counter Array............................................................................. 303
Figure 25.1. PCA Block Diagram............................................................................ 303
Figure 25.2. PCA Counter/Timer Block Diagram.................................................... 304
Figure 25.3. PCA Interrupt Block Diagram............................................................. 305
Figure 25.4. PCA Capture Mode Diagram.............................................................. 306
Figure 25.5. PCA Software Timer Mode Diagram.................................................. 307
Figure 25.6. PCA High Speed Output Mode Diagram............................................ 308
Figure 25.7. PCA Frequency Output Mode............................................................ 309
Figure 25.8. PCA 8-Bit PWM Mode Diagram......................................................... 310
Figure 25.9. PCA 16-Bit PWM Mode...................................................................... 311
Figure 25.10. PCA0CN: PCA Control Register ...................................................... 312
Figure 25.11. PCA0MD: PCA0 Mode Register....................................................... 313
Figure 25.12. PCA0CPMn: PCA0 Capture/Compare Mode Registers................... 314
Figure 25.13. PCA0L: PCA0 Counter/Timer Low Byte........................................... 315
Figure 25.14. PCA0H: PCA0 Counter/Timer High Byte ......................................... 315
Figure 25.15. PCA0CPLn: PCA0 Capture Module Low Byte................................. 316
Figure 25.16. PCA0CPHn: PCA0 Capture Module High Byte................................ 316
26.JTAG (IEEE 1149.1) .............................................................................................. 317
Figure 26.1. IR: JTAG Instruction Register............................................................. 317
Figure 26.2. DEVICEID: JTAG Device ID Register................................................ 321
Figure 26.3. FLASHCON: JTAG Flash Control Register........................................ 323
Figure 26.4. FLASHDAT: JTAG Flash Data Register............................................. 324
Figure 26.5. FLASHADR: JTAG Flash Address Register....................................... 324
27.Document Change List ........................................................................................ 327
C8051F060/1/2/3/4/5/6/7
16 Rev. 1.2
C8051F060/1/2/3/4/5/6/7
Rev. 1.2 17
List of Tables
1. System Overview ................................................................................................... 19
Table 1.1.Product Selection Guide .......................................................................... 20
2. Absolute Maximum Ratings ................................................................................. 37
Table 2.1.Absolute Maximum Ratings* ................................................................... 37
3. Global DC Electrical Characteristics ................................................................... 38
Table 3.1.Global DC Electrical Characteristics ....................................................... 38
4. Pinout and Package Definitions ........................................................................... 39
Table 4.1.Pin Definitions ......................................................................................... 39
5. 16-Bit ADCs (ADC0 and ADC1) ............................................................................ 51
Table 5.1.Conversion Timing (tConv) ...................................................................... 55
Table 5.2.16-Bit ADC0 and ADC1 Electrical Characteristics .................................. 73
Table 5.3.Voltage Reference 0 and 1 Electrical Characteristics ............................. 74
6. Direct Memory Access Interface (DMA0) ............................................................ 75
Table 6.1.DMA0 Instruction Set .............................................................................. 76
7. 10-Bit ADC (ADC2, C8051F060/1/2/3) ................................................................... 87
Table 7.1.ADC2 Electrical Characteristics ............................................................ 101
8. DACs, 12-Bit Voltage Mode (DAC0 and DAC1, C8051F060/1/2/3) ................... 103
Table 8.1.DAC Electrical Characteristics .............................................................. 109
9. Voltage Reference 2 (C8051F060/2) ................................................................... 111
Table 9.1.Voltage Reference Electrical Characteristics ........................................ 112
10.Voltage Reference 2 (C8051F061/3) .................................................................. 113
Table 10.1.Voltage Reference Electrical Characteristics ...................................... 114
11.Voltage Reference 2 (C8051F064/5/6/7) ............................................................. 115
Table 11.1.Voltage Reference Electrical Characteristics ...................................... 116
12.Comparators ........................................................................................................ 117
Table 12.1.Comparator Electrical Characteristics ................................................. 122
13.CIP-51 Microcontroller ........................................................................................ 123
Table 13.1.CIP-51 Instruction Set Summary ......................................................... 126
Table 13.2.Special Function Register (SFR) Memory Map ................................... 141
Table 13.3.Special Function Registers .................................................................. 143
Table 13.4.Interrupt Summary ............................................................................... 152
14.Reset Sources ...................................................................................................... 163
Table 14.1.Reset Electrical Characteristics ........................................................... 169
15. Oscillators ............................................................................................................ 171
Table 15.1.Internal Oscillator Electrical Characteristics ........................................ 173
16.Flash Memory ...................................................................................................... 177
Table 16.1.Flash Electrical Characteristics ........................................................... 178
17.External Data Memory Interface and On-Chip XRAM ....................................... 187
Table 17.1.AC Parameters for External Memory Interface .................................... 202
18.Port Input/Output ................................................................................................. 203
Table 18.1.Port I/O DC Electrical Characteristics .................................................. 203
19.Controller Area Network (CAN0, C8051F060/1/2/3) .......................................... 225
C8051F060/1/2/3/4/5/6/7
18 Rev. 1.2
Table 19.1.CAN Register Index and Reset Values ............................................... 229
20.System Management BUS / I2C BUS (SMBUS0) ............................................... 235
Table 20.1.SMB0STA Status Codes and States ................................................... 248
21.Enhanced Serial Peripheral Interface (SPI0) ..................................................... 251
Table 21.1.SPI Slave Timing Parameters ............................................................. 264
22.UART0 ................................................................................................................... 265
Table 22.1.UART0 Modes ..................................................................................... 266
Table 22.2.Oscillator Frequencies for Standard Baud Rates ................................ 273
23.UART1 ................................................................................................................... 277
Table 23.1.Timer Settings for Standard Baud Rates Using the Internal Oscillator 284
Table 23.2.Timer Settings for Standard Baud Rates Using an External Oscillator 284
Table 23.3.Timer Settings for Standard Baud Rates Using an External Oscillator 285
Table 23.4.Timer Settings for Standard Baud Rates Using an External Oscillator 285
Table 23.5.Timer Settings for Standard Baud Rates Using an External Oscillator 286
Table 23.6.Timer Settings for Standard Baud Rates Using an External Oscillator 286
24.Timers ................................................................................................................... 287
25.Programmable Counter Array ............................................................................ 303
Table 25.1.PCA Timebase Input Options .............................................................. 304
Table 25.2.PCA0CPM Register Settings for PCA Capture/Compare Modules ..... 305
26.JTAG (IEEE 1149.1) ............................................................................................. 317
Table 26.1.Boundary Data Register Bit Definitions (C8051F060/2/4/6) ................ 318
Table 26.2.Boundary Data Register Bit Definitions (C8051F061/3/5/7) ................ 320
27.Document Change List ....................................................................................... 327
C8051F060/1/2/3/4/5/6/7
Rev. 1.2 19
1. System Overview
The C8051F06x fa mily of de vices ar e fully in te grated mixed-signal System-on-a-Chip MCUs with 59 digita l
I/O pins (C8051F060/2/4/6) or 24 digital I/O pins (C8051F061/3/5/7), and two integrated 16-bit 1 Msps
ADCs. Highlighted features are listed below; refer to Table 1.1 for specific product feature selection.
• High-Speed pipelined 8051-compatible CIP-51 microcon troller core (up to 25 MIPS)
• Two 16-bit 1 Msps ADCs with a Direct Memory Access controller
• Controller Area Network (CAN 2.0B) Controller with 32 message objects, each with its own indentifier
mask (C8051F060/1/2/3)
• In-system, full-speed, non-intrusive debug interface on-chip
• 10-bit 200 ksps ADC with PGA and 8-channel analog multiplexer ( C8051F060/1/2/3)
• Two 12-bit DACs with programmable update scheduling (C8051F060/1/2/3)
• 64 kB (C8051F060/1/2/3/4/5) or 32 kB (C8051F066/7) of in-system programmable Flash memory
• 4352 (4096 + 256) bytes of on-chip RAM
• External Data Memory Interface with 64 kB direct address space (C8051F060/2/4/6)
• SPI, SMBus/I2C, and (2) UART serial interfaces implemented in hardware
• Five general purpose 16-bit Timers
• Programmable Counter/Timer Array with six capture/compare modules
• On-chip Watchdog Timer, VDD Monitor, and Temperature Sensor
With on-chip VDD monitor, Wa tchdog Timer , and clock oscillator, the C8051F06x family of devices are truly
stand-alone System-on-a-Chip solutions. All analog and digital peripherals are enabled/disabled and con-
figured by user firmware. The Flash memory can be reprogrammed even in-circuit, providing non-volatile
data storage, and also allowing field upgrades of the 8051 firmware.
On-board JTAG debug circuitry allows non-intrusive (uses no on-chip resources), full speed, in-circuit
debugging using the produ ctio n MCU inst a lled in the fina l app lication. This debug system supports inspec-
tion and modification of memory and registers, setting breakpoints, watchpoints, single stepping, Run and
Halt commands. All analog and digital peripherals are fully functional while debug ging using JTAG.
Each MCU is specified for 2.7 to 3.6 V operation over the industr ial temperatur e range (-4 5 to +85 °C). The
C8051F060/2/4/6 are available in a 100-pin TQFP package and the C8051F061/3/5/7 are available in a
64-pin TQFP package (see block diagrams in Figure 1.1, Figure 1.2, Figure 1.3 and Figure 1.4).
C8051F060/1/2/3/4/5/6/7
20 Rev. 1.2
Table 1.1. Product Selection Guide
MIPS (Peak)
Flash Memory
RAM
External Memory Interface
SMBus/I2C and SPI
CAN
UARTS
Timers (16-bi t)
Programmable Counter Array
Digital Port I/O’s
16-bit 1 Msps ADC Typical INL (LSBs)
10-bit 200 ksps ADC Inputs
Voltage Reference
Temperature Sensor
DAC Resolution (bits)
DAC Outputs
Analog Comparators
Package
C8051F060 25 64 k 4352
25
59 ±0.75 8
12 2 3 100 TQFP
C8051F061 25 64 k 4352 -
25
24 ±0.75 8
12 2 3 64 TQFP
C8051F062 25 64 k 4352
25
59 ±1.5 8
12 2 3 100 TQFP
C8051F063 25 64 k 4352 -
25
24 ±1.5 8
12 2 3 64 TQFP
C8051F064 25 64 k 4352
-25
59 ±0.75 -
- - - 3 100 TQFP
C8051F065 25 64 k 4352 -
-25
24 ±0.75 -
---364TQFP
C8051F066 25 32 k 4352
-25
59 ±0.75 -
- - - 3 100 TQFP
C8051F067 25 32 k 4352 -
-25
24 ±0.75 -
---364TQFP
C8051F060/1/2/3/4/5/6/7
Rev. 1.2 21
Figure 1.1. C8051F060 / C8051F062 Block Diagram
P0, P1, P2,
P3 Latches
JTAG
Logic
TCK
TMS
TDI
TDO
UART1
SMBus
SPI Bus
PCA
64kbyte
FLASH
256 byte
RAM
VDD Monitor
SFR B us
8
0
5
1
C
o
r
e
Time r s 0, 1 ,
2,3,4
P0
Drv
C
R
O
S
S
B
A
R
Reset
/RST
XTAL1
XTAL2 External Oscillator
Circuit System Clock
Trimmed Internal
Oscillator
Digital Power
Analog Power
Debug HW
Boundar y Sc an
4kbyte R AM
P2.0
P2.7
P1.0/
AIN2.0
P1.7/
AIN2.7
P0.0
P0.7
P1
Drv
P2
Drv
Data Bus
Address Bus
Bus C ontrol
DAC0 DAC0
(12-Bit)
VREFVREF
UART0
P3.0
P3.7
P3
Drv
ADC2
200ksps
(10-Bit)
A
M
U
X
MONEN WDT
VREF2
VREFD
P4 Latch
P7 Latch
P5 Latch
P6 Latch
P7.0
P7.7
P7
DRV
P5.0
P5.7
P5
DRV
P6.0
P6.7
P6
DRV
P4
DRV P4.5
P4.6
P4.7
External Data Memory Bus
Addr[7:0]
Addr[15:8]
Ctrl Latch
Data Latch
CANTX
CANRX
CAN
2.0B
ADC0
1Msps
(16-Bit)
VRGND0
A
D
C
0
D
A
T
A
A
D
C
1
D
A
T
A
-
+D
I
F
F
DMA
Interface
DAC1
Temp
Sensor
EMIF
Control
VDD
VDD
VDD
DGND
DGND
DGND
AV+
AGND
VREF0
AGND
AV+
VRGND
1
VREF1
AGND
AVDD
AIN0
AIN0G
VBGAP
0
CNVSTR
0
ADC1
1Msps
(16-Bit)
AGND
AV+
AIN1
AIN1G
VBGAP
1CNVSTR
1
32X136
CANRAM
P2.7
P2.6
+
-
CP0
P2.3
P2.2
+
-
CP1
P2.5
P2.4
+
-
CP2
C8051F060/1/2/3/4/5/6/7
22 Rev. 1.2
Figure 1.2. C8051F061 / C8051F063 Block Diagram
P3
Drv
P0, P1, P2,
P3 Latches
JTAG
Logic
TCK
TMS
TDI
TDO
UART1
SMBus
SPI Bus
PCA
64kbyte
FLASH
256 byte
RAM
VDD Monitor
SFR Bus
8
0
5
1
C
o
r
e
Timer s 0, 1,
2,3,4
P0
Drv
C
R
O
S
S
B
A
R
Reset
/RST
XTAL1
XTAL2 External Oscillator
Circuit System Clock
Trimm ed Internal
Oscillator
Digital Power
Analog Pow er
Debug HW
Boundar y Scan
4kby te R AM
P2.0
P2.7
P1.0/
AIN2.0
P1.7/
AIN2.7
P0.0
P0.7
P1
Drv
P2
Drv
DAC0 DAC0
(12-Bit)
VREFVREF
UART0
ADC2
200ksps
(10-Bit)
A
M
U
X
MONEN WDT
VREF2
VREF2
External Data Memory Bus
CANTX
CANRX
CAN
2.0B
ADC0
1Msps
(16-Bit)
VRGND0
A
D
C
0
D
A
T
A
A
D
C
1
D
A
T
A
-
+D
I
F
F
DMA
Interface
DAC1
Temp
Sensor
EMIF
Control
VDD
VDD
VDD
DGND
DGND
DGND
AV+
AGND
VREF0
AGND
AV+
VRGND
1
VREF1
AGND
AVDD
AIN0
AIN0G
VBGAP
0
CNVSTR
0
ADC1
1Msps
(16-Bit)
AGND
AV+
AIN1
AIN1G
VBGAP
1CNVSTR
1
32X136
CANRAM
P2.7
P2.6
+
-
CP0
P2.3
P2.2
+
-
CP1
P2.5
P2.4
+
-
CP2
P4 Latch
P7 Latch
P5 Latch
P6 Latch
P7
DRV
P5
DRV
P6
DRV
P4
DRV
Addr[7:0]
Addr[15:8]
Ctrl Latch
Data Latch
C8051F060/1/2/3/4/5/6/7
Rev. 1.2 23
Figure 1.3. C8051F064 / C8051F066 Block Diagram
P0, P1, P2,
P3 Latches
JTAG
Logic
TCK
TMS
TDI
TDO
UART1
SMBus
SPI Bus
PCA
256 byte
RAM
VDD Monitor
SFR Bus
8
0
5
1
C
o
r
e
Timers 0,
1, 2,3,4
P0
Drv
C
R
O
S
S
B
A
R
Reset
/RST
XTAL1
XTAL2 External Oscillator
Circuit System Clock
Trimmed Internal
Oscillator
Digital Power
Analog Power
Debug HW
Boundary Scan
4kbyte RAM
P2.0
P2.7
P1.0
P1.7
P0.0
P0.7
P1
Drv
P2
Drv
Data Bus
Address Bus
Bus Control
VREFVREF
UART0
P3.0
P3.7
P3
Drv
MONEN WDT
P4 Latch
P7 Latch
P5 Latch
P6 Latch
P7.0
P7.7
P7
DRV
P5.0
P5.7
P5
DRV
P6.0
P6.7
P6
DRV
P4
DRV P4.5
P4.6
P4.7
External Data Memory Bus
Addr[7:0]
Addr[15:8]
Ctrl Latch
Data Latch
ADC0
1Msps
(16-Bit)
VRGND0
A
D
C
0
D
A
T
A
A
D
C
1
D
A
T
A
-
+D
I
F
F
DMA
Interface
EMIF
Control
VDD
VDD
VDD
DGND
DGND
DGND
AV+
AGND
VREF0
AGND
AV+
VRGND1
VREF1
AGND
AVDD
AIN0
AIN0G
VBGAP0
CNVSTR0
ADC1
1Msps
(16-Bit)
AGND
AV+
AIN1
AIN1G
VBGAP1
CNVSTR1
P2.3
P2.2
+
-
CP1
P2.5
P2.4
+
-
CP2
P2.7
P2.6
+
-
CP0
FLASH
Memory
64k byte
(C8051F064)
32k byte
(C8051F066)
C8051F060/1/2/3/4/5/6/7
24 Rev. 1.2
Figure 1.4. C8051F065 / C8051F067 Block Diagram
P3
Drv
P0, P1, P2,
P3 Latches
JTAG
Logic
TCK
TMS
TDI
TDO
UART1
SMBus
SPI Bus
PCA
FLASH
Memory
64k byte
(C8051F065)
32k byte
(C8051F067)
256 byte
RAM
VDD Monitor
SFR Bus
8
0
5
1
C
o
r
e
Timers 0,
1, 2,3,4
P0
Drv
C
R
O
S
S
B
A
R
Reset
/RST
XTAL1
XTAL2 External Oscillator
Circuit System Clock
Trimmed Internal
Oscillator
Digital Power
Analog Power
Debug HW
Boundary Scan
4kbyte RAM
P2.0
P2.7
P1.0
P1.7
P0.0
P0.7
P1
Drv
P2
Drv
VREFVREF
UART0
MONEN WDT
External Data Memory Bus
ADC0
1Msps
(16-Bit)
VRGND0
A
D
C
0
D
A
T
A
A
D
C
1
D
A
T
A
-
+D
I
F
F
DMA
Interface
EMIF
Control
VDD
VDD
VDD
DGND
DGND
DGND
AV+
AGND
VREF0
AGND
AV+
VRGND1
VREF1
AGND
AVDD
AIN0
AIN0G
VBGAP0
CNVSTR0
ADC1
1Msps
(16-Bit)
AGND
AV+
AIN1
AIN1G
VBGAP1
CNVSTR1
P4 Latch
P7 Latch
P5 Latch
P6 Latch
P7
DRV
P5
DRV
P6
DRV
P4
DRV
Addr[7:0]
Addr[15:8]
Ctrl Latch
Data Latch
P2.3
P2.2
+
-
CP1
P2.5
P2.4
+
-
CP2
P2.7
P2.6
+
-
CP0
C8051F060/1/2/3/4/5/6/7
Rev. 1.2 25
1.1. CIP-51™ Microcontroller Core
1.1.1. Fully 8051 Compatible
The C8051F06x family of devices utilizes Silicon Labs' proprietary CIP-51 microcontroller core. The CIP-
51 is fully compatible with the MCS-51™ instruction set; standard 803x/805x assemblers and compilers
can be used to develop software. The core has all the peripherals included with a standard 805 2, inclu din g
five 16-bit counter/timers, two full-duplex UARTs, 256 bytes of internal RAM, 128 byte Special Function
Register (SFR) address space, and bit-addressable I/O Ports.
1.1.2. Improved Throughput
The CIP-51 employ s a p ipelined architectu re that grea tly increases it s instr uction throughpu t over the st an-
dard 8051 architecture. In a standard 8051, all instructions except for MUL and DIV take 12 or 24 system
clock cycles to execute with a maximum system clock of 12-to-24 MHz. By contrast, the CIP-51 core exe-
cutes 70% of its instructions in one or two syste m cloc k cycles, with only four instructions taking more than
four system clock cycles.
The CIP-51 has a total of 109 instructions. The table below shows the total number of instructions that
require each execution time.
With the CIP-51's maximum system clock at 25 MHz, it has a peak throughput of 25 MIPS. Figure 1.5
shows a comparison of peak throughputs of various 8-bit microcontroller cores with their maximum system
clocks.
Figure 1.5. Comparison of Peak MCU Execution Speeds
Clocks to Execute 1 22/333/444/55 8
Number of Instructions 26505147 3 1 2 1
5
10
15
20
ADuC812
8051
(16 MHz clk)
Philips
80C51
(33 MHz clk)
Microchip
PIC17C75x
(33 MHz clk)
Silicon Labs
CIP-51
(25 MH z clk)
MIPS
25
C8051F060/1/2/3/4/5/6/7
26 Rev. 1.2
1.1.3. Additional Features
The C8051F06x MCU family includes several key enhancements to the CIP-51 core and peripherals to
improve overall performance and ease of use in end applications.
The extended interrupt handler provides 22 interrupt sources into the CIP-51, allowing the numerous ana-
log and digital peripherals to interrupt the controller. An interrupt driven system requires less intervention
by the MCU, giving it more effective throughput. The extra interrupt s ources ar e very u seful wh en build ing
multi-tasking, real-time systems.
There are up to se ve n reset sou rces for the MCU: an on-bo ard VDD mo nitor, a Watch dog Timer, a missing
clock detector, a voltage level detection from Comparator0, a forced software reset, the CNVSTR2 input
pin, and the /RST pin. The /RST pin is bi-directional, accommodating an external reset, or allowing the
internally generated POR to be output on the /RST pin. Each reset source except for the VDD monitor and
Reset Input pin may be disabled by the user in software; the VDD monitor is enabled/disabled via the
MONEN pin. The Watchdog Timer may be permanently enabled in software after a power-on reset during
MCU initialization.
The MCU has an internal, stand alone clock generator which is used by default as the system clock after
any reset. If desired, the clock source may be switched on the fly to the external oscillator, which can use a
crystal, ceramic resonator, capacitor, RC, or external clock source to generate the system clock. This can
be extremely useful in low power applications, allowing the MCU to run from a slow (power saving) exter-
nal crystal source, while periodically switching to the fast (up to 25 MHz) internal oscillator as needed.
Figure 1.6. On-Board Clock and Reset
WDT
XTAL1
XTAL2
OSC
Internal
Clock
Generator System
Clock
CIP-51
Microcontroller
Core
Missing
Clock
Detector
(one-
shot)
WDT
Strobe
Software Reset
Extended Interrupt
Handler
Clock Select
/RST
+
-
VDD
Supply
Reset
Timeout
(wired-OR)
System Reset
Supply
Monitor
PRE
Reset
Funnel
+
-
CP0+
Comparator0
CP0-
(Port
I/O)
Crossbar CNVSTR2
(CNVSTR
reset
enable)
(CP0
reset
enable)
EN
WDT
Enable
EN
MCD
Enable
(wired-OR)
VDD Monitor
reset enable
C8051F060/1/2/3/4/5/6/7
Rev. 1.2 27
1.2. On-Chip Memory
The CIP-51 has a standard 8051 program and data address configuration. It includes 256 bytes of data
RAM, with the upper 128 bytes dual-mapped. Indir ect addressing accesses the upper 128 bytes of general
purpose RAM, and direct addressing accesses the 128 byte SFR address space. The CIP-51 SFR
address space contains up to 256 SFR Pages. In this way, the CIP-51 MCU can accommodate the many
SFRs required to control and configure the various peripherals featured on the device. The lower
128 bytes of RAM are ac cessible via dir ect and indir ect addressing. The first 32 bytes are addressable as
four banks of gene ral purpose registers, a nd the next 16 bytes can be byte addressable or bit addressable.
The CIP-51 in the C8051F060/1/2/3/4/5/6/7 MCUs additionally has an on-chip 4 kB RAM block. The on-
chip 4 kB block can be addressed over the entire 64 k external data memory address range (overlapping
4 k boundaries). The C8051F060/2/4/6 also have an external memory interface (EMIF) for accessing off-
chip data memory or memory-mapped peripherals. External data memory address space can be mapped
to on-chip memory only, off-chip memory only, or a combination of the two (addresses up to 4 k directed to
on-chip, above 4 k directed to EMIF). The EMIF is also configurable for multiplexed or non-multiplexed
address/data lines.
The MCU’ s program mem ory consist s of 64 k (C8051 F060/1/2/3/4/5) or 32 k (C8051F066/7) of Flash. This
memory may be reprogrammed in-system in 512 byte sectors, and requires no special off-chip program-
ming voltage. On the C8051F060/1/2/3/4/5, the 1024 bytes from addresses 0xFC00 to 0xFFFF are
reserved. There is also a single 128 byte Scratchpad Memory sector on all devices which may be used by
firmware for non-volatile data storage. See Figure 1.7 for the MCU system memory map.
Figure 1.7. On-Chip Memory Map
PROGRAM/DATA MEMORY
(FLASH)
(Direct and Indirect
Addressing)
0x00
0x7F
Upper 128 RAM
(Indirect Addressing
Only)
0x80
0xFF
Special Function
Registers
(Direct Addressing Only)
DATA MEMORY (RAM)
General Purpose
Registers
0x1F
0x20
0x2F
Bit Addr essable Lower 128 RAM
(Direct and Indirect
Addressing)
0x30
INTERNAL DATA ADDRESS SPACE
EXTERNAL DATA ADDRESS SPACE
XRAM - 4096 Bytes
(accessable using MOVX
instruction)
0x0000
0x0FFF
Off-chip XRAM space
(C8051F060/2/4/6 O nly)
0x1000
0xFFFF
FLASH
(In-System
Prog r ammable in 51 2
Byte Sectors)
0x0000
0xFFFF RESERVED
0xFC00
0xFBFF
Scrachpad Memory
(data only)
0x1007F
0x10000
Up To
256 SFR Pages
1
3
02
C8051F060/1/2/3/4/5
FLASH
(In-System
Prog r ammable in 51 2
Byte Sectors)
0x0000
0xFFFF
RESERVED
0x8000
0x7FFF
Scrachpad Memory
(data only)
0x1007F
0x10000
C8051F066/7
C8051F060/1/2/3/4/5/6/7
28 Rev. 1.2
1.3. JTAG Debug and Boundary Scan
The C8051F06x family has on-chip JTAG boundary scan and debug circuitry that provides non-intrusive,
full speed, in-circuit debugging using the production part installed in the end application, via the four-pin
JTAG interface. The JTAG port is fully compliant to IEEE 1149.1, providing full bounda ry scan for test and
manufacturing purposes.
Silicon Laboratories' debugging system supports inspection and modification of memory and registers,
breakpoints, watchpoints, a stack monitor, and single stepping. No additional target RAM, program mem-
ory, timers, or communications channels are required. All the digital and analog peripherals are functional
and work correctly while debugging. All the peripher als (except for the ADCs and SMBus) are stalled when
the MCU is halted, during single stepping, or at a breakpoint in order to keep them synchronized with
instruction execution.
The C8051F060DK development kit provides all the hardware and software necessa ry to develop applica-
tion code and perform in-circuit debugging with the C8051F06x MCUs. The kit includes a Windows (95 or
later) developm ent environm ent, a serial ad apter for conn ecting to the JTAG port , and a target application
board with a C8051F060 MCU installed. All of the necessary communication cables and a wall-mount
power supply are also supplied with the development kit. Silicon Labs’ debug environment is a vastly supe-
rior configuration for developing and debugging embedded applications compared to standard MCU emu-
lators, which use on-board "ICE Chips" and target cables and require the MCU in the application board to
be socketed. Silicon Labs' debug environment both increases ease of use and preserves the performance
of the precision, on-chip analog peripherals.
Figure 1.8. Development/In-System Debug Diagram
TARGET PCB
Serial
Adapter
C8051
F060
JTAG (x4), VDD, GND
WINDOWS 95 OR LATER
Silicon Labs Integrated
Development Environment
C8051F060/1/2/3/4/5/6/7
Rev. 1.2 29
1.4. Programmable Digital I/O and Crossbar
Three standard 8051 Ports (0, 1, and 2) are available on the MCUs. The C8051F060/2/4/6 have 4 addi-
tional 8-bit ports (3, 5, 6, and 7), and a 3-bit port (port 4) for a total of 59 general-purpose I/O Pins. The
Ports behave like the standard 8051 with a few enhancements.
Each port pin can be configur ed as ei ther a pu sh-pull or open- drain outpu t. Also, the "weak pu ll-up s" which
are normally fixed on an 8051 can be globally disabled, providing additional power s aving capabilities for
low-power applications.
Perhaps the most uniq ue enhancement is the Digit al Crossba r. This is a large digital switching network that
allows mapping of internal digital system resources to Port I/O pins on P0, P1, P2, and P3.
(See Figure 1.9) Unlike microcontrollers with standard multiplexed digital I/O ports, all combinations of
functions are supported with all package options offered.
The on-chip counter/timers, serial buses, HW interrupts, comparator outputs, and other digital signals in
the controller can be configured to appear on the Port I/O pins specified in the Crossbar Control registers.
This allows the user to select the exact mix of general purpose Port I/O and digital resources needed for
the particular applicat ion .
Figure 1.9. Digital Crossbar Diagram
External
Pins
Digital
Crossba
r
Priority
Decoder
SMBus
2
SPI 4
UART0
2
PCA
2
T0, T1, T2,
T2EX, T3,
T3EX,
T4,T4EX,
/INT0,
/INT1
P1.0
P1.7
P2.0
P2.7
P0.0
P0.7
Highest
Priority
Lowest
Priority
8
8
Comptr.
Outputs
(Int ernal D igital Signals )
Highest
Priority
Lowest
Priority
UART1
6
2
P3.0
P3.7
8
8
P0MDOUT, P1MDOUT,
P2MDOUT, P3MDOUT
Registers
XB R0, XBR 1, XB R2 ,
XBR3 P1MDIN,
P2MDIN, P3MDIN
Registers
P1
I/O
Cells
P3
I/O
Cells
P0
I/O
Cells
P2
I/O
Cells
8
Port
Latches
P0
P1
P2
8
8
8
P3
8
(P2.0-P2.7)
(P1.0-P1.7)
(P0.0-P0.7)
(P3.0-P3.7)
To ADC 2 Input
(C8051F060/1/2/3)
To Com par at ors
/SYSCLK
CNVSTR2
C8051F060/2/4/6
Only
C8051F060/1/2/3/4/5/6/7
30 Rev. 1.2
1.5. Programmable Counter Array
The C8051F06x MCU family includes an on-board Programmable Counter/Timer Array (PCA) in addition
to the five 16-bit general purpose counter/timers. The PCA consists of a dedicated 16-bit counter/timer
time base with 6 programmable capture/compare modules. The timebase is clocked from one of six
sources: the system clock divided by 12, the system clock divided by 4, Timer 0 overflow, an External
Clock Input (ECI pin), the system clock, or the external oscillator source divided by 8.
Each capture/compare module can be configured to operate in one of six modes: Edge-Triggered Capture,
Software Timer, High Speed Output, Frequency Ou tput, 8-Bit Pulse Wid th Mo dulator, or 16-Bit Pu lse Wid t h
Modulator. The PCA Captur e/Co mpare Modu le I/O and Ex ternal Clo ck Inp ut ar e route d to the M CU Port I/
O via the Digital Crossbar.
Figure 1.10. PCA Block Diagram
Capture/Compare
Module 1
Capture/Compare
Module 0 Capture/Compare
Module 2 Capture/Compare
Module 3
CEX1
ECI
Crossbar
CEX2
CEX3
CEX0
Port I/O
16-Bit Counter/T ime r
PCA
CLOCK
MUX
SYSCLK/12
SYSCLK/4
Timer 0 Overflow
ECI
SYSCLK
External Clock/8
Capture/Compare
Module 4
CEX4
Capture/Compare
Module 5
CEX5
C8051F060/1/2/3/4/5/6/7
Rev. 1.2 31
1.6. Controller Area Network
The C8051F060/1/2/3 devices feature a Controller Area Network (CAN) controller that implements serial
communication using the CAN protocol. The CAN controller facilitates communication on a CAN network
in accordance with th e Bosch spe cification 2.0A ( basic CAN) and 2.0B (full CAN). The CAN controller con-
sists of a CAN Core, Message RAM (separate from the C8051 RAM), a message handler state machine,
and control registers.
The CAN controller can operate at bit rates up to 1 Mbit/second. Silicon Labs CAN has 32 message
objects each having its own identifier mask used for acceptance filtering of received messages. Incoming
data, message o bject s and identifier masks are stor ed in the CAN me ssage RAM . All protocol functions for
transmission of data and acceptance filtering is performed by the CAN controller and not by the C8051
MCU. In this way, minimal CPU bandwidth is used for CAN communication. The C8051 configures the
CAN controller, accesses receiv ed data, and passes data for transmission via Special Function Registers
(SFR) in the C8051.
Figure 1.11. CAN Controller Overview
Message Handler
REGISTERS
Message RAM
(32 Message Objects)
CAN
Core
TX RX
CAN Controller C
8
0
5
1
M
C
U
Interrupt
S
F
R
's
CANTX CANRX
C8051F060/1/2/3
C8051F060/1/2/3/4/5/6/7
32 Rev. 1.2
1.7. Serial Ports
The C8051F06x MCU Family includes two Enhanced Full-Duplex UARTs, an enhanced SPI Bus, and
SMBus/I2C. Each of the serial buses is fully implemented in hardware and makes extensive use of the
CIP-51's interrupts, thus requiring very little intervention by the CPU. The serial buses do not "share"
resources such as timers, interr upts, or Por t I/O, so any or all of th e serial buses may be used tog ether with
any other.
C8051F060/1/2/3/4/5/6/7
Rev. 1.2 33
1.8. 16-Bit Analog to Digital Converters
The C8051F060/1/2/3/4/5/6/7 devices have two on-chip 16-bit SAR ADCs (ADC0 and ADC1), which can
be used independently in single-ended mode, or together in differential mode. ADC0 and ADC1 can
directly access on-chip or external RAM, using the DMA interface. With a maximum throughput of 1 Msps,
the ADCs offer 16 bit performance with two available linearity grades. ADC0 and ADC1 each have the
capability to use dedicated, on-chip voltage reference circuitry or an external voltage reference source.
The ADCs are under full control of the CIP-51 microcontroller via the associated Special Function Regis-
ters. The system controller can also put the ADCs into shutdown mode to save power.
Conversions can be started in four ways; a software command, an overflow of Timer 2, an overflow of
Timer 3, or an external signal input. This flexibility allows the start of conversion to be triggered by sof tware
events, external HW signals, or a periodic timer overflow signal. The two ADCs can operate independently,
or be synchronized to perform con versions at the same time. Con version comp letions are indicated by st a-
tus bits, and can generate interrupts. The resulting 16-bit data words are latched into SFRs upon comple-
tion of a conversion. A DMA interface is also provided, which can gather conversions from the ADCs, and
directly store them to on-chip or external RAM.
ADC0 also contains Window Compare registers, which can be configured to interrupt the controller when
ADC0 data is within or outside of a specified range. ADC0 can monitor a key voltage continuously in back-
ground mode, and not interrupt the controller unle ss the converted data is within the specified window.
Figure 1.12. 16-Bit ADC Block Diagram
AIN0G
REF
AIN0
Start Conversion
Timer 3 Overflow
Timer 2 Overflow
Write to AD1BUSY
CNVSTR1
16-Bit
SAR
ADC0
(DC, -0.2 to 0.6 V)
AIN1G
REF
AIN1
Start Conversion
16-Bit
SAR
ADC1
(DC, -0.2 to 0.6 V)
Write to AD0BUSY
Timer 3 Overflow
Timer 2 Overflow
W rite to AD0BUSY
CNVSTR0
Configuration and Control
Registers
DMA
Interface
ADC0
Window
Compare
Logic
16
ADC Data
Registers
16
C8051F060/1/2/3/4/5/6/7
34 Rev. 1.2
1.9. 10-Bit Analog to Digital Converter
The C8051F060/1/2/3 devices have an on-board 10-bit SAR ADC (ADC2) with a 9-channel input multi-
plexer and programmable gain amplifier. This ADC features a 200 ksps maximum throughput and true 10-
bit performance with an INL of ±1LSB. Eight input pins are available for measurement and can be pro-
grammed as single-ended or differential inputs. Additionally, the on-chip temperature sensor can be used
as an input to the ADC. The ADC is under full control of the CIP-51 microcontroller via the S pecial Fun ction
Registers. The ADC2 voltage reference is selected between the analog power supply (AV+) and the exter-
nal VREF2 pin. User software may put ADC2 into shutdown mode to save power.
A flexible conversion scheduling system allows ADC2 conversions to be initiated by software command s,
timer overflows, or an external input signal. Conversion completions are indicated by a status bit and an
interrupt (if e na bled), an d the resu ltin g 10 -bit d ata word is la tched in to two SF R locations up on co mpletio n.
ADC2 also contains Window Compare registers, which can be configured to interrupt the controller when
ADC2 data is within or outside of a specified range. ADC2 can monitor a key voltage continuously in back-
ground mode, and not interrupt the controller unle ss the converted data is within the specified window.
Figure 1.13. 10-Bit ADC Diagram
10
9-to-1
AMUX
AIN2.0
AIN2.1
AIN2.2
AIN2.3
AIN2.4
AIN2.5
AIN2.6
AIN2.7
Configuration and Control Registers
Analog Multiplexer
10-Bit
SAR
ADC
Start Conversion Timer 3 Overflow
Timer 2 Overflow
Write to AD2BUSY
CNVSTR2 Input
ADC Data
Registers
Conversion
Complete
Interrupt
VREF2 Pin
AV+
VREF
Single-ended or
Differential Measurement
TEMP
SENSOR
AGND
ADC2
Window
Compare
Logic
10
C8051F060/1/2/3/4/5/6/7
Rev. 1.2 35
1.10. 12-bit Digital to Analog Converters
The C8051F060/1/2/3 MCUs have two integrated 12-bit Digital to Analog Converters (DACs). The MCU
data and control interface to each DAC is via the Special Function Registers. The MCU can place either or
both of the DACs in a low power shutdown mode.
The DACs are voltage output mode and include a flexible output scheduling mechanism. This scheduling
mechanism allows DAC output updates to be forced by a software write or scheduled on a Timer 2, 3, or 4
overflow. The DAC voltage reference is supplied from the dedicated VREFD input pin on C8051F060/2
devices or via the VREF2 pin on C8051F061/3 devices, which is shared with ADC2. The DACs are espe-
cially useful as references for the comparators or offsets for the differential inputs of the ADCs.
Figure 1.14. DAC System Block Diagram
DAC0
DAC1
VREF
VREF
CIP-51
and
Interrupt
Handler
DAC0
DAC1
SFR's
(Data
and
Control)
C8051F060/1/2/3/4/5/6/7
36 Rev. 1.2
1.11. Analog Comparators
The C8051F060/1/2/3/4/5/6/7 MCUs include three analog comparators on-chip. The comparators have
software programmable hysteresis and response time. Each comparator can generate an interrupt on its
rising edge, falling edge, or both. The interrupts are capable of waking up the MCU from sleep mode, and
Comparator 0 can be used as a reset source. The output state of the comparators can be polled in soft-
ware or routed to Port I/O pins via the Crossbar. Outputs from the comparator can be routed through the
crossbar. The comparators can be programmed to a low power shutdown mode when not in use.
Figure 1.15. Comparator Block Diagram
+
-
CPn+
CPn-
CIP-51
and
Interrupt
Handler
CPn
CPn Output
(Port I/O)
SFR's
(Data
and
Control)
CROSSBAR
3 Comparators
Com parator i nput s
Por t 2. [ 7: 2]
C8051F060/1/2/3/4/5/6/7
Rev. 1.2 37
2. Absolute Maximum Ratings
Table 2.1. Absolute Maximum Ratings*
Parameter Conditions Min Typ Max Units
Ambient temperature under bias -55 125 °C
Storage Temperature -65 150 °C
Voltage on any pin (except VDD, AV+, AVDD, and
Port 0) with respect to DGND -0.3 VDD +
0.3 V
Voltage on any Port 0 Pin with respect to DGND. -0.3 5.8 V
Voltage on VDD, AV+, or AVDD with respect to DGND -0.3 4.2 V
Maximum Total current through VDD, AV+, AVDD,
DGND, and AGND 800 mA
Maximum output current sunk by any Port pin 100 mA
Maximum output current sunk by any other I/O pin 50 mA
Maximum output current sourced by any Port pin 100 mA
Maximum output current sourced by any other I/O pin 50 mA
* Stre sse s ab ov e th os e lis te d un der “Abso l u te M axi mum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device s at those or any other conditions
above those indicated in the operation listings of this specification is not implied. Exposure to maximum
rating conditions for extended periods may affect device reliability.
C8051F060/1/2/3/4/5/6/7
38 Rev. 1.2
3. Global DC Electrical Characteristics
Table 3.1. Global DC Electrical Characteristics
-40 to +85 °C, 25 M Hz System Clock unl es s oth erw is e spe ci fie d .
Parameter Conditions Min Typ Max Units
Analog Supply Voltage (AV+,
AVDD) (Note 1) 2.7 3. 0 3.6 V
Digital Supply Voltage (VDD) 2.7 3.0 3.6 V
Analog-to-Digital Supply Delta
(|VDD - AV+| or |VDD - AVDD|) 0.5 V
Supply Current from Analog
Peripherals (active) Internal REF, ADC, DAC, Com-
parators all enabled. (Note 2) 14 mA
Supply Current from Analog
Peripherals (inactive) Internal REF, ADC, DAC, Com-
parators all disabled, oscillator
disabled.
0.2 µA
Supply Current from CPU and
Digital Peripherals (CPU active)
(Note 3)
VDD=2.7 V, Clock=25 MHz
VDD=2.7 V, Clock=1 MHz
VDD=2.7 V, Clock=32 kHz
VDD=3.0 V, Clock=25 MHz
VDD=3.0 V, Clock=1 MHz
VDD=3.0 V, Clock=32 kHz
18
0.7
30
20
1.0
35
mA
mA
µA
mA
mA
µA
Supply Current from CPU and
Digital Peripherals (CPU inac-
tive, not accessing Flash)
(Note 3)
VDD=2.7 V, Clock=25 MHz
VDD=2.7 V, Clock=1 MHz
VDD=2.7 V, Clock=32 kHz
VDD=3.0 V, Clock=25 MHz
VDD=3.0 V, Clock=1 MHz
VDD=3.0 V, Clock=32 kHz
13
0.5
20
16
0.8
23
mA
mA
µA
mA
mA
µA
Supply Current with all systems
shut down Oscillator not running 0.2 µA
VDD Supply RAM Data Reten-
tion Voltage 1.5 V
SYSCLK (System Clock) (Note 4) 0 25 MHz
Specified Operating Tempera-
ture Range -40 +85 °C
Note 1: Analog Supply AV+ must be greater than 1 V for VDD monitor to operate.
Note 2: Internal Oscillator and VDD Monitor current not included. Individual supply current contributions
for each peripheral are listed in the chapter.
Note 3: Current increases linearly with supply Voltage.
Note 4: SYSCLK must be at least 32 kHz to enable debugging.
C8051F060/1/2/3/4/5/6/7
Rev. 1.2 39
4. Pinout and Package Definitions
Table 4.1. Pin Definitions
Name
Pin Numbers
Type DescriptionF060 F061 F064 F065
F062 F063 F066 F067
VDD 37, 64,
90 26, 40,
55 37, 64,
90 26, 40,
55 Digital Supply Voltage. Must be tied to +2.7 to
+3.6 V.
DGND 38, 63,
89 27, 39,
54 38, 63,
89 27, 39,
54 Digital Ground. Must be tied to Ground.
AV+ 11, 16,
24 7, 10,
18 11, 16,
24 7, 10,
18 Analog Supply Voltage. Must be tied to +2.7 to
+3.6 V.
AVDD 13 23 13 23 Analog Supply Voltage. Must be tied to +2.7 to
+3.6 V.
AGND 10, 14,
17, 23 6, 11,
19, 22 10, 14,
17, 23 6, 11,
19, 22 Analog Ground. Must be tied to Ground.
TMS 96 52 96 52 D In JTAG Test Mode Select with internal pull-up.
TCK 97 53 97 53 D In JTAG Test Clock with internal pull-up.
TDI 98 56 98 56 D In JTAG Test Data Input with internal pull-up. TDI is
latched on the rising edge of TCK.
TDO 99 57 99 57 D Out JTAG Test Data Output with internal pull-up. Data is
shifted out on TDO on the falling edge of TCK. TDO
output is a tri-state driver.
/RST 100 58 100 58 D I/O Device Reset. Open-drain output of internal VDD
monitor. Is driven low when VDD is <2.7 V and
MONEN is high. An external source can initiate a
system reset by driving this pin low.
XTAL1 26 20 26 20 A In Crystal Input. This pin is the return for the internal
oscillator circuit for a crystal or ceramic resonator.
For a precision internal clock, connect a crystal or
ceramic resonator from XTAL1 to XTAL2. If over-
driven by an external CMOS clock, this becomes
the system clock.
XTAL2 27 21 27 21 A Out Crystal Output. This pin is the excitation driv er for a
crystal or ceramic resonator.
MONEN 28 63 28 63 D In VDD Monitor Enable. When tied high, this pin
enables the internal VDD monitor, which forces a
system reset when VDD is < 2.7 V. When tied low,
the internal VDD monitor is disabled. Recom-
mended configuration is to connect directly to VDD.
VREF 4 61 4 61 A Out Bandgap Voltage Reference Output
VREF0 21 15 21 15 A I/O Bandgap Voltage Reference Output for ADC0.
ADC0 Voltage Reference Input.
C8051F060/1/2/3/4/5/6/7
40 Rev. 1.2
VRGND0 20 14 20 14 A In ADC0 Voltage Reference Ground. This pin should
be grounded if using the ADC.
VBGAP0 22 16 22 16 A Out ADC0 Bandgap Bypass Pin.
VREF1 6 2 6 2 A I/O Bandgap Voltage Reference Output for ADC1.
ADC1 Voltage Reference Input.
VRGND1 7 3 7 3 A In ADC1 Voltage Reference Ground. This pin should
be grounded if using the ADC.
VBGAP1 5 1 5 1 A Out ADC1 Bandgap Bypass Pin.
VREF2 2 A In ADC2 Voltage Reference Input.
62 A In ADC2, DAC0, and DAC1 Voltage Reference Input.
VREFD 3 A In DAC0 and DAC1 Voltage Refe re nc e Inp u t.
AIN0 18 12 18 12 A In ADC0 Signal Input (See ADC0 Specification for
complete description).
AIN0G 19 13 19 13 A In ADC0 DC Bias Input (See ADC0 Specification for
complete description).
AIN1 9 5 9 5 A In ADC1 Signal Input (See ADC1 Specification for
complete description).
AIN1G 8 4 8 4 A In ADC1 DC Bias Input (See ADC1 Specification for
complete description).
CNVSTR0 15 9 15 9 D In External Conversion Start Source for ADC0
CNVSTR1 12 8 12 8 D In External Conversion Start Source for ADC1
CANTX 94 59 D Out Controller Area Network Transmit Output.
CANRX 95 6 0 D In Controller Area Network Receive Input.
DAC0 25 17 A Out Digital to Analog Converter 0 Voltage Output. (See
DAC Specification for complete description).
DAC1 1 64 A Out Digital to Analog Converter 1 Voltage Output. (See
DAC Specification for complete description).
P0.0 62 51 62 51 D I/O Port 0. 0. See Port Input/Ou tput section for complete
description.
P0.1 61 50 61 50 D I/O Port 0. 1. See Port Input/Ou tput section for complete
description.
P0.2 60 49 60 49 D I/O Port 0. 2. See Port Input/Ou tput section for complete
description.
P0.3 59 48 59 48 D I/O Port 0. 3. See Port Input/Ou tput section for complete
description.
P0.4 58 47 58 47 D I/O Port 0. 4. See Port Input/Ou tput section for complete
description.
Table 4.1. Pin Definitions (Continued)
Name
Pin Numbers
Type DescriptionF060 F061 F064 F065
F062 F063 F066 F067
C8051F060/1/2/3/4/5/6/7
Rev. 1.2 41
P0.5 57 46 57 46 D I/O Port 0. 5. See Port Input/Ou tput section for complete
description.
P0.6 56 45 56 45 D I/O Port 0. 6. See Port Input/Ou tput section for complete
description.
P0.7 55 44 55 44 D I/O Port 0. 7. See Port Input/Ou tput section for complete
description.
P1.0/AIN2.0 36 33 36 33 D I/O
A In Port 1.0. See Port Input/Output se ction for complete
description.
ADC2 Input Channel 0 (C8051F060/1/2/3 Only).
P1.1/AIN2.1 35 32 35 32 D I/O
A In Port 1.1. See Port Input/Output se ction for complete
description.
ADC2 Input Channel 1 (C8051F060/1/2/3 Only).
P1.2/AIN2.2 34 31 34 31 D I/O
A In Port 1.2. See Port Input/Output se ction for complete
description.
ADC2 Input Channel 2 (C8051F060/1/2/3 Only).
P1.3/AIN2.3 33 30 33 30 D I/O
A In Port 1.3. See Port Input/Output se ction for complete
description.
ADC2 Input Channel 3 (C8051F060/1/2/3 Only).
P1.4/AIN2.4 32 29 32 29 D I/O
A In Port 1.4. See Port Input/Output se ction for complete
description.
ADC2 Input Channel 4 (C8051F060/1/2/3 Only).
P1.5/AIN2.5 31 28 31 28 D I/O
A In Port 1.5. See Port Input/Output se ction for complete
description.
ADC2 Input Channel 5 (C8051F060/1/2/3 Only).
P1.6/AIN2.6 30 25 30 25 D I/O
A In Port 1.6. See Port Input/Output se ction for complete
description.
ADC2 Input Channel 6 (C8051F060/1/2/3 Only).
P1.7/AIN2.7 29 24 29 24 D I/O
A In Port 1.7. See Port Input/Output se ction for complete
description.
ADC2 Input Channel 7 (C8051F060/1/2/3 Only).
P2.0 46 43 46 43 D I/O Port 2. 0. See Port Input/Ou tput section for complete
description.
P2.1 45 42 45 42 D I/O Port 2. 1. See Port Input/Ou tput section for complete
description.
P2.2 44 41 44 41 D I/O Port 2. 2. See Port Input/Ou tput section for complete
description.
P2.3 43 38 43 38 D I/O Port 2. 3. See Port Input/Ou tput section for complete
description.
P2.4 42 37 42 37 D I/O Port 2. 4. See Port Input/Ou tput section for complete
description.
Table 4.1. Pin Definitions (Continued)
Name
Pin Numbers
Type DescriptionF060 F061 F064 F065
F062 F063 F066 F067
C8051F060/1/2/3/4/5/6/7
42 Rev. 1.2
P2.5 41 36 41 36 D I/O Port 2. 5. See Port Input/Ou tput section for complete
description.
P2.6 40 35 40 35 D I/O Port 2. 6. See Port Input/Ou tput section for complete
description.
P2.7 39 34 39 34 D I/O Port 2. 7. See Port Input/Ou tput section for complete
description.
P3.0 54 54 D I/O Port 3.0. See Port Input/Output section fo r complete
description.
P3.1 53 53 D I/O Port 3.1. See Port Inpu t/Output section for complete
description.
P3.2 52 52 D I/O Port 3.2. See Port Inpu t/Output section for complete
description.
P3.3 51 51 D I/O Port 3.3. See Port Inpu t/Output section for complete
description.
P3.4 50 50 D I/O Port 3.4. See Port Inpu t/Output section for complete
description.
P3.5 49 49 D I/O Port 3.5. See Port Inpu t/Output section for complete
description.
P3.6 48 48 D I/O Port 3.6. See Port Inpu t/Output section for complete
description.
P3.7 47 47 D I/O Port 3.7. See Port Inpu t/Output section for complete
description.
P4.5/ALE 93 93 D I/O Port 4.5. See Port Input/Ou tput section for complete
description.
ALE Strobe for External Memory Address Bus (Mul-
tiplexed mode).
P4.6/RD 92 92 D I/O Port 4.6. Se e Port Input/ Output sectio n for complete
description.
/RD Strobe for External Memory Address Bus.
P4.7/WR 91 91 D I/O Po rt 4.7. See Port Input/Out put section for c omplete
description.
/WR Strobe for External Memory Address Bus.
P5.0/A8 88 88 D I/O Port 5.0. See Port Input/Output section fo r complete
description.
Bit 8 External Memory Address Bus (Non-multi-
plexed mode).
P5.1/A9 87 87 D I/O Port 5.1. See Port Input/Output section fo r complete
description.
Table 4.1. Pin Definitions (Continued)
Name
Pin Numbers
Type DescriptionF060 F061 F064 F065
F062 F063 F066 F067
C8051F060/1/2/3/4/5/6/7
Rev. 1.2 43
P5.2/A10 86 86 D I/O Port 5.2. See Port Input/Output section for comp lete
description.
P5.3/A11 85 85 D I/O Port 5.3. See Port Input/Output section for complete
description.
P5.4/A12 84 84 D I/O Port 5.4. See Port Input/Output section for comp lete
description.
P5.5/A13 83 83 D I/O Port 5.5. See Port Input/Output section for comp lete
description.
P5.6/A14 82 82 D I/O Port 5.6. See Port Input/Output section for comp lete
description.
P5.7/A15 81 81 D I/O Port 5.7. See Port Input/Output section for comp lete
description.
P6.0/A8m/
A0 80 80 D I/O Po rt 6.0. See Port Input/Out put section for c omplete
description.
Bit 8 External Memory Address Bus (Multiplexed
mode).
Bit 0 External Memory Address Bus (Non-multi-
plexed mode).
P6.1/A9m/
A1 79 79 D I/O Po rt 6.1. See Port Input/Out put section for c omplete
description.
P6.2/A10m/
A2 78 78 D I/O Po rt 6.2. See Port Input/Out put section for c omplete
description.
P6.3/A11m/
A3 77 77 D I/O Po rt 6.3. See Port Input/Out put section for c omplete
description.
P6.4/A12m/
A4 76 76 D I/O Po rt 6.4. See Port Input/Out put section for c omplete
description.
P6.5/A13m/
A5 75 75 D I/O Po rt 6.5. See Port Input/Out put section for c omplete
description.
P6.6/A14m/
A6 74 74 D I/O Po rt 6.6. See Port Input/Out put section for c omplete
description.
P6.7/A15m/
A7 73 73 D I/O Po rt 6.7. See Port Input/Out put section for c omplete
description.
P7.0/AD0m/
D0 72 72 D I/O Po rt 7.0. See Port Input/Out put section for c omplete
description.
Bit 0 External Memory Address/Data Bus (Multi-
plexed mode).
Bit 0 External Memory Data Bus (Non-multiplexed
mode).
P7.1/AD1m/
D1 71 71 D I/O Po rt 7.1. See Port Input/Out put section for c omplete
description.
Table 4.1. Pin Definitions (Continued)
Name
Pin Numbers
Type DescriptionF060 F061 F064 F065
F062 F063 F066 F067
C8051F060/1/2/3/4/5/6/7
44 Rev. 1.2
P7.2/AD2m/
D2 70 70 D I/O Po rt 7.2. See Port Input/Out put section for c omplete
description.
P7.3/AD3m/
D3 69 69 D I/O Po rt 7.3. See Port Input/Out put section for c omplete
description.
P7.4/AD4m/
D4 68 68 D I/O Po rt 7.4. See Port Input/Out put section for c omplete
description.
P7.5/AD5m/
D5 67 67 D I/O Po rt 7.5. See Port Input/Out put section for c omplete
description.
P7.6/AD6m/
D6 66 66 D I/O Po rt 7.6. See Port Input/Out put section for c omplete
description.
P7.7/AD7m/
D7 65 65 D I/O Po rt 7.7. See Port Input/Out put section for c omplete
description.
NC 1, 2, 3,
25, 94,
95
17, 59,
60, 62,
64
No Connection.
Table 4.1. Pin Definitions (Continued)
Name
Pin Numbers
Type DescriptionF060 F061 F064 F065
F062 F063 F066 F067
C8051F060/1/2/3/4/5/6/7
Rev. 1.2 45
Figure 4.1. C8051F060 / C8051F062 Pinout Diagram (TQFP-100)
C8051F060/F062
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
42
43
44
45
46
47
48
49
50
1
2
3
4
5
6
7
8
9
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
75
74
73
72
71
70
69
68
67 P7.6/AD6m/D6
P7.7/AD7m/D7
VDD
DGND
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
P3.3
P6.5/A13m/A5
P6.6/A14m/A6
P6.7/A15m/A7
P7.0/AD0m/D0
P7.1/AD1m/D1
P7.2/AD2m/D2
P7.3/AD3m/D3
P7.4/AD4m/D4
P7.5/AD5m/D5
/RST
TDO
TDI
TCK
TMS
CANRX
CANTX
P4.5/ALE
P4.6/RD
P4.7/WR
VDD
DGND
P5.0/A8
P5.1/A9
P5.2/A10
P5.3/A11
P5.4/A12
P5.5/A13
P5.6/A14
P5.7/A15
P6.0/A8m/A0
P6.1/A9m/A1
P6.2/A10m/A2
P6.3/A11m/A3
P6.4/A12m/A4
AGND
AV+
CNVSTR1
AVDD
AGND
CNVSTR0
AV+
AGND
AIN0
AIN0G
VRGND0
VREF0
VBGAP0
AGND
AV+
DAC0
DAC1
VREF2
VREFD
VREF
VBGAP1
VREF1
VRGND1
AIN1G
AIN1
XTAL1
XTAL2
MONEN
P1.7/AIN2.7
P1.6/AIN2.6
P1.5/AIN2.5
P1.4/AIN2.4
VDD
DGND
P1.3/AIN2.3
P1.2/AIN2.2
P1.1/AIN2.1
P1.0/AIN2.0
P2.7
P2.6
P2.5
P2.4
P2.3
P2.2
P2.1
P2.0
P3.7
P3.6
P3.5
P3.4
P3.2
P3.1
P3.0
C8051F060/1/2/3/4/5/6/7
46 Rev. 1.2
Figure 4.2. C8051F064 / C8051F066 Pinout Diagram (TQFP-100)
C8051F064/F066
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
42
43
44
45
46
47
48
49
50
1
2
3
4
5
6
7
8
9
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
75
74
73
72
71
70
69
68
67 P7.6/AD6m/D6
P7.7/AD7m/D7
VDD
DGND
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
P3.3
P6.5/A13m/A5
P6.6/A14m/A6
P6.7/A15m/A7
P7.0/AD0m/D0
P7.1/AD1m/D1
P7.2/AD2m/D2
P7.3/AD3m/D3
P7.4/AD4m/D4
P7.5/AD5m/D5
/RST
TDO
TDI
TCK
TMS
NC
NC
P4.5/ALE
P4.6/RD
P4.7/WR
VDD
DGND
P5.0/A8
P5.1/A9
P5.2/A10
P5.3/A11
P5.4/A12
P5.5/A13
P5.6/A14
P5.7/A15
P6.0/A8m/A0
P6.1/A9m/A1
P6.2/A10m/A2
P6.3/A11m/A3
P6.4/A12m/A4
AGND
AV+
CNVSTR1
AVDD
AGND
CNVSTR0
AV+
AGND
AIN0
AIN0G
VRGND0
VREF0
VBGAP0
AGND
AV+
NC
NC
NC
NC
VREF
VBGAP1
VREF1
VRGND1
AIN1G
AIN1
XTAL1
XTAL2
MONEN
P1.7
P1.6
P1.5
P1.4
VDD
DGND
P1.3
P1.2
P1.1
P1.0
P2.7
P2.6
P2.5
P2.4
P2.3
P2.2
P2.1
P2.0
P3.7
P3.6
P3.5
P3.4
P3.2
P3.1
P3.0
C8051F060/1/2/3/4/5/6/7
Rev. 1.2 47
Figure 4.3. TQFP-100 Package Drawing
A
A1
A2
b
D
D1
e
E
E1
L
-
0.05
0.95
0.17
-
-
-
-
-
0.45
-
-
1.00
0.22
16.00
14.00
0.50
16.00
14.00
0.60
1.20
0.15
1.05
0.27
-
-
-
-
-
0.75
MIN
(mm) NOM
(mm) MAX
(mm)
100
e
A1
b
A2
A
PIN 1
DESIGNATOR 1
E1 E
D1
D
L
C8051F060/1/2/3/4/5/6/7
48 Rev. 1.2
Figure 4.4. C8051F061 / C8051F063 Pinout Diagram (TQFP-64)
C8051F061/063
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
DAC1
MONEN
VREF2
VREF
CANRX
CANTX
/RST
TDO
TDI
VDD
DGND
TCK
TMS
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
P2.0
P2.1
P2.2
VDD
DGND
P2.3
P2.4
P2.5
P2.6
P2.7
P1.0/AIN2.0
VBGAP1
VREF1
VRGND1
AIN1G
AIN1
AGND
AV+
CNVSTR1
CNVSTR0
AV+
AGND
AIN0
AIN0G
VRGND0
VREF0
VBGAP0
DAC0
AV+
AGND
XTAL1
XTAL2
AGND
AVDD
P1.7/AIN2.7
P1.6/AIN2.6
VDD
DGND
P1.5/AIN2.5
P1.4/AIN2.4
P1.3/AIN2.3
P1.2/AIN2.2
P1.1/AIN2.1
C8051F060/1/2/3/4/5/6/7
Rev. 1.2 49
Figure 4.5. C8051F065 / C8051F067 Pinout Diagram (TQFP-64)
C8051F065/067
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
NC
MONEN
NC
VREF
NC
NC
/RST
TDO
TDI
VDD
DGND
TCK
TMS
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
P2.0
P2.1
P2.2
VDD
DGND
P2.3
P2.4
P2.5
P2.6
P2.7
P1.0
VBGAP1
VREF1
VRGND1
AIN1G
AIN1
AGND
AV+
CNVSTR1
CNVSTR0
AV+
AGND
AIN0
AIN0G
VRGND0
VREF0
VBGAP0
NC
AV+
AGND
XTAL1
XTAL2
AGND
AVDD
P1.7
P1.6
VDD
DGND
P1.5
P1.4
P1.3
P1.2
P1.1
C8051F060/1/2/3/4/5/6/7
50 Rev. 1.2
Figure 4.6. TQFP-64 Package Drawing
A
A1
A2
b
D
D1
e
E
E1
L
-
0.05
0.95
0.17
-
-
-
-
-
0.45
-
-
-
0.22
12.00
10.00
0.50
12.00
10.00
0.60
1.20
0.15
1.05
0.27
-
-
-
-
-
0.75
MIN
(mm) NOM
(mm) MAX
(mm)
1
64
E
E1
e
A1
b
D
D1
PIN 1
DESIGNATOR
A2
A
L
C8051F060/1/2/3/4/5/6/7
Rev. 1.2 51
5. 16-Bit ADCs (ADC0 and ADC1)
The ADC subsystem for the C8051F060/1/2/3/4/5/6/7 consists of two 1 Msps, 16-bit successive-approxi-
mation-register ADCs with integrated tr ack-a nd-ho ld, a Prog ra mma ble Window De te ctor, and a DMA inte r-
face (see block diagrams in Figure 5.1 and Figure 5.2). The ADCs can be configured as two separate,
single-ended ADCs, or as a differential pair. The Data Conversion Modes, Window Detector, and DMA
interface are all configurable un der sof tware contr ol via the Special Function Registers shown in Figu re 5.1
and Figure 5.2. The voltage references used by ADC0 and ADC1 are selected as described in Section 5.2.
The ADCs and their respective track-and-hold circuitry can be independently enabled or disabled with the
Special Function Registers. Either ADC can be enabled by setting the ADnEN bit in the ADC’s Control r eg-
ister (ADCnCN) to logic 1. The ADCs are in low power shutdown when these bits are logic 0.
Figure 5.1. 16-Bit ADC0 and ADC1 Control Path Diagram
AIN0G
REF
16
AV+
AD0EN
SYSCLK
AIN0
Star t Conversion
Timer 3 Overflow
Timer 2 Overflow
00
01
10
11
AD0BUSY (W)
CNVSTR0
16-Bit
SAR
ADC0
ADC0CF
AD0OCAL
AD0LCAL
AD0GCAL
AD0SCAL
AD0SC0
AD0SC1
AD0SC2
AD0SC3
ADC0CN
AD0WINT
AD0CM0
AD0CM1
AD0BUSY
AD0INT
AD0TM
AD0EN
REF
16
AV+
AD1EN
SYSCLK
AIN1
Start Conversion
Timer 3 Overflow
Timer 2 Overflow
AD1BUSY (W)
CNVSTR1
16-Bit
SAR
ADC1
ADC1CF
AD1OCAL
AD1LCAL
AD1GCAL
AD1SCAL
AD1SC0
AD1SC1
AD1SC2
AD1SC3
ADC1CN
AD1CM0
AD1CM1
AD1CM2
AD1BUSY
AD1INT
AD1TM
AD1EN
AD0BUSY (W)
000
010
100
110
xx1
ADC0 Data Bus
ADC1 Data Bus
AIN1G
(DC, -0.2 to 0.6 V)
(DC, -0.2 to 0.6 V)
C8051F060/1/2/3/4/5/6/7
52 Rev. 1.2
Figure 5.2. 16-bit ADC0 and ADC1 Data Path Diagram
5.1. Single-Ended or Differential Operation
ADC0 and ADC1 can be programmed to operate independently as single-ended ADCs, or together to
accept a dif ferential input. In single-ende d mode, the ADCs can be configu red to sample simult aneously, or
to use different convers ion speeds . In differential mo de, ADC1 is a slave to ADC0, and its configuration is
based on ADC0 settings, except during offset or gain calibrations. The DIFFSEL bit in the Channel Select
Register AMX0SL (Figur e 5.6) selects between single -end e d and differential mo de.
5.1.1. Pseudo-Differential Inputs
The inputs to the ADCs are pseudo-differential. The actual voltage measured by each ADC is equal to the
voltage between the AINn pin and the AINnG pin. AINnG must be a DC signal between -0.2 and 0.6 V. In
most systems, AINnG will be connected to AGND. If not tied to AGND, the AINnG signal can be used to
negate a limited amo unt o f fixe d o ffset, but it is reco mmende d that th e in tern al o ffset calibration feat ure s of
the device be used for this purpose. When operating in differential m ode, AIN0G and AIN1G sho uld be tied
together. AINn must remain above AINnG in both modes for accurate conversion results.
16
AIN0
16-Bit
SAR
ADC0
AMX0SL
DIFFSEL
16
AIN1
16-Bit
SAR
ADC1
ADC0H ADC0LADC1H ADC1L
88
0
1
88
Single-Ended
Differential
ADC0LTLADC0LTHADC0GTLADC0GTH
32
16
AD0WINT
Window
Compare
16
DMA
Interface
+
-
AIN0G
AIN1G
C8051F060/1/2/3/4/5/6/7
Rev. 1.2 53
5.2. Voltage Reference
The voltage reference circuitries for ADC0 and ADC1 allow for many different voltage reference configura-
tions. Each ADC has the capability to use its own dedicated, on-chip voltage reference, or an off-chip refer-
ence circuit. A block diagram of the reference circuitry for one ADC is sho wn in Figure 5.3.
The internal voltage reference circuit for each ADC consists of an independent, temperature stable 1.2 V
bandgap voltage reference generator, with an output buffer amplifier which multiplies the bandgap refer-
ence by 2. The maximum load seen by the VREFn (VREF0 or VREF1) pin must be less than 100 µA to
AGND. Bypass capacitors of 0.1 µF and 47 µF are recommended from the VREFn pin to VRGNDn.
The voltage reference circuitry for each ADC is controlled in the Reference Control Registers. REF0CN
(defined in Figure 5 .11) is the Reference Control Register for ADC0, and REF1CN (defined in Figure 5.12)
is the Reference Control Register for ADC1. The REFnCN registers are used to enable/disable the internal
reference and bias generator circuitry for each ADC independently. The BIASEn bits enable the on-board
bias generators for each ADC, while the REFBEn bits enable the 2x buffer amplifiers which drive the
VREFn pins. When disabled, the supply current drawn by the bandgap and buffer amplifier falls to less
than 1 µA (typical) and the output of the buffer amplifier enters a high impedance state (approximately 25 k
Ohms). If the internal voltage reference for an ADC is used, the BIASEn and REFBEn bits for that ADC
must both be set to logic 1. If an external reference is used, the REFBEn bit should be set to logic 0. Note
that the BIASEn bit for an ADC must be set to logic 1 to enable that ADC, regardless of the voltage refer-
ence that is used. If an ADC is not being used, the BIASEn bit can be set to logic 0 to conserve power. The
electrical specifications for the Voltage Reference s ar e given in Table 5.3.
Figure 5.3. Voltage Reference Block Diagram
Recommended
Bypass Capacitor s
x2
ADCn
Ref
REFnCN
REFBEn
BIASEn
1.25V
Band-Gap
EN
VBGAPn
0.1
F
Bias
VREFn
47
F0.1
FVRGNDn
External
Voltage
Reference
C8051F060/1/2/3/4/5/6/7
54 Rev. 1.2
5.3. ADC Modes of Operation
ADC0 and ADC1 have a maximum conversion speed of 1 Msps. The conversion clocks for the ADCs are
derived from the system clock. The ADCnSC bits in the ADCnCF register determine how many system
clocks (from 1 to 16) are used for each conversion clock.
5.3.1. Starting a Conversion
For ADC0, conversions can be initiated in one of four ways, depending on the programmed states of the
ADC0 S t art of Conversion Mode bits (AD0CM1, AD0CM0) in ADC0CN. For ADC0, conversions may be ini-
tiated by:
1. Writing a ‘1’ to the AD0BUSY bit of ADC0CN;
2. A Timer 3 overflow (i.e. timed continuous conversions);
3. A rising edge detected on the external ADC convert start signal, CNVSTR0;
4. A Timer 2 overflow (i.e. timed continuous conversions).
ADC1 conversions can be initiated in five different ways, according to the ADC1 Start of Conversion Mode
bits (AD1CM2-AD1CM0) in ADC1CN. For ADC1, conversions may be initiated by:
1. Writing a ‘1’ to the AD1BUSY bit of ADC1CN;
2. A Timer 3 overflow (i.e. timed continuous conversions);
3. A rising edge detected on the external ADC convert start signal, CNVSTR1;
4. A Timer 2 overflow (i.e. timed continuous conversions);
5. Writing a ‘1’ to the AD0BUSY bit of ADC0CN.
The ADnBUSY bit is set to logic 1 during conversion and restored to logic 0 when conversion is complete.
The falling edge of ADnBUSY triggers an interrupt (when enabled) and sets the ADnINT interrupt flag
(ADCnCN.5). In sing le- ended mod e, the conve rted da ta for ADCn is available in the ADCn data word MSB
and LSB registers, ADCnH, ADCnL. In differential mode, the converted data (combined from ADC0 and
ADC1) is available in the ADC0 data word MSB and LSB registers, ADC0H, ADC0L.
When initiating conversions by writing a ‘1’ to ADnBUSY, the ADnINT bit should be polled to determine
when a conversion has completed (ADCn interrupts may also be used). The recommended polling proce-
dure is shown below.
Step 1. Write a ‘0’ to ADnINT;
Step 2. Write a ‘1’ to ADnBUSY;
Step 3. Poll ADnINT for ‘1’;
Step 4. Process ADCn data.
When an external start-of-conversion source is required in differential mode the two pins (CNVSTR0 and
CNVSTR1) should be tied together.
5.3.2. Tracking Modes
The ADnTM bit in register ADCnCN controls the ADCn track-and-hold mode. When the ADC is enabled,
the ADC input is continuously tracked when a conversion is not in progress. When the ADnTM bit is logic
1, each conversion is preceded by a tracking period (after the start-of-conversion signal). When the
CNVSTRn signal is used to initiate conversions, the ADC will track until a rising edge occurs on the
CNVSTRn pin (see Figure 5.4 and Table 5.1 for conversion timing parameters). Setting ADnTM to 1 can
be useful to ensure that settling time requirements are met when an external multiplexer is used on the
analog input (see Section “5.3.3. Settling Time Requirements” on page 56).
C8051F060/1/2/3/4/5/6/7
Rev. 1.2 55
Figure 5.4. ADC Track and Conversion Example Timing
Table 5.1. Conversion Timing (tConv)
ADnSC3-0 ADCnTM = 0 ADCnTM = 1 ADnSC3-0 ADCnTM = 0 ADCnTM = 1
0000 21*tSYSCLK 38*tSYSCLK 1000 171*tSYSCLK 315*tSYSCLK
0001 40*tSYSCLK 72*tSYSCLK 1001 189*tSYSCLK 349*tSYSCLK
0010 58*tSYSCLK 106*tSYSCLK 1010 208*tSYSCLK 384*tSYSCLK
0011 78*tSYSCLK 142*tSYSCLK 1011 226*tSYSCLK 418*tSYSCLK
0100 97*tSYSCLK 177*tSYSCLK 1100 245*tSYSCLK 453*tSYSCLK
0101 115*tSYSCLK 211*tSYSCLK 1101 263*tSYSCLK 487*tSYSCLK
0110 134*tSYSCLK 246*tSYSCLK 1110 282*tSYSCLK 522*tSYSCLK
0111 152*tSYSCLK 280*tSYSCLK 1111 300*tSYSCLK 556*tSYSCLK
CNVSTRn
Timer 2, Timer 3 Overflow;
Write '1' to ADnBUSY
ADCnTM=1
ADCnTM=0
A. ADC Timing for External Trigger Source
B. ADC Timing for Internal Trigger Sources
Track Convert
Track
Track
Track
Convert TrackTrack
Convert Track
t
Conv
t
Conv
t
Conv
C8051F060/1/2/3/4/5/6/7
56 Rev. 1.2
5.3.3. Settling Time Requirements
The ADC requires a minimum tra cking time before an accurate conversion can be performed. This tracking
time is determined by the ADC input resistance, the ADC sampling capacitance, any external sour ce resis-
tance, and the accuracy requ ired for the conversio n. Figure 5.5 shows the equivalent ADC input circuits for
both Differential and Single-ended modes. Notice that the equivalent time constant for both input circuits is
the same. The required settling time for a given settling accuracy (SA) may be approximated by
Equation 5.1. An absolute m inim u m tra cking time of 280 ns is required prior to the start of a conversion.
Equation 5.1. ADC0 Settling Time Requirements
Where:
SA is the settling accuracy, given as a fraction of an LSB (for example, 0.25 to settle within 1/4 LSB)
t is the required settling time in seconds
RTOTAL is the sum of the ADC input resistance and any external source resistance.
n is the ADC resolution in bits (16).
Figure 5.5. ADC0 and ADC1 Equivalent Input Circuits
t2n
SA
-------
RTOTALCSAMPLE
ln=
R
AIN
= 30
RC
Input
= R
AIN
* C
SAMPLE
R
AIN
= 30
C
SAMPLE
= 80pF
C
SAMPLE
= 80pF
Differential Mode
AIN0
AIN1
R
AIN
= 30
C
SAMPLE
= 80pF
RC
Input
= R
AIN
* C
SAMPLE
Single-Ended Mode
AIN0
or
AIN1
C8051F060/1/2/3/4/5/6/7
Rev. 1.2 57
Figure 5.6. AMX0SL: AMUX Configuration Register
Bit 7: RESERVED. Write to 0b.
Bit 6: DIFFSEL: Fully Differential Conversion Mode Select Bit.
0: Operate In Single-Ended Mode.
1: Operate In Differential Mode.
Bit 5-0: RESERVED. Write to 000000b.
NOTE: For single-ended mode, the ADC0 Data Word is stored in ADC0H and ADC0L, while the
ADC1 Data Word is stored in ADC1H and ADC1L.
In dif ferential mode, the combin ed ADC Dat a Word is stored in ADC0H and ADC0L, and is a
2’s complement number. ADC1’s Data Word (single-ended) is also stored in ADC1H and
ADC1L.
R/W R/W R/W R/W R/W R/W R/W R/W Reset Value
- DIFFSEL - - - - - - 00000000
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
SFR Address:
SFR Page: 0xBB
0
C8051F060/1/2/3/4/5/6/7
58 Rev. 1.2
Figure 5.7. ADC0CF: ADC0 Configuration Register
Bits 7-4: AD0SC3-0: ADC0 SAR Conversion Clock Period Bits.
SAR Conversion clock is divided down from the system clock according to the AD0SC bits
(AD0SC3-0). The numb er of system clocks used for each SAR conversion clock is equal to
AD0SC + 1. (Note: the ADC0 SAR Conversion Clock should be less than or equal to
25 M H z ). See Table 5.1 for conve rs ion timin g de tails.
Bit 3: AD0SCAL: System Calibration Enable.
0: Internal ground and reference voltage are used during offset and gain calibration.
1: External voltages can be use d du rin g offset and gain calibr at ion .
Bit 2: AD0GCAL: Gain Calibration.
Read:
0: Gain Calibration is completed or not yet started.
1: Gain Calibration is in progress.
Write:
0: No Effect.
1: Initiates a gain calibration if ADC0 is idle.
Bit 1: AD0LCAL: Linearity Calibration
Read
0: Linearity Calibration is completed or not yet started
1: Linearity Calibration is in progress
Write
0: No Effect
1: Initiates a linearity calibration if ADC0 is idle
Bit 0: AD0OCAL: Offset Calibration.
Read:
0: Offset Calibration is complete d or not ye t started.
1: Offset Calibration is in progre ss .
Write:
0: No Effect.
1: Initiates an offset calibration if ADC0 is idle.
R/W R/W R/W R/W R/W R/W R/W R/W Reset Value
AD0SC3 AD0SC2 AD0SC1 AD0SC0 AD0SCAL AD0GCAL AD0LCAL AD0OCAL 11110000
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
SFR Address:
SFR Page: 0xBC
0
C8051F060/1/2/3/4/5/6/7
Rev. 1.2 59
Figure 5.8. ADC1CF: ADC1 Configuration Register
Bits 7-4: AD1SC3-0: ADC1 SAR Conversion Clock Period Bits.
SAR Conversion clock is divided down from the system clock according to the AD1SC bits
(AD1SC3-0). The numb er of system clocks used for each SAR conversion clock is equal to
AD1SC + 1. (Note: the ADC1 SAR Conversion Clock should be less than or equal to
25 M H z ). See Table 5.1 for conve rs ion timin g de tails.
Bit 3: AD1SCAL: System Calibration Enable.
0: Internal ground and reference voltage ar e used for offset and gain calibration.
1: External voltages can be used for offset and gain calibration.
Bit 2: AD1GCAL: Gain Calibration.
Read:
0: Gain Calibration is completed or not yet started.
1: Gain Calibration is in progress.
Write:
0: No Effect.
1: Initiates a gain calibration if ADC1 is idle.
Bit 1: AD1LCAL: Linearity Calibration
Read
0: Linearity Calibration is completed or not yet started
1: Linearity Calibration is in progress
Write
0: No Effect
1: Initiates a linearity calibration if ADC1 is idle
Bit 0: AD1OCAL: Offset Calibration.
Read:
0: Offset Calibration is complete d or not ye t started.
1: Offset Calibration is in progre ss .
Write:
0: No Effect.
1: Initiates an offset calibration if ADC1 is idle.
R/W R/W R/W R/W R/W R/W R/W R/W Reset Value
AD1SC3 AD1SC2 AD1SC1 AD1SC0 AD1SCAL AD1GCAL AD1LCAL AD1OCAL 11110000
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
SFR Address:
SFR Page: 0xBC
1
C8051F060/1/2/3/4/5/6/7
60 Rev. 1.2
Figure 5.9. ADC0CN: ADC0 Control Register
Bit 7: AD0EN: ADC0 Enable Bit.
0: ADC0 Disabled. ADC0 is in low-power shutdown.
1: ADC0 Enabled. ADC0 is active and ready for data conversions or calibrations.
Bit 6: AD0TM: ADC Track Mode Bit.
0: When the ADC is enabled, tracking is continuous unless a conversion is in process.
1: Tracking Defined by AD0CM1-0 bits.
Bit 5: AD0INT: ADC0 Conversion Complete Interrupt Flag.
This flag must be cleared by software.
0: ADC0 has not completed a data conversion since the last time this flag was cleared.
1: ADC0 has completed a data conversion.
Bit 4: AD0BUSY: ADC0 Busy Bit.
Read:
0: ADC0 Conversion is complete or a conversion is not currently in progress. AD0INT is set
to logic 1 on the falling edge of AD0BUSY.
1: ADC0 Conversion is in progress.
Write:
0: No Effect.
1: Initiates ADC0 Conversion if AD0CM1-0 = 00b.
Bits 3-2: AD0CM1-0: ADC0 Start of Conversion Mode Select.
If AD0TM = 0:
00: ADC0 conversion initiated on every write of ‘1’ to AD0BUSY.
01: ADC0 conversion initiated on overflow of Timer 3.
10: ADC0 conversion initiated on rising edge of external CNVSTR0.
11: ADC0 conversion initiated on overflow of Timer 2.
If AD0TM = 1:
00: Tracking starts with the write of ‘1’ to AD0BUSY and is followed by the conver sion.
01: Tracking started by the overflow of Timer 3 and is follo wed by the conversion.
10: ADC0 conversion starts on rising CNVSTR0 edge.
11: Tracking started by the overflow of Timer 2 and is followed by the conversion.
See Figure 5.4 and Table 5.1 for conversion timing parameter s.
Bit 1: AD0WINT: ADC0 Window Compare Interrupt Flag.
This bit must be cleared by software.
0: ADC0 Window Comparison Data match has not occurred since this flag was last cleared.
1: ADC0 Window Comparison Data match has occurred.
Bit 0: RESERVED: Write to 0b.
R/W R/W R/W R/W R/W R/W R/W R/W Reset Value
AD0EN AD0TM AD0INT AD0BUSY AD0CM1 AD0CM0 AD0WINT - 00000000
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Bit Addressable
SFR Address:
SFR Page: 0xE8
0
C8051F060/1/2/3/4/5/6/7
Rev. 1.2 61
Figure 5.10. ADC1CN: ADC1 Control Register
Bit 7: AD1EN: ADC1 Enable Bit.
0: ADC1 Disabled. ADC1 is in low-power shutdown.
1: ADC1 Enabled. ADC1 is active and ready for data conversions or calibrations.
Bit 6: AD1TM: ADC Track Mode Bit.
0: When the ADC is enabled, tracking is continuous unless a conversion is in process.
1: Tracking Defined by AD1CM2-0 bits.
Bit 5: AD1INT: ADC1 Conversion Complete Interrupt Flag.
This flag must be cleared by software.
0: ADC1 has not completed a data conversion since the last time this flag was cleared.
1: ADC1 has completed a data conversion.
Bit 4: AD1BUSY: ADC1 Busy Bit.
Read:
0: ADC1 Conversion is complete or a conversion is not currently in progress. AD1INT is set
to logic 1 on the falling edge of AD1BUSY.
1: ADC1 Conversion is in progress.
Write:
0: No Effect.
1: Initiates ADC1 Conversion if AD1CM2-0 = 000b.
Bits 3-1: AD1CM2-0: ADC1 Start of Conversion Mode Select.
If AD1TM = 0:
000: ADC1 conversion initiated on every write of ‘1’ to AD1BUSY.
010: ADC1 conversion initiated on overflow of Timer 3.
100: ADC1 conversion initiated on rising edge of external CNVSTR1.
110: ADC1 conversion initiated on overflow of Timer 2.
xx1: ADC1 conversion initiated on every write of ‘1’ to AD0BUSY in ADC0CN
If AD1TM = 1:
000: Tracking starts with the write of ‘1’ to AD1BUSY and is followed by the conversion.
010: Tracking started by the overflow of Timer 3 and is followed by the conver sion.
100: ADC1 conversion starts on rising CNVSTR1 edge.
110: Tracking started by the overflow of Timer 2 and is followed by the conversion.
xx1: Tracking starts with the write of ‘1’ to AD0BUSY and is followed by the conversion.
See Figure 5.4 and Table 5.1 for conversion timing parameter s.
Bit 0: RESERVED: Write to 0b.
R/W R/W R/W R/W R/W R/W R/W R/W Reset Value
AD1EN AD1TM AD1INT AD1BUSY AD1CM2 AD1CM1 AD1CM0 - 00000000
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Bit Addressable
SFR Address:
SFR Page: 0xE8
1
C8051F060/1/2/3/4/5/6/7
62 Rev. 1.2
Figure 5.11. REF0CN: Re fe rence Control Register 0
Bits7-2: RESERVED. Read = 000000b; Write = 000000b.
Bit1: BIASE0: ADC0 Bias Generator Enable Bit. (Must be ‘1’ if using ADC0).
0: ADC0 Internal Bias Generator Off.
1: ADC0 Internal Bias Generator On.
Bit0: REFBE0: Internal Reference Buffer for ADC0 Enable Bit.
0: Internal Reference Buffer for ADC0 Off. External voltage reference can be used.
1: Internal Reference Buf fer for ADC0 On. Internal vo ltage reference is dr iven on the VREF0
pin.
R/W R/W R/W R/W R/W R/W R/W R/W Reset Value
- - - - - - BIASE0 REFBE0 00000000
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
SFR Address:
SFR Page: 0xD1
0
Figure 5.12. REF1CN: Reference Control Register 1
Bits7-2: RESERVED. Read = 000000b; Write = 000000b.
Bit1: BIASE1: ADC1 Bias Generator Enable Bit. (Must be ‘1’ if using ADC1).
0: ADC1 Internal Bias Generator Off.
1: ADC1 Internal Bias Generator On.
Bit0: REFBE1: Internal Reference Buffer for ADC1 Enable Bit.
0: Internal Reference Buffer for ADC1 Off. External voltage reference can be used.
1: Internal Reference Buf fer for ADC1 On. Internal vo ltage reference is dr iven on the VREF1
pin.
R/W R/W R/W R/W R/W R/W R/W R/W Reset Value
- - - - - - BIASE1 REFBE1 00000000
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
SFR Address:
SFR Page: 0xD1
1
C8051F060/1/2/3/4/5/6/7
Rev. 1.2 63
Figure 5.13. ADC0H: ADC0 Data Word MSB Register
Bits 7-0: ADC0 Data Word High-Order Bits.
R/W R/W R/W R/W R/W R/W R/W R/W Reset Value
00000000
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
SFR Address:
SFR Page: 0xBF
0
Figure 5.14. ADC0L: ADC0 Data Word LSB Register
Bits 7-0: ADC0 Data Word Low-Order Bits.
R/W R/W R/W R/W R/W R/W R/W R/W Reset Value
00000000
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
SFR Address:
SFR Page: 0xBE
0
C8051F060/1/2/3/4/5/6/7
64 Rev. 1.2
16-bit ADC0 Data Word appears in the ADC0 Data Word Registers as follows:
Example: ADC0 Data Word Conversion Map, AIN0 Input in Single-Ended Mode
(AMX0SL = 0x00)
Example: ADC0 Data Word Conversion Map, AIN0-AIN1 Differential Input Pair
(AMX0SL = 0x40)
; ‘n’ = 16 for Single-Ended; ‘n’=15 for Differential.
AIN0-AIN0G (Volts) ADC0H:ADC0L
VREF * (65535/65536) 0xFFFF
VREF / 2 0x8000
VREF * (32767/65536) 0x7FFF
0 0x0000
AIN0-AIN1 (Volts) ADC0H:ADC0L
VREF * (32767/32768) 0x7FFF
VREF / 2 0x4000
VREF * (1/32768) 0x0001
0 0x0000
-VREF * (1/32768) 0xFFFF
-VREF / 2 0xC000
-VREF 0x8000
Code Vin Gain
VREF
---------------
2n
=
Figure 5.15. ADC0 Data Word Example
C8051F060/1/2/3/4/5/6/7
Rev. 1.2 65
Figure 5.16. ADC1H: ADC1 Data Word MSB Register
Bits 7-0: ADC1 Data Word High-Order Bits.
R/W R/W R/W R/W R/W R/W R/W R/W Reset Value
00000000
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
SFR Address:
SFR Page: 0xBF
1
Figure 5.17. ADC1L: ADC1 Data Word LSB Register
Bits 7-0: ADC1 Data Word Low-Order Bits.
R/W R/W R/W R/W R/W R/W R/W R/W Reset Value
00000000
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
SFR Address:
SFR Page: 0xBE
1
Figure 5.18. ADC1 Data Word Example
16-bit ADC1 Data Word appears in the ADC1 Data Word Registers as follows:
Example: ADC1 Data Word Conversion Map, AIN1 Input in Single-Ended Mode
(AMX1SL = 0x00)
; ‘n’ = 16
For differential mode, the differential data word appears in ADC0H and ADC0L. The single-
ended ADC1 result s are always pre sent in ADC1H and ADC1L, rega rdless of the op erating
mode.
AIN1-AIN1G (Volts) ADC1H:ADC1L
VREF * (65535/65536) 0xFFFF
VREF / 2 0x8000
VREF * (32767/65536) 0x7FFF
00x0000
Code Vin Gain
VREF
---------------
2n
=
C8051F060/1/2/3/4/5/6/7
66 Rev. 1.2
5.4. Calibration
The ADCs are calibrated for linearity, offset, and gain in production. ADC0 and ADC1 can also be indepen-
dently calibrated for each of these parameters in-system. Calibrations are initiated using bits in the ADC0
or ADC1 Configuration Register. The calibration coefficients can be accessed using the ADC Calibration
Pointer Register (ADC0CPT, Figure 5.22) and the ADC Calibration Coefficient Register (ADC0CCF,
Figure 5.23). The CP TR bits in ADC0CPT allow the ADC0CCF register to read and write specific calibra-
tion coefficients. Figure 5.19 shows the Calibration Coefficient locations.
The ADCs are calibrated for linearity in production. Under normal circumstances, no additional linearity
calibration is necessary. If linearity calibrations are desired, they can be initiated by setting the ADCnLCAL
bit to ‘1’. When the calibration is finished, the ADCnLCAL bit will be set to ‘0’ by the hardware. Linearity
Calibration Coefficients are stored in the locations shown in Figure 5.19.
Offset and gain calibrations can be performed using either internal or external voltages as calibration
sources. The ADCnSCAL bit determines whether the internal or external voltages are used in the calibra-
tion process. To ensure accuracy, offset calibration should be done prior to a gain calibration. The offset
and gain calibration coefficients are decoded in Figure 5.20. Offset calibration is initiated by setting the
ADCnOCAL bit to ‘1’. When the calibration is finished, the ADCnOCAL bit will be set to ‘0’ by the hardware.
Offset calibration can compe nsate for of fset errors of approximately 3.125 % of full scale. The of fset value
is added to the AINnG input prior to digitization by the ADC. Gain calibration is initiated by setting the
ADCnGCAL bit to ‘1’. When the calibration is finished, the ADCnGCAL bit will be set to ‘0’ by the hardware.
Gain calibration can compensate for slope errors of approximately 3.125%. The gain value is added to
the ADC’s VREF path to change the slope of the converter ’s transfer fu nction. F igure 5.21 sh ows how the
offset and gain values affect the analog signals used by the ADC.
Figure 5.19. Calibration Coefficient Locations
ADC0CCF
ADC0CPT
Bits 5-0 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
0x00
Linearity Calibration Coefficients (locations 0x00 through 0x12)
.
.
0x12
0x13 Offset7 Offset6 Offset5 Offset4 Offset3 Offset2 Offset1 Offset0
0x14 Offset13 Offset12 Offset11 Offset10 Offset9 Offset8
0x15 Gain7 Gain6 Gain5 Gain4 Gain3 Gain2 Gain1 Gain0
0x16 Gain12 Gain11 Gain10 Gain9 Gain8
C8051F060/1/2/3/4/5/6/7
Rev. 1.2 67
The offset register value affects the offset at the analog input as follows:
The gain register value affects the slope of the ADC transfer function as follows:
Offset Register (14 Bits) Approximate Offset Change (V)
0x3FFF -3.125% * VREF
0x2000 0
0x0000 +3.125% * VREF
Gain Register (13 Bits) Approximate Slope Change
0x1FFF +3.125%
0x1000 0
0x0000 -3.125%
Offset Change 0x2000 Offset Register–8192
------------------------------------------------------------ 3.125% VREF
Slope Change Gain Register 0x1000–
4096
---------------------------------------------------------3.125%
Figure 5.20. Offset and Gain Register Mapping
AINn
ADCn
Offset
+
VREF
Gain
ADCn Data
16
AINnG
-
+
Figure 5.21. Offset and Gain Calibration Block Diagram
C8051F060/1/2/3/4/5/6/7
68 Rev. 1.2
Figure 5.22. ADC0CPT: ADC Calibration Pointer Register
Bit 7: INCR: Pointer Address Automatic Increment.
0: Disable Auto-Increment.
1: Enable Auto-Increment. CPTR5-0 will automatically be incremented after each read or
write to ADC0CCF.
Bit 6: ADCSEL: ADC Calibration Coefficient Select.
0: Reads and Writes of ADC0CCF will access ADC0 Calibration Coefficients.
1: Reads and Writes of ADC0CCF will access ADC1 Calibration Coefficients.
Bits 5-0: CPTR5-0: Calibration Coefficent Pointer.
Select which Calibration Coefficient location will be accessed when ADC0CCF is read or
written.
R/W R/W R/W R/W R/W R/W R/W R/W Reset Value
INCR ADCSEL CPTR5 CPTR4 CPTR3 CPTR2 CPTR1 CPTR0 11010111
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
SFR Address:
SFR Page: 0xBA
F
Figure 5.23. ADC0CCF: ADC Calibration Coefficient Register
Bits 7-0: Calibration Coefficients at the location specified in ADC0CPT. See Table 5.19.
R/W R/W R/W R/W R/W R/W R/W R/W Reset Value
Variable
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
SFR Address:
SFR Page: 0xBB
F
C8051F060/1/2/3/4/5/6/7
Rev. 1.2 69
5.5. ADC0 Programmable Window Detector
The ADC0 Programmabl e Windo w Detector contin uously compares the ADC0 output to user -prog ramme d
limits, and no tifies th e system whe n an out-of-b ound co ndition is detected. This is especially effective in an
interrupt-driven system, saving code space and CPU bandwidth while delivering faster system response
times. The window detector interrupt flag (AD0WINT in ADC0CN) can also be used in polled mode. The
high and low bytes of the reference words are loaded into the ADC0 Greater-Than and ADC0 Less-Than
registers (ADC0GTH, ADC0GTL, ADC0LTH, and ADC0LTL). The Window Detector can be used in single-
ended or differential mode. In signle-ended mode, the Window Detector compares the ADC0GTx and
ADC0LTx registers to the output of ADC0. In differential mode, the combined output of ADC0 and ADC1
(contained in the ADC0 data registers) is used for the comparison. Reference comparisons are shown
starting on page 71. Notice that the window detector flag can be asserted when the measured data is
inside or outside the user-programmed limits, depending on the programming of the ADC0GTx and
ADC0LTx registers.
Figure 5.24. ADC0GTH: ADC0 Greater-Than Data High Byte Register
Bits 7-0: High byte of ADC0 Greate r- T ha n Data Word.
R/W R/W R/W R/W R/W R/W R/W R/W Reset Value
11111111
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
SFR Address:
SFR Page: 0xC5
0
Figure 5.25. ADC0GTL: ADC0 Greater-Than Data Low Byte Register
Bits 7-0: Low byte of ADC0 Grea te r- Tha n Da ta Word.
R/W R/W R/W R/W R/W R/W R/W R/W Reset Value
11111111
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
SFR Address:
SFR Page: 0xC4
0
C8051F060/1/2/3/4/5/6/7
70 Rev. 1.2
Bits 7-0: High byte of ADC0 Less-Than Da ta Word.
R/W R/W R/W R/W R/W R/W R/W R/W Reset Value
00000000
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
SFR Address:
SFR Page: 0xC7
0
Figure 5.26. ADC0LTH: ADC0 Less-Than Data High Byte Register
Figure 5.27. ADC0LTL: ADC0 Less-Than Data Low Byte Register
Bits 7-0: Low byte of ADC0 Less- Tha n Data Word.
R/W R/W R/W R/W R/W R/W R/W R/W Reset Value
00000000
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
SFR Address:
SFR Page: 0xC6
0
C8051F060/1/2/3/4/5/6/7
Rev. 1.2 71
Figure 5.28. 16-Bit ADC0 Window Interrupt Example: Single-Ended Data
Given:
AMX0SL = 0x00,
ADC0LTH:ADC0LTL = 0x2000,
ADC0GTH:ADC0GTL = 0x1000.
An ADC0 End of Conversion will cause an
ADC0 Window Compare Interrupt (AD0WINT
= ‘1’) if the resulting ADC0 Data Word is
< 0x2000 and > 0x1000.
Given:
AMX0SL = 0x00,
ADC0LTH:ADC0LTL = 0x1000,
ADC0GTH:ADC0GTL = 0x2000.
An ADC0 End of Conversion will cause an
ADC0 Window Compare Interrupt (AD0WINT
= ‘1’) if the resulting ADC0 Data Word is
> 0x2000 or < 0x1000.
0xFFFF
0x2001
0x2000
0x1FFF
0x1001
0x1000
0x0FFF
0x0000
AD0WINT=1
AD0WINT
not affected
AD0WINT
not affected
ADC0 Data
Word
0xFFFF
0x2001
0x2000
0x1FFF
0x1001
0x1000
0x0FFF
0x0000
AD0WINT=1
AD0WINT
not a ffe cted
AD0WINT=1
ADC0LTH:ADC0LTL
ADC0GTH:ADC0GTL
ADC0 Data
Word
ADC0GTH:ADC0GTL
ADC0LTH:ADC0LTL
0
Input Voltage
(AIN0 - AIN0G)
REF x (65535/6553 6)
REF x (4096/65536)
REF x (8192/65536)
0
Input Voltage
(AIN0 - AIN0 G)
REF x (65535/65536)
REF x (4096/65536)
REF x (8192/65536)
C8051F060/1/2/3/4/5/6/7
72 Rev. 1.2
0x7FFF
0x1001
0x1000
0x0FFF
0x0000
0xFFFF
0xFFFE
0x8000
AD0WINT=1
AD0WINT
not affected
AD0WINT
not affected
0x7FFF
0x1001
0x1000
0x0FFF
0x0000
0xFFFF
0xFFFE
0x8000
AD0WINT=1
AD0WINT
not affected
Input Voltage
(AIN0 - AIN1)
AD0WINT=1
ADC0LTH:ADC0LTL
ADC0GTH:ADC0GTL
ADC0 Data
Word
ADC0 Data
Word
ADC0LTH:ADC0LTL
ADC0GTH:ADC0GTL
-REF
Input Voltage
(AIN0 - AIN1)
REF x (32767/32768)
REF x (4096/32768)
REF x (-1/32768)
-REF
REF x (32767/32768)
REF x (4096/32768)
REF x (-1/32768)
Figure 5.29. 16-Bit ADC0 Window Interrupt Example: Differential Data
Given:
AMX0SL = 0x40,
ADC0LTH:ADC0LTL = 0x1000,
ADC0GTH:ADC0GTL = 0xFFFF.
An ADC0 End of Conversion will cause an
ADC0 Window Compare Interrupt (AD0WINT
= ‘1’) if the resulting ADC0 Data Word is
< 0x1000 and > 0xFFFF. (In two’s-complement
math, 0xFFFF = -1.)
Given:
AMX0SL = 0x40,
ADC0LTH:ADC0LTL = 0xFFFF,
ADC0GTH:ADC0GTL = 0x1000.
An ADC0 End of Conversion will cause an
ADC0 Window Compare Interrupt (AD0WINT
= ‘1’) if the resulting ADC0 Data Word is
< 0xFFFF or > 0x1000. (In two’s-complement
math, 0xFFFF = -1.)
C8051F060/1/2/3/4/5/6/7
Rev. 1.2 73
Table 5.2. 16-Bit ADC0 and ADC1 Electrical Characteristics
VDD = 3.0 V, AV+ = 3.0 V, AVDD = 3.0 V, VREF = 2.50 V (REFBE=0), -40 to +85 °C unless otherwise
specified
Parameter Conditions Min Typ Max Units
DC Accuracy
Resolution 16 bits
Integral Nonlinearity
(C8051F060/1/4/5/6/7) Single-Ended
Differential ±0.75
±0.5 ±2
±1 LSB
Integral Nonlinearity
(C8051F062/3) Single-Ended
Differential ±1.5
±1 ±4
±2 LSB
Differential Nonlinearity Guaranteed Monotonic ±0.5 LSB
Offset Error 0.1 mV
Full Scale Error 0.008 %F.S.
Gain Temperature Coefficient 0.5 ppm/°C
Dynamic Performance (Sampling Rate = 1 Msps, AVDD, AV+ = 3.3V)
Signal-to-Noise Plus Distortion F in = 10 kHz, Single-En d ed
Fin = 100 kHz, Single-Ended
Fin = 10 kHz, Differential
Fin = 100 kHz, Differential
86
84
89
88
dB
dB
dB
dB
Total Harmonic Distortion Fin = 10 kHz, Single-Ended
Fin = 100 kHz, Single-Ended
Fin = 10 kHz, Differential
Fin = 100 kHz, Differential
96
84
103
93
dB
dB
dB
dB
Sp ur ious- F re e Dyn amic Rang e Fin = 10 kHz, Single-Ended
Fin = 100 kHz, Single-Ended
Fin = 10 kHz, Differential
Fin = 100 kHz, Differential
97
88
104
99
dB
dB
dB
dB
CMRR Fin = 10 kHz 86 dB
Channel Isolation 100 dB
Timing
SAR Clock Frequency 25 MHz
Conversion Time in SAR
Clocks 18 clocks
Track/Hold Acquisition Time 280 ns
Throughput Rate 1 Msps
Aperture Delay External CNVST Signal 1.5 ns
RMS Aperture Jitter External CNVST Signal 5 ps
Analog Inputs
Input Voltage Range Single-Ended (AINn - AINnG)
Differential (AIN0 - AIN1) 0
-VREF VREF
VREF V
V
Input Capacitance 80 pF
C8051F060/1/2/3/4/5/6/7
74 Rev. 1.2
Operating Input Range AIN0 or AIN1
AIN0G or AIN1G (DC Only) -0.2
-0.2 AV+
0.6 V
V
Power Specifications
Power Supply Curr e nt (each
ADC) Operating Mode, 1 Msps
AV+
AVDD
Shutdown Mode
4.0
2.0
<1
mA
mA
A
Power Supply Rejection VDD ± 5% ±0.5 LSB
Table 5.3. Voltage Reference 0 and 1 Electrical Characteristics
VDD = 3.0 V, AV+ = 3.0 V, AVDD = 3.0 V, -40 to +85 °C unless otherwise specified
Parameter Conditions Min Typ Max Units
Internal Reference
Output Voltage 25 °C ambient 2.36 2.43 2.48 V
VREF Temperature Coefficient 15 ppm/°C
Power Supply Curr e nt (each
Voltage Reference) AV+ 1.5 mA
External Referenc e
Input Voltage Range 2.0 AV+ V
Input Current ADC throughput = 1 Msps 450 µA
Table 5.2. 16-Bit ADC0 and ADC1 Elect r ical Ch ara ct e ri st ic s (Con t in ued )
VDD = 3.0 V, AV+ = 3.0 V, AVDD = 3.0 V, VREF = 2.50 V (REFBE=0), -40 to +85 °C unless otherwise
specified
Parameter Conditions Min Typ Max Units
C8051F060/1/2/3/4/5/6/7
Rev. 1.2 75
6. Direct Memory Access Interface (DMA0)
The DMA interface works in conjunction with ADC0 and ADC1 to write ADC outputs directly to a specified
region of XRAM. The DMA interface is configured by software using the Special Function Registers shown
in Figure 6.1. Up to 64 instructions can be progr amm ed into the Instruction Buffer to designate a sequence
of DMA operations. The Instr uction Buf fer is accessed by the DMA Control Logic, which ga thers the appr o-
priate data from the ADCs and controls writes to XRAM. The DMA instructions tell the DMA Control Logic
which ADC(s) to expect results from, but do not initiate the actual conversions. It is important to configure
the ADCs for the desired start-of-conversion source, voltage reference, and SAR clock frequency prior to
starting the DMA interface. For information on setting up the ADCs, refer to Section “5. 16-Bit ADCs (ADC0
and ADC1)” on page 51.
6.1. Writing to the Instruction Buffer
The Instruction Buf f er has 64 8-bit lo cations that can be progr ammed with a sequen ce of DMA instr uctions.
Filling the Instruction Buffer is done with the Special Function Registers DMA0IPT (DMA Instruction Write
Address Register, Figure 6.6) and DMA0IDT (DMA Instruction Write Data Register, Figure 6.7). Instruc-
tions are written to the Instruction Buffer at address DMA0IPT when the instruction word is written to
DMA0IDT. Reading the register DMA0IDT will return the instruction word at location DMA0IPT. After a write
or read operat ion on DMA0I DT, the DMA0IPT registe r is automatically incremented to the next Instruction
Buffer location.
AIN0
ADC0
AIN1
ADC1
DMA
Control Logic
DMA0IDT
Instruction Data
DMA0IPT
Address
Write Logic
DMA0BND
Start Address
Instruction
Buffer
(64 Bytes)
ADC0EN
ADC1EN
DIFFSEL
CCNV
DMA0ISW
Current Address
XRAM
(on-chip or
off-chip)
DMA0DSH
Current XRAM Address
DMA0DSL
DMA0DAH
Beginning XRAM Address
DMA0DAL
DMA0CSH
Curren t R e peat Counte r Value
DMA0CSLDMA0CTH
Repeat Counter Limit
DMA0CTL
Address Bus
Data Bus
DMA0CF
DMA0EO
DMA0EOE
DMA0CI
DMA0CIE
DMA0XBY
DMA0HLT
DMA0CN
DMA0DO0
DMA0DO1
DMA0DOE
DMA0DE0
DMA0DE1
DMA0MD
DMA0INT
DMA0EN
AIN0G
AIN1G
Figure 6.1. DMA0 Block Diagram
C8051F060/1/2/3/4/5/6/7
76 Rev. 1.2
6.2. DMA0 Instruction Format
DMA instructions can request single-ended data from both ADC0 and ADC1, as well as the differential
combination of the two ADC inputs. The instruction format is identical to the DMA0IDT register, shown in
Figure 6.7. Depending on which bits are set to ‘1’ in the instruction word, either 2 or 4 bytes of data will be
written to XRAM for each DMA instruction cycle (excluding End-Of-Operation instructions). Table 6.1
details all of the valid DMA instructions. Instructions not listed in the table are not valid DMA instructions,
and should not be used. Note that the ADCs can be independently controlled by the microcontroller when
their outputs are not requested by the DMA.
6.3. XRAM Addressing and Setup
The DMA Interface can be configured to access either on-chip or off-chip XRAM. Any writes to on-chip
XRAM by the DMA Control Logic occur when the processor core is not accessing the on-chip XRAM. This
ensures that the DMA will not interfere with processor instruction timing.
Off-chip XRAM access (only available on the C8051F060/2/4/6) is controlled by the DMA0HLT bit in
DMA0CF (DMA Configuration Register, Figure 6.5). The DMA will have full access to off-chip XRAM when
this bit is ‘0’, and the processor core will have full access to off-chip XRAM when this bit is ‘1’. The
DMA0HLT bit should be controlled in software when both the processor core and the DMA Interface
require access to of f-chip XRAM dat a spa ce. Before setting DMA0HLT to ‘1’, the software should check the
DMA0XBY bit to ensure that the DMA is not currently accessing off-chip XRAM. The processor core can-
not access off-chip XRAM while DMA0HLT is ‘0’. The processor will continue as though it was able to per-
form the desired memory access, but the data will not be written to or read from off-chip XRAM. When the
processor core is finished accessing off-chip XRAM, DMA0HLT should be set back to ‘0’in software to
return control to the DMA Interface. The DMA Control Logic will wait until DMA0HLT is ‘0’ before writing
data to off-chip XRAM. If new data becomes available to the DMA Interface before the previous data has
been written, an overflow condition will occur, and the new data word may be lost.
The Data Address Pointer Registers (DMA0DSH and DMA0DSL) contain the 16-bit XRAM address loca-
tion where the DMA interface will write data. When the DMA is initially enabled, the DMA Data Address
Table 6.1. DMA0 Instruction Set
Instruction
Word Description First Data Written
to XRAM (2 bytes)
Second Data
Written to XRAM
(2 bytes)
00000000b End-Of-Operation none none
10000000b End-Of-Operation with Continuous Conversion none none
x0010000b Retrieve ADC0 Data ADC0H:ADC0L none
x0100000b Retrieve ADC1 Data ADC1H:ADC1L none
x0110000b R etri eve ADC0 an d ADC1 Data ADC0H:ADC0L ADC1H:ADC1L
x10x0000b Retr ie ve Differential Data ADC0H:ADC0L
(differential result
from both ADCs) none
x11x0000b Retrieve Differential and ADC1 Data ADC0H:ADC0L
(differential result
from both ADCs) ADC1H:ADC1L
C8051F060/1/2/3/4/5/6/7
Rev. 1.2 77
Pointer Registers are initialized to the values contained in the DMA Data Address Beginning Registers
(DMA0DAH and DMA0DAL). The Data Address Pointer Registers are automatically incremented by 2 or 4
after each data write by the DMA interface .
6.4. Instruction Execution in Mode 0
When the DMA interface begins an operation cycle, the DMA Instruction Status Register (DMA0ISW,
Figure 6.9) is loaded with the address contained in the DMA Instruction Boundary Register (DMA0BND,
Figure 6.8). The instruction is fetched from the In str uction Bu ffer, and the DMA Control Log ic waits for dat a
from the appropriate ADC(s). The DMA will execute each instruction once, and then increment DMA0ISW
to the next instruction address. When the current DMA instruction is an End of Operation instruction, the
Instruction Status Register is reset to the Instruction Boundary Register. If the Continuous Conversion bit
(bit 7, CCNV) in the End of Operation instruction word is set to ‘1’, the Repeat Counter is ignored, and the
DMA will continue to execute instructions indefinitely. When CCNV is set to ‘0’, the Repeat Counter (regis-
ters DMA0CSH and DMA0CSL) is decremented, and the DMA will continue to execute instructions until
the Repeat Counter reaches 0x0000. The Repeat Counter is initialized with the Repeat Counter Limit
value (registers DMA0CTH and DMA0CTL) at the beginning of the DMA operation. An example of Mode 0
operation is shown in Figure 6.2.
00000000
0x3F
00110000
00010000
010000000x01
0x02
0x03
...
0x00
ADC0H
ADC0L
DMA0BND
ADC0H
ADC0L
DMA0CSH:L = DMA0CTH:L
DMA0CSH:L = DMA0CTH:L - 1
DMA0CSH:L = 0x00 00
INSTRUCTION
BUFFER
(64 Bytes)
XRAM
ADC0H (Diff.)
ADC0L
ADC0H (Diff.)
ADC0L (Diff.)
ADC0H
ADC0L
ADC1H
ADC1L
ADC1H
ADC1L
Figure 6.2. DMA Mode 0 Operation
C8051F060/1/2/3/4/5/6/7
78 Rev. 1.2
6.5. Instruction Execution in Mode 1
When the DMA interface begins an operation cycle, the DMA Instruction Status Register (DMA0ISW,
Figure 6.9) is loaded with the address contained within the DMA Instruction Boundary Register
(DMA0BND, Figure 6.8). The instruction is fetched from the Instruction Buffer, and the DMA Control Logic
waits for data from the appropriate ADC(s). At the end of an instruction, the Repeat Counter (Registers
DMA0CSH and DMA0CSL) is decremented, and the instruction will be repeated until the Repeat Counter
reaches 0x0000. The Repeat Counter is then reset to the Repeat Counter Limit value (Registers
DMA0CTH and DMA0CTL), and the DMA will increment DMA0ISW to the next instruc tion address. When
the current DMA instruction is an End of Operation instruction, the Instruction Status Register is reset to
the Instruction Boundary Register. If the Continuous Conversion bit (bit 7, CCNV) in the En d of Opera tion
instruction word is set to ‘1’, the DMA will continue to execute instructions. When CCNV is set to ‘0’, the
DMA will stop executing instructions at this point. An example of Mode 1 operation is shown in Figure 6.3.
00000000
0x3F
00110000
00010000
010000000x01
0x02
0x03
...
0x00
DMA0BND
ADC0H
ADC0L
INSTRUCTION
BUFFER
(64 Bytes)
XRAM
ADC0H (Diff.)
ADC0L (Diff.)
ADC0H
ADC0L
ADC1H
ADC1L
ADC0H
ADC0L
ADC0H
ADC0L
DMA0CSH:L = DMA 0CTH:L
DMA0CSH:L = DMA 0CTH:L - 1
DMA0CSH:L = 0x0000
DMA0CSH:L = DMA 0CTH:L
ADC0H (Diff.)
ADC0L (Diff.) DMA0CSH:L = 0x0000
DMA0CSH:L = DMA 0CTH:L
ADC0H
ADC0L
ADC1H
ADC1L
DMA0CSH:L = 0x0000
Figure 6.3. DMA Mode 1 Operation
C8051F060/1/2/3/4/5/6/7
Rev. 1.2 79
6.6. Interrupt Sources
The DMA contains multiple interrupt sources. Some of these can be individually enabled to generate inter-
rupts as necessary. The DMA Control Register (DMA0CN, Figure 6.4) and DMA Configuration Register
(DMA0CF, Figure 6.5) contain the enable bit s a nd flags for the DMA interr upt sources. Whe n an interrupt is
enabled and the interrupt condition occurs, a DMA interrupt will be generated (EIE2.7 is set to ‘1’).
The DMA flags that can ge n er ate a DMA0 interrupt are :
1. DMA Operations Complete (DMA0CN.6, DMA0INT) occurs when all DMA operations have
been completed, and the DMA interface is idle.
2. ADC1 Data Overflow Error (DMA0CN.4, DMA0DE1) occurs when the DMA interface cannot
access XRAM for two conversion cycles of ADC1. This flag in dic at es t ha t a t least one conv er -
sion result from ADC1 ha s be en discarded.
3. ADC0 Data Overflow Error (DMA0CN.3, DMA0DE0) occurs when the DMA interface cannot
access XRAM for two conversion cycles of ADC0. This flag in dic at es t ha t a t least one conv er -
sion result from ADC0 ha s be en discarded.
4. ADC1 Data Overflow Warning (DMA0CN.1, DMA0DO1) occurs when data from ADC0
becomes available and the DMA has not yet written the previous results to XRAM. This inter-
rupt source can be enabled and disabled with the Data Overflow Warning Enable bit
(DMA0CN.2, DMA0DOE).
5. ADC0 Data Overflow Warning (DMA0CN.0, DMA0DO0) occurs when data from ADC1
becomes available and the DMA has not yet written the previous results to XRAM. This inter-
rupt source can be enabled and disabled with the Data Overflow Warning Enable bit
(DMA0CN.2, DMA0DOE).
6. Repeat Counter Overflow (DMA0CF.2, DMA0CI) occurs when the Repeat Counter reaches
the Repeat Counter Limit. This interrupt source can be enabled and disabled with the Repeat
Counter Overflow Interrupt Enable bit (DMA0CF.3, DMA0CIE).
7. End Of Operation (DMA0CF.0, DMA0EO) occurs when an End Of Operation instruction is
reached in the Instruction Buffer. This interrupt source can be enabled and disabled with the
End Of Operation Interrupt Enable bit (DMA0CF.1, DMA0EOE).
6.7. Data Buffer Overflow Warnings and Errors
The data paths from the ADCs to XRAM are double-buffered when using the DMA interface. When a con-
version is completed by the ADC, it first enters the ADCs data register. If the DMA’s data buffer is empty,
the conversion results will immediately be written into the DMA’s internal data buffer for that ADC. Data in
the DMA’ s internal data buf fer is writte n to XRAM at the fir st availab le oppor tu nity (see Section “6.3. XRAM
Addressing an d Setup” on page 76 ). Conversion results from the ADC’s data registers are not copied into
the DMA’s data buffer until data in the buffer has been written to XRAM. When a conversion is co mpleted
and the DMA’s data buffer is not empty, an overflow warning flag is generated. If a second conversion data
word becomes availab le befor e the DMA’s dat a buffer is written to XRAM, the dat a in the ADC’s dat a r egis-
ters is over-written with the new data word, and a data overflow error flag is generated.
C8051F060/1/2/3/4/5/6/7
80 Rev. 1.2
Figure 6.4. DMA0CN: DMA0 Control Register
Bit 7: DMA0EN: DMA0 Enable.
Write:
0: Stop DMA0 Operations.
1: Begin DMA0 Operations.
Read:
0: DMA0 is Idle.
1: DMA0 Operation is in Progress.
Bit 6: DMA0INT: DMA0 Operations Complete Flag.
0: DMA0 has not completed all operations.
1: DMA0 operations are complete. This bit must be cleared by sof tware.
Bit 5: DMA0MD: DMA0 Mode Select.
0: DMA0 will operate in Mode 0.
1: DMA0 will operate in Mode 1.
Bit 4: DMA0DE1: ADC1 Data Overflow Error Flag.
0: ADC1 Data Overflow has not occured.
1: ADC1 Data Overflow has occured, and data from ADC1 has been lost. This bit must be
cleared by software.
Bit 3: DMA0DE0: ADC0 Data Overflow Error Flag.
0: ADC0 Data Overflow has not occured.
1: ADC0 Data Overflow has occured, and data from ADC0 has been lost. This bit must be
cleared by software.
Bit 2: DMA0DOE: Data Overflow Warning Interrupt Enable.
0: Disable Data Overflow Warning interrupts.
1: Enable Data Overflow Warning interrups.
Bit 1: DMA0DO1: ADC1 Data Overflow Warning Flag.
0: No ADC1 Data Buffer Warnings have been issued.
1: ADC1 Data Buffer is full, and the DMA has not written previous data to XRAM. This bit
must be cleared by software.
Bit 0: DMA0DO0: ADC0 Data Overflow Warning Flag.
0: No ADC0 Data Buffer Warnings have been issued.
1: ADC0 Data Buffer is full, and the DMA has not written previous data to XRAM. This bit
must be cleared by software.
SFR Page:
SFR Address: 3
0xD8 (bit addressable)
R/W R/W R/W R/W R/W R/W R/W R/W Reset Value
DMA0EN DMA0INT DMA0MD DMA0DE1 DMA0DE0 DMA0DOE DMA0DO1 DMA0DO0 00000000
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
C8051F060/1/2/3/4/5/6/7
Rev. 1.2 81
Figure 6.5. DMA0CF: DMA0 Configuration Register
Bit 7: DMA0HLT: Halt DMA0 Off-Chip XRAM Access (C8051F060/2/4/6 Only).
0: DMA0 has complete access to off-chip XRAM.
1: Processor core has complete access to off-chip XRAM. DMA0 will wait until this bit is ‘0’
before writing to off-chip XRAM locations.
Bit 6: DMA0XBY: Off-chip XRAM Busy Flag (C8051F060/2/4/6 Only).
0: DMA0 is not accessing off-chip XRAM.
1: DMA0 is accessing off-chip XRAM.
Bits 5-4: RESERVED. Write to 00b.
Bit 3: DMA0CIE: Repeat Counter Overflow Interrupt Enable.
0: Disable Repeat Counter Overflow Interrupt.
1: Enable Repeat Counter Overflow Interrupt.
Bit 2: DMA0CI: Repeat Counter Overflow Flag.
0: Repeat Counter Overflow has not occured.
1: Repeat Counter Overflow has occured. This bit must be cleared by software.
Bit 1: DMA0EOE: End-Of-Operation Interrupt Enable.
0: Disable End-Of-Operation Interrupt.
1: Enable End-Of-Operation Interrupt.
Bit 0: DMA0EO: End-Of-Operation Flag.
0: End-Of-Operation Instruction has not been received.
1: End-Of-Operation Instruction has been received. This bit must be cleared by software.
SFR Page:
SFR Address: 3
0xF8 (bi t addressable)
R/W R R/W R/W R/W R/W R/W R/W Reset Value
DMA0HLT DMA0XBY - - DMA0CIE DMA0CI DMA0EOE DMA0EO 00000000
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
C8051F060/1/2/3/4/5/6/7
82 Rev. 1.2
Figure 6.6. DMA0IPT: DMA0 Instruction Write Address Register
Bits 7-6: Unused.
Bits 5-0: DMA0 instruction address to write (or re ad). When DMA0IDT is written or read, this register
will be incremented to point to the next instruction address.
SFR Page:
SFR Address: 3
0xDD
R R R/W R/W R/W R/W R/W R/W Reset Value
-- 00000000
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
Figure 6.7. DMA0IDT: DMA0 Instruction Write Data Register
Bit 7: CCNV: Continuous Conversion.
0: Disable Continuous Conversion.
1: Enable Continuous Conversion. Repeat Counter value is ignored, and conversions will
continue.
Bit 6: DIFFSEL: Wait for data in differential mode.
0: Differential Data will not be collected.
1: Wait for differential data, and store to XRAM.
Bit 5: ADC1EN: Wait for data from ADC1.
0: ADC1 Data will not be collected.
1: Wait for ADC1 data, and store to XRAM.
Bit 4: ADC0EN: Wait for data from ADC0.
0: ADC0 Data will not be collected.
1: Wait for ADC0 data, and store to XRAM. If DIFFSEL is also ‘1’, only the differential data
will be stored.
Bits 3-0: RESERVED. Write to 0000b.
For more details on DMA instruction words, see Section “6.2. DMA0 Instruction Format” on page 76.
† This register points to a dedicated RAM location and its reset value is indeterminate.
SFR Page:
SFR Address: 3
0xDE
R/W R/W R/W R/W R/W R/W R/W R/W Reset Value†
CCNV DIFFSEL ADC1EN ADC0EN - - - - xxxxxxxx
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
C8051F060/1/2/3/4/5/6/7
Rev. 1.2 83
Figure 6.8. DMA0BND: DMA0 Instruction Boundary Register
Bits 7-6: Unused.
Bits 5-0: DMA0 instruction address to begin with when executing DMA instructions.
SFR Page:
SFR Address: 3
0xFD
R/W R/W R/W R/W R/W R/W R/W R/W Reset Value
-- 00000000
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
Figure 6.9. DMA0ISW: DMA0 Instruction Status Register
Bits 7-6: Unused.
Bits 5-0: Contains the address of the current DMA0 Instruction to be executed.
SFR Page:
SFR Address: 3
0xFE
R/W R/W R/W R/W R/W R/W R/W R/W Reset Value
-- 00000000
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
C8051F060/1/2/3/4/5/6/7
84 Rev. 1.2
Figure 6.10. DMA0DAH: DMA0 Data Address Beginning MSB Register
Bits 7-0: DMA0 Address Beginning High-Order Bits.
SFR Page:
SFR Address: 3
0xDA
R/W R/W R/W R/W R/W R/W R/W R/W Reset Value
00000000
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
Figure 6.11. DMA0DAL: DMA0 Data Address Beginning LSB Register
Bits 7-0: DMA0 Address Beginning Low-Order Bits.
SFR Page:
SFR Address: 3
0xD9
R/W R/W R/W R/W R/W R/W R/W R/W Reset Value
00000000
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
Figure 6.12. DMA0DSH: DMA0 Data Address Pointer MSB Register
Bits 7-0: DMA0 Address Pointer High-Order Bits.
SFR Page:
SFR Address: 3
0xDC
R/W R/W R/W R/W R/W R/W R/W R/W Reset Value
00000000
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
Figure 6.13. DMA0DSL: DMA0 Data Address Pointer LSB Register
Bits 7-0: DMA0 Address Pointer Low-Order Bits.
SFR Page:
SFR Address: 3
0xDB
R/W R/W R/W R/W R/W R/W R/W R/W Reset Value
00000000
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
C8051F060/1/2/3/4/5/6/7
Rev. 1.2 85
Figure 6.14. DMA0CTH: DMA0 Repeat Counter Limit MSB Register
Bits 7-0: DMA0 Repeat Counter Limit High-Order Bits.
SFR Page:
SFR Address: 3
0xFA
R/W R/W R/W R/W R/W R/W R/W R/W Reset Value
00000000
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
Figure 6.15. DMA0CTL: DMA0 Repeat Counter Limit LSB Register
Bits 7-0: DMA0 Repeat Counter Limit Low-Orde r Bits.
SFR Page:
SFR Address: 3
0xF9
R/W R/W R/W R/W R/W R/W R/W R/W Reset Value
00000000
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
Figure 6.16. DMA0CSH: DMA0 Repeat Counter MSB Register
Bits 7-0: DMA0 Repeat Counter High-Order Bits.
SFR Page:
SFR Address: 3
0xFC
R/W R/W R/W R/W R/W R/W R/W R/W Reset Value
00000000
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
Figure 6.17. DMA0CSL: DMA0 Repeat Counter LSB Register
Bits 7-0: DMA0 Repeat Counter Low-Order Bits.
SFR Page:
SFR Address: 3
0xFB
R/W R/W R/W R/W R/W R/W R/W R/W Reset Value
00000000
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
C8051F060/1/2/3/4/5/6/7
86 Rev. 1.2
C8051F060/1/2/3/4/5/6/7
Rev. 1.2 87
7. 10-Bit ADC (ADC2, C8051F060/1/2/3)
The ADC2 subsystem for the C8051F060/1/2/3 consists of an analog multiplexer (referre d to as AMU X2),
and a 200 ksps, 10-bit successive-approximation-register ADC with integrated track-and-hold and pro-
grammable w indow d etector ( see block diagram in Figure 7.1). T he AMUX2, data conversion modes, and
window detector can all be configured from within software via the Special Function Registers shown in
Figure 7.1. ADC2 operates in both Single-ended and Differential modes, and may be configured to mea-
sure any of the pins on Port 1, or the Temperature Sensor output. The ADC2 subsystem is enabled only
when the AD2EN bit in the ADC2 Control register (ADC2CN) is set to logic 1. The ADC2 subsystem is in
low power shutdown when this bit is logic 0.
10-Bit
SAR
ADC
REF
TEMP
SENSOR
10
9-to-1
AMUX
(SE or
DIFF)
AV+
20
10
AD2EN
SYSCLK
AIN2.0
AIN2.1
AIN2.2
AIN2.3
AIN2.4
AIN2.5
AIN2.6
AIN2.7
Start Conversion
AGND
ADC2L ADC2H
ADC2LTLADC2LTHADC2GTLADC2GTH
AD2CM
Timer 3 Overflow
Timer 2 Overflow
00
01
10
11
AD2BUSY (W )
CNVSTR2
AD2WINT
Comb.
Logic
AMX2SL
AMX2AD0
AMX2AD1
AMX2AD2
AMX2AD3
AMX2CF
AIN01IC
AIN23IC
AIN45IC
AIN67IC
ADC2CF
AD2SC0
AD2SC1
AD2SC2
AD2SC3
AD2SC4
ADC2CN
AD2LJST
AD2WINT
AD2CM0
AD2CM1
AD2BUSY
AD2INT
AD2TM
AD2EN
AD2CM
Figure 7.1. ADC2 Functional Block Diagram
C8051F060/1/2/3/4/5/6/7
88 Rev. 1.2
7.1. Analog Multiplexer
The analog multiplexer (AMUX2) selects the inputs to the ADC, allowing any of the pins on Port 1 to be
measured in single-ended mode, or as a differential pair. Additionally, the on-chip temperature sensor may
be selected as a single-ended input. The ADC2 input channels are configured and selected in the
AMX2CF and AMX2SL registers as described in Figure 7.5 and Figure 7.6, respectively. In Single-ended
Mode, the selected pin is measured with respect to AGND. In Differential Mode, the selected differential
pair is measured with respect to one another. The polarity of the differential measurement depends on the
setting of the AMX2AD3-0 bits in the AMX2SL register. For example, if pins AIN2.0 and AIN2.1 are config-
ured for differential measurement (AIN01IC = 1), and AMX2AD3-0 = 0000b, the ADC will measure the volt-
age (AIN2.0 - AIN2.1). If AMX2AD3-0 is changed to 0001b, the ADC will measure the s ame voltage, with
opposite polarity (AIN2.1 - AIN2.0).
The conversion code format differs between Single-ended and Differential modes. The registers ADC2H
and ADC2L contain the high and low bytes of the output conversion code from the ADC at th e comp letion
of each conversion. Data can be righ t-justifie d or left-justified, depend ing on the setting of the AD2LJST bit
(ADC2CN.0). When in Single-ende d Mode, conversion codes ar e rep resented as 10-bit unsign ed integ ers.
Inputs ar e measured from ‘0’ to VREF * 1023/10 24. Example codes are shown below for both right- justified
and left-justified data . Unused bits in the ADC2H and ADC2L registers are set to ‘0’.
When in Differential Mode, conversion codes are represented as 10-bit signed 2’s complement numbers.
Inputs are measured from -VREF to VREF * 511/512. Example codes are shown below for both right-justi-
fied and left-justified data. For right-justified data, the unused MSBs of ADC2H are a sign-extension of the
data word. For left-justified data, the unused LSBs in the ADC2L register are set to ‘0’.
Important Note About ADC2 Input Configuration: Port 1 pins selected as ADC2 inputs should be con-
figured as analog inputs. To configure a Port 1 pin for analog input, set to ‘1’ the corr esponding bit in regis-
ter P1MDIN. Port 1 pins use d as ADC2 inputs will be skipped by the crossbar for peripheral assignments.
See Section “18. Port Input/Output” on page 203 for more Port I/O configuration det ails.
The Temperature Sensor transfer function is shown in Figure 7.2 on Page 89. The output voltage (VTEMP)
is a single-ended input to ADC2 when the Temperature Sensor is selected by bits AMX2AD3-0 in register
AMX2SL. Typical values for the Slope an d Offset parameters can be found in Table 7.1.
Input Voltage Right-Justified ADC2H:ADC2L
(AD2LJST = 0) Left-Justified ADC2H:ADC2L
(AD2LJST = 1)
VREF * 1023/1024 0x03FF 0xFFC0
VREF * 512/1024 0x0200 0x8000
VREF * 256/1024 0x0100 0x4000
0 0x0000 0x0000
Input Voltage Right-Justified ADC2H:ADC2L
(AD2LJST = 0) Left-Justified ADC2H:ADC2L
(AD2LJST = 1)
VREF * 511/512 0x01FF 0x7FC0
VREF * 256/512 0x0100 0x4000
0 0x0000 0x0000
-VREF * 256/512 0xFF00 0xC000
- VREF 0xFE00 0x8000
C8051F060/1/2/3/4/5/6/7
Rev. 1.2 89
7.2. Modes of Operation
ADC2 has a maximum conversion speed of 200 ksps. The ADC2 conversion clock is a divided version of
the system clock, determined by the AD2SC bit s in th e ADC2CF register (system clock divided by (AD2SC
+ 1) for 0 AD2SC 31). The ADC2 conversion clock should be no more than 3 MHz.
7.2.1. Starting a Conversion
A conversion can be initiated in one of four ways, depending on the programmed states of the ADC2 Start
of Conversion Mode bits (AD2CM1-0) in register ADC2CN. Conversions may be initiated by one of the fol-
lowing:
1. Writing a ‘1’ to the AD2BUSY bit of register ADC2CN
2. A Timer 3 overflow (i.e. timed continuous conversions)
3. A rising edge on the CNVSTR2 input signal (Assigned by the crossbar)
4. A Timer 2 overflow
When CNVSTR2 is used as a conve rsion start source, it m ust be enabled in the crossbar, and the corre -
sponding pin must be set to open-drain, high-impedance mode (see Section “18. Port Input/Output” on
page 203 for more details on Port I/O configuration).
Writing a ‘1’ to AD2BUSY provides software control of ADC2 whereby conversions are performed "on-
demand". During conversion, the AD2BUSY bit is set to logic 1 and reset to logic 0 when the conver sion is
complete. The falling edge of AD2BUSY triggers an interrupt (when enabled) and sets the ADC2 interrupt
flag (AD2INT). Note: When polling for ADC conversion completions, the ADC2 interrupt flag (AD2INT)
should be used. Converted data is available in the ADC2 data registers, ADC2H and ADC2L, when bit
AD2INT is logic 1. Note that when Timer 2 or Timer 3 overflows are used as the conversion source, low
byte overf lows are used if t he tim er is in 8-bit mo de; and high byte overflows are used if the timer is in 16-
bit mode. See Section “24. Timers” on page 28 7 for timer configuration.
0-50 50 100
Temperature (Celsius)
Voltage
VTEMP = (Slope x TempC) + Offset
Offset (V at 0 Celsius)
Slope (V / deg C)
TempC = (VTEMP
- Offset) / Slope
Figure 7.2. Temperature Sensor Transfer Function
C8051F060/1/2/3/4/5/6/7
90 Rev. 1.2
7.2.2. Tracking Modes
The AD2TM bit in register ADC2CN controls the ADC2 track-and-hold mode. In its default state, the ADC2
input is continuously tracked, except when a conversion is in progress. When the AD2TM bit is logic 1,
ADC2 operates in low-power track-and-hold mode. In this mode, each conversion is preceded by a track-
ing period of 3 SAR clocks (after the start-of-conversion signal). When the CNVSTR2 signal is used to ini-
tiate conversions in low-power tracking mode, ADC2 tracks only when CNVSTR2 is low; conversion
begins on the rising edge of CNVSTR2 (see Figure 7.3). Tracking can also be disabled (shutdown) when
the device is in low power standby or sleep modes. Low-power track-and-hold mode is also useful when
AMUX settings are frequently changed, due to the settling time requirements described in Section
“7.2.3. Settling Time Requirements” on page 91.
Figure 7.3. 10-Bit ADC Track and Conversion Example Ti ming
Write '1' to AD2BUSY,
Timer 3, Timer 2 Overflow
(AD2CM[1:0]=0 0, 01, 11)
AD2TM=1 Track Convert Low Power Mode
AD2TM=0 Track or
Convert Convert Track
Low Power
or Convert
SAR Clocks
123456789101112
123456789
SAR Clocks
B. ADC2 Timing for Internal Trigger Source
123456789
CNVSTR2
(AD2CM[1:0]=10)
AD2TM=1
A. ADC2 Timing for External Trigger Source
SAR Clocks
Track or Convert Convert TrackAD2TM=0
Track Convert Low Po wer
Mode
Low Power
or Convert
10 11
13 14
10 11
C8051F060/1/2/3/4/5/6/7
Rev. 1.2 91
7.2.3. Settling Time Requirements
A minimum tracking time is requir ed before an accu rate conver sion can be pe rformed. This tracking time is
determined by the AMUX2 resistance, the ADC2 sampling capacitance, any external source resistance,
and the accuracy required for the conversion. Note that in low-power tracking mode, three SAR clocks are
used for tracking at the start of every conversion. For most applications, these three SAR clocks will meet
the minimum tracking time requirements.
Figure 7.4 shows the equivalent ADC2 input circuits for both Differential and Single-ended modes. Notice
that the equivalent time constant for both input circuits is the same. The required ADC2 settling time for a
given settling accuracy (SA) may be approximated by Equation 7.1. When measuring the Temperature
Sensor output, RTOTAL reduces to RMUX. See Table 7.1 for ADC2 minimum settling time requirements.
Where:
SA is the settling accuracy, given as a fraction of an LSB (for example, 0.25 to settle within 1/4 LSB)
t is the required settling time in seconds
RTOTAL is the sum of the AMUX2 resistance and any external source resistance.
n is the ADC resolution in bits (10).
Equation 7.1. ADC2 Settling Time Requirements
t2n
SA
-------
RTOTALCSAMPLE
ln=
R
MUX
= 5k
RC
Input
= R
MUX
* C
SAMPLE
R
MUX
= 5k
C
SAMPLE
= 5pF
C
SAMPLE
= 5pF
MUX Select
MUX Select
Differential Mode
P1.x
P1.y
R
MUX
= 5k
C
SAMPLE
= 5pF
RC
Input
= R
MUX
* C
SAMPLE
MUX Select
Single-Ended Mode
P1.x
Figure 7.4. ADC2 Equivalent Input Circuits
C8051F060/1/2/3/4/5/6/7
92 Rev. 1.2
Figure 7.5. AMX2CF: AMUX2 Configuration Register
Bits 7-4: UNUSED. Read = 0000b; Write = don’t care.
Bit 3: AIN67IC: AIN2.6, AIN2.7 Input Pair Configuration Bit.
0: AIN2.6 and AIN2.7 are independent, single-ended inputs.
1: AIN2.6 and AIN2.7 are a differential input pair.
Bit 2: AIN45IC: AIN2.4, AIN2.5 Input Pair Configuration Bit.
0: AIN2.4 and AIN2.5 are independent, single-ended inputs.
1: AIN2.4 and AIN2.5 are a differential input pair.
Bit 1: AIN23IC: AIN2.2, AIN2.3 Input Pair Configuration Bit.
0: AIN2.2 and AIN2.3 are independent, single-ended inputs.
1: AIN2.2 and AIN2.3 are a differential input pair.
Bit 0: AIN01IC: AIN2.0, AIN2.1 Input Pair Configuration Bit.
0: AIN2.0 and AIN2.1 are independent, single-ended inputs.
1: AIN2.0 and AIN2.1 are a differential input pair.
NOTE: The ADC2 Data Word is in the 2’s complement format for channels configured as differen-
tial. The polarity of a differential measurement is determined by the AMX2SL setting. See
Figure 7.5 for more details on multiplexer channel selection.
SFR Page:
SFR Address: 2
0xBA
R/W R/W R/W R/W R/W R/W R/W R/W Reset Value
- - - - AIN67IC AIN45IC AIN23IC AIN01IC 00000000
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
C8051F060/1/2/3/4/5/6/7
Rev. 1.2 93
Figure 7.6. AMX2SL: AMUX2 Channel Select Register
Bits 7-4: UNUSED. Read = 0000b; Write = don’t care.
Bits 3-0: AMX2AD3-0: AMX2 Address Bits.
0000-1111b: ADC input multiplexer channel selected per chart below.
SFR Page:
SFR Address: 2
0xBB
R/W R/W R/W R/W R/W R/W R/W R/W Reset Value
- - - - AMX2AD3 AMX2AD2 AMX2AD1 AMX2AD0 00000000
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
AMX2AD3-0 Single-Ended Measurement AMX2AD3-0 Differential Measurement
0000 AIN2.0 AIN 01IC = 0 0000 +(AIN2.0) -(AIN2.1) AIN01IC = 1
0001 AIN2.1 0001 +(AIN2.1) -(AIN2.0)
0010 AIN2.2 AIN 23IC = 0 0010 +(AIN2.2) -(AIN2.3) AIN23IC = 1
0011 AIN2.3 0011 +(AIN2.3) -(AIN2.2)
0100 AIN2.4 AIN 45IC = 0 0100 +(AIN2.4) -(AIN2.5) AIN45IC = 1
0101 AIN2.5 0101 +(AIN2.5) -(AIN2.4)
0110 AIN2.6 AIN67IC = 0 0110 +(AIN2.6) -(AIN2.7) AIN67IC = 1
0111 AIN2.7 0111 +(AIN2.7) -(AIN2.6)
1xxx Temperature
Sensor 1xxx -
C8051F060/1/2/3/4/5/6/7
94 Rev. 1.2
Figure 7.7. ADC2CF: ADC2 Configuration Register
Bits7-3: AD2SC4-0: ADC2 SAR Conversion Clock Period Bits.
SAR Conversion clock is derived from system clock by the following equation , where ADSC
refers to the 5-bit value held in bit s AD2SC4-AD2SC0. SAR Conversion clock re quirement s
are given in Table 7.1.
Bits2-0: UNUSED. Read = 000b; Write = don’t care.
SFR Page:
SFR Address: 2
0xBC
R/W R/W R/W R/W R/W R/W R/W R/W Reset Value
AD2SC4 AD2SC3 AD2SC2 AD2SC1 AD2SC0 - - - 11111000
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
ADSC SYSCLK
CLKSAR
----------------------1–=
C8051F060/1/2/3/4/5/6/7
Rev. 1.2 95
Figure 7.8. ADC2H: ADC2 Data Word MSB Register
Bits7-0: ADC2 Data Word High-Order Bits.
For AD2LJST = 0: Bits 7-2 are the sign extension of Bit 1. Bit s 1-0 are th e upper 2 bit s of the
10-bit ADC2 Data Word.
For AD2LJST = 1: Bits 7-0 are the most-significant bits of the 10-bit ADC2 Data Word.
SFR Page:
SFR Address: 2
0xBF
R/W R/W R/W R/W R/W R/W R/W R/W Reset Value
00000000
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
Figure 7.9. ADC2L: ADC2 Data Word LSB Register
Bits7-0: ADC2 Data Word Low-Order Bits.
For AD2LJST = 0: Bits 7-0 are the lower 8 bits of the 10-bit Data Word.
For AD2LJST = 1: Bits 7-6 are the lower 2 bits of the 10-bit Data Word. Bits 5-0 will always
read ‘0’.
SFR Page:
SFR Address: 2
0xBE
R/W R/W R/W R/W R/W R/W R/W R/W Reset Value
00000000
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
C8051F060/1/2/3/4/5/6/7
96 Rev. 1.2
Figure 7.10. ADC2CN: ADC2 Control Register
Bit 7: AD2EN: ADC2 Enable Bit.
0: ADC2 Disabled. ADC2 is in low-power shutdown.
1: ADC2 Enabled. ADC2 is active and ready for data conversions.
Bit6: AD2TM: ADC2 Track Mode Bit.
0: Normal Track Mode: When ADC2 is enabled, tracking is continuous unle ss a con ve rs ion
is in progress.
1: Low-power Track Mode: Tracking Defined by AD2CM2-0 bits (see below).
Bit5: AD2INT: ADC2 Conversion Complete Interrupt Flag.
0: ADC2 has not completed a data conversion since the last time AD2INT was cleared.
1: ADC2 has completed a data conversion.
Bit 4: AD2BUSY: ADC2 Busy Bit.
Read:
0: ADC2 conversion is complete or a conversion is not currently in progress. AD2INT is set
to logic 1 on the falling edge of AD2BUSY.
1: ADC2 conversion is in progress.
Write:
0: No Effect.
1: Initiates ADC2 Conversion if AD2CM2-0 = 000b
Bits 3-2: AD2CM1-0: ADC2 Start of Conversion Mode Select.
When AD2TM = 0:
00: ADC2 conversion initiated on every write of ‘1’ to AD2BUSY.
01: ADC2 conversion initiated on overflow of Timer 3.
10: ADC2 conversion initiated on rising edge of external CNVSTR2 pin.
11: ADC2 conversion initiated on overflow of Timer 2.
When AD2TM = 1:
00: Tracking initiated on write of ‘1’ to AD2BUSY and lasts 3 SAR clocks, followed by con-
version.
01: Tracking initiated on overflow of Timer 3 and lasts 3 SAR clocks, followed by conver-
sion.
10: ADC2 tracks only when CNVSTR2 input is logic low; conversion starts on rising
CNVSTR2 edge.
11: T racking initiate d on overflow of T imer 2 and lasts 3 SAR clocks, followed by conversion.
Bit 1: AD2WINT: ADC2 Window Compare Interrupt Flag.
0: ADC2 Window Comparison Data match has not occurred since this flag was last cleared.
1: ADC2 Window Comparison Data match has occurred.
Bit 0: AD2LJST: ADC2 Left Justify Select.
0: Data in ADC2H:ADC2L registers are right-justified.
1: Data in ADC2H:ADC2L registers are left-justified.
SFR Page:
SFR Address: 2
0xE8 (bit addressable)
R/W R/W R/W R/W R/W R/W R/W R/W Reset Value
AD2EN AD2TM AD2INT AD2BUSY AD2CM1 AD2CM0 AD2WINT AD2LJST 00000000
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
C8051F060/1/2/3/4/5/6/7
Rev. 1.2 97
7.3. Programmable Window Detector
The ADC Programmable Window Detector continuously compares the ADC2 output registers to user-pro-
grammed limits, and notifies the system when a de sired condition is detected. This is especially ef fective i n
an interrupt-driven system, saving code space and CPU bandwidth while delivering faster system
response times. The window detector interrupt flag (AD2WINT in register ADC2CN) can also be used in
polled mode. The ADC2 Greater-Than (ADC2GTH, ADC2GTL) and Less-Than (ADC2LTH, ADC2LTL)
registers hold the comp arison values. The window detector flag can be programmed to in dicate when mea-
sured data is inside or outside of the user-programmed limits, depending on the contents of the ADC2
Less-Than and ADC2 Greater-Than registers.
Figure 7.11. ADC2GTH: ADC2 Greater-Than Data High Byte Register
Bits7-0: High byte of ADC2 Greater-Than Data Word.
SFR Page:
SFR Address: 2
0xC5
R/W R/W R/W R/W R/W R/W R/W R/W Reset Value
11111111
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
Figure 7.12. ADC2GTL: ADC2 Greater-Than Data Low Byte Register
Bits7-0: Low byte of ADC2 Greater-Than Data Word.
SFR Page:
SFR Address: 2
0xC4
R/W R/W R/W R/W R/W R/W R/W R/W Reset Value
11111111
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
C8051F060/1/2/3/4/5/6/7
98 Rev. 1.2
Figure 7.13. ADC2LTH: ADC2 Less-Than Data High Byte Register
Bits7-0: High byte of ADC2 Less-Than Data Word.
SFR Page:
SFR Address: 2
0xC7
R/W R/W R/W R/W R/W R/W R/W R/W Reset Value
00000000
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
Figure 7.14. ADC2LTL: ADC2 Less-Than Data Low Byte Register
Bits7-0: Low byte of ADC2 Less-Than Data Word.
SFR Page:
SFR Address: 2
0xC6
R/W R/W R/W R/W R/W R/W R/W R/W Reset Value
00000000
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
C8051F060/1/2/3/4/5/6/7
Rev. 1.2 99
7.3.1. Window Detector In Single-Ended Mode
Figure 7.15 shows two example window comparisons for right-justified, single-ended data, with
ADC2LTH:ADC2LTL = 0x0080 (128d) and ADC2GTH:ADC2GTL = 0x0040 (64d). In single-ended mode,
the input voltage can range from ‘0’ to VREF * (1023/1024) with respect to AGND, and is re presented by a
10-bit unsigned integer value. In the left example, an AD2WINT interrupt will be generated if the ADC2
conversion word (ADC2H:ADC2L) is within the range defined by ADC2GTH:ADC2GTL and
ADC2LTH:ADC2LTL (if 0x0040 < ADC2H:ADC2L < 0x0080). In the right example, and AD2WINT interrupt
will be generated if the ADC2 conversion word is outside of the range defined by the ADC2GT and
ADC2LT registers (if ADC2H:ADC2L < 0x0040 or ADC2H:ADC2L > 0x0080). Figure 7.16 shows an exam-
ple using left-justified data with the same comparison values.
0x03FF
0x0081
0x0080
0x007F
0x0041
0x0040
0x003F
0x0000
0
Input Voltage
(P1.x - AGND)
VREF x (1023/1024)
VREF x (128/1024)
VREF x (64/1024)
AD2WINT=1
AD2WINT
not affected
AD2WINT
not affected
ADC2LTH:ADC2LTL
ADC2GTH:ADC2GTL
0x03FF
0x0081
0x0080
0x007F
0x0041
0x0040
0x003F
0x0000
0
Input Voltage
(P1.x - AGND)
VREF x (1023/1024)
VREF x (128/1024)
VREF x (64/1024)
AD2WINT
not affected
ADC2LTH:ADC2LTL
ADC2GTH:ADC2GTL
AD2WINT=1
AD2WINT=1
ADC2H:ADC2L ADC2H:ADC2L
Figure 7.15. ADC Window Compare Example: Right-Justified Single-Ended Data
0xFFC0
0x2040
0x2000
0x1FC0
0x1040
0x1000
0x0FC0
0x0000
0
Input Vo ltag e
(P1.x - AGND)
VREF x (1023/1024)
VREF x (128/1024)
VREF x (64/1024)
AD2WINT=1
AD2WINT
not affected
AD2WINT
not affected
ADC2LTH:ADC2LTL
ADC2GTH:ADC2GTL
0xFFC0
0x2040
0x2000
0x1FC0
0x1040
0x1000
0x0FC0
0x0000
0
Input Voltage
(P1.x - AGND )
VREF x (1023/1024)
VREF x (128/1024)
VREF x (64/10 24)
AD2WINT
not affected
ADC2LTH:ADC2LTL
ADC2GTH:ADC2GTL
AD2WINT=1
AD2WINT=1
ADC2H:ADC2L ADC2H:ADC2L
Figure 7.16. ADC Window Comp are Example: Left-Justified Single-Ended Data
C8051F060/1/2/3/4/5/6/7
100 Rev. 1.2
7.3.2. Window Detector In Differential Mode
Figure 7.17 shows two example window comparisons for right-justified, differential data, with
ADC2LTH:ADC2LTL = 0x0040 (+64d) and ADC2GTH:ADC2GTH = 0xFFFF (-1d). In differential mode, the
measurable volt age betwe en the input pins is between - VREF and VREF*(511/512). Output codes are rep-
resented as 10-bit 2’s complement signed integers. In the left example, an AD2WINT interrupt will be gen-
erated if the ADC2 conversion word (ADC2H:ADC2L) is within the range defined by ADC2GTH:ADC2GTL
and ADC2LTH:ADC2LTL (if 0xFFFF (-1d) < ADC2H:ADC2L < 0x0040 (64d)). In the right example, an
AD2WINT interrupt will be generated if the ADC2 conversion word is outside of the range defined by the
ADC2GT and ADC2LT registers (if ADC2H:ADC2L < 0xFFFF (-1d) or ADC2H:ADC2L > 0x0040 (+64d)).
Figure 7.18 shows an example using left-justified data with the same comparison values.
0x01FF
0x0041
0x0040
0x003F
0x0000
0xFFFF
0xFFFE
0x0200
-VREF
Input Voltage
(P1.x - P1 . y)
VREF x (511/512)
VREF x (64/512)
VREF x (-1/512)
0x01FF
0x0041
0x0040
0x003F
0x0000
0xFFFF
0xFFFE
0x0200
-VREF
Input Voltage
(P1.x - P1.y)
VREF x (511/512)
VREF x (64/512)
VREF x (-1/512)
AD2WINT=1
AD2WINT
not affected
AD2WINT
not affected
ADC2LTH:ADC2LTL
ADC2GTH:ADC2GTL
AD2WINT
not affected
ADC2LTH:ADC2LTL
ADC2GTH:ADC2GTL
AD2WINT=1
AD2WINT=1
ADC2H:ADC2LADC2H:ADC2L
Figure 7.17. ADC Window Compare Example: Right-Justified Differential Data
0x7FC0
0x1040
0x1000
0x0FC0
0x0000
0xFFC0
0xFF80
0x8000
-VREF
Input V o lt a g e
(P1.x - P1.y)
VREF x (511/512)
VREF x (64/512)
VREF x (-1/512)
0x7FC0
0x1040
0x1000
0x0FC0
0x0000
0xFFC0
0xFF80
0x8000
-VREF
Input Voltage
(P1.x - P 1 .y)
VREF x (511/512)
VREF x (64/512)
VREF x (-1/512)
AD2WINT=1
AD2WINT
not affected
AD2WINT
not affected
ADC2LTH:ADC2LTL
ADC2GTH:ADC2GTL
AD2WINT
no t affected
ADC2LTH:ADC2LTL
ADC2GTH:ADC2GTL
AD2WINT=1
AD2WINT=1
ADC2H:ADC2LADC2H:ADC2L
Figure 7.18. ADC Window Compare Example: Left-Justified Differential Data
C8051F060/1/2/3/4/5/6/7
Rev. 1.2 101
Table 7.1. ADC2 Electrical Characteristics
VDD = 3.0 V, VREF = 2.40 V (REFSL=0), PGA Gain = 1, -40°C to +85°C unless otherwise specified
Parameter Conditions Min Typ Max Units
DC Accuracy
Resolution 10 bits
Integral Nonlinearity ±0.5 ±1 LSB
Differential Nonlinearity Guaranteed Monotonic ±0.5 ±1 LSB
Offset Error -12 1 12 LSB
Full Scale Error Differential mode -15 -5 5 LSB
Offset Temperature Coefficient 3.6 ppm/°C
DYNAMIC PERFORMANCE (10 kHz sine-wave Differential input, 1 dB below Full Scale, 200 ksps)
Signal-to-Noise Plus Distortion 53 55.5 dB
Total Harmonic Distortion Up to the 5th harmonic -67 dB
Spurious-Free Dynamic Range 78 dB
Conversion Rate
SAR Conversion Clock 3 MHz
Conversion Time in SAR Clocks 10 clocks
Track/Hold Acquisition Time 300 ns
Throughput Rate 200 ksps
Analog Inputs
ADC Input Voltage Range Single Ended (AIN+ - AGND)
Differential (AIN+ - AIN-) 0
-VREF VREF
VREF V
V
Absolute Pin Voltage with respect
to AGND Single Ended or Differential 0 AV+ V
Input Capacitance 5 pF
Temperature Sens or
Linearity ±0.2 °C
Offset Temp = 0 °C 776 mV
Offset Error (Note 1) Temp = 0 °C ±8.9 mV
Slope 2.89 mV/°C
Slope Error (Note 1) ±63 µV/°C
Power Specifications
Power Supply Current (VDD sup-
plied to ADC2) Operating Mode, 200 ksps 400 900 µA
Power Supply Rejection ±0.3 mV/V
Note 1: Represents one standard deviation from the mean value.
C8051F060/1/2/3/4/5/6/7
102 Rev. 1.2
C8051F060/1/2/3/4/5/6/7
Rev. 1.2 103
8. DACs, 12-Bit Voltage Mode (DAC0 and DAC1, C8051F060/1/2/3)
The C8051F060/1/2/3 devices include two on-chip 12-bit voltage-mode Digital-to-Analog Converters
(DACs). Each DAC has an output swing of 0 V to (VREF-1LSB) for a corresponding input code range of
0x000 to 0xFFF. The DACs may be enabled/disabled via their corresponding control registers, DAC0CN
and DAC1CN. While disabled, the DAC output is maintained in a high-impedance state, and the DAC sup-
ply current falls to 1 µA or less. The voltage reference for each DAC is supplied at the VREFD pin
(C8051F060/2 devices) or the VREF2 pin (C8051F061/3 devices). See Section “9. Voltage Reference 2
(C8051F060/2)” on page 111 or Section “10. Voltage Reference 2 (C8051F061/3)” on page 113 for more
information on configuring the voltage reference for the DACs. Note that the BIASE bit described in the
voltage reference sections must be set to ‘1’ to use the DACs.
DAC0
AV+
12
AGND
8
8
REF
DAC0
DAC0CN
DAC0EN
DAC0MD1
DAC0MD0
DAC0DF2
DAC0DF1
DAC0DF0
DAC0HDAC0L
Dig. MUX
Latch Latch
8
8
DAC1
AV+
12
AGND
8
8
REF
DAC1
DAC1CN
DAC1EN
DAC1MD1
DAC1MD0
DAC1DF2
DAC1DF1
DAC1DF0
DAC1HDAC1L
Dig. MUX
Latch Latch
8
8
DAC0H
Timer 3
Timer 4
Timer 2
DAC1H
Timer 3
Timer 4
Timer 2
Figure 8.1. DAC Functional Block Diagram
C8051F060/1/2/3/4/5/6/7
104 Rev. 1.2
8.1. DAC Output Scheduling
Each DAC features a flexible output update mechanism which allows for seamless full-scale changes and
supports jitter-free updates for waveform generation. The following examples are written in terms of DAC0,
but DAC1 operation is identical.
8.1.1. Update Output On-Demand
In its default mode (DAC0CN.[4:3] = ‘00’) the DAC0 output is updated “on-demand” on a write to the high-
byte of the DAC0 dat a registe r (DAC0H). It is important to note that writes to DAC0L are held , and have no
effect on the DAC0 output until a write to DAC0H takes place. If writing a full 12-bit word to the DAC data
registers, the 12-bit data word is written to the low byte (DAC0L) and high byte (DAC0H) data registers.
Data is latched into DAC0 after a write to the corresponding DAC0H register, so the write sequence
should be DAC0L followed by DAC0H if the full 12-bit resolution is required. The DAC can be used in 8-
bit mode by initializing DAC0L to the desired value (typically 0x00), and writing data to only DAC0H (also
see Section 8.2 for information on formatting the 12-bit DAC data word within the 16-bit SFR space).
8.1.2. Update Output Based on Timer Overflow
Similar to the ADC operation, in which an ADC conversion can be initiated by a timer overflow indepen-
dently of the processor, the DAC outputs can use a Timer overflow to schedule an output update event.
This feature is useful in systems where the DAC is used to generate a waveform of a defined sampling rate
by eliminating the effects of variable interrupt latency and instruction execution on the timing of the DAC
output. When the DAC0MD bits (DAC0CN.[4:3]) are set to ‘01’, ‘10’, or ‘11’, writes to both DAC data regis-
ters (DAC0L and DAC0H) are held until an associated Timer overflow event (Timer 3, Timer 4, or Timer 2,
respectively) occurs, at which time the DAC0H:DAC0L contents are copie d to the DAC input latches allow-
ing the DAC output to change to the new value.
8.2. DAC Output Scaling/Justification
In some instances, input data should be shifted prior to a DAC0 write operation to properly justify data
within the DAC input registers. This action would typically require one or more load and shift operations,
adding software overhead and slowing DAC throughput. To alleviate this problem, the data-formatting fea-
ture provides a means for the user to program the orientation of the DAC0 data word within data registers
DAC0H and DAC0L. The three DAC0DF bits (DAC0CN.[2:0]) allow the user to specify one of five data
word orientations as shown in the DAC0CN register definition.
DAC1 is functionally the same as DAC0 described above. The electrical specifications for both DAC0 and
DAC1 are given in Table 8.1.
C8051F060/1/2/3/4/5/6/7
Rev. 1.2 105
Figure 8.2. DAC0H: DAC0 High Byte Register
Bits7-0: DAC0 Data Word Most Significant Byte.
R/W R/W R/W R/W R/W R/W R/W R/W Reset Value
00000000
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
SFR Address:
SFR Page: 0xD3
0
Figure 8.3. DAC0L: DAC0 Low Byte Register
Bits7-0: DAC0 Data Word Least Significant Byte.
R/W R/W R/W R/W R/W R/W R/W R/W Reset Value
00000000
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
SFR Address:
SFR Page: 0xD2
0
C8051F060/1/2/3/4/5/6/7
106 Rev. 1.2
Figure 8.4. DAC0CN: DAC0 Control Register
Bit7: DAC0EN: DAC0 Enable Bit.
0: DAC0 Disabled. DAC0 Output pin is disabled; DAC0 is in low-power shutdown mode.
1: DAC0 Enabled. DAC0 Output pin is active; DAC0 is operational.
Bits6-5: UNUSED. Read = 00b; Write = don’t care.
Bits4-3: DAC0MD1-0: DAC0 Mode Bits.
00: DAC output updat es occur on a write to DAC0H.
01: DAC output updates occur on Timer 3 overflow.
10: DAC output updates occur on Timer 4 overflow.
11: DAC output updates occur on Timer 2 overflow.
Bits2-0: DAC0DF2-0: DAC0 Data Format Bits:
000: The most significant nibble of the DAC0 Data Word is in DAC0H[3:0], while the least
significant byte is in DAC0L.
001: The most significant 5-bits of the DAC0 Data Word is in DAC0H[4:0], while the least
significant 7-bits are in DAC0L[7:1].
010: The most significant 6-bits of the DAC0 Data Word is in DAC0H[5:0], while the least
significant 6-bits are in DAC0L[7:2].
011: The most significant 7-bits of the DAC0 Data Word is in DAC0H[6:0], while the least
significant 5-bits are in DAC0L[7:3].
1xx: The most significant 8-bits of the DAC0 Data Word is in DAC0H[7:0], while the least
significant 4-bits are in DAC0L[7:4].
R/W R/W R/W R/W R/W R/W R/W R/W Reset Value
DAC0EN - - DAC0MD1 DAC0MD0 DAC0DF2 DAC0DF1 DAC0DF0 00000000
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
SFR Address:
SFR Page: 0xD4
0
DAC0H DAC0L
MSB LSB
DAC0H DAC0L
MSB LSB
DAC0H DAC0L
MSB LSB
DAC0H DAC0L
MSB LSB
DAC0H DAC0L
MSB LSB
C8051F060/1/2/3/4/5/6/7
Rev. 1.2 107
Figure 8.5. DAC1H: DAC1 High Byte Register
Bits7-0: DAC1 Data Word Most Significant Byte.
R/W R/W R/W R/W R/W R/W R/W R/W Reset Value
00000000
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
SFR Address:
SFR Page: 0xD3
1
Figure 8.6. DAC1L: DAC1 Low Byte Register
Bits7-0: DAC1 Data Word Least Significant Byte.
R/W R/W R/W R/W R/W R/W R/W R/W Reset Value
00000000
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
SFR Address:
SFR Page: 0xD2
1
C8051F060/1/2/3/4/5/6/7
108 Rev. 1.2
Figure 8.7. DAC1CN: DAC1 Control Register
Bit7: DAC1EN: DAC1 Enable Bit.
0: DAC1 Disabled. DAC1 Output pin is disabled; DAC1 is in low-power shutdown mode.
1: DAC1 Enabled. DAC1 Output pin is active; DAC1 is operational.
Bits6-5: UNUSED. Read = 00b; Write = don’t care.
Bits4-3: DAC1MD1-0: DAC1 Mode Bits:
00: DAC output updat es occur on a write to DAC1H.
01: DAC output updates occur on Timer 3 overflow.
10: DAC output updates occur on Timer 4 overflow.
11: DAC output updates occur on Timer 2 overflow.
Bits2-0: DAC1DF2: DAC1 Data Format Bits:
000: The most significant nibble of the DAC1 Data Word is in DAC1H[3:0], while the least
significant byte is in DAC1L.
001: The most significant 5-bits of the DAC1 Data Word is in DAC1H[4:0], while the least
significant 7-bits are in DAC1L[7:1].
010: The most significant 6-bits of the DAC1 Data Word is in DAC1H[5:0], while the least
significant 6-bits are in DAC1L[7:2].
011: The most significant 7-bits of the DAC1 Data Word is in DAC1H[6:0], while the least
significant 5-bits are in DAC1L[7:3].
1xx: The most significant 8-bits of the DAC1 Data Word is in DAC1H[7:0], while the least
significant 4-bits are in DAC1L[7:4].
R/W R/W R/W R/W R/W R/W R/W R/W Reset Value
DAC1EN - - DAC1MD1 DAC1MD0 DAC1DF2 DAC1DF1 DAC1DF0 00000000
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
SFR Address:
SFR Page: 0xD4
1
DAC1H DAC1L
MSB LSB
DAC1H DAC1L
MSB LSB
DAC1H DAC1L
MSB LSB
DAC1H DAC1L
MSB LSB
DAC1H DAC1L
MSB LSB
C8051F060/1/2/3/4/5/6/7
Rev. 1.2 109
.
Table 8.1. DAC Electrical Characteristics
VDD = 3.0 V, AV+ = 3.0 V, VREF = 2.40 V (REFBE = 0), No Output Load unless otherwise specified
Parameter Conditions Min Typ Max Units
Static Performance
Resolution 12 bits
Integral Nonlinearity ±1.5 LSB
Differential Nonlinearity ±1 LSB
Output Noise No Output Filter
100 k Hz Output Filter
10 kHz Output Filter
250
128
41
µVrms
Offset Error Data Word = 0x014 ±3 ±30 mV
Offset Tempco 6 ppm/°C
Full-Scale Error ±20 ±60 mV
Full-Scale Error Te mpco 10 ppm/°C
VDD Power Supply Rejection
Ratio -60 dB
Output Impedance in Shutdown
Mode DACnEN = 0 100 k
Output Sink Curren t 300 µA
Output Short-Circuit Current Data Word = 0xFFF 15 mA
Dynamic Performance
Voltage Output Slew Rate Load = 40pF 0.44 V/µs
Output Settling Time to 1/2 LSB Load = 40pF, Output swing from
code 0xFFF to 0x014 10 µs
Output Voltage Swing 0 VREF-
1LSB V
Startup Time 10 µs
Analog Outputs
Load Regulation IL = 0.01mA to 0.3mA at code
0xFFF 60 ppm
Power Consumption (each DAC)
Power Supply Current (AV+
supplied to DAC) Data Word = 0x7FF 300 500 µA
C8051F060/1/2/3/4/5/6/7
110 Rev. 1.2
C8051F060/1/2/3/4/5/6/7
Rev. 1.2 111
9. Voltage Reference 2 (C8051F060/2)
The voltage reference circuitry offers full flex ibility in operating the ADC2 and DAC modules. Two voltage
reference input pins allow ADC2 and the two DACs to reference an external voltage reference or the on-
chip voltage reference output. ADC2 may also reference the analog power supply voltage, via the VREF
multiplexer shown in Figure 9.1.
The internal voltage reference circuit consists of a 1.2 V, temperature stable bandgap voltage reference
generator and a gain -o f-t wo outp ut buffer amplifier. The internal reference may b e r oute d via the VREF pi n
to external system components or to the voltage reference input pins shown in Figure 9.1. The maximum
load seen by the VREF pin must be less than 200 µA to AGND. Bypass capacitors of 0.1 µF and 4.7 µF
are recommended from the VREF pin to AGND, as shown in Figure 9.1.
The Refere nce Control Register 2, RE F2 CN (defined in Fig ure 9.2) enables/disa bles the in tern al refe rence
generator and selects the reference input for ADC2. The BIASE bit in REF2CN enables the on-board refer-
ence generator while the REFBE bit enables the gain-of-two buffer amplifier which drives the VREF pin.
When disable d, the sup ply current drawn by the ban dgap an d buffer amplifier falls to less than 1 µA (typi-
cal) and the output of the buffer amplifier enters a high impedance state. If the internal bandgap is used as
the reference voltage generator, BIASE and REFBE must both be set to logic 1. If the internal reference is
not used, REFBE may be set to logic 0. Note that the BIASE bit must be set to logic 1 if ADC2 or either
DAC is used, regardless of the voltage r eference used. If n either ADC2 nor the DACs ar e being used, bo th
of these bit s can be set to logic 0 to conserve power. Bit AD2VRS selects between VREF2 and AV+ for the
ADC2 voltage reference source. The electrical specifications for the Voltage Reference are given in
Table 9.1.
Recommended Bypass
Capacitors
x2
VREF
DAC0
DAC1
Ref
VREFD
AV+
ADC2
VREF2
Ref
1
0
4.7
F0.1
F
REF2CN
REFBE
BIASE
TEMPE
AD2VRS
REFBE
BIASE
Bias to
ADC2,
DACs
1.2V
Band-Gap
EN
External
Voltage
Reference
Circuit
R
VDD
+
Figure 9.1. Voltage Reference Functional Block Diagram
C8051F060/1/2/3/4/5/6/7
112 Rev. 1.2
The temperature sensor connects to the highest order input of the ADC2 input multiplexer (see Section
“7. 10-Bit ADC (ADC2, C8051 F060/1/2/3)” on page 87). The TEMPE bit within REF2CN enables and dis-
ables the temperature sensor. While disabled, the temperature sensor defaults to a high impedance state,
and any A/D measurements performed on the sensor while disabled result in meaningless data.
Table 9.1. Voltage Reference Electrical Characteristics
VDD = 3.0 V, AV+ = 3.0 V, -40 to +85 °C unless otherwise specified
Parameter Conditions Min Typ Max Units
Internal Reference (REFBE = 1)
Output Voltage 25 °C ambient 2.36 2.43 2.48 V
VREF Power Supply Current 50 µA
VREF Short-Circuit Current 30 mA
VREF Temperature Coefficient 15 ppm/°C
Load Regulation Load = 0 to 200 µA to AGND 0.5 ppm/µA
VREF Turn-on Time 1 4.7 µF tantalum, 0.1 µF ceramic
bypass 2ms
VREF Turn-on Time 2 0.1 µF ceramic bypass 20 µs
VREF Turn-on Time 3 no bypass cap 10 µs
External Referenc e (REF BE = 0)
Input Voltage Range 1.00 (AV+) -
0.3 V
Input Current 0 1 µA
Figure 9.2. REF2CN: Reference Control Register 2
Bits7-4: UNUSED. Read = 0000b; Write = don’t care.
Bit3: AD2VRS: ADC2 Voltage Reference Select.
0: ADC2 voltage reference from VREF2 pin.
1: ADC2 voltage reference fro m AV+.
Bit2: TEMPE: Temperat ur e Sen so r Enab l e Bit.
0: Internal Temperature Sensor Off.
1: Internal Temperature Sensor On.
Bit1: BIASE: ADC/DAC Bias Generator Enable Bit. (Must be ‘1’ if using ADC2 or DACs).
0: Internal Bias Generator Off.
1: Internal Bias Generator On.
Bit0: REFBE: Internal Reference Buffer Enable Bit.
0: Internal Reference Buffer Off.
1: Internal Reference Buffer On. Internal voltage reference is driven on the VREF pin.
R/W R/W R/W R/W R/W R/W R/W R/W Reset Value
- - - - AD2VRS TEMPE BIASE REFBE 00000000
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
SFR Address:
SFR Page: 0xD1
2
C8051F060/1/2/3/4/5/6/7
Rev. 1.2 113
10. Voltage Reference 2 (C8051F061/3)
The internal voltage reference circuit consists of a 1.2 V, temperature stable bandgap voltage reference
generator and a gain -o f-t wo outp ut buffer amplifier. The internal reference may b e r oute d via the VREF pi n
to external system components or to the VREF2 input pin shown in Figure 10.1. The maximum load seen
by the VREF pin must be less than 200 µA to AGND. Bypass capacitors of 0.1 µF and 4.7 µF are recom-
mended from the VREF pin to AGND, as shown in Figure 10.1.
The VREF2 pin provides a voltage reference input for ADC2 and the DACs. ADC2 may also reference the
analog power supply voltage, via the VREF multiplexers shown in Figure 10.1.
The Reference Control Register 2, REF2CN (defined in Figure 10.2) enables/disables the internal refer-
ence generator and sele cts the refere nce inp ut for ADC2. The BIASE bit in REF2CN enables the on-board
reference generator while the REFBE bit enables the gain-of-two buffer amplifier which drives the VREF
pin. When disabled, the supply current drawn by the bandgap and buffer amplifier falls to less than 1 µA
(typical) and the output of the buffer amplifier enters a high impedance state. If the internal bandgap is
used as the reference voltage generator, BIASE and REFBE must both be set to logic 1. If the internal ref-
erence is not used, REFBE may be set to logic 0. Note that the BIASE bit must be set to logic 1 if ADC2 or
either DAC is used, regardless of the voltage reference used. If neither ADC2 nor the DACs are being
used, both of these bits can be set to logic 0 to conserve power. Bit AD2VRS selects between VREF2 and
AV+ for the ADC2 voltage reference source. The electrical specifications for the Voltage Reference are
given in Table 10.1.
Recommended Bypass
Capacitors
x2
VREF
DAC0
DAC1
Ref
AV+
ADC2
Ref
1
0
VREF2
4.7
F0.1
F
REF2CN
REFBE
BIASE
TEMPE
AD2VRS
REFBE
BIASE
Bias to
ADC2,
DACs
1.2V
Band-Gap
EN
External
Voltage
Reference
Circuit
R
VDD
+
Figure 10.1. Voltage Reference Functional Block Diagram
C8051F060/1/2/3/4/5/6/7
114 Rev. 1.2
The temperature sensor connects to the highest order input of the ADC2 input multiplexer (see Section
“7. 10-Bit ADC (ADC2, C8051 F060/1/2/3)” on page 87). The TEMPE bit within REF2CN enables and dis-
ables the temperature sensor. While disabled, the temperature sensor defaults to a high impedance state,
and any A/D measurements performed on the sensor while disabled result in meaningless data.
Table 10.1. Voltage Reference Electrical Characteristics
VDD = 3.0 V, AV+ = 3.0 V, -40 to +85 °C unless otherwise specified
Parameter Conditions Min Typ Max Units
Internal Reference (REFBE = 1)
Output Voltage 25 °C ambient 2.36 2.43 2.48 V
VREF Power Supply Current 50 µA
VREF Short-Circuit Current 30 mA
VREF Temperature Coefficient 15 ppm/°C
Load Regulation Load = 0 to 200 µA to AGND 0.5 ppm/µA
VREF Turn-on Time 1 4.7 µF tantalum, 0.1 µF ceramic
bypass 2ms
VREF Turn-on Time 2 0.1 µF ceramic bypass 20 µs
VREF Turn-on Time 3 no bypass cap 10 µs
External Referenc e (REF BE = 0)
Input Voltage Range 1.00 (AV+) -
0.3 V
Input Current 0 1 µA
Figure 10.2. REF2CN: Reference Control Register 2
Bits7-4: UNUSED. Read = 0000b; Write = don’t care.
Bit3: AD2VRS: ADC2 Voltage Reference Select.
0: ADC2 voltage reference from VREF2 pin.
1: ADC2 voltage reference fro m AV+.
Bit2: TEMPE: Temperat ur e Sen so r Enab l e Bit.
0: Internal Temperature Sensor Off.
1: Internal Temperature Sensor On.
Bit1: BIASE: ADC/DAC Bias Generator Enable Bit. (Must be ‘1’ if using ADC2 or DACs).
0: Internal Bias Generator Off.
1: Internal Bias Generator On.
Bit0: REFBE: Internal Reference Buffer Enable Bit.
0: Internal Reference Buffer Off.
1: Internal Reference Buffer On. Internal voltage reference is driven on the VREF pin.
R/W R/W R/W R/W R/W R/W R/W R/W Reset Value
- - - - AD2VRS TEMPE BIASE REFBE 00000000
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
SFR Address:
SFR Page: 0xD1
2
C8051F060/1/2/3/4/5/6/7
Rev. 1.2 115
11. Voltage Reference 2 (C8051F064/5/6/7)
The internal voltage reference circuit consists of a 1.2 V, temperature stable bandgap voltage reference
generator and a gain-of-two output buffer amplifier. The internal reference may be routed to the VREF pin
as shown in Figure 11.1. The maximum load seen by the VREF pin must be less than 200 µA to AGND.
Bypass capacitors of 0.1 µF and 4.7 µF are recommended from the VREF pin to AGND, as shown in
Figure 11.1.
The Reference Control Register 2, REF2CN (defined in Figure 11.2) enables/disables the internal refer-
ence generator. The BIASE bit in REF2CN enables the on-board reference generator while the REFBE bit
enables the gain-of-two buffer amplifier which drives the VREF pin. When disabled, the supply current
drawn by the bandgap and buffer amplifier falls to less than 1 µA (typical) and the output of the buffer
amplifier enters a high imped ance st ate. If the in ternal band gap is used as the reference vo lt age generato r,
BIASE and REFBE must both be set to logic 1. If the internal referenc e is not used , REF BE may b e se t to
logic 0. The electrical specifications for the Voltage Reference are given in Table 11.1.
Recommended Bypass
Capacitors
x2
VREF
4.7F0.1F
REFBE
BIASE
1.2V
Band-Gap
EN
+
External
Circuitry
Figure 11.1. Voltage Reference Functional Block Diagram
C8051F060/1/2/3/4/5/6/7
116 Rev. 1.2
Table 11.1. Voltage Reference Electrical Characteristics
VDD = 3.0 V, AV+ = 3.0 V, -40 to +85 °C unless otherwise specified
Parameter Conditions Min Typ Max Units
Internal Reference (REFBE = 1)
Output Voltage 25 °C ambient 2.36 2.43 2.48 V
VREF Power Supply Current 50 µA
VREF Short-Circuit Current 30 mA
VREF Temperature Coefficient 15 ppm/°C
Load Regulation Load = 0 to 200 µA to AGND 0.5 ppm/µA
VREF Turn-on Time 1 4.7 µF tantalum, 0.1 µF ceramic
bypass 2ms
VREF Turn-on Time 2 0.1 µF ceramic bypass 20 µs
VREF Turn-on Time 3 no bypass cap 10 µs
Figure 11.2. REF2CN: Re fe re nce Control Register 2
Bits7-4: UNUSED. Read = 0000b; Write = don’t care.
Bits2-3: RESERVED. Must Write to 00b.
Bit1: BIASE: ADC/DAC Bias Generator Enable Bit. (Must be ‘1’ if using ADC2 or DACs).
0: Internal Bias Generator Off.
1: Internal Bias Generator On.
Bit0: REFBE: Internal Reference Buffer Enable Bit.
0: Internal Reference Buffer Off.
1: Internal Reference Buffer On. Internal voltage reference is driven on the VREF pin.
R/W R/W R/W R/W R/W R/W R/W R/W Reset Value
- - - - 0 0 BIASE REFBE 00000000
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
SFR Address:
SFR Page: 0xD1
2
C8051F060/1/2/3/4/5/6/7
Rev. 1.2 117
12. Comparators
C8051F06x family of devices include three on-chip programmable voltage comparators, shown in
Figure 12.1. Each comparator offers programmable response time and hysteresis. When assigned to a
Port pin, the Comparator output may be configured as open drain or push-pull, and Comparator inputs
should be configured as analog inputs (see Section “18.1.5. Configuring Port 1 and 2 pins as Analog
Inputs” on page 207). The Comparator may also be used as a reset source (see Section
“14.5. Comparator0 Reset” on page 165).
The output of a Comparator can be polled by software, used as an interrupt source, used as a reset
source, and/or routed to a Port pin. Each comp ar ator can be individually enabl ed and disabl ed (shutdown).
When disabled, the Comparator output (if assigned to a Port I/O pin via the Crossbar) defaults to the logic
low state, and its supply current falls to less than 1 µA. See Section “18.1.1. Crossbar Pin Assignment and
Allocation” on page 205 for details on configuring the Comparator output via the digital Crossbar. The
Figure 12.1. Comparator Functiona l Block Diagram
VDD
CPTnCN
Reset
Decision
Tree
+
-
Crossbar
Interrupt
Logic
Q
Q
SET
CLR
D
Q
Q
SET
CLR
D
(SYNCHRONIZER)
CPn +
CPn -
CPnEN
CPnOUT
CPnRIF
CPnFIF
CPnHYP1
CPnHYP0
CPnHYN1
CPnHYN0
CPTnMD
CPnRIE
CPnFIE
CPnMD1
CPnMD0
CPn
Rising-edge
Interrupt Flag
CPn
Falling-edge
Interrupt Flag
CPn
CP0 +
CP0 -
CP1 +
CP1 -
CP2 +
CP2 -
P2.6
P2.7
P2.2
P2.3
P2.4
P2.5
Comparator Pin Assignments
GND
CPn
Interrupt
C8051F060/1/2/3/4/5/6/7
118 Rev. 1.2
Comparator inputs can be externally driven from -0.25 V to (VDD) + 0.25 V without damage or upset. The
complete electrical specifications for the Comparator are given in Table 12.1.
The Comparator response time may be configured in software using the CPnMD1-0 bits in register CPT-
nMD (see Figu re 12.4). Se lecting a longer respo nse time reduces the am ount of power consu med by the
comparator. See Table 12.1 for complete timing and current consumption specifications.
The hysteresis of the Comparator is software-programmable via its Comparator Control register (CPT-
nCN). The user can progr am both the am oun t of hystere sis voltage (referre d to the input voltage) and the
positive and negative-going symmetry of this hysteresis around the threshold voltage.
The Comparator hysteresis is programmed using Bits3-0 in the Comparator Control Register CPTnCN
(shown in Figure 12.3). The amount of negative hysteresis voltage is determined by the settings of the
CPnHYN bits. As shown in Figure 12.2, the negative hysteresis can be pro gramm ed t o thr ee di fferent set-
tings, or negative hysteresis can be disabled. In a similar way, the amount of positive hysteresis is deter-
mined by the settin g the CPn HYP bits.
Posit iv e Hyst e re sis V olt age
(Programmed with CPnHYP Bits)
Negative Hyste r esi s Voltage
(Programmed by CPnHYN Bits)
VIN-
VIN+
INPUTS
CIRCUI T CONFIGURATION
+
_
CPn+
CPn- CPn
VIN+
VIN- OUT
V
OH
Posit iv e Hyst e re sis
Disabled Maximum
Positive Hysteresis
Negative Hysteresis
Disabled Maximum
Negative Hysteresis
OUTPUT
V
OL
Figure 12.2. Comparator Hysteresis Plot
C8051F060/1/2/3/4/5/6/7
Rev. 1.2 119
Comparator interrupts can be generated on either rising-edge and falling-edge output transitions. (For
Interrupt enable and priority control, see Section “13.3. Interrupt Handler” on page 151). The rising and/or
falling -edge interrupts ar e enabled using the comparator’s Rising/Falling Edge Interrupt Enable Bits (CPn-
RIE and CPnFIE) in their respective Comparator Mode Selection Register (CPTnMD), shown in
Figure 12.4. These bits allow the user to control which edge (or both) will cause a comparator interrupt.
However, the comparator interrupt must also be enabled in the Extended Interrupt Enable Register (EIE1).
The CPnFIF flag is set to logic 1 upon a Comparator falling-edge interrupt, and the CPnRIF flag is set to
logic 1 upon the Comparator rising-edge interrupt. Once set, these bits remain set until cleared by soft-
ware. The output state of a Comparator can be obtained at any time by reading the CPnOUT bit. A Com-
parator is enabled by setting its respective CPnEN bit to logic 1, and is disabled by clearing this bit to logic
0.Upon enabling a comparator, the output of the comparator is not immediately valid. Before using a com-
parator as an interrupt or reset source, software should wait for a minimum of the specified “Power-up
time” as specified in Table 12.1, “Comparator Electrical Characteristics,” on page 122.
12.1. Comparator Inputs
The Port pins selected as comp arator inputs should be configured a s analog input s in the Por t 2 Input Con-
figuration Register (for details on Port configuration, see Section “18.1.3. Configuring Port Pins as Digital
Inputs” on page 207). The inputs for Comparator are on Port 2 as follows:
Comparator Input Port PIN
CP0 + P2.6
CP0 - P2.7
CP1 + P2.2
CP1 - P2.3
CP2 + P2.4
CP2 - P2.5
C8051F060/1/2/3/4/5/6/7
120 Rev. 1.2
Figure 12.3. CPTnCN: Comparator 0, 1, and 2 Cont rol Register
Bit7: CPnEN: Comparator Enable Bit. (Please see note below.)
0: Comparator Disabled.
1: Comparator Enabled.
Bit6: CPnOUT: Comparator Output State Flag.
0: Voltage on CPn+ < CPn-.
1: Voltage on CPn+ > CPn-.
Bit5: CPnRIF: Comparator Rising-Edge Interrupt Flag.
0: No Comparator Rising Edge Interrupt has occurred since this flag was last cleared.
1: Comparator Rising Edge Interrupt has occurred . Must be cleared by software.
Bit4: CPnFIF: Comparator Falling-Edge Interrupt Flag.
0: No Comparator Falling-Edge Interrupt has occurred since this flag was last cleared.
1: Comparator Falling-Edge Interrupt has occurred. Must be cleared by software.
Bits3-2: CPnHYP1-0: Comparator Positive Hysteresis Control Bits.
00: Positive Hysteresis Disabled.
01: Positive Hysteresis = 5 mV.
10: Positive Hysteresis = 10 mV.
11: Positive Hysteresis = 20 mV.
Bits1-0: CPnHYN1-0: Comparator Negative Hysteresis Control Bits.
00: Negative Hysteresis Disabled.
01: Negative Hysteresis = 5 mV.
10: Negative Hysteresis = 10 mV.
11: Negative Hysteresis = 20 mV.
NOTE: Upon enabling a comparator, the output of the comparator is not immediately valid. Before
using a comparator as an interrupt or reset source, software should wait for a minimum of
the specified “Power-u p time” as specified in Table 12.1, “Comparator Electr ical Characteris-
tics,” on page 122.
R/W R/W R/W R/W R/W R/W R/W R/W Reset Value
CPnEN CPnOUT CPnRIF CPnFIF CPnHYP1 CPnHYP0 CPnHYN1 CPnHYN0 00000000
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Bit
Addressable
SFR Address: CPT0CN: 0x88; CPT1CN: 0x88; CPT2CN: 0x88
SFR Pages: CPT0CN: page 1; CPT1CN: page 2; CPT2CN: page 3
C8051F060/1/2/3/4/5/6/7
Rev. 1.2 121
Figure 12.4. CPTnMD: Comparator Mode Selection Register
Bits7-6: UNUSED. Read = 00b, Write = don’t care.
Bit 5: CPnRIE: Comparator Rising-Edge Interrupt Enable Bit.
0: Comparator rising-edge interrupt disabled.
1: Comparator rising-edge interrupt enabled.
Bit 4: CPnFIE: Comparator Falling-Edge Interrupt Enable Bit.
0: Comparator falling-edge interrupt disabled.
1: Comparator falling-edge interrupt enabled.
Bits3-2: UNUSED. Read = 00b, Write = don’t care.
Bits1-0: CPnMD1-CPnMD0: Comparator Mode Select
These bits select the response time for the Comparator.
R/W R/W R/W R/W R R R/W R/W Reset Value
- - CPnRIE CPnFIE - - CPnMD1 CPnMD0 00000010
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
SFR Address: CPT0MD: 0x89; CPT1MD: 0x89; CPT2MD: 0x89
SFR Page: CPT0MD: page 1; CPT1MD: page 2; CPT2MD: page 3
Mode CPnMD1 CPnMD0 Notes
0 0 0 Fastest Response Time
101 -
210 -
311
Lowest Power Consump-
tion
C8051F060/1/2/3/4/5/6/7
122 Rev. 1.2
Table 12.1. Comparator Electrical Characteristics
VDD = 3.0 V, -40 to +85 °C unless otherwise specified.
Parameter Conditions Min Typ Max Units
Response Time,
Mode 0 CPn+ - CPn- = 100 mV 100 ns
CPn+ - CPn- = 10 mV 250 ns
Response Time,
Mode 1 CPn+ - CPn- = 100 mV 175 ns
CPn+ - CPn- = 10 mV 500 ns
Response Time,
Mode 2 CPn+ - CPn- = 100 mV 320 ns
CPn+ - CPn- = 10 mV 1100 ns
Response Time,
Mode 3 CPn+ - CPn- = 100 mV 1050 ns
CPn+ - CPn- = 10 mV 5200 ns
Common-Mode Rejection
Ratio 1.5 4 mV/V
Positive Hysteresis 1 CPnHYP1-0 = 00 0 1 mV
Positive Hysteresis 2 CPnHYP1-0 = 01 3 5 7 mV
Positive Hysteresis 3 CPnHYP1-0 = 10 7 10 15 mV
Positive Hysteresis 4 CPnHYP1-0 = 11 15 20 25 mV
Negative Hysteresis 1 CP nHY N1-0 = 00 0 1 mV
Negative Hysteresis 2 CP nHY N1-0 = 01 3 5 7 mV
Negative Hysteresis 3 CPnHYN1-0 = 10 7 10 15 mV
Negative Hysteresis 4 CPnHYN1-0 = 11 15 20 25 mV
Inverting or Non-Inverting
Input Voltage Range -0.25 VDD +
0.25 V
Input Capacitance 7 pF
Input Bias Current -5 0.001 +5 nA
Input Offset Voltage -5 +5 mV
Power Supply
Power Supply Rejection 0.1 1 m V/V
Power-up Time 10 µs
Supply Current at DC
Mode 0 7.6 µA
Mode 1 3.2 µA
Mode 2 1.3 µA
Mode 3 0.4 µA
C8051F060/1/2/3/4/5/6/7
Rev. 1.2 123
13. CIP-51 Microcontroller
The MCU system controller core is the CIP-51 microcontroller. The CIP-51 is fully compatible with the
MCS-51™ instruction set; standard 803x/805x assemblers and compilers can be used to develop soft-
ware. The MCU family has a superset of all the peripherals included with a standard 8051. Included are
five 16-bit counter/timers (see de scription in Sectio n 24), two full-duplex UARTs (see description in Section
22 and Section 23), 256 bytes of internal RAM, 128 byte Special Function Register (SFR) address space
(see Section 13.2.6), and 59/2 4 General-Pur pose I/O Pins (see description in Se ction 18). The CIP- 51 also
includes on-chip debug hardware (see description in Section 26), and interfaces directly with the MCU’s
analog and d igital subsystems pro viding a com plete data acquisition or control-system solution in a single
integrated circuit.
- Fully Compatible with MCS-51 Instruction Set
- 25 MIPS Peak Throughput with 25 MHz Clock
- 0 to 25 MHz Clock Frequency
- 256 Bytes of Internal RAM
- 59/24 General-Purpose I/O Pins
- Extended Interrupt Handler
- Reset Input
- Power Management Modes
- On-chip Debug Logic
- Program and Data Memory Security
C8051F060/1/2/3/4/5/6/7
124 Rev. 1.2
The CIP-51 Microcontroller core implements the standard 8051 organization and peripherals as well as
additional custom peripherals and functions to extend its capability (see Figure 13.1 for a block diagram).
The CIP-51 includes the following features:
Performance
The CIP-51 employ s a p ipelined architectu re that grea tly increases it s instr uction throughpu t over the st an-
dard 8051 architecture. In a standard 8051, all instructions except for MUL and DIV take 12 or 24 system
clock cycles to execute, and usually have a maximum system clock of 12 MHz. By contrast, the CIP-51
core executes 70% of its instructions in one or two system clock cycles, with no instructions taking more
than eight system clock cycles.
With the CIP-51's maximum system clock at 25 MHz, it has a peak throughput of 25 MIPS. The CIP-51 has
a total of 109 instructions. The table below shows the total number of instructions that require each execu-
tion time.
Clocks to Execute 1 22/333/444/55 8
Number of Instructions 26505147 3 1 2 1
Figure 13.1. CIP-51 Block Diagram
DATA BUS
TMP1 TMP2
PRGM. ADDRESS REG.
PC INCREMENTER
ALU
PSW
DATA BUS
DATA B US
MEMORY
INTERFACE
MEM_ADDRESS
D8
PIPELINE
BUFFER
DATA POINTER
INTERRUPT
INTERFACE
SYSTEM_IRQs
DEBUG_IRQ
MEM_CONTROL
CONTROL
LOGIC
A16
PROGRAM COUNTER (PC)
STOP
CLOCK
RESET
IDLE POWER CONTROL
REGISTER
DATA BUS
SFR
BUS
INTERFACE
SFR_ADDRESS
SFR_CONTROL
SFR_WRITE_DATA
SFR_READ_DATA
D8
D8
B REGISTER
D8
D8
ACCUMULATOR
D8
D8
D8
D8
D8
D8
D8
D8
MEM_WRITE_DATA
MEM_READ_DATA
D8
SRAM
ADDRESS
REGISTER
SRAM
(256 X 8)
D8
STACK POINTER
D8
C8051F060/1/2/3/4/5/6/7
Rev. 1.2 125
Programming and Debugging Support
A JTAG-based serial interface is provided for in-system programming of the Flash program memory and
communication with on-chip debug support logic. The re-programmable Flash can also be read and
changed a single byte at a time by the application software using the MOVC and MOVX instructions. This
feature allows program memory to be used for non-volatile data storage as well as updating program code
under software control.
The on-chip debug support logic facilitates full speed in-circuit debugging, allowing the setting of hardware
breakpoints and watch points, starting, stopping and single stepping through program execution (including
interrupt service routin es), e xaminatio n of th e progr am' s ca ll stack, and reading/writing the conten t s of reg-
isters and memory. This method of on-chip debug is completely non-intrusive and non-invasive, requiring
no RAM, Stack, timers, or other on-chip resources.
The CIP-51 is supported by development tools from Silicon Labs and third party vendors. Silicon Labs pro-
vides an integrated developme nt environment (IDE) which interfaces to the CIP- 51 via its JTAG port to pro-
vide fast and efficient in-system device prog ramming and debugging. Third party macro assemblers and C
compilers are als o ava ila ble.
13.1. Instruction Set
The instruction set of the CIP-51 System Controller is fully compatible with the st and ard MCS-51 ™ inst ruc-
tion set; standard 8051 development tools can be used to develop software for the CIP-51. All CIP-51
instructions are the binary and functional equivalent of their MCS-51™ counterparts, including opcodes,
addressing modes and effect on PSW flags. However, instruction timing is different than that of the stan-
dard 8051.
13.1.1. Instruction and CPU Timing
In many 8051 implementations, a distinction is made between machine cycles and clock cycles, with
machine cycles varying from 2 to 12 clock cycles in length. However, the CIP-51 implementation is based
solely on clock cycle timing. All instruction timings are specified in terms of clock cycles.
Due to the pipelined architecture of the CIP-51, most instructions execute in the same number of clock
cycles as there are program bytes in the instruction. Conditional branch instructions take one less clock
cycle to complete when the branch is not taken as opposed to when the branch is taken. Table 13.1 is the
CIP-51 Instruction Set Summary, which includes the mnemonic, number of bytes, and number of clock
cycles for each instruction.
13.1.2. MOVX Instruction and Program Memory
In the CIP-51, the M OVX instruction serves th ree purposes: accessing on-chip XRAM, accessing off-chip
XRAM, and writing to on-chip program Flash memory. The Flash access feature provides a mechanism for
user software to update program code and use the program memory space for non-volatile data storage
(see Section “16. Flash Memory” on page 177). The External Memory Interface provides a fast access to
off-chip XRAM (or memory-mapped peripherals) via the MOVX instruction. Refer to Section “17. External
Data Memory Interface and On-Chip XRAM” on page 187 for details.
C8051F060/1/2/3/4/5/6/7
126 Rev. 1.2
Table 13.1. CIP-51 Instruction Set Summary
Mnemonic Description Bytes Clock
Cycles
Arithmetic Operations
ADD A, Rn Add register to A 1 1
ADD A, direct Add direct byte to A 2 2
ADD A, @Ri Add indirect RAM to A 1 2
ADD A, #data Add immediate to A 2 2
ADDC A, Rn Add register to A with carry 1 1
ADDC A, direct Add direct byte to A with carry 2 2
ADDC A, @Ri Add indirect RAM to A with carry 1 2
ADDC A, #data Add immediate to A with carry 2 2
SUBB A, Rn Subtract register from A with bo rr ow 1 1
SUBB A, direct Subtract direct byte from A with borrow 2 2
SUBB A, @Ri S ubtract indirect RAM fro m A with bo rr ow 1 2
SUBB A, #data Subtract immediate from A with borrow 2 2
INC A Increment A 1 1
INC Rn Increment register 1 1
INC direct Increment direct byte 2 2
INC @Ri Increment indirect RAM 1 2
DEC A Decrement A 1 1
DEC Rn Decrement register 1 1
DEC direct Decrement direct byte 2 2
DEC @Ri Decrement indirect RAM 1 2
INC DPTR Increment Data Pointer 1 1
MUL AB Multiply A and B 1 4
DIV AB Divide A by B 1 8
DA A Decimal adjust A 1 1
Logical Operations
ANL A, Rn AND Register to A 1 1
ANL A, direct AND direct byte to A 2 2
ANL A, @Ri AND indirect RAM to A 1 2
ANL A, #data AND immediate to A 2 2
ANL direct, A AND A to direct byte 2 2
ANL direct, #data AND immediate to direct byte 3 3
ORL A, Rn OR Register to A 1 1
ORL A, direct OR direct byte to A 2 2
ORL A, @Ri OR indirect RAM to A 1 2
ORL A, #data OR immediate to A 2 2
ORL direct, A OR A to direct byte 2 2
ORL direct, #data OR immediat e to dire ct byt e 3 3
XRL A, Rn Exclusive-OR Register to A 1 1
XRL A, direct Exclusive-OR direct byte to A 2 2
XRL A, @Ri Exclusive-OR indirect RAM to A 1 2
XRL A, #data Exclusive-OR immediate to A 2 2
XRL direct, A Exclusive-OR A to direct byte 2 2
C8051F060/1/2/3/4/5/6/7
Rev. 1.2 127
XRL direct, #data Exclusive-OR immediate to direct byte 3 3
CLR A Clear A 1 1
CPL A Complement A 1 1
RL A Rotate A left 1 1
RLC A Rotate A left through Carry 1 1
RR A Rotate A right 1 1
RRC A Rotate A right through Carry 1 1
SWAP A Swap nibbles of A 1 1
Data Transfer
MOV A, Rn Move Register to A 1 1
MOV A, direct Move direct byte to A 2 2
MOV A, @Ri Move indirect RAM to A 1 2
MOV A, #data Move immediate to A 2 2
MOV Rn, A Move A to Register 1 1
MOV Rn, direct Move direct byte to Register 2 2
MOV Rn, #data Move immediate to Register 2 2
MOV direct, A Move A to direct byte 2 2
MOV direct, Rn Move Register to direct byte 2 2
MOV direct, direct Move direct byte to direct byte 3 3
MOV direct, @Ri Move indirect RAM to direct byte 2 2
MOV direct, #data Move immediate to direct byte 3 3
MOV @Ri, A Move A to indirect RAM 1 2
MOV @Ri, direct Move direct byte to indirect RAM 2 2
MOV @Ri, #data Move immediate to indirect RAM 2 2
MOV DPTR, #data16 Load DPTR with 16-bit constant 3 3
MOVC A, @A+DPTR Move code byte relative DPTR to A 1 3
MOVC A, @A+PC Move code byte relative PC to A 1 3
MOVX A, @Ri Move external data (8-bit address) to A 1 3
MOVX @Ri, A Move A to external data (8-bit address) 1 3
MOVX A, @DPTR Move external data (16-bit address) to A 1 3
MOVX @DPTR, A Move A to external data (16-bit address) 1 3
PUSH direct Push direct byte onto stack 2 2
POP direct Pop direct byte from stack 2 2
XCH A, Rn Exchange Register with A 1 1
XCH A, direct Exchange direct byte with A 2 2
XCH A, @Ri Exchange indirect RAM with A 1 2
XCHD A, @Ri Exchange low nibble of indirect RAM with A 1 2
Boolean Manipulation
CLR C Clear Carry 1 1
CLR bit Clear direct bit 2 2
SETB C Set Carry 1 1
SETB bit Set direct bit 2 2
CPL C Complement Carry 1 1
CPL bit Complement direct bit 2 2
ANL C, bit AND direct bit to Carry 2 2
Table 13.1. CIP-51 Instruc tion Set Summary (Continued)
Mnemonic Description Bytes Clock
Cycles
C8051F060/1/2/3/4/5/6/7
128 Rev. 1.2
ANL C, /bit AND complement of direct bit to Carry 2 2
ORL C, bit OR direct bit to carry 2 2
ORL C, /bit OR complement of direct bit to Carry 2 2
MOV C, bit Move direct bit to Carry 2 2
MOV bit, C Move Carry to direct bit 2 2
JC rel Jump if Carry is set 2 2/3
JNC rel Jump if Carry is not set 2 2/3
JB bit, rel Jump if direct bit is set 3 3/4
JNB bit, rel Jump if direct bit is not set 3 3/4
JBC bit, rel Jump if direct bit is set and clear bit 3 3/4
Program Branch in g
ACALL addr11 Absolute subroutine call 2 3
LCALL addr16 Long subroutine call 3 4
RET Return from subroutine 1 5
RETI Return from interrupt 1 5
AJMP addr11 Absolute jump 2 3
LJMP addr16 Long jump 3 4
SJMP rel Short jump (relative address) 2 3
JMP @A+DPTR Jump indirect relative to DPTR 1 3
JZ rel Jump if A equals zero 2 2/3
JNZ rel Jump if A does not equal zero 2 2/3
CJNE A, direct, rel Compare direct byte to A and jump if not equal 3 3/4
CJNE A, #data, rel Compare immediate to A and jump if not equal 3 3/4
CJNE Rn, #data, rel Compare immediate to Register and jump if not
equal 33/4
CJNE @Ri, #data, rel Compare immediate to indirect and jump if not
equal 34/5
DJNZ Rn, rel Decrement Register and jump if not zero 2 2/3
DJNZ direct, rel Dec r eme nt dir ec t byte and jump if not zero 3 3/4
NOP No operation 1 1
Table 13.1. CIP-51 Instruc tion Set Summary (Continued)
Mnemonic Description Bytes Clock
Cycles
C8051F060/1/2/3/4/5/6/7
Rev. 1.2 129
Notes on Registers, Operands and Addressing Modes:
Rn - Register R0-R7 of the currently selected register bank.
@Ri - Data RAM location addre ssed indirectly through R0 or R1.
rel - 8-bit, signed (two’s complement) offset relative to the first byte of the following instruction. Used by
SJMP and all conditional jumps.
direct - 8-bit internal data location’s address. This could be a direct-access Data RAM location (0x00-
0x7F) or an SFR (0x80-0xFF).
#data - 8-bit constant
#data16 - 16-bit constant
bit - Direct-accessed bit in Data RAM or SFR
addr11 - 11-bit destination address used by ACALL and AJMP. The destination must be within the same
2K-byte page of program memory as the first byte of the following instruction.
addr16 - 16-bit destination address used by L CALL and LJMP. The destination may be anywhere within
the 64K-byte pr og ra m mem o ry space.
There is one unused opcode (0xA5) that performs the same function as NOP.
All mnemonics copyrighted © Intel Corporation 1980.
