TLC32040C, TLC32040I, TLC32041C, TLC32041I ANALOG INTERFACE CIRCUITS SLAS014E - SEPTEMBER 1987 - REVISED MAY 1995 D D D D D D D N PACKAGE (TOP VIEW) 14-Bit Dynamic Range ADC and DAC Variable ADC and DAC Sampling Rate Up to 19,200 Samples per Second Switched-Capacitor Antialiasing Input Filter and Output-Reconstruction Filter Serial Port for Direct Interface to TMS32011, TMS320C17, TMS32020, and TMS320C25 Digital Signal Process Synchronous or Asynchronous ADC and DAC Conversion Rate With Programmable Incremental ADC and DAC Conversion Timing Adjustments Serial Port Interface to SN74299 Serial-to-Parallel Shift Register for Parallel Interface to TMS32010, TMS320C15, or Other Digital Processors 600-Mil Wide N Package (CL to CL) 2s Complement Format CMOS Technology PART NUMBER DESCRIPTION TLC32040 Analog interface circuit with internal reference. Also a plug-in replacement for TLC32041. TLC32041 NU RESET EODR FSR DR MSTR CLK VDD REF DGTL GND SHIFT CLK EODX DX WORD/BYTE FSX 1 28 2 27 3 26 4 25 5 24 6 23 7 22 8 21 9 20 10 19 11 18 12 17 13 16 14 15 NU NU IN + IN - AUX IN + AUX IN - OUT + OUT - VCC + VCC - ANLG GND ANLG GND NU NU FN PACKAGE (TOP VIEW) FSR EODR RESET NU NU NU IN + D D DR MSTR CLK VDD REF DGTL GND SHIFT CLK EODX Analog interface circuit without internal reference description 3 2 1 28 27 26 25 6 24 7 23 8 22 9 21 10 20 11 19 12 13 14 15 16 17 18 IN - AUX IN + AUX IN - OUT + OUT - VCC + VCC - DX WORD/BYTE FSX NU NU ANLG GND ANLG GND The TLC32040 and TLC32041 are complete analog-to-digital and digital-to-analog input/ output systems, each on a single monolithic CMOS chip. This device integrates a bandpass switched-capacitor antialiasing input filter, a 14-bit-resolution A/D converter, four microprocessor-compatible serial port modes, a 14-bit-resolution D/A converter, and a low-pass switched-capacitor output-reconstruction filter. 4 5 NU - Nonusable; no external connection should be made to these terminals. AVAILABLE OPTIONS PACKAGE TA 0C to 70C PLASTIC CHIP CARRIER (FN) PLASTIC DIP (N) TLC32040CFN TLC32041CFN TLC32040CN TLC32041CN - 40C to 85C TLC32040IN TLC32041IN Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 1995, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 1 TLC32040C, TLC32040I, TLC32041C, TLC32041I ANALOG INTERFACE CIRCUITS SLAS014E - SEPTEMBER 1987 - REVISED MAY 1995 description (continued) The device offers numerous combinations of master clock input frequencies and conversion/sampling rates, which can be changed via digital processor control. Typical applications for this integrated circuit include modems (7.2-, 8-, 9.6-, 14.4-, and 19.2-kHz sampling rate), analog interface for digital signal processors (DSPs), speech recognition/storage systems, industrial process control, biomedical instrumentation, acoustical signal processing, spectral analysis, data acquisition, and instrumentation recorders. Four serial modes, which allow direct interface to the TMS32011, TMS320C17, TMS32020, and TMS320C25 digital signal processors, are provided. Also, when the transmit and receive sections of the analog interface circuit (AIC) are operating synchronously, it can interface to two SN74299 serial-to-parallel shift registers. These serial-to-parallel shift registers can then interface in parallel to the TMS32010, TMS320C15, other digital signal processors, or external FIFO circuitry. Output data pulses are emitted to inform the processor that data transmission is complete or to allow the DSP to differentiate between two transmitted bytes. A flexible control scheme is provided so that the functions of this integrated circuit can be selected and adjusted coincidentally with signal processing via software control. The antialiasing input filter comprises seventh-order and fourth-order CC-type (Chebyshev/elliptic transitional) low-pass and high-pass filters, respectively and a fourth-order equalizer. The input filter is implemented in switched-capacitor technology and is preceded by a continuous time filter to eliminate any possibility of aliasing caused by sampled data filtering. When no filtering is desired, the entire composite filter can be switched out of the signal path. A selectable, auxiliary, differential analog input is provided for applications where more than one analog input is required. The A/D and D/A converters each have 14 bits of resolution. The A/D and D/A architectures ensure no missing codes and monotonic operation. An internal voltage reference is provided on the TLC32040 to ease the design task and to provide complete control over the performance of this integrated circuit. The internal voltage reference is brought out to a terminal and is available to the designer. Separate analog and digital voltage supplies and grounds are provided to minimize noise and ensure a wide dynamic range. Also, the analog circuit path contains only differential circuitry to keep noise to an absolute minimum. The only exception is the DAC sample and hold, which utilizes pseudo-differential circuitry. The output-reconstruction filter is a seventh-order CC-type (Chebyshev/elliptic transitional low-pass filter followed by a fourth-order equalizer) and is implemented in switched-capacitor technology. This filter is followed by a continuous-time filter to eliminate images of the digitally encoded signal. The TLC32040C and TLC32041C are characterized for operation from 0C to 70C, and the TLC32040I and TLC32041I are characterized for operation from - 40C to 85C. 2 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 TLC32040C, TLC32040I, TLC32041C, TLC32041I ANALOG INTERFACE CIRCUITS SLAS014E - SEPTEMBER 1987 - REVISED MAY 1995 functional block diagram Band-Pass Filter M U X IN + A/D Serial Port DR M U X IN - AUX IN + EODR AUX IN - Internal Voltage Reference (TLC32040 only) MSTR CLK SHIFT CLK WORD/BYTE DX Low-Pass Filter - + OUT - FSX - + OUT + FSR D/A EODX Transmit Section VCC + VCC - ANLG GND DTGL VDD GND (DIGITAL) REF RESET Terminal Functions TERMINAL NAME ANLG GND NO. I/O 17,18 DESCRIPTION Analog ground return for all internal analog circuits. Not internally connected to DGTL GND. AUX IN + 24 I Noninverting auxiliary analog input state. This input can be switched into the bandpass filter and A/D converter t path th via i software ft control. t l If the th appropriate i t bit in i the th control t l register i t is i a 1, 1 the th auxiliary ili inputs i t replace inputs. re lace the IN + and IN - in uts. If the bit is a 0, the IN + and IN - inputs in uts are used (see the AIC DX data word format section). AUX IN - 23 I Inverting auxiliary analog input (see the above AUX IN + description) DGTL GND 9 DR 5 O DR is used to transmit the ADC output bits from the AIC to the TMS320 serial port. This transmission of bits from the AIC to the TMS320 serial port is synchronized with the SHIFT CLK signal. DX 12 I DX is used to receive the DAC input bits and timing and control information from the TMS320. This serial transmission from the TMS320 serial port to the AIC is synchronized with the SHIFT CLK signal. EODR 3 O End of data receive. See the WORD/BYTE description and the Serial Port Timing diagrams. During the word-mode timing, EODR is a low-going pulse that occurs immediately after the 16 bits of A/D information have been transmitted from the AIC to the TMS320 serial port. EODR can be used to interrupt a microprocessor upon completion of serial communications. Also, EODR can be used to strobe and enable external serial-to-parallel shift registers, latches, or external FIFO RAM, and to facilitate parallel data bus communications between the AIC and the serial-to-parallel shift registers. During the byte-mode timing, EODR goes low after the first byte has been transmitted from the AIC to the TMS320 serial port and is kept low until the second byte has been transmitted. The TMS32011 or TMS320C17 can use this low-going signal to differentiate between the two bytes as to which is first and which is second. EODR does not occur after secondary communication. Digital ground for all internal logic circuits. Not internally connected to ANLG GND. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 3 TLC32040C, TLC32040I, TLC32041C, TLC32041I ANALOG INTERFACE CIRCUITS SLAS014E - SEPTEMBER 1987 - REVISED MAY 1995 Terminal Functions (continued) TERMINAL NAME NO. I/O DESCRIPTION EODX 11 O End of data transmit. See the WORD/BYTE description and the Serial Port Timing diagram. During the word-mode timing, EODX is a low-going pulse that occurs immediately after the 16 bits of D/A converter and control or register information have been transmitted from the TMS320 serial port to the AIC. EODX can be used to interrupt a microprocessor upon the completion of serial communications. Also, EODX can be used to strobe and enable external serial-to-parallel shift registers, latches, or an external FIFO RAM, and to facilitate parallel data-bus communications between the AIC and the serial-to-parallel shift registers. During the byte-mode timing, EODX goes low after the first byte has been transmitted from the TMS320 serial port to the AIC and is kept low until the second byte has been transmitted. The TMS32011 or TMS320C17 can use this low-going signal to differentiate between the two bytes as to which is first and which is second. FSR 4 O Frame sync receive. In the serial transmission modes, which are described in the WORD/BYTE description, FSR is held low during bit transmission. When FSR goes low, the TMS320 serial port begins receiving bits from the AIC via DR of the AIC. The most significant DR bit is present on DR before FSR goes low. (See Serial Port Timing and Internal Timing Configuration diagrams.) FSR does not occur after secondary communication. FSX 14 O Frame sync goes low,, the TMS320 serial port begins transmitting y transmit. When FSX g g g bits to the AIC via DX of the AIC. In all serial transmission modes, which are described in the WORD/BYTE description, FSX is held low during bit transmission (see the Serial Port Timing and Internal Timing Configuration diagrams). IN + 26 I Noninverting input to analog input amplifier stage IN - 25 I Inverting input to analog input amplifier stage MSTR CLK 6 I Master clock. MSTR CLK is used to derive all the key logic signals of the AIC, such as the shift clock, the switched-capacitor filter clocks, and the A/D and D/A timing signals. The Internal Timing Configuration diagram shows how these key signals are derived. The frequencies of these key signals are synchronous submultiples of the master clock frequency to eliminate unwanted aliasing when the sampled analog signals are transferred between the switched-capacitor filters and the A/D and D/A converters (see the Internal Timing Configuration). OUT + 22 O Noninverting output of analog output power amplifier. OUT + can drive transformer hybrids or high-impedance loads directly in either a differential or a single-ended configuration. OUT - 21 O Inverting output of analog output power amplifier. OUT - is functionally identical with and complementary to OUT +. REF 8 I/O Internal voltage reference for the TLC32040. For the TLC32040 and TLC32041 an external voltage reference can be applied to this terminal. RESET 2 I Reset. A reset function is provided to initialize the TA, TA', TB, RA, RA', RB, and control registers. This reset function initiates serial communications between the AIC and DSP. The reset function initializes all AIC registers including the control register. After a negative-going pulse on RESET, the AIC registers are initialized to provide an 8-kHz data conversion rate for a 5.184-MHz master clock input signal. The conversion rate adjust registers, TA' and RA', are reset to 1. The control register bits are reset as follows (see AIC DX data word format section): d7 = 1, d6 = 1, d5 = 1, d4 = 0, d3 = 0, d2 = 1 This initialization allows normal serial-port communication to occur between AIC and DSP. SHIFT CLK 10 O Shift clock. SHIFT CLK is obtained by dividing the master clock signal frequency by four. SHIFT CLK is used to clock the serial data transfers of the AIC, described in the WORD/BYTE description below (see the Serial Port Timing and Internal Timing Configuration diagrams). VDD VCC + 7 Digital supply voltage, 5 V 5% 20 Positive analog supply voltage, 5 V 5% VCC - 19 Negative analog supply voltage, - 5 V 5% 4 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 TLC32040C, TLC32040I, TLC32041C, TLC32041I ANALOG INTERFACE CIRCUITS SLAS014E - SEPTEMBER 1987 - REVISED MAY 1995 Terminal Functions (continued) TERMINAL NAME NO. WORD/BYTE 13 I/O DESCRIPTION I WORD/BYTE, in conjunction with a bit in the control register, is used to establish one of four serial modes. These four serial modes are described below. AIC transmit and receive sections are operated asynchronously. The following description applies when the AIC is configured to have asynchronous transmit and receive sections. If the appropriate data bit in the control register is a 0 (see the AIC DX data word format section), the transmit and receive sections are asynchronous. L Serial port directly interfaces with the serial port of the TMS32011 or TMS320C17 and communicates in two 8-bit bytes. The operation sequence is as follows (see Serial Port Timing diagrams). 1. FSX or FSR is brought low. 2. One 8-bit byte is transmitted or one 8-bit byte is received. 3. EODX or EODR is brought low. 4. FSX or FSR emits a positive frame-sync pulse that is four shift clock cycles wide. 5. One 8-bit byte is transmitted or one 8-bit byte is received. 6. EODX or EODR is brought high. 7. FSX or FSR is brought high. H Serial port directly interfaces with the serial port of the TMS32020, TMS320C25, or TMS320C30 and communicates in one 16-bit word. The operation sequence is as follows (see Serial Port Timing diagrams): 1. FSX or FSR is brought low. 2. One 16-bit word is transmitted or one 16-bit word is received. 3. FSX or FSR is brought high. 4. EODX or EODR emits a low-going pulse. AIC transmit and receive sections are operated synchronously. If the appropriate data bit in the control register is a 1, the transmit and receive sections are configured to be synchronous. In this case, the bandpass switched-capacitor filter and the A/D conversion timing are derived from the TX counter A, TX counter B, and TA, TA', and TB registers, rather than the RX counter A, RX counter B, and RA, RA', and RB registers. In this case, the AIC FSX and FSR timing are identical during primary data communication; however, FSR is not asserted during secondary data communication since there is no new A/D conversion result. The synchronous operation sequences are as follows (see Serial Port Timing diagrams). L Serial port directly interfaces with the serial port of the TMS32011 or TMS320C17 and communicates in two 8-bit bytes. The operation sequence is as follows (see Serial Port Timing diagrams): 1. FSX and FSR are brought low. 2. One 8-bit byte is transmitted and one 8-bit byte is received. 3. EODX and EODR are brought low. 4. FSX and FSR emit positive frame-sync pulses that are four shift clock cycles wide 5. One 8-bit byte is transmitted and one 8-bit byte is received. 6. EODX and EODR are brought high. 7. FSX and FSR are brought high. H Serial port directly interfaces with the serial port of the TMS32020, TMS320C25, or TMS320C30 and communicates in one 16-bit word. The operation sequence is as follows (see Serial Port Timing diagrams): 1. FSX and FSR are brought low. 2. One 16-bit word is transmitted and one 16-bit word is received. 3. FSX and FSR are brought high. 4. EODX or EODR emit low-going pulses. Since the transmit and receive sections of the AIC are now synchronous, the AIC serial port with additional NOR and AND gates will interface to two SN74299 serial-to-parallel shift registers. Interfacing the AIC to the SN74299 shift register allows the AIC to interface to an external FIFO RAM and facilitates parallel data bus communications between the AIC and the digital signal processor. The operation sequence is the same as the above sequence (see Serial Port Timing diagrams). POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 5 TLC32040C, TLC32040I, TLC32041C, TLC32041I ANALOG INTERFACE CIRCUITS SLAS014E - SEPTEMBER 1987 - REVISED MAY 1995 detailed description analog input Two sets of analog inputs are provided. Normally, the IN + and IN - input set is used; however, the auxiliary input set, AUX IN + and AUX IN - , can be used if a second input is required. Each input set can be operated in either differential or single-ended modes, since sufficient common-mode range and rejection are provided. The gain for the IN +, IN -, AUX IN +, and AUX IN - inputs can be programmed to be either 1, 2, or 4 (see Table 2). Either input circuit can be selected via software control. It is important to note that a wide dynamic range is assured by the differential internal analog architecture and by the separate analog and digital voltage supplies and grounds. A/D bandpass filter, A/D bandpass filter clocking, and A/D conversion timing The A/D bandpass filter can be selected or bypassed via software control. The frequency response of this filter is presented in the following pages. This response results when the switched-capacitor filter clock frequency is 288 kHz. Several possible options can be used to attain a 288-kHz switched-capacitor filter clock. When the filter clock frequency is not 288 kHz, the filter transfer function is frequency scaled by the ratio of the actual clock frequency to 288 kHz. The low-frequency roll-off of the high-pass section is 300 Hz. The internal timing configuration and AIC DX data word format sections of this data sheet indicate the many options for attaining a 288-kHz bandpass switched-capacitor filter clock. These sections indicate that the RX counter A can be programmed to give a 288-kHz bandpass switched-capacitor filter clock for several master clock input frequencies. The A/D conversion rate is then attained by frequency dividing the 288-kHz bandpass switched-capacitor filter clock with the RX counter B. Thus, unwanted aliasing is prevented because the A/D conversion rate is an integral submultiple of the bandpass switched-capacitor filter sampling rate, and the two rates are synchronously locked. A/D converter performance specifications Fundamental performance specifications for the A/D converter circuitry are presented in the A/D converter operating characteristics section of this data sheet. The realization of the A/D converter circuitry with switched-capacitor techniques provides an inherent sample-and-hold. analog output The analog output circuitry is an analog output power amplifier. Both noninverting and inverting amplifier outputs are brought out of this integrated circuit. This amplifier can drive transformer hybrids or low-impedance loads directly in either a differential or single-ended configuration. D/A low-pass filter, D/A low-pass filter clocking, and D/A conversion timing The frequency response of this filter is presented in the following pages. This response results when the low-pass switched-capacitor filter clock frequency is 288 kHz. Like the A/D filter, the transfer function of this filter is frequency scaled when the clock frequency is not 288 kHz. A continuous-time filter is provided on the output on the output of the D/A low-pass filter to greatly attenuate any switched-capacitor clock feedthrough. The D/A conversion rate is then attained by frequency dividing the 288-kHz switched-capacitor filter clock with TX counter B. Thus, unwanted aliasing is prevented because the D/A conversion rate is an integral submultiple of the switched-capacitor low-pass filter sampling rate, and the two rates are synchronously locked. 6 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 TLC32040C, TLC32040I, TLC32041C, TLC32041I ANALOG INTERFACE CIRCUITS SLAS014E - SEPTEMBER 1987 - REVISED MAY 1995 asynchronous versus synchronous operation If the transmit section of the AIC (low-pass filter and DAC) and receive section (bandpass filter and ADC) are operated asynchronously, the low-pass and band-pass filter clocks are independently generated from the master clock signal. Also, the D/A and A/D conversion rates are independently determined. If the transmit and receive sections are operated synchronously, the low-pass filter clock drives both low-pass and bandpass filters. In synchronous operation, the A/D conversion timing is derived from, and is equal to, the D/A conversion timing. (See description of WORD/BYTE in the Terminal Functions table.) D/A converter performance specifications Fundamental performance specifications for the D/A converter circuitry are presented in the D/A converter operating characteristics section of the data sheet. The D/A converter has a sample-and-hold that is realized with a switched-capacitor ladder. system frequency response correction The (sin x) / x correction circuitry is performed in the digital processor software. The system frequency response can be corrected via DSP software to 0.1-dB accuracy to band edge of 3000 Hz for all sampling rates. This correction is accomplished with a first-order digital correction filter, which requires only seven TMS320 instruction cycles. With a 200-ns instruction cycle, seven instructions represent an overhead factor of only 1.1% and 1.3% for sampling rates of 8 and 9.6 kHz, respectively (see the (sin x) / x correction section for more details). serial port The serial port has four possible modes that are described in detail in the Terminal Functions table. These modes are briefly described below and in the description for WORD/BYTE in the Terminal Functions Table. D D D D The transmit and receive sections are operated asynchronously, and the serial port interfaces directly with the TMS32011 and TMS320C17. The transmit and receive sections are operated asynchronously, and the serial port interfaces directly with the TMS32020 and the TMS320C25. The transmit and receive sections are operated synchronously, and the serial port interfaces directly with the TMS32011 and TMS320C17. The transmit and receive sections are operated synchronously, and the serial port interfaces directly with the TMS32020, TMS320C25, or two SN74299 serial-to-parallel shift registers, which can then interface in parallel to the TMS320C10, TMS32015, to any other digital signal processor, or to external FIFO circuitry. operation of TLC32040 with internal voltage reference The internal reference of the TLC32040 eliminates the need for an external voltage reference and provides overall circuit cost reduction. Thus, the internal reference eases the design task and provides complete control over the performance of this integrated circuit. The internal reference is brought out to a terminal and is available to the designer. To keep the amount of noise on the reference signal to a minimum, an external capacitor may be connected between REF and ANLG GND. operation of TLC32040 or TLC32041 with external voltage reference REF can be driven from an external reference circuit if so desired. This external circuit must be capable of supplying 250 A and must be adequately protected from noise such as crosstalk from the analog input. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 7 TLC32040C, TLC32040I, TLC32041C, TLC32041I ANALOG INTERFACE CIRCUITS SLAS014E - SEPTEMBER 1987 - REVISED MAY 1995 reset A reset function is provided to initiate serial communications between the AIC and DSP and allow fast, cost-effective testing during manufacturing. The reset function initializes all AIC registers, including the control register. After a negative-going pulse on RESET, the AIC is initialized. This initialization allows normal serial port communications activity to occur between AIC and DSP (see AIC DX data word format section). loopback This feature allows the user to test the circuit remotely. In loopback, OUT + and OUT - are internally connected to IN + and IN -. Thus, the DAC bits (d15 to d2), which are transmitted to DX, can be compared with the ADC bits (d15 to d2), which are received from DR. An ideal comparison would be that the bits on DR equal the bits on DX. However, in practice there is some difference in these bits due to the ADC and DAC output offsets. In loopback, if IN + and N - are enabled, the external signals on IN + and IN - are ignored. If AUX IN + and AUX IN- are enabled, the external signals on these terminals are added to the OUT + and OUT - signals in loopback operation. The loopback feature is implemented with digital signal processor control by transmitting the appropriate serial port bit to the control register (see AIC DX data word format section). explanation of internal timing configuration All of the internal timing of the AIC is derived from the high-frequency clock signal that drives the master clock input. The shift clock signal, which strobes the serial port data between the AIC and DSP, is derived by dividing the master clock input signal frequency by four. SCF Clock Frequency Clock Frequency + 2 Master Contents of Counter A Conversion Frequency SCF Clock Frequency + Contents of Counter B Shift Clock Frequency + Master Clock4 Frequency TX counter A and TX counter B, which are driven by the master clock signal, determine the D/A conversion timing. Similarly, RX counter A and RX counter B determine the A/D conversion timing. In order for the switched-capacitor low-pass and band pass filters to meet their transfer function specifications, the frequency of the clock inputs of the switched-capacitor filters must be 288 kHz. If the frequencies of the clock inputs are not 288 kHz, the filter transfer function frequencies are scaled by the ratios of the clock frequencies to 288 kHz. Thus, to obtain the specified filter responses, the combination of master clock frequency and TX counter A and RX counter A values must yield 288-kHz switched-capacitor clock signals. These 288-kHz clock signals can then be divided by the TX counter B and RX counter B to establish the D/A and A/D conversion timings. TX counter A and TX counter B are reloaded every D/A conversion period, while RX counter A and RX counter B are reloaded every A/D conversion period. The TX counter B and RX counter B are loaded with the values in the TB and RB registers, respectively. Via software control, the TX counter A can be loaded with either the TA register, the TA register less the TA' register, or the TA register plus the TA' register. By selecting the TA register less the TA' register option, the upcoming conversion timing will occur earlier by an amount of time that equals TA' times the signal period of the master clock. By selecting the TA register plus the TA' register option, the upcoming conversion timing will occur later by an amount of time that equals TA' times the signal period of the master clock. Thus, the D/A conversion timing can be advanced or retarded. An identical ability to alter the A/D conversion timing is provided. In this case, however, the RX counter A can be programmed via software control with the RA register, the RA register less the RA' register, or the RA register plus the RA' register. 8 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 TLC32040C, TLC32040I, TLC32041C, TLC32041I ANALOG INTERFACE CIRCUITS SLAS014E - SEPTEMBER 1987 - REVISED MAY 1995 explanation of internal timing configuration (continued) The ability to advance or retard conversion timing is particularly useful for modem applications. This feature allows controlled changes in the A/D and D/A conversion timing. This feature can be used to enhance signal-to-noise performance, to perform frequency-tracking functions, and to generate nonstandard modem frequencies. If the transmit and receive sections are configured to be synchronous (see WORD/BYTE description), then both the low-pass and bandpass switched-capacitor filter clocks are derived from TX counter A. Also, both the D/A and A/D conversion timing are derived from the TX counter A and TX counter B. When the transmit and receive sections are configured to be synchronous, the RX counter A, RX counter B, RA register, RA' register, and RB registers are not used. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 9 TLC32040C, TLC32040I, TLC32041C, TLC32041I ANALOG INTERFACE CIRCUITS SLAS014E - SEPTEMBER 1987 - REVISED MAY 1995 MSTR CLK 5.184 MHz (1) 10.368 MHz (2) SHIFT CLK 1.296 MHz (1) 2.592 MHz (2) Divide by 4 20.736 MHz (1) 41.472 MHz (2) XTAL OSC TMS320 DSP TA Register (5 bits) Optional External Circuitry for Full-Duplex Modems Divide by 135 153.6 -kHz Clock (1) Commercial External Front-End Full-Duplex Split-Band Filters TA' Register (6 bits) (2's compl) Divide by 2 Adder/ Subtractor (6 bits) Low-Pass/ Switched Capacitor Filter CLK= 288-kHz Square Wave TB Register (6 bits) d0, d1 = 0,0 d0, d1 = 1,1 d0, d1 = 0,1 d0, d1 = 1,0 TX Counter A [TA = 9 (1)] [TA = 18 (2)] (6 bits) RA Register (5 bits) 576-kHz Pulses TX Counter B [TB = 40; 7.2 kHz [TB = 36; 8.0 kHz [TB = 30; 9.6 kHz [TB = 20; 14.4 kHz [TB = 15; 19.2 kHz RA' Register (6 bits) (2's compl) Divide by 2 Adder/ Subtractor (6 bits) D/A Conversion Frequency Band-Pass Switched Capacitor Filter CLK= 288-kHz Square Wave RB Register (6 bits) d0, d1 = 0,0 d0, d1 = 1,1 d0, d1 = 0,1 d0, d1 = 1,0 RX Counter A [RA = 9 (1)] [RA = 18 (2)] (6 bits) SCF Clock Frequency 576-kHz Pulses RX Counter B [RB = 40; 7.2 kHz [RB = 36; 8.0 kHz [RB = 30; 9.6 kHz [RB = 20; 14.4 kHz [RB = 15; 19.2 kHz A/D Conversion Frequency Clock Frequency + 2 Master Contents of Counter A Split-band filtering can alternatively be performed after the analog input function via software in the TMS320. These control bits are described in the AIC DX data word format section. NOTE A: Frequency 1 (20.736 MHz) is used to show how 153.6 kHz (for commercially available modem split-band filter clock), popular speech and modem sampling signal frequencies, and an internal 288-kHz switched-capacitor filter clock can be derived synchronously and as submultiples of the crystal oscillator frequency. Since these derived frequencies sre synchronous submultiples of the crystal frequency, aliasing does not occur as the sampled analog signal passes between the analog converter and switched-capacitor filter stages. Frequency 2 (41.472 MHz) is used to show that the AIC can work with high-frequency signals, which are used by high-speed digital signal processors. Figure 1. Internal Timing Configuration 10 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 TLC32040C, TLC32040I, TLC32041C, TLC32041I ANALOG INTERFACE CIRCUITS SLAS014E - SEPTEMBER 1987 - REVISED MAY 1995 AIC DR or DX word bit pattern A/D or D/A MSB, 1st bit sent D15 D14 D13 1st bit sent of 2nd byte D12 D11 D10 D9 D8 D7 D6 A/D or D/A LSB D5 D4 D3 D2 D1 D0 AIC DX data word format section d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 COMMENTS d15 (MSB) through d2 go to the D/A converter register 0 0 The TX and RX counter As are loaded with the TA and RA register values. The TX and RX counter Bs are loaded with TB and RB register values. d15 (MSB) through d2 go to the D/A converter register 0 1 The TX and RX counter As are loaded with the TA + TA' and RA + RA' register values. The TX and RX counter Bs are loaded with TB and RB register values. Bits d1 = 0 and d0 =1 cause the next D/A and A/D conversion periods to be changed by the addition of TA' and RA' master clock cycles, in which TA' and R/A' can be positive or negative or zero (refer to Table 1). d15 (MSB) through d2 go to the D/A converter register 1 0 The TX and RX counter As are loaded with the TA - TA' and RA - RA' register values. The TX and RX counter Bs are loaded with TB and RB register values. Bits d1 = 1 and d0 = 0 cause the next D/A and A/D conversion periods to be changed by the subtraction of TA' and RA' master clock cycles, in which TA' and R/A' can be positive or negative or zero (refer to Table 1). d15 (MSB) through d2 go to the D/A converter register 1 1 The TX and RX counter As are loaded with the TA and RA register values. The TX and RX counter Bs are loaded with the TB and RB register values. After a delay of four shift clock cycles, a secondary transmission immediately follows to program the AIC to operate in the desired configuration. primary DX serial communication protocol NOTE: Setting the two least significant bits to 1 in the normal transmission of DAC information (primary communications) to the AIC initiates secondary communications upon completion of the primary communications. Upon completion of the primary communication, FSX remains high for four SHIFT CLK cycles and then goes low and initiates the secondary communication. The timing specifications for the primary and secondary communications are identical. In this manner, the secondary communication, if initiated, is interleaved between successive primary communications. This interleaving prevents the secondary communication from interfering with the primary communications and DAC timing, thus preventing the AIC from skipping a DAC output. In the synchronous mode, FSR is not asserted during secondary communications. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 11 TLC32040C, TLC32040I, TLC32041C, TLC32041I ANALOG INTERFACE CIRCUITS SLAS014E - SEPTEMBER 1987 - REVISED MAY 1995 secondary DX serial communication protocol x x | to TA register | x x | to RA register | 0 0 d13 and d6 are MSBs (unsigned binary) x | to TA' register | x | to RA' register | 0 1 d14 and d7 are 2's complement sign bits x | to TB register | x | to RB register | 1 0 d14 and d7 are MSBs (unsigned binary) x x x x x x x x d7 d6 d5 d4 d3 d2 Control register 1 1 d2 = 0/1 deletes/inserts the bandpass filter d3 = 0/1 disables/enables the loopback function d4 = 0/1 disables/enables the AUX IN + and AUX IN - terminals d5 = 0/1 asynchronous/synchronous transmit receive sections d6 = 0/1 gain control bits (see gain control section) d7 = 0/1 gain control bits (see gain control section) reset function A reset function is provided to initiate serial communications between the AIC and DSP. The reset function initializes all AIC registers, including the control register. After power has been applied to the AIC, a negative-going pulse on RESET initializes the AIC registers to provide an 8-kHz A/D and D/A conversion rate for a 5.184-MHz master clock input signal. The AIC, except the control register, is initialized as follows (see AIC DX data word format section): INITIALIZED REGISTER VALUE (HEX) REGISTER TA 9 TA' 1 TB 24 RA 9 RA' 1 RB 24 The control register bits are reset as follows (see AIC DX data word format section): d7 = 1, d6 = 1, d5 = 1, d4 = 0, d3 = 0, d2 = 1 This initialization allows normal serial port communications to occur between AIC and DSP. If the transmit and receive sections are configured to operate synchronously and the user wishes to program different conversion rates, only the TA, TA', and TB register need to be programmed, since both transmit and receive timing are synchronously derived from these registers (see the terminal descriptions and AIC DX word format sections). The circuit shown below provides a reset on power up when power is applied in the sequence given under power-up sequence. The circuit depends on the power supplies reaching their recommended values a minimum of 800 ns before the capacitor charges to 0.8 V above DGTL GND. TLC32040/ TLC32041 VCC + 5V 200 k RESET 0.5 F VCC - 12 POST OFFICE BOX 655303 -5 V * DALLAS, TEXAS 75265 TLC32040C, TLC32040I, TLC32041C, TLC32041I ANALOG INTERFACE CIRCUITS SLAS014E - SEPTEMBER 1987 - REVISED MAY 1995 power-up sequence To ensure proper operation of the AIC, and as a safeguard against latch-up, it is recommended that a Schottky diode with a forward voltage less than or equal to 0.4 V be connected from VCC - to ANLG GND (see Figure 17). In the absence of such a diode, power should be applied in the following sequence: ANLG GND and DGTL GND, VCC -, then VCC + and VDD. Also, no input signal should be applied until after power up. AIC responses to improper conditions The AIC has provisions for responding to improper conditions. These improper conditions and the response of the AIC to these conditions are presented in Table 1 below. AIC register constraints The following constraints are placed on the contents of the AIC registers: 1. TA register must be 4 in word mode (WORD/BYTE = high). 2. TA register must be 5 in byte mode (WORD/BYTE = low). 3. TA' register can be either positive, negative, or zero. 4. RA register must be 4 in word mode (WORD/BYTE = high). 5. RA register must be 5 in byte mode (WORD/BYTE = low). 6. RA' register can be either positive, negative, or zero. 7. (TA register TA' register) must be > 1. 8. (RA register RA' register) must be > 1. 9. TB register must be > 1. Table 1. AIC Responses To Improper Conditions IMPROPER CONDITIONS AIC RESPONSE TA register + TA' register = 0 or 1 TA register - TA' register = 0 or 1 Reprogram TX counter A with TA register value TA register + TA' register < 0 MODULO 64 arithmetic is used to ensure that a positive value is loaded into the TX counter A, i.e., TA register + TA' register + 40 hex is loaded into TX counter A. RA register + RA' register = 0 or 1 RA register - RA' register = 0 or 1 Reprogram RX counter A with RA register value RA register + RA' register = 0 or 1 MODULO 64 arithmetic is used to ensure that a positive value is loaded into RX counter A, i.e., RA register + RA' register + 40 hex is loaded into RX counter A. TA register = 0 or 1 RA register = 0 or 1 The AIC is shut down. TA register < 4 in word mode TA register < 5 in byte mode RA register < 4 in word mode RA register < 5 in byte mode The AIC serial port no longer operates. TB register = 0 or 1 Reprogram TB register with 24 hex RB register = 0 or 1 Reprogram RB register with 24 hex AIC and DSP cannot communicate Hold last DAC output POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 13 TLC32040C, TLC32040I, TLC32041C, TLC32041I ANALOG INTERFACE CIRCUITS SLAS014E - SEPTEMBER 1987 - REVISED MAY 1995 improper operation due to conversion times being too close together If the difference between two successive D/A conversion frame syncs is less than 1/19.2 kHz, the AIC operates improperly. In this situation, the second D/A conversion frame sync occurs too quickly and there is not enough time for the ongoing conversion to be completed. This situation can occur if the A and B registers are improperly programmed or if the A + A' register or A - A' register result is too small. When incrementally adjusting the conversion period via the A + A' register options, the designer should be very careful not to violate this requirement (see following diagram). t1 t2 Frame Sync FSX or FSR Ongoing Conversion t2 - t1 1/19.2 kHz asynchronous operation -- more than one receive frame sync occurring between two transmit frame syncs When incrementally adjusting the conversion period via the A + A' or A - A' register options, a specific protocol is followed. The command to use the incremental conversion period adjust option is sent to the AIC during a FSX frame sync. The ongoing conversion period is then adjusted. However, either receive conversion period A or B may be adjusted. For both transmit and receive conversion periods, the incremental conversion period adjustment is performed near the end of the conversion period. Therefore, if there is sufficient time between t1 and t2, the receive conversion period adjustment is performed during receive conversion period A. Otherwise, the adjustment is performed during receive conversion period B. The adjustment command only adjusts one transmit conversion period and one receive conversion period. To adjust another pair of transmit and receive conversion periods, another command must be issued during a subsequent FSX frame (see figure below). t1 FSX Transmit Conversion Period t2 FSR Receive Conversion Period A 14 Receive Conversion Period B POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 TLC32040C, TLC32040I, TLC32041C, TLC32041I ANALOG INTERFACE CIRCUITS SLAS014E - SEPTEMBER 1987 - REVISED MAY 1995 asynchronous operation -- more than one receive frame sync occurring between two receive frame syncs When incrementally adjusting the conversion period via the A + A' or A - A' register options, a specific protocol is followed. For both transmit and receive conversion periods, the incremental conversion period adjustment is performed near the end of the conversion period. The command to use the incremental conversion period adjust options is sent to the AIC during a FSX frame sync. The ongoing transmit conversion period is then adjusted. However, three possibilities exist for the receive conversion period adjustment in the diagram as shown in the following figure. If the adjustment command is issued during transmit conversion period A, receive conversion period A is adjusted if there is sufficient time between t1 and t2. Or, if there is not sufficient time between t1 and t2, receive conversion period B is adjusted. Or, the receive portion of an adjustment command can be ignored if the adjustment command is sent during a receive conversion period, which is already being or is adjusted due to a prior adjustment command. For example, if adjustment commands are issued during transmit conversion periods A, B, and C, the first two commands can cause receive conversion periods A and B to be adjusted, while the third receive adjustment command is ignored. The third adjustment command is ignored since it was issued during receive conversion period B, which already is adjusted via the transmit conversion period B adjustment command. t1 FSX Transmit Conversion Period A Transmit Conversion Period B Transmit Conversion Period C t2 FSR Receive Conversion Period A Receive Conversion Period B asynchronous operation -- more than one set of primary and secondary DX serial communication occurring between two receive frame sync (see AIC DX data word format section) The TA, TA', TB, and control register information that is transmitted in the secondary communications is always accepted and is applied during the ongoing transmit conversion period. If there is sufficient time between t1 and t2, the TA, RA', and RB register information, which is sent during transmit conversion period A, is applied to receive conversion period A. Otherwise, this information is applied during receive conversion period B. If RA, RA', and RB register information has already been received and is being applied during an ongoing conversion period, any subsequent RA, RA', or RB information that is received during this receive conversion period is disregarded (see diagram below). Primary t1 Secondary Primary Secondary Primary Secondary FSX Transmit Conversion Period A Transmit Conversion Period B Transmit Conversion Period C t2 FSR Receive Conversion Period A Receive Conversion Period B POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 15 TLC32040C, TLC32040I, TLC32041C, TLC32041I ANALOG INTERFACE CIRCUITS SLAS014E - SEPTEMBER 1987 - REVISED MAY 1995 Table 2. Gain Control Table Analog Input Signal Required for Full-Scale A/D Conversion CONTROL REGISTER BITS INPUT CONFIGURATIONS Differential configuration Analog input = IN + - IN - = AUX IN + - AUX IN - Single-ended configuration Analog input = IN + - ANLG GND = AUX IN + - ANLG GND d6 d7 1 1 0 0 1 0 1 1 0 0 1 0 ANALOG INPUT A/D CONVERSION RESULT 6 V Full scale 0 3 V Full scale 1 1.5 V Full scale 3 V Half scale 3 V Full scale 0 1 1.5 V Full scale In this example, Vref is assumed to be 3 V. In order to minimize distortion, it is recommended that the analog input not exceed 0.1 dB below full scale. Rfb Rfb R R IN + + IN - - - To Multiplexer AUX IN + + AUX IN - - To Multiplexer + R + R - Rfb Rfb Rfb = R for d6 = 1, d7 = 1 d6 = 0, d7 = 0 Rfb = 2R for d6 = 1, d7 = 0 Rfb = 4R for d6 = 0, d7 = 1 Rfb = R for d6 = 1, d7 = 1 d6 = 0, d7 = 0 Rfb = 2R for d6 = 1, d7 = 0 Rfb = 4R for d6 = 0, d7 = 1 Figure 2. IN + and IN - Gain Control Circuitry Figure 3. AUX IN + and AUX IN - Gain Control Circuitry (sin x) / x correction section The AIC does not have (sin x) / x correction circuitry after the digital-to-analog converter.The (sin x) / x correction can be accomplished easily and efficiently in digital signal processor (DSP) software. Excellent correction accuracy can be achieved to a band edge of 3000 Hz by using a first-order digital correction filter. The results, which are shown below, are typical of the numerical correction accuracy that can be achieved for sample rates of interest. The filter requires only seven instruction cycles per sample on the TMS320 DSPs. With a 200-ns instruction cycle, nine instructions per sample represents an overhead factor of 1.4% and 1.7% for sampling rates of 8000 Hz and 9600 Hz, respectively. This correction adds a slight amount of group delay at the upper edge of the 300-3000-Hz band. 16 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 TLC32040C, TLC32040I, TLC32041C, TLC32041I ANALOG INTERFACE CIRCUITS SLAS014E - SEPTEMBER 1987 - REVISED MAY 1995 (sin x) / x roll-off for a zero-order hold function The (sin x) / x roll-off for the AIC DAC zero-order hold function at a band-edge frequency of 3000 Hz for the various sampling rates is shown in the table below. Table 3. (sin x)/x Roll-Off sin f/fs f/fs (f = 3000 Hz) 20 log fs (Hz) ( ) (dB) 7200 - 2.64 8000 - 2.11 9600 - 1.44 14400 - 0.63 19200 - 0.35 The actual AIC (sin x) / x roll-off is slightly less than the above figures, because the AIC has less than a 100% duty cycle hold interval. correction filter To compensate for the (sin x) / x roll-off of the AIC, a first-order correction filter shown below, is recommended. + u(i + 1) y(i + 1) + z-1 (1 - p1)P2 p1 The difference equation for this correction filter is: yi + 1 = p2(1 - p1) (ui + 1) + p1 yi where the constant p1 determines the pole locations. The resulting squared magnitude transfer function is: (1 * p1) + 1 * 2p1p2cos(2 p ff ) ) p1 2 |H(f)| 2 2 s 2 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 17 TLC32040C, TLC32040I, TLC32041C, TLC32041I ANALOG INTERFACE CIRCUITS SLAS014E - SEPTEMBER 1987 - REVISED MAY 1995 correction results Table 4 below shows the optimum p values and the corresponding correction results for 8000-Hz and 9600-Hz sampling rates. Table 4. Correction Results ERROR (dB) fs = 8000 Hz p1 = - 0.14813 p2 = 0.9888 ERROR (dB) fs = 9600 Hz p1 = - 0.1307 p2 = 0.9951 300 - 0.099 - 0.043 600 - 0.089 - 0.043 f (Hz) 900 - 0.054 0 1200 - 0.002 0 1500 0.041 0 1800 0.079 0.043 2100 0.100 0.043 2400 0.091 2700 - 0.043 3000 - 0.102 0.043 0 - 0.043 TMS320 software requirements The digital correction filter equation can be written in state variable form as follows: Y = k1 x Y + k2 x U where k1 = p1 k2 = (1 - p1) x p2 Y = filter state U = next I/O sample The coefficients k1 and k2 must be represented as 16-bit integers. The SACH instruction (with the proper shift) will yield the correct result. With the assumption that the TMS320 processor page pointer and memory configuration are properly initialized, the equation can be executed in seven instructions or seven cycles with the following program: ZAC LT K2 MPY U LTA K1 MPY Y APAC SACH (dma), (shift) 18 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 TLC32040C, TLC32040I, TLC32041C, TLC32041I ANALOG INTERFACE CIRCUITS SLAS014E - SEPTEMBER 1987 - REVISED MAY 1995 absolute maximum ratings over operating free-air temperature (unless otherwise noted) Supply voltage range, VCC + (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.3 V to 15 V Supply voltage range, VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.3 V to 15 V Output voltage range, VO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.3 V to 15 V Input voltage range, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.3 V to 15 V Digital ground voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.3 V to 15 V Operating free-air temperature range, TA: TLC32040C, TLC32041C . . . . . . . . . . . . . . . . . . . . . . 0C to 70C TLC32040I, TLC32041 . . . . . . . . . . . . . . . . . . . . . . - 40C to 85C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 40C to 125C Case temperature for 10 seconds: FN package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: N package . . . . . . . . . . . . . . . . . . . . . 260C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: Voltage values for maximum ratings are with respect to VCC -.. recommended operating conditions MIN NOM MAX UNIT Supply voltage, VCC + (see Note 2) 4.75 5 5.25 V Supply voltage, VCC - (see Note 2) - 4.75 -5 - 5.25 V 4.75 5 5.25 V Digital supply voltage, VDD (see Note 2) Digital ground voltage with respect to ANLG GND, DGTL GND 0 Reference input voltage, Vref(ext) (see Note 2) 2 High-level input voltage, VIH 2 Low-level input voltage, VIL (see Note 3) 4 VDD + 0.3 0.8 - 0.3 Load resistance at OUT + and /or OUT -, RL 100 MSTR CLK frequency (see Note 4) 0.075 5 10.368 1.5 Analog input amplifier common mode input voltage (see Note 5) A/D or D/A conversion rate 20 TLC32040C, TLC32041C TLC32040I, TLC32041I V V V 300 Load capacitance at OUT + and /or OUT -, CL Operating free-air free air temperature, temperature TA V 0 70 - 40 85 pF MHz V kHz C NOTES: 2. Voltages at analog inputs and outputs, REF, VCC +, and VCC -, are with respect to ANLG GND. Voltages at digital inputs and outputs and VDD are with respect to DGTL GND. 3. The algebraic convention, in which the least positive (most negative) value is designated minimum, is used in this data sheet for logic voltage levels and temperature only. 4. The bandpass low-pass switched-capacitor filter response specifications apply only when the switched-capacitor clock frequency is 288 kHz. For switched-capacitor filter clocks at frequencies other than 288 kHz, the filter response is shifted by the ratio of switched-capacitor filter clock frequency to 288 kHz. 5. This range applies when (IN + - IN -) or (AUX IN + - AUX IN -) equals 6 V. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 19 TLC32040C, TLC32040I, TLC32041C, TLC32041I ANALOG INTERFACE CIRCUITS SLAS014E - SEPTEMBER 1987 - REVISED MAY 1995 electrical characteristics over recommended operating free-air temperature range, VCC+ = 5 V, VCC- = -5 V, VDD = 5 V (unless otherwise noted) total device, MSTR CLK frequency = 5.184 MHz, outputs not loaded PARAMETER VOH VOL TEST CONDITIONS High-level output voltage VDD = 4.75 V, VDD = 4.75 V, Low-level output voltage IOH = - 300 A IOL = 2 mA MIN TYP MAX 2.4 UNIT V 0.4 TLC3204_C 35 TLC3204_I 40 V ICC + Supply current from VCC + ICC - Supply current from VCC - IDD Vref Supply current from VDD Vref Temperature coefficient of internal reference voltage 200 ppm/C ro Output resistance at REF 100 k TLC3204_C - 35 TLC3204_I - 40 fMSTR CLK = 5.184 MHz Internal reference output voltage 7 3 3.3 mA mA mA V receive amplifier input TYP MAX A/D converter offset error (filters bypassed) 25 65 mV A/D converter offset error (filters in) 25 65 mV PARAMETER TEST CONDITIONS CMRR Common-mode rejection ratio at IN +, IN -, or AUX IN +, AUX IN - rl Input resistance at IN +, IN -, or AUX IN +,AUX IN -, REF MIN See Note 6 UNIT 55 dB 100 k transmit filter output PARAMETER TEST CONDITIONS VOO Output offset voltage at OUT +, OUT -, (single-ended relative to ANLG GND) VOM Maximum peak output voltage swing across RL at OUT + or OUT -, (single ended) RL 300 , VOM Maximum peak output voltage swing between RL at OUT + and OUT -, (differential output) RL 600 Offset voltage = 0 MIN TYP MAX 15 75 UNIT mV 3 V 6 V system distortion specifications, SCF clock frequency = 288 kHz PARAMETER TEST CONDITIONS Attenuation of second harmonic of A/D input signal Single ended Attenuation of third and higher g harmonics of A/D input signal Single ended Attenuation of second harmonic of D/A input signal Single ended Attenuation of third and higher g harmonics of D/A input signal Single ended Differential Differential Differential Differential MIN TYP 70 VI = - 0.5 dB to - 24 dB referred to Vref, See Note 7 62 VI = - 0.5 dB to - 24 dB referred to Vref, See Note 7 57 VI = - 0 dB to - 24 dB referred to Vref, See Note 7 62 VI = - 0 dB to - 24 dB referred to Vref, See Note 7 57 70 65 65 70 70 65 65 MAX UNIT dB dB dB dB All typical values are at TA = 25C. NOTES: 6. The test condition is a 0-dBm, 1-kHz input signal with an 8-kHz conversion rate. 7. The test condition VI is a 1-kHz input signal with an 8-kHz conversion rate (0 dB relative to Vref). The load impedance for the DAC is 600 . 20 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 TLC32040C, TLC32040I, TLC32041C, TLC32041I ANALOG INTERFACE CIRCUITS SLAS014E - SEPTEMBER 1987 - REVISED MAY 1995 A/D channel signal-to-distortion ratio TEST CONDITIONS (see Note 7) PARAMETER A/D channel signal-to-distortion ratio Av = 1 MIN MAX Av = 2 MIN MAX > 58 Av = 4 MIN MAX > 58 VI = - 6 dB to - 0.1 dB VI = - 12 dB to - 6 dB 58 58 58 > 58 VI = - 18 dB to - 12 dB VI = - 24 dB to - 18 dB 56 58 58 50 56 58 VI = - 30 dB to - 24 dB VI = - 36 dB to - 30 dB 44 50 56 38 44 50 VI = - 42 dB to - 36 dB VI = - 48 dB to - 42 dB 32 38 44 26 32 38 VI = - 54 dB to - 48 dB 20 26 32 UNIT dB D/A channel signal-to-distortion ratio TEST CONDITIONS (see Note 7) PARAMETER D/A channel signal-to-distortion ratio MIN VI = - 6 dB to 0 dB VI = - 12 dB to - 6 dB 58 VI = - 18 dB to - 12 dB VI = - 24 dB to - 18 dB 56 VI = - 30 dB to - 24 dB VI = - 36 dB to - 30 dB 44 VI = - 42 dB to - 36 dB VI = - 48 dB to - 42 dB 32 VI = - 54 dB to - 48 dB 20 MAX UNIT 58 50 dB 38 26 gain and dynamic range PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Absolute transmit gain tracking error while transmitting into 600 - 48-dB to 0-dB signal range, See Note 8 0.05 0.15 dB Absolute receive gain tracking error - 48-dB to 0-dB signal range, See Note 8 0.05 0.15 dB Absolute gain of the A/D channel Signal input is a - 0.5-dB, 1-kHz sinewave Absolute gain of the D/A channel Signal input is a 0-dB, 1-kHz sinewave 0.2 dB - 0.3 dB power supply rejection and crosstalk attenuation PARAMETER TEST CONDITIONS VCC + or VCC - supply y voltage g rejection ratio, receive channel f = 0 to 30 kHz VCC + or VCC - supply voltage rejection ratio, ratio transmit channel (single ended) f = 0 to 30 kHz f = 30 kHz to 50 kHz f = 30 kHz to 50 kHz Idle channel,, supplyy signal at 200 mV p-p g measured at DR (ADC output) Idle channel,, supplyy signal g at 200 mV p-p measured at OUT + MIN TYP 30 45 MAX UNIT dB 30 dB 45 Crosswalk attenuation, transmit-to-receive (single ended) 80 dB Av is the programmable gain of the input amplifier. All typical values are at TA = 25C. A value > 58 is overrange and signal clipping occurs. NOTES: 7. The test condition Vin is a 1-kHz input signal with an 8-kHz conversion rate (0 dB relative to Vref). The load impedance for the DAC is 600 . 8. Gain tracking is relative to the absolute gain at 1 kHz and 0 dB (0 dB relative to Vref). POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 21 TLC32040C, TLC32040I, TLC32041C, TLC32041I ANALOG INTERFACE CIRCUITS SLAS014E - SEPTEMBER 1987 - REVISED MAY 1995 delay distortion, SCF clock frequency = 288 kHz 2%, input (IN+ - IN-) is 3-V sinewave Refer to filter response graphs for delay distortion specifications. TLC32040 and TLC32041 bandpass filter transfer function (see curves), SCF clock frequency = 288 kHz, 2%, input (IN+ - IN-) is a 3-V sinewave (see Note 9) PARAMETER TEST CONDITIONS FREQUENCY RANGE MIN f = 100 Hz Input signal reference is 0 dB UNIT - 42 f = 170 Hz Filter gain, (see Note 10) MAX - 25 300 Hz f 3.4 kHz - 0.5 0.5 f = 4 kHz - 16 f 4.6 kHz - 58 dB low-pass filter transfer function, SCF clock frequency = 288 kHz 2% (see Note 9) PARAMETER TEST CONDITIONS FREQUENCY RANGE f 3.4 kHz Filter gain, gain (see Note 10) Output signal reference is 0 dB MIN MAX - 0.5 0.5 f = 3.6 kHz -4 f = 4 kHz - 30 f 4.4 kHz - 58 UNIT dB serial port PARAMETER TEST CONDITIONS MIN IOH = - 300 A IOL = 2 mA TYP MAX High-level output voltage II Ci Input current Input capacitance 15 pF Co Output capacitance 15 pF Low-level output voltage 2.4 UNIT VOH VOL V 0.4 V 10 A operating characteristics over recommended operating free-air temperature range, VCC+ = 5 V, VCC- = -5 V, VDD = 5 V noise (measurement includes low-pass and bandpass switched-capacitor filters) PARAMETER TEST CONDITIONS Single ended Transmit noise Differential Receive noise (see Note 11) MIN TYP MAX V rms 200 DX input i t = 00 00 00 00 00 00 00 00, constant input in ut code 300 500 20 Inputs grounded grounded, gain = 1 300 20 UNIT V rms dBrncO 475 V rms dBrncO All typical values are at TA = 25C. NOTES: 9. The above filter specifications are for a switched-capacitor filter clock range of 288 kHz 2%. For switched-capacitor filter clocks at frequencies other than 288 kHz 2%, the filter response is shifted by the ratio of switched-capacitor filter clock frequency to 288 kHz. 10. The filter gain outside of the passband is measured with respect to the gain at 1 kHz. The filter gain within the passband is measured with respect to the average gain within the passband. The passbands are 300 to 3400 Hz and 0 to 3400 Hz for the bandpass and low-pass filters respectively. 11. The noise is reffered to the input with a buffer gain of one. If the buffer gain is two or four, the noise figure is correspondingly reduced. The noise is computed by statistically evaluating the digital output of the A/D converter. 22 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 TLC32040C, TLC32040I, TLC32041C, TLC32041I ANALOG INTERFACE CIRCUITS SLAS014E - SEPTEMBER 1987 - REVISED MAY 1995 timing requirements serial port recommended input signals MIN tc(MCLK) tr(MCLK) Master clock cycle time tf(MCLK) Master clock fall time 42% RESET pulse duration (see Note 12) DX setup time before SCLK DX hold time after SCLK UNIT ns Master clock rise time Master clock duty cycle tsu(DX) th(DX) MAX 95 10 ns 10 ns 58% 800 ns 20 ns tc(SCLK)/4 ns serial port - AIC output signals, CL = 30 pF for SHIFT CLK output, CL = 15 pF for all other outputs MIN TYP MAX 380 UNIT tc(SCLK) tf(SCLK) Shift clock (SCLK) cycle time Shift clock (SCLK) fall time 3 8 ns tr(SCLK) Shift clock (SCLK) rise time 3 8 ns Shift clock (SCLK) duty cycle ns 45 55 % td(CH-FL) td(CH-FH) Delay from SCLK to FSR / FSX / FSD 30 Delay from SCLK to FSR / FSX / FSD 35 90 ns td(CH-DR) td(CH-EL) DR valid after SCLK 90 ns Delay from SCLK to EODX / EODR in word mode 90 ns td(CH-EH) tf(EODX) Delay from SCLK to EODX / EODR in word mode 90 ns EODX fall time 2 8 ns tf(EODR) td(CH-EL) EODR fall time 2 8 ns Delay from SCLK to EODX / EODR in byte mode 90 ns td(CH-EH) td(MH-SL) Delay from SCLK to EODX / EODR in byte mode 90 ns 170 ns Delay from MSTR CLK to SCLK 65 ns td(MH-SH) Delay from MSTR CLK to SCLK 65 170 ns Typical values are at TA = 25C. NOTE 12: RESET pulse duration is the amount of time that the reset terminal is held below 0.8 V after the power supplies have reached their recommended values. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 23 TLC32040C, TLC32040I, TLC32041C, TLC32041I ANALOG INTERFACE CIRCUITS SLAS014E - SEPTEMBER 1987 - REVISED MAY 1995 serial port - AIC output signals TEST CONDITIONS MIN TYP MAX 380 UNIT tc(SCLK) tf(SCLK) Shift clock (SCLK) cycle time Shift clock (SCLK) fall time 50 ns tr(SCLK) Shift clock (SCLK) rise time 50 ns Shift clock (SCLK) duty cycle ns 55 % td(CH-FL) td(CH-FH) Delay from SCLK to FSR / FSX CL = 50 pF 45 52 ns Delay from SCLK to FSR / FSX CL = 50 pF 52 ns td(CH-DR) td(CH-EL) DR valid after SCLK 90 ns Delay from SCLK to EODX / EODR in word mode 90 ns td(CH-EH) tf(EODX) Delay from SCLK to EODX / EODR in word mode 90 ns EODX fall time 15 ns tf(EODR) td(CH-EL) EODR fall time 15 ns Delay from SCLK to EODX / EODR in byte mode 100 ns td(CH-EH) td(MH-SL) Delay from SCLK to EODX / EODR in byte mode 100 ns Delay from MSTR CLK to SCLK 65 ns td(MH-SH) Delay from MSTR CLK to SCLK Typical values are at TA = 25C. 65 ns 24 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 TLC32040C, TLC32040I, TLC32041C, TLC32041I ANALOG INTERFACE CIRCUITS SLAS014E - SEPTEMBER 1987 - REVISED MAY 1995 PARAMETER MEASUREMENT INFORMATION tf(SCLK) 2V SHIFT CLK tr(SCLK) 2V 0.8 V td(CH-FL) tc(SCLK) 2V 2V 0.8 V 2V 2V td(CH-FL) td(CH-FH) 0.8 V FSR, FSX 2V 2V td(CH-FH) 2V 0.8 V td(CH-DR) 2V DR D15 D14 D13 D9 D8 D7 D6 D7 D6 D2 D1 D0 D1 D0 tsu(DX) Don't Care D15 DX D14 D13 D9 D8 th(DX) D2 td(CH-EL) td(CH-EH) 0.8 V EODR, EODX 2V (a) BYTE-MODE TIMING tc(SCLK) SHIFT CLK 2V 2V 2V 0.8 V 0.8 V 0.8 V td(CH-FH) td(CH-FL) FSX, FSR 2V 2V 0.8 V td(CH-DR) DR D15 D14 D13 D12 D11 D2 D13 D12 D11 D2 D1 D0 tsu(DX) Don't Care DX D15 D14 th(DX) D1 D0 td(CH-EL) EODR, EODX 0.8 V td(CH-EH) 2V (b) WORD-MODE TIMING MSTR CLK td(MH-SL) td(MH-SH) SHIFT CLK (c) SHIFT-CLOCK TIMING Figure 4. Serial Port Timing POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 25 TLC32040C, TLC32040I, TLC32041C, TLC32041I ANALOG INTERFACE CIRCUITS SLAS014E - SEPTEMBER 1987 - REVISED MAY 1995 PARAMETER MEASUREMENT INFORMATION CLK OUT DEN S0, G1 D0 - D15 Valid (a) IN INSTRUCTION TIMING CLK OUT WE SN74LS138 Y1 SN74LS299 CLK D0 - D15 Valid (b) OUT INSTRUCTION TIMING Figure 5. TMS32010 -TLC32040 /TLC32041 Interface Timing 26 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 TLC32040C, TLC32040I, TLC32041C, TLC32041I ANALOG INTERFACE CIRCUITS SLAS014E - SEPTEMBER 1987 - REVISED MAY 1995 TYPICAL CHARACTERISTICS AIC TRANSMIT CHANNEL FILTER 0.3 10 Magnitude 0 0.25 Group Delay Magnitude - dB - 20 0.15 - 30 0.1 See Note B - 40 0.05 - 50 0 0.05 - 60 See Note A - 70 0.1 See Note C - 80 0.15 - 90 0.2 0 1 2 Normalized Frequency - kHz x NOTES: A. B. C. D. Relative Group Delay - ms 0.2 - 10 4 5 3 SCF clock frequency 288 kHz Maximum relative delay (0 Hz to 600 Hz) = 125 s Maximum relative delay (600 Hz to 3000 Hz) = 50 s Absolute delay (600 Hz to 3000 Hz) = 700 s Test conditions are VCC +, VCC -, and VDD within recommended operating conditions, SCF clock f = 288 kHz 2% input = 3-V sinewave, and TA = 25C. Figure 6 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 27 TLC32040C, TLC32040I, TLC32041C, TLC32041I ANALOG INTERFACE CIRCUITS SLAS014E - SEPTEMBER 1987 - REVISED MAY 1995 TYPICAL CHARACTERISTICS TLC32040 AND TLC32041 RECEIVE CHANNEL FILTER 0.35 10 See Note A Magnitude 0.3 - 10 0.25 - 20 0.2 - 30 0.15 - 40 0.1 Group Delay - 50 0.05 - 60 0 - 70 Relative Group Delay - ms Magnitude - dB 0 0.05 See Note B - 80 0.1 See Note C - 90 0.15 0 1 2 Normalized Frequency - kHz x NOTES: A. B. C. D. 3 4 5 SCF clock frequency 288 kHz Maximum relative delay (200 Hz to 600 Hz) = 3350 s Maximum relative delay (600 Hz to 3000 Hz) = 50 s Absolute delay (600 Hz to 3000 Hz) = 1230 s Test conditions are VCC +, VCC -, and VDD within recommended operating conditions, SCF clock f = 288 kHz 2%, input = 3-V sinewave, and TA = 25C. Figure 7 28 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 TLC32040C, TLC32040I, TLC32041C, TLC32041I ANALOG INTERFACE CIRCUITS SLAS014E - SEPTEMBER 1987 - REVISED MAY 1995 TYPICAL CHARACTERISTICS A/D SIGNAL-TO-DISTORTION RATIO vs INPUT SIGNAL A/D GAIN TRACKING (GAIN RELATIVE TO GAIN AT 0-dB INPUT SIGNAL) 80 1-kHz Input Signal 8-kHz Conversion Rate 0.4 0.3 Gain = 4X Gain = 1X 60 Gain Tracking - dB Signal-to-Distortion Ratio - dB 70 0.5 1-kHz Input Signal With an 8-kHz Conversion Rate 50 40 30 0.2 0.1 0 - 0.1 - 0.2 20 - 0.3 10 0 - 50 - 0.4 - 40 - 30 - 20 - 10 0 - 0.5 - 50 10 - 40 Input Signal Relative to Vref - dB Figure 8 0 10 1.0 1-kHz Input Signal into 600 8-kHz Conversion Rate 0.8 80 0.6 70 0.4 Gain Tracking - dB Signal-to-Distortion Ratio - dB - 10 D/A GIAN TRACKING vs (GAIN RELATIVE TO GAIN AT 0 0dB INPUT SIGNAL) 100 60 50 40 30 1-kHz Input Signal into 600 8-kHz Conversion Rate 0.2 0 - 0.2 - 0.4 - 0.6 20 - 0.8 10 0 - 50 - 20 Figure 9 D/A CONVERTER SIGNAL-TO-DISTORTION RATIO vs INPUT SIGNAL 90 - 30 Input Signal Relative to Vref - dB - 40 - 30 - 20 - 10 0 10 -1 - 50 - 40 - 30 - 20 - 10 0 10 Input Signal Relative to Vref - dB Input Signal Relative to Vref - dB Figure 10 Figure 11 NOTE: Test conditions are VCC +, VCC -, VDD and within recommended operating conditions set clock f = 288 kHz 2%, and TA = 25C. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 29 TLC32040C, TLC32040I, TLC32041C, TLC32041I ANALOG INTERFACE CIRCUITS SLAS014E - SEPTEMBER 1987 - REVISED MAY 1995 TYPICAL CHARACTERISTICS ATTENUATION OF THIRD HARMONIC OF A/D INPUT vs INPUT SIGNAL 100 100 90 90 Attenuation of Third Harmonic - dB Attenuation of Second Harmonic - dB ATTENUATION OF SECOND HARMONIC OF A/D INPUT vs INPUT SIGNAL 80 70 60 50 40 30 20 1-kHz Input Signal 8-kHz Conversion Rate 10 0 - 50 1-kHz Input Signal 8-kHz Conversion Rate 80 70 60 50 40 30 20 10 0 - 40 - 30 - 20 - 10 0 - 50 10 - 40 Input Signal Relative to Vref - dB ATTENUATION OF SECOND HARMONIC OF D/A INPUT vs INPUT SIGNAL - 10 0 10 ATTENUATION OF THIRD HARMONIC OF D/A INPUT vs INPUT SIGNAL 100 1-kHz Input Signal into 600 8-kHz Conversion Rate 90 Attenuation of Third Harmonic - dB Attenuation of Second Harmonic - dB 90 - 20 Figure 13 Figure 12 100 - 30 Input Signal Relative to Vref - dB 80 70 60 50 40 30 20 80 70 60 50 40 30 20 10 10 0 - 50 1-kHz Input Signal into 600 8-kHz Conversion Rate 0 0 - 40 - 30 - 20 - 10 Input Signal Relative to Vref - dB 10 - 50 0 - 40 - 30 - 20 - 10 Input Signal Relative to Vref - dB Figure 14 10 Figure 15 NOTE: Test conditions are VCC +, VCC -, and VDD within recommended operating conditions set clock f = 288 kHz 2%, and TA = 25C. 30 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 TLC32040C, TLC32040I, TLC32041C, TLC32041I ANALOG INTERFACE CIRCUITS SLAS014E - SEPTEMBER 1987 - REVISED MAY 1995 APPLICATION INFORMATION TMS32010 SN74LS299 S1 QH G2 DEN G1 A0/PA0 A A1/PA1 B A2/PA2 C S0 Y1 Y0 D8-D15 G1 A-H DX TLC32040/ TLC32041 CLK SR SHIFT CLK SN74LS299 S1 QH G2 SN74LS138 S0 G1 D0-D15 FSX Q 2D C2 CLK D0-D7 A-H D0 - D15 SN74LS74 C1 SR Q 1D DR WE MSTR CLK EODX CLKOUT INT Figure 16. TMS32010 -TLC32040 /TLC32041 Interface Circuit POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 31 TLC32040C, TLC32040I, TLC32041C, TLC32041I ANALOG INTERFACE CIRCUITS SLAS014E - SEPTEMBER 1987 - REVISED MAY 1995 APPLICATION INFORMATION TMS32020/C25 TLC32040 /TLC32041 MSTR CLK CLKOUT FSX FSX DX DX FSR FSR DR DR CLKR VCC + REF ANLG GND 5V C C BAT 42 C VCC - VDD -5 V DGTL GND 0.1 F SHIFT CLK 5V CLKX C = 0.2 F, Ceramic Thomson Semiconductors Figure 17. AIC Interface to the TMS32020/C25 Showing Decoupling Capacitors and Schottky Diode VCC R 3 V Output 500 0.01 F TL431 0.1 F Ceraminc 2500 For: VCC = 12 V, R = 7200 VCC = 10 V, R = 5600 VCC = 5 V, R = 1600 Figure 18. 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