M25P05-AVMN6P - STMicroelectronics

1/42January 2005

M25P05-A

512 Kbit, Low Voltage, Serial Flash Memory

With 50MHz SPI Bus Interface

FEATURES SUMMARY

■512 Kbit of Flash Memory

■Page Program (up to 256 Bytes) in 1.4ms

(typical)

■Sector Erase (256 Kbit) in 1s (typical)

■Bulk Erase (512 Kbit) in 2.5s (typical)

■2.7 to 3.6V Single Supply Voltage

■SPI Bus Compa tib le Se rial Interf ace

■50MHz Clock Rate (m ax im um)

■Deep Power-down Mode 1 µA (typi cal)

■Electronic Signature

– JEDEC Standard two-Byte Signature

(2010h)

– RES Instruction, One-Byte, Signature

(05h), for backward compatibility

■More than 100,000 Erase/Program Cycles per

Sector

■More than 20 Year Data Retention

Figure 1. Packages

SO8 (MN)

150 mil width

VDFPN8 (MP)

(MLP8)

TSSOP8 (DW)

M25P05-A

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TABLE OF CONTENTS

FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Figure 1. Packages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

SUMMARY DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Figure 3. SO, VDFPN and TSSOP Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

SIGNAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Serial Data Output (Q). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Serial Data Input (D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Serial Clock (C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Chip Select (S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Hold (HOLD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Write Protect (W). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6

SPI MODES. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Figure 4. Bus Master and Memory Devices on the SPI Bus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Figure 5. SPI Modes Supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

OPERATING FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Page Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Sector Erase and Bulk Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Polling During a Write, Program or Erase Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Active Power, Standby Power and Deep Power-Down Modes . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

WIP bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

WEL bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

BP1, BP0 bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

SRWD bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Protection Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Table 2. Protected Area Sizes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Hold Condition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Figure 6. Hold Condition Activation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

MEMORY ORGANIZATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Table 3. Memory Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

Figure 7. Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

INSTRUCTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Table 4. Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Write Enable (WREN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Figure 8. Write Enable (WREN) Instruction Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

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M25P05-A

Write Disable (WRDI). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Figure 9. Write Disable (WRDI) Instruction Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Read Identification (RDID) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Table 5. Read Identification (RDID) Data-Out Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Figure 10.Read Identification (RDID) Instruction Sequence and Data-Out Sequence . . . . . . . . . . 15

Read Status Register (RDSR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Table 6. Status Register Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

WIP bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

WEL bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

BP1, BP0 bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

SRWD bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Figure 11.Read Status Register (RDSR) Instruction Sequence and Data-Out Sequence . . . . . . . 16

Write Status Register (WRSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Figure 12.Write Status Register (WRSR) Instruction Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Table 7. Protection Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Read Data Bytes (READ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Figure 13.Read Data Bytes (READ) Instruction Sequence and Data-Out Sequence . . . . . . . . . . . 19

Read Data Bytes at Higher Speed (FAST_READ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Figure 14.Read Data Bytes at Higher Speed (FAST_READ) Instruction Sequence

and Data-Out Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Page Program (PP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Figure 15.Page Program (PP) Instruction Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Sector Erase (SE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Figure 16.Sector Erase (SE) Instruction Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Bulk Erase (BE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Figure 17.Bulk Erase (BE) Instruction Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Deep Power-down (DP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Figure 18.Deep Power-down (DP) Instruction Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Release from Deep Power-down and Read Electronic Signature (RES) . . . . . . . . . . . . . . . . . 25

Figure 19.Release from Deep Power-down and Read Electronic Signature (RES) Instruction

Sequence and Data-Out Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Figure 20.Release from Deep Power-down (RES) Instruction Sequence. . . . . . . . . . . . . . . . . . . . 26

POWER-UP AND POWER-DOWN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Figure 21.Power-up Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Table 8. Power-Up Timing and VWI Threshold. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

INITIAL DELIVERY STATE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Table 9. Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Table 10. Operating Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Table 11. AC Measurement Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Figure 22.AC Measurement I/O Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

M25P05-A

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Table 12. Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Table 13. DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Table 14. Instruction Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Table 15. AC Characteristics (25MHz Operation) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Table 16. AC Characteristics (40MHz Operation) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Table 17. AC Characteristics (50MHz Operation) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Figure 23.Serial Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Figure 24.Write Protect Setup and Hold Timing during WRSR when SRWD=1 . . . . . . . . . . . . . . . 35

Figure 25.Hold Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Figure 26.Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Figure 27.SO8 narrow – 8 lead Plastic Small Outline, 150 mils body width, Package Outline . . . . 37

Table 18. SO8 narrow – 8 lead Plastic Small Outline, 150 mils body width,

Package Mechanical Data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Figure 28.VDFPN8 (MLP8) 8-lead Very thin Dual Flat Package No lead, Package Outline. . . . . . 38

Table 19. VDFPN8 (MLP8) 8-lead Very thin Dual Flat Package No lead,

Package Mechanical Data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Figure 29.TSSOP8 – 8 lead Thin Shrink Small Outline, Package Outline . . . . . . . . . . . . . . . . . . . 39

Table 20. TSSOP8 – 8 lead Thin Shrink Small Outline, Package Mechanical Data . . . . . . . . . . . . 39

PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Table 21. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Table 22. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

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M25P05-A

SUMMARY D ESCRIPTION

The M25P05-A is a 512 Kbit (64K x 8) Serial Flash

Memory, with advanced write protection mecha-

nisms, ac cesse d by a high s peed SPI-co mpatib le

bus.

The memory can be programmed 1 to 256 bytes at

a time, using the Page Program instruction.

The memory is or ga nized as 2 sec tors , eac h c on -

taining 128 pages. Each page is 256 bytes wide.

Thus, the whole memory can be viewed as con-

sisting of 256 pages, or 65,536 bytes.

The whol e memory can be eras ed using th e Bulk

Erase instruction, or a sector at a time, using the

Sector Erase instruction.

Figure 2. Logic Diagram

Figure 3. SO, VDFPN and TSSOP Connections

Note: 1. There is an exposed die paddle on the underside of the

MLP8 package. This is pulled, internally, to VSS, and

must not be allowed to be connec ted to any ot her voltage

or signal li ne on the PCB.

2. See PACKAGE MECHANICAL section for package di-

mensions, and how to identify pin-1.

Table 1. Signal Names

AI05757

VCC

M25P05-A

HOLD

VSS

AI05758B

5DVSS C

HOLDQ

M25P05-A

C Serial Clock

D Serial Data Input

Q Serial Data Output

SChip Select

W Write Protect

HOLD Hold

VCC Supply Voltage

VSS Ground

M25P05-A

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SIGNAL DESCRIPTION

Serial Data Output (Q). This output signal is

used to transfer data serially out of the device.

Data is shifted out on the falling edge of Serial

Clock (C).

Serial Data Input (D). This i nput sig nal is us ed t o

transfer data serially into the device. It receives in-

structions, addresses, and the data to be pro-

grammed. Values are latched on the rising edge of

Serial Clock (C).

Serial Clock (C). This input signal provides the

timing of the serial interface. Instructions, address-

es, or data present at Serial Data Input (D) are

latched on the rising edge of Serial Clock (C). Data

on Serial Data Output (Q) changes after the falling

edge of Serial Clo ck (C) .

Chip Select (S). When this input signal is High,

the device is deselected and Serial Data Output

(Q) is at hi gh impedance. Unl ess an interna l Pro-

gram, Erase or Write Status Register cycle is in

progress, the device will be in the Standby mode

(this is not the Deep Power-down mode). Driving

Chip Select (S) Low ena bl es the devi ce, pla ci ng it

in the Active Power mode.

After Power-up, a falling edge on Chip Select (S)

is required prior to the start of any instruction.

Hold (HOLD). The Hold (HOLD) signal is used to

pause any serial c ommunicatio ns with the dev ice

without deselecting the device.

During the Ho ld condition, the S erial Data Output

(Q) is high impedance, and Serial Data Input (D)

and Serial Clock (C) are Don’t Care.

To start the Hold condition, the device must be se-

lected, with Chip Select (S) driv en Low.

Write Protect (W). The main purpose of this in-

put signal is to freeze the size of the area of mem-

ory that is protected against program or erase

instructions (as specified by the values in the BP1

and BP0 bits of the Status Regis ter) .

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M25P05-A

SPI MODES

These de vices can be dr iven by a m icroco ntroller

with its SPI per ipheral run ning in either of the two

following modes:

– CPOL=0, CPHA=0

– CPOL=1, CPHA=1

For these two modes, input data is latched in on

the rising edge of Serial Clock (C), and output data

is available from the falling edge of Serial Clock

(C).

The difference between the two modes, as shown

in Figure 5., is the clock polarity when the bus

master is in Stand-by mode and not transferring

data:

– C remain s at 0 for (CPOL=0, CPHA=0)

– C remain s at 1 for (CPOL=1, CPHA=1)

Figure 4. Bus Master and Memory Devices on the SPI Bus

Note: 1. The Write Protect (W) and Hold (HOLD) signals sh ould be driven, High or Low as appropriate.

Figure 5. SPI Modes Supported

AI03746D

Bus Master

(ST6, ST7, ST9,

ST10, Others) SPI Memory

Device

SDO

SDI

SCK

CQD

SPI Memory

Device

CQD

SPI Memory

Device

CQD

CS3 CS2 CS1

SPI Interface with

(CPOL, CPHA) =

(0, 0) or (1, 1)

WHOLD WHOLD WHOLD

AI01438B

MSB

CPHA

CPOL

MSB

M25P05-A

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OPERATING FEATURES

Page Programming

To program one data byte, two instructions are re-

quired: Write Enable (WREN), which is one byte,

and a Page Program (PP) sequence, which con-

sists of four bytes plus data. This is followed by the

internal Program cycle (of duration tPP).

To spread this ove rhead, the Pa ge Progr am (PP)

instruction allows up to 256 bytes to be pro-

grammed at a time (changing bits from 1 to 0), pro-

vided that they lie in consecutive addresses on the

same page of memory.

Sector Erase and Bulk Erase

The Page Program (PP) inst ruction allows bits to

be reset from 1 to 0. Before this can be applied, the

bytes of me mory need to h ave been er ased to all

1s (FFh). This can be achieved either a sector at a

time, using the Sector Erase (SE) instruction, or

throughout the entire memory, using the Bulk

Erase (BE) instruction. This starts an internal

Erase cycle (of duration tSE or tBE).

The Erase instruction must be preceded by a Write

Enable (WREN) instruction.

Polling During a Write, Program or Erase Cycle

A further improvement in the time to Write S tatus

BE) can be achieved by not waiting for the worst

case delay (tW, tPP, tSE, or tBE). The Write In

Progress (WIP) bit is provided in the Status Regis-

ter so that the applic ati on progr am can mo nit or its

value, polling it to establish when the previous

Write cy cle, Pr og ra m cy cle or Eras e cycl e is com -

plete.

Active Power, Standby Power and Deep

Power-Down M odes

When Chip Select (S) is Low, the de vi ce is sele c t-

ed, and in the Active Power mode.

When Chip Sel ec t ( S ) is High, the d evic e i s dese-

lect ed, but c ould rema in in the Ac tive Po wer mode

until all inte rnal cy cles have comp leted (Prog ram,

Erase, Write Status Register). The device then

goes in to the Standby Power mode. The device

consumptio n drops to I CC1.

The Deep Power-down mode is entered when the

specific instruction (the Deep Power-down (DP) in-

struction) is executed. The device consumption

drops further to ICC2. The device remains in this

mode until another specific instruction (the Re-

lease from Deep Power-down and Read Electron-

ic Signature (RES) instruction) is executed.

All other instru ctions a re ignored while the device

is in the Deep Power-down mode. This can be

used as an e xtra softwar e protection mechanism,

when the device is not in active use, to protect the

device from inadvertent Write, Program or Erase

instructions.

Status Register

The Status Register contains a number of status

and control bits, as shown in Tabl e 6., that can be

read or set (as appropriate) by specific instruc-

tions.

WIP bit. The Write In Progress (WIP) bit indicates

whether the memory is busy with a Write Status

WEL bit. The Write Enable Latch (WEL) bit indi-

cates the status of the internal Write Enable Latch.

BP1, BP0 bits. The Block Protect (BP1, BP0) bits

are non-volatile. They define the size of the area to

be software protected against Program and Erase

instructions.

SRWD bit. The Status Register Write Disable

(SRWD) bit is operated in conjunction with the

Write Protect (W) signal. The Status Register

Write Disable (SRWD) bit and Write Protect (W)

signal allow the de vice to b e put in the Hardware

Protected mode. In this mode, the non-volatile bits

of the Status Register (SRWD, BP1, BP0) become

read-only bits.

9/42

M25P05-A

Protection Modes

The environments where non-volatile memory de-

vices are used can be very noisy. No SPI device

can operate correctly in the presence of excessive

noise. To help combat this, the M25P05-A fea-

tures the following data protection mechanisms:

■Power On Reset and an internal timer (tPUW)

can provide protection against inadvertant

changes while the power supply is outside the

operati ng sp eci fi ca tio n.

■Program, Erase and Write Status Register

instr ucti ons ar e check ed th at they cons ist of a

number of clock pulses that is a multiple of

eight, before they are accepted for execution.

■All instructions that modify data must be

preceded by a Write Enable (WREN)

instruction to set the Write Enable Latch

(WEL) bit. This bit is returned to its reset state

by the following events:

–Power-up

– Write Disable (WRDI) instruction completion

– Write Status Register (WRSR) instruction

completion

– Page Program (PP) instruction completion

– Sector Erase (SE) instruction completion

– Bulk Erase (BE ) instruction completion

■The Block Protect (BP1, BP0) bits allow part of

the memory to be configured as read-only.

This is the Software Protected Mode (SPM).

■The Write Protect (W) signal, in co-operation

with the Status Register Write Disable

(SRWD) bit, allows the Block Protect (BP1,

BP0) bits and Status Register Write Disable

(SRWD) bit to be write-protected. This is the

Hardware Protected Mode (HPM).

■In addition to the low power consumption

feature, the Deep Power-down mode offers

extra software protection from inadvertant

Write, Program and Erase instructions, as all

instructions are ignored except one particular

instruction (the Release from Deep Power-

down instruction).

Table 2. Protected Area Sizes

Note: 1. The device is ready to accept a Bulk Erase instruction if, and only if, both Block Protect (BP1 , BP0) are 0.

Status Register

Content Memory Content

BP1 Bit BP0 Bit Protected Area Unprotected Area

0 0 none All sectors (Sectors 0 and 1)

0 1 No protection against Page Program (PP) and Sector Erase (SE)

All sectors (Sectors 0 and 1) protected against Bulk Erase (BE)

1 0

1 1 All sectors (Sectors 0 and 1) none

M25P05-A

10/42

Hold Condition

The Hol d ( HO LD) sign al is us ed to pau se any se-

rial communications with the device without reset-

ting the clocking sequence. However, taking this

signal Low does not terminate any Write Status

in progress.

To enter the Hold condition, the device must be

selected, with Chip Select (S) Low.

The Hold condition starts on the falling edge of the

Hold (HOLD) signal, provided that this coincides

with Seri al Cloc k (C) b eing Lo w (as s hown i n Fig-

ure 6.).

The Hold cond ition e nds on the risin g edge of the

Hold (HOLD) signal, provided that this coincides

with Serial Clock (C) being Low.

If the falling edge does not coincide with Serial

Clock (C) be ing Low, th e Hold conditio n starts af -

ter Serial Clock (C) next goes Low. Similarly, if the

rising edge does not coincide with Serial Clock (C)

being Low, the Hold condition ends after Serial

Clock (C) next goes Low. (This is shown in Figure

6.).

During the Ho ld condition, the S erial Data Output

(Q) is high impedance, and Serial Data Input (D)

and Serial Clock (C) are Don’t Care.

Normally, the device is kept selected, with Chip

Select (S) driven Low, for the whole duration of the

Hold condition. This is to ensure that the state of

the internal logic remains unchanged from the mo-

ment of entering the Hold condition.

If Chip Selec t (S) goe s High wh ile the de vic e is in

the Hold con dition, this ha s the effect of re setting

the internal logic of the device. To restart commu-

nication with the device, it is necessary to drive

Hold (HOLD) High, a nd then to drive Chip Select

(S) Low. This prevents the device from going back

to the Hold condition.

Figure 6. Hold Condition Activation

AI02029D

HOLD

Hold

Condition

(standard use)

Hold

Condition

(non-standard use)

11/42

M25P05-A

MEMORY ORGANIZATION

The memory is organized as:

■65,536 bytes (8 bits each)

■2 sectors (256 Kbits, 32768 bytes each)

■256 pages (256 bytes each).

Each page can be individually programmed (bits

are programmed from 1 to 0). The device is Sector

or Bulk Erasable (bits a re erased from 0 to 1 ) but

not Page Erasable.

Table 3. Memory Organization

Figure 7. Block Diagram

Sector Address Range

1 08000h 0FFFFh

0 00000h 07FFFh

AI05759

HOLD

WControl Logic High Voltage

Generator

I/O Shift Register

Address Register

and Counter 256 Byte

Data Buffer

256 Bytes (Page Size)

X Decoder

Y Decoder

Status

00000h

08000h

0FFFFh

000FFh

Size of the

read-only

memory area

M25P05-A

12/42

INSTRUCTIONS

All instr uctions , addresses and data are shifte d in

and out of the device, most significant bit first.

Serial D ata Input (D) is s ample d on the fi rst ri sing

edge of Serial Clock (C) after Chip Select (S) is

driven Low. Then, the one-byte instruction code

must be shifted in to the device, most significant bit

first, on Serial Data Input (D), each bit being

latched on the rising edges of Serial Clock (C).

The instruction set is listed in Table 4.

Every in structio n sequenc e starts with a o ne-byte

instruction code. Depending on the instruction,

this might be followed by address bytes, or by data

bytes, or by both or none. Chip Select (S) must be

driven High after the last bit of th e instruction se-

quence has been shifted in.

In the case of a Read Data Bytes (READ), Read

Data Bytes at Higher Speed (Fast_Read), Read

Status Register (RDSR) or Release from Deep

Power-down, and Read Electronic Signature

(RES) instruction, the shifted-in instruction se-

quence is followed by a data-out sequence. Chip

Select (S) can be driven High after any bit of the

data-out sequence is being shifted out.

In the case of a Page Program (PP), Sector Erase

(SE), Bulk Erase (BE), Write Status Register

(WRSR), Write Enable (WREN), Write Disable

(WRDI) or Deep Power-down (DP) instruction,

Chip Select (S) must be driven High exactly at a

byte bou ndary, otherwis e the instructi on is reject-

ed, and is not executed. That is, Chip Select (S)

must driven High when the number of clock pulses

after Chip S elec t (S) being d ri ven Lo w is an e xa ct

multiple of eigh t.

All attempt s to access th e memory array during a

Write Status Register cycle, Program cycle or

Erase cycle are ignored, and the internal Write

Status Register cycle, Program cycle or Erase cy-

cle continues unaffected.

Table 4. Instruction Set

Note: 1. The Read Identification (RDID) instruction is available only in products with Process Technology code X (see Application Note

AN1995).

Instruction Description One-byte Instruction Code Address

Bytes Dummy

Bytes Data

Bytes

WREN Write Enable 0000 0110 06h 0 0 0

WRDI Write Disable 0000 0100 04h 0 0 0

RDID(1) Read Identification 1001 1111 9Fh 0 0 1 to 3

RDSR Read Status Register 0000 0101 05h 0 0 1 to ∞

WR SR Write Status Re gis ter 0000 000 1 01h 0 0 1

READ Read Data Bytes 0000 0011 03h 3 0 1 to ∞

FAST_READ Read Data Bytes at Higher Speed 0000 1011 0Bh 3 1 1 to ∞

PP Page Program 0000 0010 02h 3 0 1 to 256

SE Sector Erase 1101 1000 D8h 3 0 0

BE Bulk Erase 1100 0111 C7h 0 0 0

DP Deep Power-down 1011 1001 B9h 0 0 0

RES Rele as e f ro m De ep Pow er - do wn ,

and Read Electronic Signature 1010 1011 ABh 0 3 1 to ∞

Release from Deep Power-down 0 0 0

13/42

M25P05-A

Write Enable (WREN)

The Write Enable (WREN) instruction (Figure 8.)

sets the Write Enable Latch (WEL) bit.

The Write Enable Latch (WEL) bit must be set pri-

or to every Page Program (PP), Sector Erase

(SE), Bulk Erase (BE) and Write Status Register

(WRSR) instruction.

The Write Enable (WREN) instruction is entered

by driving Chip Select (S) Low, sending the in-

struction code, and then driving Chip Select (S)

High.

Figure 8. Write Enable (WREN) Instruction Sequence

AI02281E

21 34567

High Impedance

Instruction

M25P05-A

14/42

Write Disable (WRDI)

The Write Disable (WRDI) instruction (Figure 9.)

resets the Write Enable Latch (WEL) bit.

The Write Disable (WRDI) instruction is entered by

driving Chip Select (S) Low, sending the instruc-

tion code, and then driving Chip Select (S) High.

The Write Enable Latch (WEL) bit is reset under

the following conditions:

– Power-up

– Write Disable (WRDI) instruction completion

– Write St atus R egiste r (WRS R) ins tructio n com -

pletion

– Page Program (PP) instruction completion

– Sector Erase (SE) instruction completion

– Bulk Erase (BE) instruction completion

Figure 9. Write Disable (WRDI) Instruction Sequence

AI03750D

21 34567

High Impedance

Instruction

15/42

M25P05-A

Read Identification (RDID)

The Read Identification (RDID) instruction is avail-

able in pro ducts with Proc ess Tec hnolo gy cod e X

only.

The Read Identification (RDID) instruction allows

the 8-bit manufacturer identification to be read, fol-

lowed by two bytes of device identification. The

manufacturer identification is assigned by JEDEC,

and has the value 20h for STMicroelectronics. The

device identification is assigned by the device

manufacturer, and indicates the memory type in

the first byte (20h), and the memory capacity of the

device in the second byte (10h).

Any Read Identification (RDID) instruction while

an Erase or Program cycle is in progress, is not

decoded, and has no effect on the cycle that is in

progress.

The devi ce is first sel ected by driv ing Chip Se lect

(S) Low. Then, the 8-bit instruction code for the in-

struction is shifted in. This is followed by the 24-bit

device identification , stored in the memory, being

shifted out on Serial Data Output (Q), each bit be-

ing shifted out during the falling edge of Serial

Clock (C).

The instruction sequence is shown in Fi gur e 10.

The Read Identification (RDID) instruction is termi-

nated by dr iving Chip Sel ect (S) High at any time

during data output.

When Chip Select (S) is driven High, the device is

put in the Stand-by Power mode. Once in the

Stand-by Power mode , the device waits to be se -

lected, so that it can receive, decode and execute

instructions.

Table 5. Read Identification (RDID) Data-Out Sequence

Figure 10. Read Identification (RDID) Instruction Sequence and Data-Out Sequence

Manufacturer Identification Device Ide nt ific at ion

Memory Type Memory Capacity

20h 20h 10h

21 3456789101112131415

Instruction

AI06809b

Manufacturer Identification

High Impedance

MSB

15 1413 3210

Device Identification

MSB

16 17 18 28 29 30 31

M25P05-A

16/42

Read Status Register (RDSR)

The Read Status Register (RDSR) instruction al-

lows the Status Register to be read. The Status

Program, Erase or Write Status Register cycle is in

progress. When one of these cycles is in progress,

it is reco mmende d to check the Write In P rogr ess

(WIP) bit before sending a new instruction to the

device. It is also possible to read the Status Reg-

ister continuously, as shown in Figure 11.

Table 6. Status Register Format

The statu s and c ontrol bits of the S tatus Register

are as follows:

WIP bit. The Write In Progress (WIP) bit indicates

whether the memory is busy with a Write Status

such a cycle is in progress, when reset to 0 no

such cycle is in progress.

WEL bit. The Write Enable Latch (WEL) bit indi-

cates the status of the internal Write Enable Latch.

When set to 1 the internal Write Enable Latch is

set, when set to 0 t he interna l Wr ite Ena ble Latc h

is reset and no Wr ite Sta tus Regi ster , Program or

Erase instruction is accepted.

BP1, BP0 bits. The Block Protect (BP1, BP0) bits

are non-volatile. They define the size of the area to

be software protected against Program and Erase

instructions. These bits are written with the Write

Status Regis te r (WRS R) inst ruc tio n. Wh en one or

both of the Bloc k Protec t (B P1, BP0) bits i s se t to

1, the rele vant mem ory area (as defined in Table

2.) becomes protected against Page Program

(PP) and Sector Erase (SE) instructions. The

Block Protect (BP 1, BP0) bits can b e written p ro-

vided that the Hardware Protected mode has not

been set. The Bulk Erase (BE) instruction is exe-

cuted if, and only if, both Block Protect (BP1, BP0)

bits ar e 0.

SRWD bit. The Status Register Write Disable

(SRWD) bit is operated in conjunction with the

Write Protect (W) signal. The Status Register

Write Disable (SRWD) bit and Write Protect (W)

signal allow the de vice to b e put in the Hardware

Protected mode (when the Status Register Write

Disable (SRWD) bit is set to 1, and Writ e Protect

(W) is driven Low). In this mode, the non-volatile

bits of the Status Register (SRWD, BP1, BP0) be-

come read-only bits and the Write Status Register

(WRSR) instruction is no longer accepted for exe-

cution.

Figure 11. Read Status Register (RDSR) Instruction Sequence and Data-Out Sequence

b7 b0

SRWD 0 0 0 BP1 BP0 WEL WIP

Status Register Write Protect

Block Protect Bits

Write Enable Latch Bit

Write In Progress Bit

21 3456789101112131415

Instruction

AI02031E

Q76543210

Status Register Out

High Impedance

MSB

76543210

Status Register Out

MSB

17/42

M25P05-A

Write Status Register (WRSR)

The Write Status Reg ister (WRSR ) instructi on al-

lows new values to be written to the Status Regis-

ter. Before it can be accepted, a Write Enable

(WREN) instruction must previously have been ex-

ecuted. After the Write Enable (WREN) instruction

has been de coded and executed , the device sets

the Write Enable Latch (WEL).

The Write Status Register (WRSR) instruction is

entered by driving Chip Select (S) Low, followed

by the instruction code and the data byte on Serial

Data Input (D).

The instruction sequence is shown in Figure 12.

The Write Status Register (WRSR) instruction has

no effect on b6, b5, b4, b1 and b0 of the Status

Chip Select (S) must be driven High after the

eighth bit of the data byte has been latched in. If

not, the Write Status Register (W RSR) instruc tion

is not executed. As soon as Chip Select (S) is dr iv-

en H igh, t he se lf-tim ed Wri te St atus Regist er cycl e

(whose duration is tW) is initiated. While the Write

Status Register cycle is in progress, the Status

Write In Progress (WIP) bit. The Write In Progress

(WIP) bit is 1 during the self-timed Write Status

some unspecified time before the cycle is complet-

ed, the Write Enable Latch (WEL) is reset.

The Write Status Reg ister (WRSR ) instructi on al-

lows the user to change the values of the Block

Protect (BP1, BP0) bits, to define the size of the

area that is to be treat ed as r ead-onl y, as de fined

in Table 2. The Wr ite S tatus Regi ster (WRSR) in -

struction also allows the user to set or reset the

Status Register Write Disable (SRWD) bit in ac-

cordance with the Write Protect (W) signal. The

Status Register Write Disable (SRWD) bit and

Write Protect (W) signal allow the device to be put

in the Hardware Protected Mode (HPM). The Write

Status Reg is ter ( W RS R) in str uct ion is no t e xe cut -

ed once the Hardware Protected Mode (HPM) is

entered.

The prote ction featu res of the devi ce are summa -

rized in T ab le 7.

When the Status Register Write Disable (SRWD)

bit of the Status Register is 0 (its initial delivery

state), it is possi bl e to w ri te to the S tatu s Re gi ste r

provided that the Write Enable Latch (WEL) bit has

previously been set by a Write Enable (WREN) in-

struction, regardless of the whethe r Write Prote ct

(W) is driven High or Low.

When the Status Register Write Disable (SRWD)

bit of the Status Register is set to 1, two cases

need to be cons idered, de pending on the sta te of

Write Protect (W):

– If Write Prote ct ( W ) is driven High, it is possible

to write to the St at us R egi ste r pro vide d tha t the

Write Enable Latch (WEL) bit has previously

been set by a Write Enable (WREN) instruction.

– If Writ e Protect ( W) is driven Low, it is

not

pos-

sible to write to the Status Register

even

if the

Write Enable Latch (WEL) bit has previously

been set by a Write Enable (WREN) instruction.

(Attempts to write to the Status Register are re-

jected, and are not accepted for execution) . As

a consequence, all the data bytes in the memo-

ry area that are software protected (SPM) by the

Block Protect (BP1, BP0) bits of the Sta tus Reg-

ister, ar e also hardwa re protected a gainst data

modification.

Regardless of the order of the two events, the

Hardware Protected Mode (HPM) can be entered:

– by setting the Status Register Write Disable

(SRWD) bit after driving Write Protect (W) Low

– or by driving Write Protect (W) Low after setting

the Status Register Write Disable (SRWD) bit.

The only way to exit the Hardware Protected Mode

(HPM) once entered is to pull Write Protect (W)

High.

If Write Protect (W) is permanently tied High, the

Hardware Protected Mode (HPM) can never be

activated, and only the Software Protected Mode

(SPM), using the Blo ck Prote ct (BP1, BP 0) bits of

the Status Register, can be used.

M25P05-A

18/42

Figure 12. Write Status Register (WRSR) Instruction Sequence

Table 7. Protection Modes

Note: 1. As defined by the values in the Block Protect (BP1, BP0) bi ts of the Status Register, as shown in Table 2.

Signal SRWD

Bit Mode Write Protection of the Status Register Memory Content

Protected Area(1) Unpro te cted Are a(1)

Software

Protected

(SPM)

Status Register is Writable (if the WREN

instruction has set the WEL bit)

The val ues in th e SRWD , BP1 and BP 0 bit s

can be changed

Protected against

Page Pr ogram, S ector

Erase and Bulk Erase

Ready to accept Page

Program and Sector

Erase instructions

Hardware

Protected

(HPM)

Status Register is Hardware write protected

The value s in the SRWD BP1 and BP0 bits

cannot be ch anged

Protected against

Page Pr ogram, S ector

Erase and Bulk Erase

Ready to accept Page

Program and Sector

Erase instructions

AI02282D

21 3456789101112131415

High Impedance

Instruction Status

765432 0

MSB

19/42

M25P05-A

Read Data Bytes (READ)

The devi ce is first sel ected by driv ing Chip Se lect

(S) Low. The instruction code for the Read Data

Bytes (READ) instruction is followed by a 3-byte

address (A23-A0), each bit being latched-in during

the rising edge of Serial Clock (C). Then the mem-

ory contents, at that address, is shifted out on Se-

rial Data Out put (Q ), each bi t being shifte d out, at

a maximum frequency fR, during the falling edge of

Serial Clock (C).

The instruction sequence is shown in Figure 13.

The first byte addressed can be at any location.

The address is automatically incremented to the

next higher address after each byte of data is shift-

ed out. The whole memory can, therefore, be read

with a single Read Data Bytes (READ) instruction.

There is no address roll-over; when the highest

address (0FFFFh) is reached, the instruction

should be terminated.

The Read Data By tes (RE AD ) in struc ti on is term i-

nat ed by dri ving Ch ip Se le ct ( S) High. Chip Select

(S) can be driven High at any time during data out-

put. Any Read Data Bytes (READ) instruction,

while an Erase, Program or Write cycle is in

progress, is rejected without having any effects on

the cycle that is in progress.

Figure 13. Read Data Bytes (READ) Instruction Sequence and Data-Out Sequence

Note: 1. Address bits A23 to A16 must be set to 00h.

AI03748D

21 345678910 2829303132333435

2221 3210

36 37 38

76543 1 7

High Impedance Data Out 1

Instruction 24-Bit Address

MSB

Data Out 2

M25P05-A

20/42

Read Data Bytes at Higher Speed

(FAST_READ)

The devi ce is first sel ected by driv ing Chip Se lect

(S) Low. The instruction code for the Read Data

Bytes at Higher Speed (FAST_READ) instruction

is followed by a 3-byte address (A23-A0) and a

dummy byte, each bit be ing latched-in during the

rising edge of S erial Cloc k (C). The n the memory

contents, at that address, is shifted out on Serial

Data Output (Q), each bit being shifted out, at a

maximum frequency fC, du ring the falling edge of

Serial Clock (C).

The instruction sequence is shown in Figure 14.

The first byte addressed can be at any location.

The address is automatically incremented to the

next higher address after each byte of data is shift-

ed out. The whole memory can, therefore, be read

with a single Read Data Bytes at Higher Speed

(FAS T_READ) instruction.

There is no address roll-over; when the highest

address (0FFFFh) is reached, the instruction

should be terminated.

The Read Data Bytes at Higher Speed

(FAST_READ) instruction is terminated by driving

Chip Select (S) High. Chip Select (S) can be driv-

en High at any tim e du ring d ata o utput. Any Re ad

Data Bytes at Higher Speed (FAST_READ) in-

struction, while an E rase, Program or Write cycle

is in progress, is rejected without having any ef-

fects on the cycle that is in progress.

Figure 14. Read Data Bytes at Higher Speed (FAST_READ) Instruction Sequence

and Data-Out Sequence

Note: 1. Address bits A23 to A16 must be set to 00h.

AI04006

21 345678910 28293031

2221 3210

High Impedance

Instruction 24 BIT ADDRESS

32 33 34 36 37 38 39 40 41 42 43 44 45 46

765432 0

DATA OUT 1

Dummy Byte

MSB

76543210

DATA OUT 2

MSB MSB

765432 0

21/42

M25P05-A

Page Program (PP)

The Page Program (PP) instruction allows bytes to

be programmed in the memory (changing bits from

1 to 0). B efo re i t c an be a cc ep ted, a W rite E nab le

(WREN) instruction must previously have been ex-

ecuted. After the Write Enable (WREN) instruction

has been decoded, th e device sets the W rite En-

able Latch (WEL).

The Page Program (PP) instruction is entered by

driving Chip Select (S) Low, followed by the in-

struction code, three address bytes and at least

one data byte on Serial Data Input (D). If the 8

least significant address bits (A7-A0) are not all

zero, all transmitted data that goes beyond the end

of the current page are programmed from the start

address of the same page (from the address

whose 8 least significant bits (A7-A0) are all zero).

Chip Se lect (S) m ust be driven Low for the entire

duration of the sequence.

The instruction sequence is shown in Figure 15.

If more than 256 bytes are sent to the device, pre-

viously latched data are discarded and the last 256

data bytes are guaranteed to be programmed cor-

rectly wi thi n th e sam e page . If less than 256 Data

bytes are sent to device, they are correctly pro-

grammed at the requested addresses without hav-

ing any effects on the other bytes of the same

page.

Chip Select (S) must be driven High after the

eighth bit of the last data byte has been latched in,

otherwise the Page Program (PP) instruction is not

executed.

As soon as Chi p Select (S) is driven High, the self-

timed Page Program cycle (whose duration is tPP)

is initiated. While the Page Program cycle is in

progress, the Status Register may be read to

check the value of the Write In Progress (WIP) bit.

The Write In Progress (WIP) bit is 1 during the self-

timed Page Program cycle, and is 0 when it is

completed. At some unspecified time before the

cycle is completed, the Write Enable Latch (WEL)

bit is reset.

A Page Program (PP) instruction applied to a page

which is protected by the Block Protect (BP1, BP0)

bits (see Table 3. and Table 2.) is not executed.

Figure 15. Page Program (PP) Instruction Se quence

Note: 1. Address bits A23 to A16 must be set to 00h.

AI04082B

4241 43 44 45 46 47 48 49 50 52 53 54 5540

21 345678910 2829303132333435

2221 3210

36 37 38

Instruction 24-Bit Address

765432 0

Data Byte 1

765432 0

Data Byte 2

765432 0

Data Byte 3 Data Byte 256

2079

2078

2077

2076

2075

2074

2073

765432 0

2072

MSB MSB

MSB MSB MSB

M25P05-A

22/42

Sector Erase (SE)

The Sect or Erase ( SE) ins truction s ets to 1 (FFh)

all bits inside the ch osen sector. Before it can be

accepted, a Write Enable (WREN) instruction

must previously have been executed. After the

Write Enable (WREN) instruction has been decod-

ed, the device sets the Write Enable Latch (WEL).

The Sector Erase (SE) instruction is entered by

driving Chip Select (S) Low, followed by the in-

struction c ode, and th ree addres s bytes on S erial

Data Input (D). Any address inside the Sector (see

Table 3.) is a valid address for the Sector Erase

(SE) instruction. Chip Select (S) must be driven

Low for the entire duration of the sequence.

The instruction sequence is shown in Figure 16.

Chip Select (S) must be driven High after the

eighth bit of the last address byte has been latched

in, otherwise the Sector Erase (SE) instruction is

not executed. As soon as Chip Select (S) is driven

High, the self-timed Sector Erase cycle (whose du-

ration is tSE) is initiated. While the Sector Erase cy-

cle is in progress, the Status Register may be read

to check the v alue of the Write In P rogress (WIP )

bit. The Write In Progress (WIP) bit is 1 during the

self-timed Sector Erase cycle, and is 0 when it is

completed. At some unspecified time before the

cycle is completed, the Write Enable Latch (WEL)

bit is reset.

A Sector Erase (SE) instruc tion a pplie d to a pa ge

which is protected by the Block Protect (BP1, BP0)

bits (see Table 3. and Table 2.) is not executed.

Figure 16. Sector Erase (SE) Instruction Sequence

Note: 1. Address bits A23 to A16 must be set to 00h.

24 Bit Address

AI03751D

21 3456789 293031

Instruction

23 22 2 0

MSB

23/42

M25P05-A

Bulk Erase (BE)

The Bulk Erase (BE) instruction sets all bits to 1

(FFh). Before it can be accepted, a Write Enable

(WREN) instruction must previously have been ex-

ecuted. After the Write Enable (WREN) instruction

has been decoded, th e device sets the W rite En-

able Latch (WEL).

The Bulk Erase (BE) instruction is entered by driv-

ing Chip Select (S) Low, followed by the instruction

code on Serial Data Input (D). Chip Select (S)

must be driven Low for the entire duration of the

sequence.

The instruction sequence is shown in Figure 17.

Chip Select (S) must be driven High after the

eighth bit of the instruction code has been latched

in, otherwise the Bulk Erase instruction is not exe-

cuted. As soon as Chip S elect (S) is dr iven High,

the self-timed Bulk Erase cycle (whose duration is

tBE) is initiated. While the Bulk Erase cycle is in

progress, the Status Register may be read to

check the value of the Write In Progress (WIP) bit.

The Write In Progress (WIP) bit is 1 during the self-

timed Bulk Erase cycle, and is 0 when it is com-

pleted. At som e un specifi ed ti me bef ore the cyc le

is compl eted, the Write E nable Latc h (WEL) bit i s

reset.

The Bulk Erase (BE) instruction is executed only if

both Block Protect (BP1, BP0) bits are 0. The Bulk

Erase (BE) instruction is ignored if one, or more,

sectors are protected.

Figure 17. Bulk Erase (BE) Instruction Sequence

AI03752D

21 345670

Instruction

M25P05-A

24/42

Deep Power-down (DP)

Executing the Deep Power -down (DP) instruction

is the only way to put the device in the lowest con-

sumption mode (the Deep Power-down mode). It

can also be used as an extra software protection

mechanism, while the device is not in active use,

since in this mode, the device ignores all Write,

Program and Erase instructions.

Drivi n g Ch ip Sele ct (S) High deselects the device,

and puts the d evice i n the Stan dby mode ( if there

is no internal cycle currently in progress). But this

mode is not the Deep Power-down mode. The

Deep Power-down mode can only be entered by

executin g the Dee p Power -down (DP) instruc tion,

subsequently reducing the standby current (from

ICC1 to ICC2, as specified in Ta ble 13.).

Once the device has entered the Deep Power-

down mode, all instructions are ignored except the

Release from Deep Powe r-down a nd Read Elec-

tronic Signature (RES) instruction. This releases

the device from this mode. The Release from

Deep Power-down and Read Electronic Signature

(RES) ins truct ion al so allo ws the Elec troni c Sign a-

ture of the device to be output on Serial Data Out-

put (Q).

The Deep Power-down mode au tomatical ly stops

at Power-down, and the device always Powers-up

in the Standby mode.

The Deep Power-down (DP) instruction is entered

by driving Chip Select (S) Low, followed by the in-

struction code on Serial Data Input (D). Chip Se-

lect (S) mu st be dri ven Low f or the e ntire duration

of the sequence.

The instruction sequence is shown in Fi gur e 18.

Chip Select (S) must be driven High after the

eighth bit of the instruction code has been latched

in, otherwise the Deep Power-down (DP) instruc-

tion is not executed. As soon as Chip Select (S) is

driven High, it requires a delay of tDP before the

supply current is reduced to ICC2 and the Deep

Power-down mode is entered.

Any Deep Power-down (DP) instruction, while an

Erase, Program or Write cycle is in progress, is re-

jected without having any effects on the cycle that

is in progress.

Figure 18. Deep Power-down (DP) Instruction Sequence

AI03753D

21 345670tDP

Deep Power-down Mode

Stand-by Mode

Instruction

25/42

M25P05-A

Release from Deep Power-down and Read

Electronic Signature (RES)

Once the device has entered the Deep Power-

down mode, all instructions are ignored except the

Release from Deep Powe r-down a nd Read Elec-

tronic Signature (RES) instruction. Executing this

instruct ion takes the de vice out of the Deep Pow-

er-down mode.

The instruction can also be used to read, on Serial

Data Output (Q), the 8-bit Electronic Signature,

whose value for the

M25P05-A

05h

Except while an Erase, Program or Write Status

Deep Power-down and Read Electronic Signature

(RES) instruction always provides access to the 8-

bit Electron ic Signa ture of the devic e, and can be

applied even if the Deep Power-down mode has

not been entered.

Any Release from Deep Power-down and Read

Electronic Signature (RES) instruction while an

Erase, Program or Write Status Register cycle is in

progress, is not decoded, and has no effect on the

cycle that is in progress.

The devi ce is first sel ected by driv ing Chip Se lect

(S) Low. The instruction code is followed by 3

dummy bytes, each bit being latched-in on Serial

Data Input (D) during the rising edge of Serial

Clock (C). Then, the 8-bit Electronic Signature,

st ored in th e memo ry , is shift ed o ut on Seri al Da ta

Output (Q), each bit being shifted out during the

falling edge of Serial Clock (C).

The instruction sequence is shown in Figure 19.

The Release from Deep Power-down and Read

Electronic Signature (RES) instruction is terminat-

ed by driving Chip Select (S) High after th e Elec-

tronic Signature has been read at least once.

Sending additional clock cycles on Serial Clock

(C), while Chip Select (S) is dr iven Lo w, ca us e the

Electronic Signature to be output repeatedly.

When Chip Select (S) is driven High, the device is

put in the Standby Power mode. If the device was

not previously in the Deep Power-down mode, the

transition to the Standby Power mode is immedi-

ate. If the device was previously in the Deep Pow-

er-down mode, though, the transition to the

Standby Power mode is delayed by tRES2, and

Chip Select (S) must remain High for at least

tRES2(max), as sp ecified in Table 15. Once in t he

Standby Power mode, the device waits to be se-

lected, so that it can receive, decode and execute

instructions.

Drivi ng Ch ip Sele ct (S ) High after the 8-bit inst ruc-

tion byte has been received by the device, but be-

fore the whole of the 8-bit Electronic Signature has

been transmitted for the first time (as shown in Fig-

ure 20.), still ensures that the device is put into

Standby Power mode. If the device was not previ-

ously in the Deep Power-down mode, the transi-

tion to the Standby Power mode is immediate. If

the device was previously in the Deep Power-

down mode, though , the transition to the Sta ndby

Power mode is delayed by tRES1, and Chip Sele ct

(S) must remain High for at least tRES1(max), as

specified in Table 15. Once in the Standby Power

mode, the device waits to be selected, so that it

can receive, decode and execute instructions.

Figure 19. Release from Deep Power-down and Read Electronic Signature (RES) Instruction

Sequence and Data-Out Sequence

Note: The value of the 8-bit Electronic Si gnature, for t he M25P05-A, is 05h.

AI04047C

21 345678910 2829303132333435

2221 3210

36 37 38

765432 0

High Impedance Electronic Signature Out

Instruction 3 Dummy Bytes

MSB

Stand-by Mode

Deep Power-down Mode

MSB

tRES2

M25P05-A

26/42

Figure 20. Release from Deep Power-down (RES) Instruction Sequence

AI04078B

21 345670tRES1

Stand-by Mode

Deep Power-down Mode

QHigh Impedance

Instruction

27/42

M25P05-A

POWER-UP AND POWER-DOWN

At Power-up and Power-down, the device must

not be selected (that is Chip Select (S) must follow

the voltage applied on VCC) until VCC reac hes the

correct value:

–V

CC(min) at Power-up, and then for a further de-

lay of tVSL

–V

SS at Power-down

Usually a simple pull-up resistor on Chip Select (S)

can be used to ensure sa fe and proper Po wer-up

and Power-d own.

To avoid data corruption and inadvertent write

operations during power-up, a Power On Reset

(POR) circuit is included. The logic inside the

device is held reset while VCC is less than the

Power On Reset (POR) threshold voltage, VWI –

all operations are disabled, and the device does

not respond to any instruction.

Moreover, the device ignores all Write Enable

(WREN), Page Pr ogram (P P), Secto r Erase (SE) ,

Bulk Erase (BE) and Write Status Register

(WRSR) instructions until a time delay of tPUW has

elapsed after the moment that VCC rises above the

VWI threshold. However, the correct operation of

the device is not guaranteed if, by this time, VCC is

still below VCC(min). No Write Status Register,

Program or Erase instructions should be sent until

the later of:

–t

PUW after VCC passed the VWI threshold

–t

VSL after VCC passed the VCC(min) level

These values are specified in Table 8.

If the delay, tVSL, has elapsed, after VCC has rise n

above VCC(min), the device can be selected for

READ instructions even if the tPUW delay is not yet

fully elapsed.

At Power-up, the device is in the following state:

– The device is in the Standby mode (not the

Deep Power-down mode).

– The Write Enable Latch (WEL) bit is reset.

Normal precautions must be taken for supply rail

decoupling, to stabilize the VCC supply. Each

device in a system should have the VCC rail

decoupled by a suitable capacitor close to the

package pins. (Generally, this capacitor is of the

order of 0.1µF).

At Power-down, when VCC drops from the

operating voltage, to below the Power On Reset

(POR) threshold voltage, VWI, all operations are

disabled and the device does not respond to any

instruct ion. (The designer n eeds to be aware that

if a Power-do wn occu rs while a Wr it e, Pr ogram or

Erase cycle is in progress, some data corruption

can result.)

Figure 21. Power-up Timing

VCC

AI04009C

VCC(min)

VWI

Reset State

of the

Device

Chip Selection Not Allowed

Program, Erase and Write Commands are Rejected by the Device

tVSL

tPUW

time

Read Access allowed Device fully

accessible

VCC(max)

M25P05-A

28/42

Table 8. Power-Up Timing and VWI Threshold

Note: 1. These parameters are characterized only.

INITIAL DELIVERY STATE

The device is delivered with the memory array

erased: all bits are set to 1 (each byte contains FFh). The Status Register contains 00h (all Status

Symbol Parameter Min. Max. Unit

tVSL(1) VCC(min) to S low 10 µs

tPUW(1) Time delay to Write instruction 1 10 ms

VWI(1) Write Inhibit Voltage 1 2 V

29/42

M25P05-A

MAXIMUM RATING

Stressing the dev ice above the ratin g lis ted in the

Absolute Maximum Ratings" table may cause per-

manent damage to the device. These are stress

ratings only and operation of the device at these or

any other cond itions above thos e indicated i n the

Operating sections of this specification is not im-

plie d. Exposu re to Abso lute Max imum Rat ing con-

ditions for extended periods may affect device

reliability. Refer also to the STMicroelectronics

SURE Program and other relevant quality docu-

ments.

Table 9. Absolute Maximum Ratings

Note: 1. Compliant with the JEDEC Std J-STD-020C (for small body, Sn-Pb or Pb assembly), the ST ECOPACK® 7191395 specification,

and the European directive on Restrictions on Hazardous Substances (RoHS) 2002/95/EU.

2. JEDEC Std JESD22-A 114A (C1=100 pF, R1=1500 Ω, R2=500 Ω)

Symbol Parameter Min. Max. Unit

TSTG Storage Tempera ture –65 150 °C

TLEAD Lead Temperature during Soldering (1) °C

VIO Input and Output Voltage (with respect to Ground) –0.6 4.0 V

VCC Supply Voltage –0.6 4.0 V

VESD Elect ros tatic Dis ch arg e Voltage (Human Body mode l) 3–2000 2000 V

M25P05-A

30/42

DC AND AC PARA METERS

This section summarizes the operating and mea-

suremen t cond itions, and the D C and A C ch arac -

teristics of the device. The parameters in the DC

and AC Characteristic tables that follow are de-

rived from tests performed under the Measure-

ment Conditions summarized in the relevant

tables. De si gne rs s ho uld c heck tha t th e op er ati ng

conditio ns in their circ uit match the meas urement

conditions when relying on the quoted parame-

ters.

Table 10. Operating Conditions

Table 11. AC Measurement Conditions

Note: 1. Output Hi-Z is defined as the point where data out is no longer driv en.

Figure 22. AC Measurement I/O Waveform

Table 12. Capacitance

Note: Sampled only, no t 100% tested , at TA=25°C and a frequency of 20 MHz.

Symbol Parameter Min. Max. Unit

VCC Supply Voltage 2.7 3.6 V

TAAmbient Operating Temperature –40 85 °C

Symbol Parameter Min. Max. Unit

CLLoad Capacitance 30 pF

Input Rise and Fall Times 5 ns

Input Pulse Voltages 0.2VCC to 0.8VCC V

Input Timing Reference Voltages 0.3VCC to 0.7VCC V

Output Timing Reference Voltages VCC / 2 V

Symbol Parameter Test Condition Min.Max.Unit

COUT Outp ut Ca pa cita nc e (Q) VOUT = 0V 8 pF

CIN Input Capacitance (other pins) VIN = 0V 6 pF

AI07455

0.8VCC

0.2VCC

0.7VCC

0.3VCC

Input and Output

Timing Reference Levels

Input Levels

0.5VCC

31/42

M25P05-A

Table 13. DC Characteristics

Table 14. Instruction Times

Symbol Parameter Test Cond itio n

(in addition to those in Table 10.)Min. Max. Unit

ILI Input Leakage Current ± 2 µA

ILO Output Leakage Current ± 2 µA

ICC1 Standby Current S = VCC, VIN = VSS or VCC 50 µA

ICC2 Deep Power-down Current S = VCC, VIN = VSS or VCC 5µA

ICC3 Operating Current (READ)

C=0.1V

CC / 0.9.VCC at 40MHz,

Q = open 8mA

C=0.1V

CC / 0.9.VCC at 20MHz,

Q = open 4mA

ICC4 Operating Current (PP) S = VCC 15 mA

ICC5 Operatin g Current (WRSR) S = VCC 15 mA

ICC6 Operating Current (SE) S = VCC 15 mA

ICC7 Operating Current (BE) S = VCC 15 mA

VIL Input Low Voltage – 0.5 0.3VCC V

VIH Input High Voltage 0.7VCC VCC+0.4 V

VOL Output Low Voltage IOL = 1.6 mA 0.4 V

VOH Output High Voltage IOH = –100 µAV

CC–0.2 V

Test conditions specified in Table 10. and Table 11.

Symbol Alt. Parameter Min. Typ. Max. Unit

tWWrite Status Register Cycle Time 5 15 ms

tPP Page Program Cycle Time 1.4 5 ms

tSE Sector Erase Cycle Time 0.8 3 s

tBE Bulk Erase Cycle Time 2.5 6 s

M25P05-A

32/42

Table 15. AC Characteristics (25MHz Operation)

Note: 1. tCH + tCL must be greater than or equal to 1/ fC

2. Value guar anteed by characterization, not 100% tested in production .

3. Expressed as a slew-rate.

4. Only applic able as a constraint for a WRSR instruction when SRWD is set at 1.

Test conditions specified in Table 10. and Table 11.

Symbol Alt. Parameter Min. Typ. Max. Unit

fCfCClock Frequency for the following instructions: F AST_READ,

PP, SE, BE, DP, RES, WREN, WRDI, DSR, WRSR D.C. 25 MHz

fRClock Frequency for READ instructions D.C. 20 MHz

tCH (1) tCLH Clock High Time 18 ns

tCL (1) tCLL Clock Low Time 18 ns

tCLCH (2) Clock Rise Time3 (peak to peak) 0.1 V/ns

tCHCL (2) Clock Fall Time3 (pea k to pe ak) 0.1 V/ns

tSLCH tCSS S Active Setup Time (relative to C) 10 ns

tCHSL S Not Active Hold Time (relative to C) 10 ns

tDVCH tDSU Data In Setup Time 5 ns

tCHDX tDH Data In Hold Time 5 ns

tCHSH S Active Hold Time (relative to C) 10 ns

tSHCH S Not Active Se tup Time (relativ e to C) 10 ns

tSHSL tCSH S Dese lec t Time 100 ns

tSHQZ (2) tDIS O utp ut Dis ab le Time 15 ns

tCLQV tVClock Low to Output Valid 15 ns

tCLQX tHO Outp ut Ho ld Time 0 ns

tHLCH HOLD Setup Time (relative to C) 10 ns

tCHHH HOLD Hol d Time (relative to C) 10 ns

tHHCH HOLD Setup Time (relative to C) 10 ns

tCHHL HOL D Hol d Time (relative to C) 10 ns

tHHQX (2) tLZ HOLD to Output Low-Z 15 ns

tHLQZ (2) tHZ HOLD to Output High-Z 20 ns

tWHSL (4) Write Protect Setup Time 20 ns

tSHWL (4) Write Pro te ct Ho ld Time 100 ns

tDP (2) S High to Deep Powe r-d ow n Mo de 3 µs

tRES1 (2) S High to Standb y Mo de without Ele ctr on ic Sig na tur e Rea d 3 µs

tRES2 (2) S High to Standb y Mo de with Electro ni c Sign at ure Rea d 1.8 µs

33/42

M25P05-A

Table 16. AC Characteristics (40MHz Operation)

Note: 1. tCH + tCL must be greater than or equal to 1/ fC

2. Value guar anteed by characterization, not 100% tested in production .

3. Expressed as a slew-rate.

4. Only applic able as a constraint for a WRSR instruction when SRWD is set at 1.

5. Details of how to find the date of marking are given in Application Note,

AN1995

40MHz available for products marked since week 20 of 2004, only(5)

Test conditions specified in Table 10. and Table 11.

Symbol Alt. Parameter Min. Typ. Max. Unit

fCfCClock Frequency for the following instructions:

FAST_READ, PP, SE, BE, DP, RES,

WREN, WRDI, RDSR, WRSR D.C. 40 MHz

fRClock Frequency for READ instructions D.C. 20 MHz

tCH (1) tCLH Clock High Time 11 ns

tCL (1) tCLL Clock Lo w Time 11 ns

tCLCH (2) Clo ck Ris e Time3 (peak to peak) 0.1 V/ns

tCHCL (2) Clo ck Fa ll Time3 (peak to peak) 0.1 V/ns

tSLCH tCSS S Active Setup Time (relative to C) 5 ns

tCHSL S Not Active Hold Time (relative to C) 5 ns

tDVCH tDSU Data In Setup Time 2 ns

tCHDX tDH Data In Hold Time 5 ns

tCHSH S Active Hold Time (relative to C) 5 ns

tSHCH S Not Active Setup Time (relative to C) 5 ns

tSHSL tCSH S Deselect Time 100 ns

tSHQZ (2) tDIS Output Disable Time 9 ns

tCLQV tVClock Low to Output Valid 9 ns

tCLQX tHO Output Hold Time 0 ns

tHLCH HOLD Setup Time (relative to C) 5 ns

tCHHH HOLD Hold Time (relative to C) 5 ns

tHHCH HOLD Setup Time (relative to C) 5 ns

tCHHL HOLD Hold Time (relative to C) 5 ns

tHHQX (2) tLZ HOLD to Output Low-Z 9 ns

tHLQZ (2) tHZ HOLD to Output High-Z 9 ns

tWHSL (4) Write Protect Setup Time 20 ns

tSHWL (4) Write Protect Hold Time 100 ns

tDP (2) S High to Deep Power-down Mode 3 µs

tRES1 (2) S High to Standby Mode without Electronic Signature Read 3 µs

tRES2 (2) S High to Standby Mode with Electronic Signature Read 1.8 µs

M25P05-A

34/42

Table 17. AC Characteristics (50MHz Operation)

Note: 1. tCH + tCL must be greater than or equal to 1/ fC

2. Value guar anteed by characterization, not 100% tested in production .

3. Expressed as a slew-rate.

4. Only applic able as a constraint for a WRSR instruction when SRWD is set at 1.

5. Details of how to find the process on the device marking are given in Application Note AN1995.

50MHz available only in p roducts with Process Technology code X(5)

Test con di tions spec ifie d in Table 10. and Table 11.

Symbol Alt. Parameter Min. Typ. Max. Unit

fCfCClock Frequency(1) for the following instructions:

FAST_READ, PP, SE, BE, DP, RES, WREN, WRDI,

RDID, RDSR, WRSR D.C. 50 MHz

fRClock Frequency for READ instructions D.C. 20 MHz

tCH (1) tCLH Clock High Time 9 ns

tCL (1) tCLL Clock Low Time 9 ns

tCLCH (2) Clock Rise Time3 (pea k to pe ak) 0.1 V/ns

tCHCL (2) Clock Fall Time3 (peak to peak) 0.1 V/ns

tSLCH tCSS S Active Setup Time (relative to C) 5 ns

tCHSL S Not Active Hold Time (relative to C) 5 ns

tDVCH tDSU Data In Setup Time 2 ns

tCHDX tDH Data In Hold Time 5 ns

tCHSH S Active Hold Time (relative to C) 5 ns

tSHCH S Not Active Setup Time (relative to C) 5 ns

tSHSL tCSH S Deselect Time 100 ns

tSHQZ (2) tDIS Output Disable Time 8 ns

tCLQV tVClock Low to Output Valid 8 ns

tCLQX tHO Output Hold Time 0 ns

tHLCH HOLD Setup Time (relative to C) 5 ns

tCHHH HOLD Hold Time (relative to C) 5 ns

tHHCH HOLD Setup Time (relative to C) 5 ns

tCHHL HOLD Hold Time (relative to C) 5 ns

tHHQX (2) tLZ HOLD to Output Low-Z 8 ns

tHLQZ (2) tHZ HOLD to Output High-Z 8 ns

tWHSL (4) Write Protect Setup Time 20 ns

tSHWL (4) Write Protect Hold Time 100 ns

tDP (2) S High to Deep Power-down Mode 3 µs

tRES1 (2) S High to Standby Mode without Electronic Sig n ature

Read 30 µs

tRES2 (2) S High to Standby Mode with Electronic Signature Read 30 µs

35/42

M25P05-A

Figure 23. Serial Input Timing

Figure 24. Write Protect Setup and Hold Timing during WRSR when SRWD=1

AI01447C

MSB IN

tDVCH

High Impedance

LSB IN

tSLCH

tCHDX

tCHCL

tCLCH

tSHCH

tSHSL

tCHSHtCHSL

High Impedance

tWHSL tSHWL

AI07439

M25P05-A

36/42

Figure 25. Hold Timing

Figure 26. Output Timing

AI02032

HOLD

tCHHL

tHLCH

tHHCH

tCHHH

tHHQXtHLQZ

AI01449D

LSB OUT

ADDR.LSB IN

tSHQZ

tCH

tCL

tQLQH

tQHQL

tCLQX

tCLQV

tCLQX

tCLQV

37/42

M25P05-A

PACKAGE MECHANICAL

Figure 27. SO8 narrow – 8 lead Plastic Small Outline, 150 mils body width, Package Outline

Note: Drawing is not to scale.

Table 18. SO8 narrow – 8 lead Plastic Small Outline, 150 mils body width,

Package Mechanical Data

Symbol millimeters inches

Typ. Min. Max. Typ. Min. Max.

A 1.35 1.75 0.053 0.069

A1 0.10 0.25 0.004 0.010

B 0.33 0.51 0.013 0.020

C 0.19 0.25 0.007 0.010

D 4.80 5.00 0.189 0.197

E 3.80 4.00 0.150 0.157

e 1.27 – – 0.050 – –

H 5.80 6.20 0.228 0.244

h 0.25 0.50 0.010 0.020

L 0.40 0.90 0.016 0.035

α0° 8° 0° 8°

N8 8

CP 0.10 0.004

SO-a

LA1 α

h x 45˚

M25P05-A

38/42

Figure 28. VDFPN8 (MLP8) 8-lead Very thin Dual Flat Package No lead, Package Outline

Note: Drawing is not to scale.

Table 19. VDFPN8 (MLP8) 8-lead Very thin Dual Flat Package No lead,

Package Mechanical Data

Symbol millimeters inches

Typ. Min. Max. Typ. Min. Max.

A 0.85 1.00 0.0335 0.0394

A1 0.00 0.05 0.0000 0.0020

A2 0.65 0.0256

A3 0.20 0.0079

b 0.40 0.35 0.48 0.0157 0.0138 0.0189

D 6.00 0.2362

D1 5.75 0.2264

D2 3.40 3.20 3.60 0.1339 0.1260 0.1417

E 5.00 0.1969

E1 4.75 0.1870

E2 4.00 3.80 4.20 0.1575 0.1496 0.1654

e 1.27 0.0500

L 0.60 0.50 0.75 0.0236 0.0197 0.0295

θ12° 12°

VDFPN-01

eE2

39/42

M25P05-A

Figure 29. TSSOP8 – 8 lead Thin Shrink Small Outline, Package Outline

Note: 1. Drawing is not to scale.

Table 20. TSSOP8 – 8 lead Thin Shrink Small Outline, Package Mechanical Data

Symbol millimeters inches

Typ Min Max Typ Min Max

A 1.200 0.0472

A1 0.050 0.150 0.0020 0.0059

A2 1.000 0.800 1.050 0.0394 0.0315 0.0413

b 0.190 0.300 0.0075 0.0118

c 0.090 0.200 0.0035 0.0079

CP 0.100 0.0039

D 3.000 2.900 3.100 0.1181 0.1142 0.1220

e 0.650 – – 0.0256 – –

E 6.400 6.200 6.600 0.2520 0.2441 0.2598

E1 4.400 4.300 4.500 0.1732 0.1693 0.1772

L 0.600 0.450 0.750 0.0236 0.0177 0.0295

L1 1.000 0.0394

α0° 8° 0° 8°

N8 8

TSSOP8AM

EE1

A2A

M25P05-A

40/42

PART NUMBERING

Table 21. Ordering Information Scheme

Note: 1. The TSSOP8 p ackage is available in products with Process Technology code X only (details of how to f ind the process on the de vice

marking are given in Application Note AN1995).

For a list of available options (speed, package,

etc.) or for further information on any aspect of this device, please c ontact yo ur neare st ST Sal es Of-

fice.

Example: M25P05-A V MN 6 T P

Device Type

M25P

Device Function

05-A = 512 Kbit (64K x 8) Enhanced Technology in line

with the M25P10-A, M25P20, M25P40, M25P80

Operatin g Voltage

V = VCC = 2.7 to 3.6V

Package

MN = SO8 (150 mil width)

MP = VDFPN8 (MLP8)

DW = TSSOP8(1)

Temperature Range

6 = –40 to 85 °C

Option

blank = Standard Pa ck ing

T = Tape & Reel Packing

Plating Technology

blank = Standard Sn Pb plati ng

P or G = RoHS comp liant

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M25P05-A

REVISION HISTORY

Table 22. Document Revision History

Date Rev. Descrip tio n of Re vis io n

25-Feb-2001 1.0 Document written

11-Apr-2002 1.1 Clarification of descriptions of entering Standby Power mode from Deep Power-down mode,

and of terminating an instruction sequence or data-out sequence

12-Sep-2002 1.2 VFQFPN8 package (MLP8) added

13-Dec-2002 1.3 Typical Page Program time improved. Write Protect setup and hold times specified, for

applications that switch Write Protect to exit the Hardware Protection mode immediately before

a WRSR, and to enter the Hardware Protection mode again immediately after

24-Nov-2003 2.0 Table of contents, warning about exposed paddle on MLP8, and Pb-free options added.

40MHz AC Characteristics table included as well as 25MHz. ICC3(max), tSE(typ) and tBE(typ)

values improved. Change of naming for VDFPN8 package

13-Jan-2005 3.0

Devices with Process technology Code X added (Read Identification (RDID) and Table

17., AC Characteristics (50MHz Operation)) added. TSSOP8 package added.

Notes 1 and 2 removed from Table 21., Ordering Information Scheme and Note 1 added.

Note 1 to Table 9., Absolute Maximum Ratings changed, note 2 and TLEAD values removed.

Small text changes.

M25P05-A

42/42

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