INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: * The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications * The IC06 74HC/HCT/HCU/HCMOS Logic Package Information * The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines 74HC/HCT574 Octal D-type flip-flop; positive edge-trigger; 3-state Product specification File under Integrated Circuits, IC06 December 1990 Philips Semiconductors Product specification Octal D-type flip-flop; positive edge-trigger; 3-state 74HC/HCT574 FEATURES GENERAL DESCRIPTION * 3-state non-inverting outputs for bus oriented applications The 74HC/HCT574 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. * 8-bit positive edge-triggered register * Common 3-state output enable input * Independent register and 3-state buffer operation * Output capability: bus driver * ICC category: MSI The 74HC/HCT574 are octal D-type flip-flops featuring separate D-type inputs for each flip-flop and non-inverting 3-state outputs for bus oriented applications. A clock (CP) and an output enable (OE) input are common to all flip-flops. The 8 flip-flops will store the state of their individual D-inputs that meet the set-up and hold time requirements on the LOW-to-HIGH CP transition. When OE is LOW, the contents of the 8 flip-flops are available at the outputs. When OE is HIGH, the outputs go to the high impedance OFF-state. Operation of the OE input does not affect the state of the flip-flops. The "574" is functionally identical to the "564", but has non-inverting outputs. The "574" is functionally identical to the "374", but has a different pinning. QUICK REFERENCE DATA GND = 0 V; Tamb = 25 C; tr = tf = 6 ns TYPICAL SYMBOL PARAMETER CONDITIONS CL = 15 pF; VCC = 5 V UNIT HC HCT 14 15 ns tPHL/ tPLH propagation delay CP to Qn fmax maximum clock frequency 123 76 MHz CI input capacitance 3.5 3.5 pF CPD power dissipation capacitance per flip-flop 22 25 pF notes 1 and 2 Notes 1. CPD is used to determine the dynamic power dissipation (PD in W): PD = CPD x VCC2 x fi + (CL x VCC2 x fo) where: fi = input frequency in MHz fo = output frequency in MHz (CL x VCC2 x fo) = sum of outputs CL = output load capacitance in pF VCC = supply voltage in V 2. For HC the condition is VI = GND to VCC For HCT the condition is VI = GND to VCC - 1.5 V ORDERING INFORMATION See "74HC/HCT/HCU/HCMOS Logic Package Information". December 1990 2 Philips Semiconductors Product specification Octal D-type flip-flop; positive edge-trigger; 3-state 74HC/HCT574 PIN DESCRIPTION PIN NO. SYMBOL NAME AND FUNCTION 1 OE 3-state output enable input (active LOW) 2, 3, 4, 5, 6, 7, 8, 9 D0 to D7 data inputs 10 GND ground (0 V) 11 CP clock input (LOW-to-HIGH, edge-triggered) 19, 18, 17, 16, 15, 14, 13, 12 Q0 to Q7 3-state flip-flop outputs 20 VCC positive supply voltage Fig.1 Pin configuration. December 1990 Fig.2 Logic symbol. 3 Fig.3 IEC logic symbol. Philips Semiconductors Product specification Octal D-type flip-flop; positive edge-trigger; 3-state 74HC/HCT574 FUNCTION TABLE OPERATING MODES INPUTS OUTPUTS OE CP Dn INTERNAL FLIP-FLOPS load and read register L L l h L H L H load register and disable outputs H H l h L H Z Z Q0 to Q7 Notes 1. H = HIGH voltage level h = HIGH voltage level one set-up time prior to the LOW-to-HIGH CP transition L = LOW voltage level l = LOW voltage level on set-up time prior to the LOW-to-HIGH CP transition Z = HIGH impedance OFF-state = LOW-to-HIGH clock transition Fig.4 Functional diagram. Fig.5 Logic diagram. December 1990 4 Philips Semiconductors Product specification Octal D-type flip-flop; positive edge-trigger; 3-state 74HC/HCT574 DC CHARACTERISTICS FOR 74HC For the DC characteristics see "74HC/HCT/HCU/HCMOS Logic Family Specifications". Output capability: bus driver ICC category: MSI AC CHARACTERISTICS FOR 74HC GND = 0 V; tr = tf = 6 ns; CL = 50 pF Tamb (C) TEST CONDITIONS 74HC SYMBOL PARAMETER +25 min. -40 to +85 typ. max. min. max. -40 to +125 min. UNIT V CC WAVEFORMS (V) max. tPHL/ tPLH propagation delay CP to Qn 47 17 14 150 30 26 190 35 33 225 45 38 ns 2.0 4.5 6.0 Fig.6 tPZH/ tPZL 3-state output enable time OE to Qn 44 16 13 140 28 24 175 35 30 210 42 36 ns 2.0 4.5 6.0 Fig.7 tPHZ/ tPLZ 3-state output disable time OE to Qn 39 14 11 125 25 21 155 31 26 190 38 32 ns 2.0 4.5 6.0 Fig.7 tTHL/ tTLH output transition time 14 5 4 60 12 10 75 15 13 90 18 15 ns 2.0 4.5 6.0 Fig.6 tW clock pulse width HIGH or LOW 80 16 14 14 5 4 100 20 17 120 24 20 ns 2.0 4.5 6.0 Fig.6 tsu set-up time Dn to CP 60 12 10 6 2 2 75 15 13 90 18 15 ns 2.0 4.5 6.0 Fig.8 th hold time Dn to CP 5 5 5 0 0 0 5 5 5 5 5 5 ns 2.0 4.5 6.0 Fig.8 fmax maximum clock pulse frequency 6.0 30 35 37 112 133 4.8 24 28 4.0 20 24 MHz 2.0 4.5 6.0 Fig.6 December 1990 5 Philips Semiconductors Product specification Octal D-type flip-flop; positive edge-trigger; 3-state 74HC/HCT574 DC CHARACTERISTICS FOR 74HCT For the DC characteristics see "74HC/HCT/HCU/HCMOS Logic Family Specifications". Output capability: bus driver ICC category: MSI Note to HCT types The value of additional quiescent supply current (ICC) for a unit load of 1 is given in the family specifications. To determine ICC per input, multiply this value by the unit load coefficient shown in the table below. INPUT UNIT LOAD COEFFICIENT Dn OE CP 0.5 1.25 1.5 AC CHARACTERISTICS FOR 74HCT GND = 0 V; tr = tf = 6 ns; CL = 50 pF Tamb (C) TEST CONDITIONS 74HCT SYMBOL PARAMETER +25 min. -40 to +85 typ. max. min. max. -40 to +125 min. UNIT V CC WAVEFORMS (V) max. tPHL/ tPLH propagation delay CP to Qn 18 33 41 50 ns 4.5 Fig.6 tPZH/ tPZL 3-state output enable time OE to Qn 19 33 41 50 ns 4.5 Fig.7 tPHZ/ tPLZ 3-state output disable time OE to Qn 16 28 35 42 ns 4.5 Fig.7 tTHL/ tTLH output transition time 5 12 15 18 ns 4.5 Fig.6 tW clock pulse width HIGH or LOW 16 7 20 24 ns 4.5 Fig.6 tsu set-up time Dn to CP 12 3 15 18 ns 4.5 Fig.8 th hold time Dn to CP 5 -1 5 5 ns 4.5 Fig.8 fmax maximum clock pulse frequency 30 69 24 20 MHz 4.5 Fig.6 December 1990 6 Philips Semiconductors Product specification Octal D-type flip-flop; positive edge-trigger; 3-state 74HC/HCT574 AC WAVEFORMS (1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V. (1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V. Fig.6 Waveforms showing the clock input (CP) pulse width, the CP input to output (Qn) propagation delays, the output transition times and the maximum clock pulse frequency. Fig.7 Waveforms showing the 3-state enable and disable times. PACKAGE OUTLINES See "74HC/HCT/HCU/HCMOS Logic Package Outlines". The shaded areas indicate when the input is permitted to change for predictable output performance. (1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V. Fig.8 Waveforms showing the data set-up and hold times for Dn input to CP input. December 1990 7