LTC2494
1
2494fe
For more information www.linear.com/LTC2494
Features
applications
Description
16-Bit 8-/16-Channel
DS
ADC
with PGA and Easy Drive
Input Current Cancellation
The LTC
®
2494 is a 16-channel (8-differential), 16-bit, No
Latency DS™ ADC with Easy Drive technology. The pat-
ented sampling scheme eliminates dynamic input current
errors and the shortcomings of on-chip buffering through
automatic cancellation of differential input current. This
allows large external source impedances, and rail-to-rail
input signals to be directly digitized while maintaining
exceptional DC accuracy.
The LTC2494 includes programmable gain, a high accu-
racy temperature sensor and an integrated oscillator. This
device can be configured to measure an external signal
(from combinations of 16 analog input channels operat-
ing in single-ended or differential modes) or its internal
temperature sensor. The integrated temperature sensor
offers 1/2°C resolution and 2°C absolute accuracy. The
LTC2494 can be configured to provide a programmable
gain from 1 to 256 in 8 steps.
The LTC2494 allows a wide common mode input range
(0V to VCC), independent of the reference voltage. Any
combination of single-ended or differential inputs can be
selected and the first conversion, after a new channel is
selected, is valid.
Data Acquisition System with Temperature Compensation
n Up to 8 Differential or 16 Single-Ended Inputs
n Easy Drive
TM
Technology Enables Rail-to-Rail
Inputs with Zero Differential Input Current
n Directly Digitizes High Impedance Sensors with
Full Accuracy
n 600nV RMS Noise
n Programmable Gain from 1 to 256
n Integrated High Accuracy Temperature Sensor
n GND to VCC Input/Reference Common Mode Range
n Programmable 50Hz, 60Hz or Simultaneous
50Hz/60Hz Rejection Mode
n 2ppm INL, No Missing Codes
n 1ppm Offset and 15ppm Full-Scale Error
n 2x Speed Mode/Reduced Power Mode (15Hz Using
Internal Oscillator and 80µA at 7.5Hz Output)
n No Latency: Digital Filter Settles in a Single Cycle,
Even After a New Channel Is Selected
n Single-Supply 2.7V to 5.5V Operation
n Internal Oscillator
n Tiny 5mm × 7mm QFN Package
n Direct Sensor Digitizer
n Direct Temperature Measurement
n Instrumentation
n Industrial Process Control
Absolute Temperature Error
SDI
SCK
SDO
CS
fO
REF+
VCC
MUXOUT/
ADCIN
MUXOUT/
ADCIN
2.7V TO 5.5V
0.1µF
COM REF–
16-BIT ∆Σ ADC
WITH EASY-DRIVE
16-CHANNEL
MUX
TEMPERATURE
SENSOR
IN+
IN–
2494 TA01a
4-WIRE
SPI INTERFACE
CH0
CH1
•
•
•
•
•
•
CH7
CH8
CH15
10µF
OSC
TEMPERATURE (°C)
–55 –30 –5
ABSOLUTE ERROR (°C)
5
4
3
2
1
–4
–3
–2
–1
0
12095704520
2494 TA01b
–5
typical application
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and
No Latency ∆∑ and Easy Drive are trademarks of Linear Technology Corporation. All other
trademarks are the property of their respective owners.
LTC2494
2
2494fe
For more information www.linear.com/LTC2494
pin conFiguration
absolute MaxiMuM ratings
Supply Voltage (VCC) ................................... –0.3V to 6V
Analog Input Voltage
(CH0 to CH15, COM) .................–0.3V to (VCC + 0.3V)
REF+, REF– ................................ –0.3V to (VCC + 0.3V)
ADCINN, ADCINP, MUXOUTP,
MUXOUTN ................................–0.3V to (VCC + 0.3V)
Digital Input Voltage......................–0.3V to (VCC + 0.3V)
Digital Output Voltage ...................–0.3V to (VCC + 0.3V)
Operating Temperature Range
LTC2494C ................................................ 0°C to 70°C
LTC2494I .............................................–40°C to 85°C
Storage Temperature Range .................. –65°C to 150°C
(Notes 1, 2)
13 14 15 16
TOP VIEW
39
UHF PACKAGE
38-LEAD (5mm × 7mm) PLASTIC QFN
17 18 19
38 37 36 35 34 33 32
24
25
26
27
28
29
30
31
8
7
6
5
4
3
2
1GND
NC
GND
GND
GND
GND
COM
CH0
CH1
CH2
CH3
CH4
GND
REF–
REF+
VCC
MUXOUTN
ADCINN
ADCINP
MUXOUTP
CH15
CH14
CH13
CH12
SCK
SDO
CS
fO
SDI
GND
GND
CH5
CH6
CH7
CH8
CH9
CH10
CH11
23
22
21
20
9
10
11
12
TJMAX = 125°C, θJA = 34°C/W
EXPOSED PAD (PIN 39) IS GND, MUST BE SOLDERED TO PCB
orDer inForMation
LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE
LTC2494CUHF#PBF LTC2494CUHF#TRPBF 2494 38-Lead (5mm × 7mm) Plastic QFN 0°C to 70°C
LTC2494IUHF#PBF LTC2494IUHF#TRPBF 2494 38-Lead (5mm × 7mm) Plastic QFN –40°C to 85°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Consult LTC Marketing for information on non-standard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
LTC2494
3
2494fe
For more information www.linear.com/LTC2494
electrical characteristics (norMal speeD)
The l denotes the specifications which
apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Notes 3, 4)
PARAMETER CONDITIONS MIN TYP MAX UNITS
Resolution (No Missing Codes) 0.1V ≤ VREF ≤ VCC, –FS ≤ VIN ≤ +FS (Note 5) 16 Bits
Integral Nonlinearity 5V ≤ VCC ≤ 5.5V, VREF = 5V, VIN(CM) = 2.5V (Note 6)
2.7V ≤ VCC ≤ 5.5V, VREF = 2.5V, VIN(CM) = 1.25V (Note 6)
l2
1
20 ppm of VREF
ppm of VREF
Offset Error 2.5V ≤ VREF ≤ VCC, GND ≤ IN+ = IN– ≤ VCC (Note 14) l0.5 5 µV
Offset Error Drift 2.5V ≤ VREF ≤ VCC, GND ≤ IN+ = IN– ≤ VCC 10 nV/°C
Positive Full-Scale Error 2.5V ≤ VREF ≤ VCC, IN+ = 0.75VREF, IN– = 0.25VREF l32 ppm of VREF
Positive Full-Scale Error Drift 2.5V ≤ VREF ≤ VCC, IN+ = 0.75VREF, IN– = 0.25VREF 0.1 ppm of VREF/°C
Negative Full-Scale Error 2.5V ≤ VREF ≤ VCC, IN+ = 0.25VREF, IN– = 0.75VREF l32 ppm of VREF
Negative Full-Scale Error Drift 2.5V ≤ VREF ≤ VCC, IN+ = 0.25VREF, IN– = 0.75VREF 0.1 ppm of VREF/°C
Total Unadjusted Error 5V ≤ VCC ≤ 5.5V, VREF = 2.5V, VIN(CM) = 1.25V
5V ≤ VCC ≤ 5.5V, VREF = 5V, VIN(CM) = 2.5V
2.7V ≤ VCC ≤ 5.5V, VREF = 2.5V, VIN(CM) = 1.25V
15
15
15
ppm of VREF
ppm of VREF
ppm of VREF
Output Noise 2.7V ≤ VCC ≤ 5.5V, 2.5V ≤ VREF ≤ VCC,
GND ≤ IN+ = IN– ≤ VCC (Note 13)
0.6 µVRMS
Internal PTAT Signal TA = 27°C (Note 14) 27.8 28.0 28.2 mV
Internal PTAT Temperature Coefficient 93.5 µV/°C
Programmable Gain l1 256
electrical characteristics (2x speeD)
The l denotes the specifications which apply over the
full operating temperature range, otherwise specifications are at TA = 25°C. (Notes 3, 4)
PARAMETER CONDITIONS MIN TYP MAX UNITS
Resolution (No Missing Codes) 0.1V ≤ VREF ≤ VCC, –FS ≤ VIN ≤ +FS (Note 5) 16 Bits
Integral Nonlinearity 5V ≤ VCC ≤ 5.5V, VREF = 5V, VIN(CM) = 2.5V (Note 6)
2.7V ≤ VCC ≤5.5V, VREF = 2.5V, VIN(CM) = 1.25V (Note 6)
l2
1
20 ppm of VREF
ppm of VREF
Offset Error 2.5V ≤ VREF ≤ VCC, GND ≤ IN+ = IN– ≤ VCC (Note 14) l0.2 2 mV
Offset Error Drift 2.5V ≤ VREF ≤ VCC, GND ≤ IN+ = IN– ≤ VCC 100 nV/°C
Positive Full-Scale Error 2.5V ≤ VREF ≤ VCC, IN+ = 0.75VREF, IN– = 0.25VREF l32 ppm of VREF
Positive Full-Scale Error Drift 2.5V ≤ VREF ≤ VCC, IN+ = 0.75VREF, IN– = 0.25VREF 0.1 ppm of VREF/°C
Negative Full-Scale Error 2.5V ≤ VREF ≤ VCC, IN+ = 0.25VREF, IN– = 0.75VREF l32 ppm of VREF
Negative Full-Scale Error Drift 2.5V ≤ VREF ≤ VCC, IN+ = 0.25VREF, IN– = 0.75VREF 0.1 ppm of VREF/°C
Output Noise 5V ≤ VCC ≤ 2.5V, VREF = 5V, GND ≤ IN+ = IN– ≤ VCC 0.85 µVRMS
Programmable Gain l1 128
converter characteristics
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 3)
PARAMETER CONDITIONS MIN TYP MAX UNITS
Input Common Mode Rejection DC 2.5V ≤ VREF ≤ VCC, GND ≤ IN+ = IN– ≤ VCC (Note 5) l140 dB
Input Common Mode Rejection 60Hz ±2% 2.5V ≤ VREF ≤ VCC, GND ≤ IN+ = IN– ≤ VCC (Note 5) l140 dB
Input Common Mode Rejection 50Hz ±2% 2.5V ≤ VREF ≤ VCC, GND ≤ IN+ = IN– ≤ VCC (Note 5) l140 dB
Input Normal Mode Rejection 50Hz ±2% 2.5V ≤ VREF ≤ VCC, GND ≤ IN+ = IN– ≤ VCC (Notes 5, 7) l110 120 dB
Input Normal Mode Rejection 60Hz ±2% 2.5V ≤ VREF ≤ VCC, GND ≤ IN+ = IN– ≤ VCC (Notes 5, 8) l110 120 dB
Input Normal Mode Rejection 50Hz/60Hz ±2% 2.5V ≤ VREF ≤ VCC, GND ≤ IN+ = IN– ≤ VCC (Notes 5, 9) l87 dB
Reference Common Mode Rejection DC 2.5V ≤ VREF ≤ VCC, GND ≤ IN+ = IN– ≤ VCC (Note 5) l120 140 dB
Power Supply Rejection DC VREF = 2.5V, IN+ = IN– = GND 120 dB
Power Supply Rejection, 50Hz ±2% VREF = 2.5V, IN+ = IN– = GND (Notes 7, 9) 120 dB
Power Supply Rejection, 60Hz ±2% VREF = 2.5V, IN+ = IN– = GND (Notes 8, 9) 120 dB
LTC2494
4
2494fe
For more information www.linear.com/LTC2494
Digital inputs anD Digital outputs
The l denotes the specifications which apply over the
full operating temperature range, otherwise specifications are at TA = 25°C. (Note 3)
analog input anD reFerence
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 3)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
IN+Absolute/Common Mode IN+ Voltage
(IN+ Corresponds to the Selected Positive Input Channel)
GND – 0.3V VCC + 0.3V V
IN–Absolute/Common Mode IN– Voltage
(IN– Corresponds to the Selected Negative Input Channel or COM)
GND – 0.3V VCC + 0.3V V
VIN Input Voltage Range (IN+ – IN–) Differential/Single-Ended l–FS +FS V
FS Full-Scale of the Input (IN+ – IN–) Differential/Single-Ended l0.5VREF/Gain V
LSB Least Significant Bit of the Output Code lFS/216
REF+Absolute/Common Mode REF+ Voltage l0.1 VCC V
REF–Absolute/Common Mode REF– Voltage lGND REF+ – 0.1V V
VREF Reference Voltage Range (REF+ – REF–)l0.1 VCC V
CS(IN+) IN+ Sampling Capacitance 11 pF
CS(IN–) IN– Sampling Capacitance 11 pF
CS(VREF) VREF Sampling Capacitance 11 pF
IDC_LEAK(IN+)IN+ DC Leakage Current Sleep Mode, IN+ = GND l–10 1 10 nA
IDC_LEAK(IN–)IN– DC Leakage Current Sleep Mode, IN– = GND l–10 1 10 nA
IDC_LEAK(REF+)REF+ DC Leakage Current Sleep Mode, REF+ = VCC l–100 1 100 nA
IDC_LEAK(REF–)REF– DC Leakage Current Sleep Mode, REF– = GND l–100 1 100 nA
tOPEN MUX Break-Before-Make 50 ns
QIRR MUX Off Isolation VIN = 2VP-P DC to 1.8MHz 120 dB
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VIH High Level Input Voltage (CS, fO, SDI) 2.7V ≤ VCC ≤ 5.5V (Note 18) lVCC – 0.5 V
VIL Low Level Input Voltage (CS, fO, SDI) 2.7V ≤ VCC ≤ 5.5V l0.5 V
VIH High Level Input Voltage (SCK) 2.7V ≤ VCC ≤ 5.5V (Notes 10, 15) lVCC – 0.5 V
VIL Low Level Input Voltage (SCK) 2.7V ≤ VCC ≤ 5.5V (Notes 10, 15) l0.5 V
IIN Digital Input Current (CS, fO, SDI) 0V ≤ VIN ≤ VCC l–10 10 µA
IIN Digital Input Current (SCK) 0V ≤ VIN ≤ VCC (Notes 10, 15) l–10 10 µA
CIN Digital Input Capacitance (CS, fO, SDI) 10 pF
CIN Digital Input Capacitance (SCK) (Notes 10, 15) 10 pF
VOH High Level Output Voltage (SDO) IO = –800µA lVCC – 0.5 V
VOL Low Level Output Voltage (SDO) IO = 1.6mA l0.4 V
VOH High Level Output Voltage (SCK) IO = –800µA (Notes 10, 17) lVCC – 0.5 V
VOL Low Level Output Voltage (SCK) IO = 1.6mA (Notes 10, 17) l0.4 V
IOZ Hi-Z Output Leakage (SDO) l–10 10 µA
power requireMents
The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 3)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VCC Supply Voltage l2.7 5.5 V
ICC Supply Current Conversion Current (Note 12)
Temperature Measurement (Note 12)
Sleep Mode (Note 12)
l
l
l
160
200
1
275
300
2
µA
µA
µA
LTC2494
5
2494fe
For more information www.linear.com/LTC2494
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
fEOSC External Oscillator Frequency Range (Note 16) l10 1000 kHz
tHEO External Oscillator High Period l0.125 50 µs
tLEO External Oscillator Low Period l0.125 50 µs
tCONV_1 Conversion Time for 1x Speed Mode 50Hz Mode
60Hz Mode
Simultaneous 50/60Hz Mode
External Oscillator
l
l
l
157.2
131
144.1
160.3
133.6
146.9
41036/fEOSC (in kHz)
163.5
136.3
149.9
ms
ms
ms
ms
tCONV_2 Conversion Time for 2x Speed Mode 50Hz Mode
60Hz Mode
Simultaneous 50/60Hz Mode
External Oscillator
l
l
l
78.7
65.6
72.2
80.3
66.9
73.6
20556/fEOSC (in kHz)
81.9
68.2
75.1
ms
ms
ms
ms
fISCK Internal SCK Frequency Internal Oscillator (Notes 10, 17)
External Oscillator (Notes 10, 11, 15)
38.4
fEOSC/8
kHz
kHz
DISCK Internal SCK Duty Cycle (Notes 10, 17) l45 55 %
fESCK External SCK Frequency Range (Notes 10, 11, 15) l4000 kHz
tLESCK External SCK LOW Period (Notes 10, 11, 15) l125 ns
tHESCK External SCK HIGH Period (Notes 10, 11, 15) l125 ns
tDOUT_ISCK Internal SCK 24-Bit Data Output Time Internal Oscillator (Notes 10, 17)
External Oscillator (Notes 10, 11, 15)
l0.61 0.625
192/fEOSC (in kHz)
0.64 ms
ms
tDOUT_ESCK External SCK 24-Bit Data Output Time (Notes 10, 11, 15) 24/fESCK (in kHz) ms
t1CS↓ to SDO LOW l0 200 ns
t2CS↑ to SDO Hi-Z l0 200 ns
t3CS↓ to SCK↑Internal SCK Mode l0 200 ns
t4CS↓ to SCK↑External SCK Mode l50 ns
tKQMAX SCK↓ to SDO Valid l200 ns
tKQMIN SDO Hold After SCK↓(Note 5) l15 ns
t5SCK Set-Up Before CS↓l50 ns
t7SDI Setup Before SCK↑(Note 5) l100 ns
t8SDI Hold After SCK↑(Note 5) l100 ns
Digital inputs anD Digital outputs
The l denotes the specifications which apply over the
full operating temperature range, otherwise specifications are at TA = 25°C. (Note 3)
Note 1: Stresses beyond those listed under Absolute Maximum Ratings may
cause permanent damage to the device. Exposure to any Absolute Maximum
Rating condition for extended periods may affect device reliability and lifetime.
Note 2: All voltage values are with respect to GND.
Note 3: VCC = 2.7V to 5.5V unless otherwise specified.
VREFCM = VREF/2, fS = 0.5VREF/Gain
VIN = IN+ – IN–, VIN(CM) = (IN+ – IN–)/2,
where IN+ and IN– are the selected input channels.
Note 4: Use internal conversion clock or external conversion clock source
with fEOSC = 307.2kHz unless other wise specified.
Note 5: Guaranteed by design, not subject to test.
Note 6: Integral nonlinearity is defined as the deviation of a code from a
straight line passing through the actual endpoints of the transfer curve.
The deviation is measured from the center of the quantization band.
Note 7: 50Hz mode (internal oscillator) or fEOSC = 256kHz ±2% (external
oscillator).
Note 8: 60Hz mode (internal oscillator) or fEOSC = 307.2kHz ±2% (external
oscillator).
Note 9: Simultaneous 50Hz/60Hz mode (internal oscillator) or fEOSC =
280kHz ±2% (external oscillator).
Note 10: The SCK can be configured in external SCK mode or internal SCK
mode. In external SCK mode, the SCK pin is used as a digital input and the
driving clock is fESCK. In the internal SCK mode, the SCK pin is used as a
digital output and the output clock signal during the data output is fISCK.
Note 11: The external oscillator is connected to the fO pin. The external
oscillator frequency, fEOSC, is expressed in kHz.
Note 12: The converter uses its internal oscillator.
Note 13: The output noise includes the contribution of the internal
calibration operations.
Note 14: Guaranteed by design and test correlation.
Note 15: The converter is in external SCK mode of operation such that the
SCK pin is used as a digital input. The frequency of the clock signal driving
SCK during the data output is fESCK and is expressed in Hz.
Note 16: Refer to Applications Information section for performance vs
data rate graphs.
Note 17: The converter is in internal SCK mode of operation such that the
SCK pin is used as a digital output.
Note 18: For VCC < 3V, VIH is 2.5V for Pin fO.
LTC2494
6
2494fe
For more information www.linear.com/LTC2494
typical perForMance characteristics
Integral Nonlinearity
(VCC = 5V, VREF = 5V)
Integral Nonlinearity
(VCC = 5V, VREF = 2.5V)
Integral Nonlinearity
(VCC = 2.7V, VREF = 2.5V)
Total Unadjusted Error
(VCC = 5V, VREF = 5V)
Total Unadjusted Error
(VCC = 5V, VREF = 2.5V)
Total Unadjusted Error
(VCC = 2.7V, VREF = 2.5V)
Noise Histogram (6.8sps) Noise Histogram (7.5sps) Long-Term ADC Readings
INPUT VOLTAGE (V)
–3
INL (ppm OF V
REF
)
–1
1
3
–2
0
2
–1.5 –0.5 0.5 1.5
2494 G01
2.5–2–2.5 –1 0 1 2
VCC = 5V
VREF = 5V
VIN(CM) = 2.5V
fO = GND
85°C
–45°C 25°C
INPUT VOLTAGE (V)
–3
INL (ppm OF V
REF
)
–1
1
3
–2
0
2
–0.75 –0.25 0.25 0.75
2494 G02
1.25–1.25
VCC = 5V
VREF = 2.5V
VIN(CM) = 1.25V
fO = GND
–45°C, 25°C, 85°C
INPUT VOLTAGE (V)
–3
INL (ppm OF V
REF
)
–1
1
3
–2
0
2
–0.75 –0.25 0.25 0.75
2494 G03
1.25–1.25
VCC = 2.7V
VREF = 2.5V
VIN(CM) = 1.25V
fO = GND
–45°C, 25°C, 85°C
INPUT VOLTAGE (V)
–12
TUE (ppm OF V
REF
)
–4
4
12
–8
0
8
–1.5 –0.5 0.5 1.5
2494 G04
2.5–2–2.5 –1 0 1 2
VCC = 5V
VREF = 5V
VIN(CM) = 2.5V
fO = GND 85°C
25°C
–45°C
INPUT VOLTAGE (V)
–12
TUE (ppm OF V
REF
)
–4
4
12
–8
0
8
–0.75 –0.25 0.25 0.75
2494 G05
1.25–1.25
VCC = 5V
VREF = 2.5V
VIN(CM) = 1.25V
fO = GND
85°C
25°C
–45°C
INPUT VOLTAGE (V)
–12
TUE (ppm OF V
REF
)
–4
4
12
–8
0
8
–0.75 –0.25 0.25 0.75
2494 G06
1.25–1.25
VCC = 2.7V
VREF = 2.5V
VIN(CM) = 1.25V
fO = GND 85°C
25°C
–45°C
OUTPUT READING (µV)
–3
NUMBER OF READINGS (%)
8
10
12
0.6
2494 G07
6
4
–1.8 –0.6
–2.4 1.2
–1.2 0 1.8
2
0
14
10,000 CONSECUTIVE
READINGS
VCC = 5V
VREF = 5V
VIN = 0V
TA = 25°C
GAIN = 256
RMS = 0.60µV
AVERAGE = –0.69µV
OUTPUT READING (µV)
–3
NUMBER OF READINGS (%)
8
10
12
0.6
2494 G08
6
4
–1.8 –0.6
–2.4 1.2
–1.2 0 1.8
2
0
14 10,000 CONSECUTIVE
READINGS
VCC = 2.7V
VREF = 2.5V
VIN = 0V
TA = 25°C
GAIN = 256
RMS = 0.59µV
AVERAGE = –0.19µV
TIME (HOURS)
0
–5
–3
–1
1
10 20 30 40
2494 G09
50
3
–4
–2
0
2
4
60
VCC = 5V, VREF = 5V, VIN = 0V, VIN(CM) = 2.5V
TA = 25°C, RMS NOISE = 0.60µV, GAIN = 256
LTC2494
7
2494fe
For more information www.linear.com/LTC2494
typical perForMance characteristics
RMS Noise
vs Input Differential Voltage RMS Noise vs VIN(CM) RMS Noise vs Temperature (TA)
RMS Noise vs VCC RMS Noise vs VREF Offset Error vs VIN(CM)
Offset Error vs Temperature Offset Error vs VCC Offset Error vs VREF
INPUT DIFFERENTIAL VOLTAGE (V)
0.4
RMS NOISE (µV)
0.6
0.8
1.0
0.5
0.7
0.9
–1.5 –0.5 0.5 1.5
2494 G10
2.5–2–2.5 –1 0 1 2
VCC = 5V
VREF = 5V
VIN(CM) = 2.5V
TA = 25°C
VIN(CM) (V)
–1
RMS NOISE (µV)
0.8
0.9
1.0
2 4
2494 G11
0.7
0.6
0 1 3 5 6
0.5
0.4
VCC = 5V
VREF = 5V
VIN = 0V
VIN(CM) = GND
TA = 25°C
GAIN = 256
TEMPERATURE (°C)
–45
0.4
RMS NOISE (µV)
0.5
0.6
0.7
0.8
1.0
–30 –15 15
0 30 45 60
2494 G12
75 90
0.9
VCC = 5V
VREF = 5V
VIN = 0V
VIN(CM) = GND
GAIN = 256
VCC (V)
2.7
RMS NOISE (µV)
0.8
0.9
1.0
3.9 4.7
2494 G13
0.7
0.6
3.1 3.5 4.3 5.1 5.5
0.5
0.4
VREF = 2.5V
VIN = 0V
VIN(CM) = GND
TA = 25°C
GAIN = 256
VREF (V)
0
0.4
RMS NOISE (µV)
0.5
0.6
0.7
0.8
0.9
1.0
1 2 3 4
2494 G14
5
VCC = 5V
VIN = 0V
VIN(CM) = GND
TA = 25°C
GAIN = 256
VIN(CM) (V)
–1
OFFSET ERROR (ppm OF VREF)
0.1
0.2
0.3
2 4
2494 G15
0
–0.1
0 1 3 5 6
–0.2
–0.3
VCC = 5V
VREF = 5V
VIN = 0V
TA = 25°C
TEMPERATURE (°C)
–45
–0.3
OFFSET ERROR (ppm OF V
REF
)
–0.2
0
0.1
0.2
–15 15 30 90
2494 G16
–0.1
–30 0 45 60 75
0.3
VCC = 5V
VREF = 5V
VIN = 0V
VIN(CM) = GND
fO = GND
VREF (V)
0
–0.3
OFFSET ERROR (ppm OF VREF)
–0.2
–0.1
0
0.1
0.2
0.3
1 2 3 4
2494 G18
5
VCC = 5V
REF– = GND
VIN = 0V
VIN(CM) = GND
TA = 25°C
VCC (V)
2.7
OFFSET ERROR (ppm OF V
REF
)
0.1
0.2
0.3
3.9 4.7
2494 G17
0
–0.1
3.1 3.5 4.3 5.1 5.5
–0.2
–0.3
REF+ = 2.5V
REF– = GND
VIN = 0V
VIN(CM) = GND
TA = 25°C
LTC2494
8
2494fe
For more information www.linear.com/LTC2494
typical perForMance characteristics
On-Chip Oscillator Frequency
vs Temperature
On-Chip Oscillator Frequency
vs VCC PSRR vs Frequency at VCC
PSRR vs Frequency at VCC PSRR vs Frequency at VCC
Conversion Current
vs Temperature
Sleep Mode Current
vs Temperature
Conversion Current
vs Output Data Rate
Integral Nonlinearity (2x Speed
Mode; VCC = 5V, VREF = 5V)
TEMPERATURE (°C)
–45 –30
300
FREQUENCY (kHz)
304
310
–15 30 45
2494 G19
302
308
306
150 60 75 90
VCC = 4.1V
VREF = 2.5V
VIN = 0V
VIN(CM) = GND
fO = GND
VCC (V)
2.5
300
FREQUENCY (kHz)
302
304
306
308
310
3.0 3.5 4.0 4.5
2494 G20
5.0 5.5
VREF = 2.5V
VIN = 0V
VIN(CM) = GND
fO = GND
TA = 25°C
FREQUENCY AT VCC (Hz)
1
0
–20
–40
–60
–80
–100
–120
–140 1k 100k
2494 G21
10 100 10k 1M
REJECTION (dB)
VCC = 4.1V DC
VREF = 2.5V
IN+ = GND
IN– = GND
fO = GND
TA = 25°C
FREQUENCY AT VCC (Hz)
0
–140
REJECTION (dB)
–120
–80
–60
–40
0
20 100 140
2494 G22
–100
–20
80 180 220200
40 60 120 160
VCC = 4.1V DC ±1.4V
VREF = 2.5V
IN+ = GND
IN– = GND
fO = GND
TA = 25°C
FREQUENCY AT VCC (Hz)
30600
–60
–40
0
30750
2494 G23
–80
–100
30650 30700 30800
–120
–140
–20
REJECTION (dB)
VCC = 4.1V DC ±0.7V
VREF = 2.5V
IN+ = GND
IN– = GND
fO = GND
TA = 25°C
TEMPERATURE (°C)
–45
100
CONVERSION CURRENT (µA)
120
160
180
200
–15 15 30 90
2494 G24
140
–30 0 45 60 75
VCC = 5V
VCC = 2.7V
fO = GND
CS = GND
SCK = NC
SDO = NC
SDI = GND
TEMPERATURE (°C)
–45
0
SLEEP MODE CURRENT (µA)
0.2
0.6
0.8
1.0
2.0
1.4
–15 15 30 90
2494 G25
0.4
1.6
1.8
1.2
–30 0 45 60 75
VCC = 5V
VCC = 2.7V
fO = GND
CS = VCC
SCK = NC
SDO = NC
SDI = GND
OUTPUT DATA RATE (READINGS/SEC)
SUPPLY CURRENT (µA)
500
450
400
350
300
250
200
150
100
2494 G26
0 20 3010
VREF = VCC
IN+ = GND
IN– = GND
SCK = NC
SDO = NC
SDI = GND
CS GND
fO = EXT OSC
TA = 25°C
VCC = 3V
VCC = 5V
INPUT VOLTAGE (V)
–3
INL (ppm OF V
REF
)
–1
1
3
–2
0
2
–1.5 –0.5 0.5 1.5
2494 G27
2.5–2–2.5 –1 0 1 2
VCC = 5V
VREF = 5V
VIN(CM) = 2.5V
fO = GND
25°C, 85°C
–45°C
LTC2494
9
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For more information www.linear.com/LTC2494
Offset Error vs VCC
(2x Speed Mode)
Offset Error vs VREF
(2x Speed Mode)
PSRR vs Frequency at VCC
(2x Speed Mode)
typical perForMance characteristics
Integral Nonlinearity (2x Speed
Mode; VCC = 5V, VREF = 2.5V)
Integral Nonlinearity (2x Speed
Mode; VCC = 2.7V, VREF = 2.5V)
Noise Histogram
(2x Speed Mode)
RMS Noise vs VREF
(2x Speed Mode)
Offset Error vs VIN(CM)
(2x Speed Mode)
Offset Error vs Temperature
(2x Speed Mode)
INPUT VOLTAGE (V)
–3
INL (ppm OF V
REF
)
–1
1
3
–2
0
2
–0.75 –0.25 0.25 0.75
2494 G28
1.25–1.25
VCC = 5V
VREF = 2.5V
VIN(CM) = 1.25V
fO = GND
85°C
–45°C, 25°C
INPUT VOLTAGE (V)
–3
INL (ppm OF V
REF
)
–1
1
3
–2
0
2
–0.75 –0.25 0.25 0.75
2494 G29
1.25–1.25
VCC = 2.7V
VREF = 2.5V
VIN(CM) = 1.25V
fO = GND
85°C
–45°C, 25°C
OUTPUT READING (µV)
179
NUMBER OF READINGS (%)
8
10
12
186.2
2494 G30
6
4
181.4 183.8 188.6
2
0
16
14
10,000 CONSECUTIVE
READINGS
VCC = 5V
VREF = 5V
VIN = 0V
GAIN = 128
TA = 25°C
RMS = 0.85µV
AVERAGE = 0.184mV
VREF (V)
0
RMS NOISE (µV)
0.6
0.8
1.0
4
2494 G31
0.4
0.2
01235
VCC = 5V
VIN = 0V
VIN(CM) = GND
fO = GND
TA = 25°C
GAIN = 128
VIN(CM) (V)
–1
180
OFFSET ERROR (µV)
182
186
188
190
200
194
134
2494 G32
184
196
198
192
0256
VCC = 5V
VREF = 5V
VIN = 0V
fO = GND
TA = 25°C
TEMPERATURE (°C)
–45
OFFSET ERROR (µV)
200
210
220
75
2494 G33
190
180
160 –15 15 45
–30 90
030 60
170
240
230
VCC = 5V
VREF = 5V
VIN = 0V
VIN(CM) = GND
fO = GND
VCC (V)
2 2.5
0
OFFSET ERROR (µV)
100
250
344.5
2494 G34
50
200
150
3.5 55.5
VREF = 2.5V
VIN = 0V
VIN(CM) = GND
fO = GND
TA = 25°C
VREF (V)
0
OFFSET ERROR (µV)
190
200
210
35
2494 G35
180
170
160 1 2 4
220
230
VCC = 5V
VIN = 0V
VIN(CM) = GND
fO = GND
TA = 25°C
FREQUENCY AT VCC (Hz)
1
0
–20
–40
–60
–80
–100
–120
–140 1k 100k
2494 G36
10 100 10k 1M
REJECTION (dB)
VCC = 4.1V DC
REF+ = 2.5V
REF– = GND
IN+ = GND
IN– = GND
fO = GND
TA = 25°C
LTC2494
10
2494fe
For more information www.linear.com/LTC2494
pin Functions
GND (Pins 1, 3, 4, 5, 6, 31, 32, 33): Ground. Multiple
ground pins internally connected for optimum ground
current flow and VCC decoupling. Connect each one of
these pins to a common ground plane through a low
impedance connection. All eight pins must be connected
to ground for proper operation.
NC (Pin 2): No Connection. This pin can be left floating
or tied to GND.
COM (Pin 7): The Common Negative Input (IN–) for All
Single-Ended Multiplexer Configurations. The voltage on
CH0 to CH15 and COM pins can have any value between
GND – 0.3V to VCC + 0.3V. Within these limits, the two
selected inputs (IN+ and IN–) provide a bipolar input range
VIN = (IN+ – IN–) from –0.5 • VREF/Gain to 0.5 • VREF/Gain.
Outside this input range, the converter produces unique
overrange and underrange output codes.
CH0 to CH15 (Pins 8 to 23): Analog Inputs. May be pro-
grammed for single-ended or differential mode.
MUXOUTP (Pin 24): Positive Multiplexer Output. Used
to drive an external buffer/amplifier or can be shorted
directly to ADCINP
.
ADCINP (Pin 25): Positive ADC Input. Tie to the output
of a buffer/amplifier driven by MUXOUTP or tie directly
to MUXOUTP.
ADCINN (Pin 26): Negative ADC Input. Tie to the output
of a buffer/amplifier driven by MUXOUTN or tie directly
to MUXOUTN.
MUXOUTN (Pin 27): Negative Multiplexer Output. Used
to drive an external buffer/amplifier or can be shorted
directly to ADCINN.
VCC (Pin 28): Positive Supply Voltage. Bypass to GND with
a 10µF tantalum capacitor in parallel with a 0.1µF ceramic
capacitor as close to the part as possible.
REF+ (Pin 29), REF– (Pin 30): Differential Reference Input.
The voltage on these pins can have any value between
GND and VCC as long as the reference positive input,
REF+, remains more positive than the negative reference
input, REF–, by at least 0.1V. The differential voltage VREF
= (REF+ – REF–) sets the full-scale range (
–0.5 • VREF/
Gain to 0.5 • VREF/Gain)
for all input channels. When
performing an on-chip temperature measurement, the
minimum value of REF = 2V.
typical perForMance characteristics
PSRR vs Frequency at VCC
(2x Speed Mode)
PSRR vs Frequency at VCC
(2x Speed Mode)
FREQUENCY AT VCC (Hz)
0
–140
RREJECTION (dB)
–120
–80
–60
–40
0
20 100 140
2494 G37
–100
–20
80 180 220200
40 60 120 160
VCC = 4.1V DC ±1.4V
REF+ = 2.5V
REF– = GND
IN+ = GND
IN– = GND
fO = GND
TA = 25°C
FREQUENCY AT VCC (Hz)
30600
–60
–40
0
30750
2494 G38
–80
–100
30650 30700 30800
–120
–140
–20
REJECTION (dB)
VCC = 4.1V DC ±0.7V
REF+ = 2.5V
REF– = GND
IN+ = GND
IN– = GND
fO = GND
TA = 25°C
LTC2494
11
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For more information www.linear.com/LTC2494
pin Functions
SDI (Pin 34): Serial Data Input. This pin is used to select the
gain, line frequency rejection mode, 1x or 2x speed mode,
temperature sensor, as well as the input channel. The serial
data input is applied under control of the serial clock (SCK)
during the data output/input operation. The first conversion
following a new input or mode change is valid.
fO (Pin 35): Frequency Control Pin. Digital input that
controls the internal conversion clock rate. When fO is
connected to GND, the converter uses its internal oscillator
running at 307.2kHz. The conversion clock may also be
overridden by driving the fO pin with an external clock
in order to change the output rate and the digital filter
rejection null.
CS (Pin 36): Active LOW Chip Select. A LOW on this pin
enables the digital input/output and wakes up the ADC.
Following each conversion, the ADC automatically enters
the sleep mode and remains in this low power state as
long as CS is HIGH. A LOW-to-HIGH transition on CS
during the data output aborts the data transfer and starts
a new conversion.
SDO (Pin 37): Three-State Digital Output. During the data
output period, this pin is used as the serial data output.
When the chip select pin is HIGH, the SDO pin is in a high
impedance state. During the conversion and sleep periods,
this pin is used as the conversion status output. When
the conversion is in progress this pin is HIGH; once the
conversion is complete SDO goes LOW. The conversion
status is monitored by pulling CS LOW.
SCK (Pin 38): Bidirectional, Digital I/O, Clock Pin. In internal
serial clock operation mode, SCK is generated internally
and is seen as an output on the SCK pin . In external serial
clock operation mode, the digital I/O clock is externally
applied to the SCK pin. The serial clock operation mode
is determined by the logic level applied to the SCK pin at
power-up and during the most recent falling edge of CS.
Exposed Pad (Pin 39): Ground. This pin is ground and
must be soldered to the PCB ground plane. For prototyping
purposes, this pin may remain floating.
Functional block DiagraM
Figure 1. Functional Block Diagram
AUTOCALIBRATION
AND CONTROL
DIFFERENTIAL
3RD ORDER
ΔΣ MODULATOR
DECIMATING FIR
ADDRESS
INTERNAL
OSCILLATOR
SERIAL
INTERFACE
GND
VCC
CH0
CH1
•
•
•
CH15
COM
MUX
MUXOUTP
MUXOUTN
ADCINP
ADCINN
SDO
SCK
REF+
REF–
CS
SDI
fO
(INT/EXT)
2494 BD
+
–
TEMP
SENSOR
LTC2494
12
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For more information www.linear.com/LTC2494
tiMing DiagraMs
test circuits
Timing Diagram Using Internal SCK (SCK HIGH with CS↓)
Timing Diagram Using External SCK (SCK LOW with CS↓)
1.69k
SDO
2494 TC02
Hi-Z TO VOL
VOH TO VOL
VOL TO Hi-Z
CLOAD = 20pF
VCC
1.69k
SDO
2494 TC01
Hi-Z TO VOH
VOL TO VOH
VOH TO Hi-Z
CLOAD = 20pF
CS
SDO
SCK
SDI
t1
Hi-Z Hi-Z
t3
t7
t8
SLEEP
tKQMAX
CONVERSIONDATA IN/OUT
tKQMIN
t2
2494 TD01
CS
SDO
SCK
SDI
t1
Hi-Z Hi-Z
t5t4
t7
t8
SLEEP
tKQMAX
CONVERSIONDATA IN/OUT
tKQMIN
t2
2494 TD02
LTC2494
13
2494fe
For more information www.linear.com/LTC2494
applications inForMation
CONVERTER OPERATION
Converter Operation Cycle
The LTC2494 is a multichannel, low power, delta-sigma,
analog-to-digital converter with an easy to use, 4-wire in-
terface and automatic differential input current cancellation.
Its operation is made up of four states (See Figure 2). The
converter’s operating cycle begins with the conversion,
followed by the sleep state, and ends with the data input/
output cycle. The 4-wire interface consists of serial data
output (SDO), serial clock (SCK), chip select (CS) and
serial data input (SDI). The interface, timing, operation
cycle and data output format is compatible with Linear’s
entire family of DS converters.
Initially, at power-up, the LTC2494 performs a conversion.
Once the conversion is complete, the device enters the
sleep state. While in this sleep state, if CS is HIGH, power
consumption is reduced by two orders of magnitude. The
part remains in the sleep state as long as CS is HIGH. The
conversion result is held indefinitely in a static shift register
while the part is in the sleep state.
Once CS is pulled LOW, the device powers up, exits the
sleep state, and enters the data input/output state. If CS
is brought HIGH before the first rising edge of SCK, the
device returns to the sleep state and the power is reduced.
If CS is brought HIGH after the first rising edge of SCK, the
data output cycle is aborted and a new conversion cycle
begins. The data output corresponds to the conversion
just completed. This result is shifted out on the serial data
output pin (SDO) under the control of the serial clock pin
(SCK). Data is updated on the falling edge of SCK allowing
the user to reliably latch data on the rising edge of SCK (see
Figure 3). The configuration data for the next conversion
is also loaded into the device at this time. Data is loaded
from the serial data input pin (SDI) on each rising edge
of SCK. The data input/output cycle is concluded once 24
bits are read out of the ADC or when CS is brought HIGH.
The device automatically initiates a new conversion and
the cycle repeats.
Through timing control of the CS and SCK pins, the LTC2494
offers several flexible modes of operation (internal or
external SCK and free-running conversion modes). These
various modes do not require programming and do not
disturb the cyclic operation described above. These modes
of operation are described in detail in the Serial Interface
Timing Modes section.
Ease of Use
The LTC2494 data output has no latency, filter settling
delay, or redundant data associated with the conversion
cycle. There is a one-to-one correspondence between the
conversion and the output data. Therefore, multiplexing
multiple analog inputs is straightforward. Each conversion,
immediately following a newly selected input or mode, is
valid and accurate to the full specifications of the device.
The LTC2494 automatically performs offset and full-scale
calibration every conversion cycle independent of the
input channel selected. This calibration is transparent to
the user and has no effect with the operation cycle previ-
ously described. The advantage of continuous calibration
is extreme stability of offset and full-scale readings with
respect to time, supply voltage variation, input channel
and temperature drift.
Easy Drive Input Current Cancellation
The LTC2494 combines a high precision, delta-sigma ADC
with an automatic, differential, input current cancellation
front end. A proprietary front end passive sampling net-
work transparently removes the differential input current.
Figure 2. LTC2494 State Transition Diagram
CONVERT
SLEEP
CHANNEL SELECT
CONFIGURATION SELECT
DATA OUTPUT
POWER UP
IN+= CH0, IN–= CH1
GAIN = 1, 50/60Hz,1X
2494 F02
CS = LOW
AND
SCK
LTC2494
14
2494fe
For more information www.linear.com/LTC2494
applications inForMation
This enables external RC networks and high impedance
sensors to directly interface to the LTC2494 without
external amplifiers. The remaining common mode input
current is eliminated by either balancing the differential
input impedances or setting the common mode input
equal to the common mode reference (see the Automatic
Differential Input Current Cancellation section). This unique
architecture does not require on-chip buffers, thereby
enabling signals to swing beyond ground or up to VCC.
Moreover, the cancellation does not interfere with the
transparent offset and full-scale auto-calibration and the
absolute accuracy (full-scale + offset + linearity + drift) is
maintained even with external RC networks.
Power-Up Sequence
The LTC2494 automatically enters an internal reset state
when the power supply voltage, VCC, drops below ap-
proximately 2V. This feature guarantees the integrity of
the conversion result, input channel selection and serial
clock mode.
When VCC rises above this threshold, the converter creates
an internal power-on reset (POR) signal with a duration
of approximately 4ms. The POR signal clears all internal
registers. The conversion immediately following a POR
cycle is performed on the input channels IN+ = CH0 and
IN– = CH1 with simultaneous 50Hz/60Hz rejection 1x output
rate, and gain = 1. The first conversion following a POR
cycle is accurate within the specification of the device if
the power supply voltage is restored to (2.7V to 5.5V)
before the end of the POR interval. A new input channel,
rejection mode, speed mode, temperature selection, or
gain can be programmed into the device during this first
data input/output cycle.
Reference Voltage Range
This converter accepts a truly differential external reference
voltage. The absolute/common mode voltage range for the
REF+ and REF– pins covers the entire operating range of
the device (GND to VCC). For correct converter operation,
VREF must be positive (REF+ > REF–).
The LTC2494 differential reference input range is 0.1V to
VCC. For the simplest operation, REF+ can be shorted to
VCC and REF– can be shorted to GND. The converter out-
put noise is determined by the thermal noise of the front
end circuits, and as such, its value in nanovolts is nearly
constant with reference voltage. A decrease in reference
voltage will not significantly improve the converter’s effec-
tive resolution. On the other hand, a decreased reference
will improve the converter’s overall INL performance.
Input Voltage Range
The LTC2494 input measurement range is –0.5 • VREF
to +0.5 • VREF in both differential and single-ended
configurations as shown in Figure 39. Highest linearity
is achieved with Fully Differential drive and a constant
common mode voltage (Figure 39b). Other drive schemes
may incur an INL error of approximately 50ppm. This error
can be calibrated out using a three point calibration and a
second-order curve fit.
The analog input is truly differential with an absolute,
common mode range for CH0 to CH15 and COM input pins
extending from GND – 0.3V to VCC + 0.3V. Outside these
limits, the ESD protection devices begin to turn on and the
errors due to input leakage current increase rapidly. Within
these limits, the LTC2494 converts the bipolar differential
input signal VIN = IN+ – IN– (where IN+ and IN– are the
selected input channels), from –FS = –0.5 • VREF/Gain to
+FS = 0.5 • VREF/Gain where VREF = REF+ – REF–. Outside
this range, the converter indicates the overrange or the
underrange condition using distinct output codes.
Signals applied to the input (CH0 to CH15, COM) may
extend 300mV below ground and above VCC. In order to
limit any fault current, resistors of up to 5k may be added
in series with the input. The effect of series resistance on
the converter accuracy can be evaluated from the curves
presented in the Input Current/Reference Current sections.
In addition, series resistors will introduce a temperature
dependent error due to input leakage current. A 1nA
input leakage current will develop a 1ppm offset error
on a 5k resistor if VREF = 5V. This error has a very strong
temperature dependency.
LTC2494
15
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For more information www.linear.com/LTC2494
applications inForMation
MUXOUT/ADCIN
The output of the multiplexer (MUXOUT) and the input
to the ADC (ADCIN) can be used to perform input signal
conditioning on any of the selected input channels or sim-
ply shorted together for direct digitization. If an external
amplifier is used, the LTC2494 automatically calibrates
both the offset and drift of this circuit and the Easy Drive
sampling scheme enables a wide variety of amplifiers to
be used.
In order to achieve optimum performance, if an external
amplifier is not used, short these pins directly together
(ADCINP to MUXOUTP and ADCINN to MUXOUTN) and
minimize their capacitance to ground.
SERIAL INTERFACE PINS
The LTC2494 transmits the conversion result, reads the
input configuration, and receives a START of conversion
command through a synchronous 3- or 4-wire interface.
During the conversion and sleep states, this interface
can be used to access the converter status. During the
data output state, it is used to read the conversion result,
program the input channel, rejection frequency, speed
multiplier, select the temperature sensor and set the gain.
Serial Clock Input/Output (SCK)
The serial clock pin (SCK) is used to synchronize the data
input/output transfer. Each bit is shifted out of the SDO
pin on the falling edge of SCK and data is shifted into the
SDI pin on the rising edge of SCK.
The serial clock pin (SCK) can be configured as either a
master (SCK is an output generated internally) or a slave
(SCK is an input and applied externally). Master mode
(internal SCK) is selected by simply floating the SCK pin.
Slave mode (external SCK) is selected by driving SCK LOW
during power-up and each falling edge of CS. Specific
details of these SCK modes are described in the Serial
Interface Timing Modes section.
Serial Data Output (SDO)
The serial data output pin (SDO) provides the result of the
last conversion as a serial bit stream (MSB first) during
the data output state. In addition, the SDO pin is used as
an end of conversion indicator during the conversion and
sleep states.
When CS is HIGH, the SDO driver is switched to a high
impedance state in order to share the data output line with
other devices. If CS is brought LOW during the conversion
phase, the EOC bit (SDO pin) will be driven HIGH. Once
the conversion is complete, if CS is brought LOW, EOC will
be driven LOW indicating the conversion is complete and
the result is ready to be shifted out of the device.
Chip Select (CS)
The active LOW CS pin is used to test the conversion status,
enable I/O data transfer, initiate a new conversion, control
the duration of the sleep state and set the SCK mode.
At the conclusion of a conversion cycle, while CS is HIGH,
the device remains in a low power sleep state where the
supply current is reduced several orders of magnitude. In
order to exit the sleep state and enter the data output state,
CS must be pulled LOW. Data is now shifted out the SDO
pin under control of the SCK pin as described previously.
A new conversion cycle is initiated either at the conclusion
of the data output cycle (all 24 data bits read) or by pulling
CS HIGH any time between the first and 24th rising edges
of the serial clock (SCK). In this case, the data output is
aborted and a new conversion begins.
Serial Data Input (SDI)
The serial data input (SDI) is used to select the input
channel, rejection frequency, speed multiplier, gain, and to
access the integrated temperature sensor. Data is shifted
into the device during the data output/input state on the
rising edge of SCK while CS is LOW.
OUTPUT DATA FORMAT
The LTC2494 serial output stream is 24 bits long. The
first bit indicates the conversion status, the second bit is
always zero, and the third bit conveys sign information.
The next 17 bits are the conversion result, MSB first. The
remaining 4 bits are always LOW.
Bit 23 (first output bit) is the end of conversion (EOC)
indicator. This bit is available on the SDO pin during the
LTC2494
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conversion and sleep states whenever CS is LOW. This
bit is HIGH during the conversion cycle, goes LOW once
the conversion is complete, and is Hi-Z when CS is HIGH.
Bit 22 (second output bit) is a dummy bit (DMY) and is
always LOW.
Bit 21 (third output bit) is the conversion result sign
indicator (SIG). If the selected input (VIN = IN+ – IN–) is
greater than or equal to 0V, this bit is HIGH. If VIN < 0,
this bit is LOW.
Bit 20 (fourth output bit) is the most significant bit (MSB)
of the result. This bit in conjunction with Bit 21 also pro-
vides underrange and overrange indication. If both Bit 21
and Bit 20 are HIGH, the differential input voltage is above
+FS. If both Bit 21 and Bit 20 are LOW, the differential
input voltage is below –FS. The function of these bits is
summarized in Table 1.
Table 1. LTC2494 Status Bits
Input Range
Bit 23
EOC
Bit 22
DMY
Bit 21
SIG
Bit 20
MSB
VIN ≥ 0.5 • VREF/Gain 0 0 1 1
0V ≤ VIN < 0.5 • VREF/Gain 0 0 1/0 0
–0.5 • VREF/Gain ≤ VIN < 0V 0 0 0 1
VIN < –0.5 • VREF/Gain 0 0 0 0
Bits 20 to 4 are the 16-bit plus sign conversion result
MSB first.
Bit 4 is the least significant bit (LSB16).
Bits 3 to 0 are always LOW.
Data is shifted out of the SDO pin under control of the
serial clock (SCK) (see Figure 3). Whenever CS is HIGH,
SDO remains high impedance and SCK is ignored.
In order to shift the conversion result out of the device,
CS must first be driven LOW. EOC is seen at the SDO pin
of the device once CS is pulled LOW. EOC changes in real
time from HIGH to LOW at the completion of a conversion.
This signal may be used as an interrupt for an external
microcontroller. Bit 23 (EOC) can be captured on the first
rising edge of SCK. Bit 22 is shifted out of the device on
the first falling edge of SCK. The final data bit (Bit 0) is
shifted out on the on the falling edge of the 23rd SCK and
may be latched on the rising edge of the 24th SCK pulse.
On the falling edge of the 24th SCK pulse, SDO goes HIGH
indicating the initiation of a new conversion cycle. This
bit serves as EOC (Bit 23) for the next conversion cycle.
Table 2 summarizes the output data format.
As long as the voltage on the IN+ and IN– pins remains
between –0.3V and VCC + 0.3V (absolute maximum op-
erating range) a conversion result is generated for any
differential input voltage VIN from –FS = –0.5 • VREF /Gain
to +FS = 0.5 • VREF/Gain. For differential input voltages
greater than +FS, the conversion result is clamped to the
value corresponding to +FS + 1LSB. For differential input
voltages below –FS, the conversion result is clamped to
the value –FS – 1LSB.
Figure 3. Channel Selection, Configuration Selection and Data Output Timing
EOC
CS
SCK
(EXTERNAL)
SDI
SDO
2494 F03
CONVERSION SLEEP DATA INPUT/OUTPUT CONVERSION
MSB
BIT 20 BIT 19 BIT 18 BIT 17 BIT 16 BIT 15 BIT 14 BIT 13 BIT 12 BIT 11
SIG
BIT 21
“0”
BIT 22BIT 23
1 0 EN SGL A2 A1 A0 EN2 IM FA FB SPD GS2 GS1 GS0ODD
BIT 10 BIT 9 BIT 0
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 24
DON'T CAREDON'T CARE
Hi-Z Hi-Z
LTC2494
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INPUT DATA FORMAT
The LTC2494 serial input word is 16 bits long and contains
two distinct sets of data. The first set (SGL, ODD, A2, A1,
A0) is used to select the input channel. The second set of
data (IM, FA, FB, SPD, GS2, GS1, GS0) is used to select
the frequency rejection, speed mode (1x, 2x), temperature
measurement and gain.
After power-up, the device initiates an internal reset cycle
which sets the input channel to CH0 – CH1 (IN+ = CH0, IN– =
CH1), the frequency rejection to simultaneous 50Hz/60Hz,
1x output rate (auto-calibration enabled), and gain = 1. The
first conversion automatically begins at power-up using this
default configuration. Once the conversion is complete, a
new word may be written into the device.
The first three bits shifted into the device consist of two
preamble bits and an enable bit. These bits are used to
enable the device configuration and input channel selec-
tion. Valid settings for these three bits are 000, 100 and
101. Other combinations should be avoided. If the first
three bits are 000 or 100, the following data is ignored
(don’t care) and the previously selected input channel and
configuration remain valid for the next conversion.
If the first three bits shifted into the device are 101, then
the next five bits select the input channel for the next
conversion cycle (see Table 3).
The first input bit following the 101 sequence (SGL) de-
termines if the input selection is differential (SGL = 0) or
single-ended (SGL = 1). For SGL = 0, two adjacent channels
can be selected to form a differential input. For SGL = 1, one
of 16 channels is selected as the positive input. The negative
input is COM for all single-ended operations. The remaining
4 bits (ODD, A2, A1, A0) determine which channel(s) is/are
selected and the polarity (for a differential input).
The next serial input bit immediately following the input
channel selection is the enable bit for the conversion
configuration (EN2). If this bit is set to 0, then the next
conversion is performed using the previously selected
converter configuration. This is useful in systems using
the same rejection/speed for all input channels and for
backward compatibility with the LTC2418/LTC2414 families
of delta-sigma ADCs.
The second set of configuration data can be loaded into the
device by setting EN2 = 1 (see Table 4). The first bit (IM)
is used to select the internal temperature sensor. If IM = 1,
the following conversion will be performed on the internal
temperature sensor rather than the selected input channel.
The next 2 bits (FA and FB) are used to set the rejection
frequency. The next bit (SPD) is used to select either the
1x output rate if SPD = 0 (auto-calibration is enabled and
the offset is continuously calibrated and removed from
the final conversion result) or the 2x output rate if SPD
Table 2. LTC2494 Output Data Format
DIFFERENTIAL INPUT VOLTAGE
VIN*
BIT 23
EOC
BIT 22
DMY
BIT 21
SIG
BIT 20
MSB
BIT 19 BIT 18 BIT 17 … BIT 4 BITS 3 TO 0
VIN* ≥ FS** 0 0 1 1 0 0 0 … 0 0000
FS** – 1LSB 0 0 1 0 1 1 1 … 1 0000
0.5 • FS** 0 0 1 0 1 0 0 … 0 0000
0.5 • FS** – 1LSB 0 0 1 0 0 1 1 … 1 0000
0 0 0 1/0*** 0 0 0 0 … 0 0000
–1LSB 0 0 0 1 1 1 1 … 1 0000
–0.5 • FS** 0 0 0 1 1 0 0 … 0 0000
–0.5 • FS** – 1LSB 0 0 0 1 0 1 1 … 1 0000
–FS** 0 0 0 1 0 0 0 … 0 0000
VIN* < –FS** 0 0 0 0 1 1 1 … 1 0000
*The differential input voltage VIN = IN+ – IN–. **The full-scale voltage FS = 0.5 • VREF/Gain.
***The sign bit changes state during the 0 output code when the device is operating in the 2x speed mode.
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Table 3. Channel Selection
MUX ADDRESS CHANNEL SELECTION
SGL
ODD/
SIGN A2 A1 A0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 COM
*0 0 0 0 0 IN+IN–
00001 IN+IN–
00010 IN+IN–
00011 IN+IN–
00100 IN+IN–
00101 IN+IN–
00110 IN+IN–
00111 IN+IN–
01000IN–IN+
01001 IN–IN+
01010 IN–IN+
01011 IN–IN+
01100 IN–IN+
01101 IN–IN+
01110 IN–IN+
01111 IN–IN+
10000IN+IN–
10001 IN+IN–
10010 IN+IN–
10011 IN+IN–
10100 IN+IN–
10101 IN+IN–
10110 IN+IN–
10111 IN+IN–
11000 IN+IN–
11001 IN+IN–
11010 IN+IN–
11011 IN+IN–
11100 IN+IN–
11101 IN+IN–
11110 IN+IN–
11111 IN+IN–
*Default at power-up
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= 1 (offset calibration disabled, multiplexing output rates
up to 15Hz with no latency). When IM = 1 (temperature
measurement), SPD, GS2, GS1, GS0 will be ignored and
the device will operate in 1x mode. The final 3 bits (GS2,
GS1, GS0) are used to select the gain. The configuration
remains valid until a new input word with EN = 1 (the first
3 bits are 101) and EN2 = 1 is shifted into the device.
Rejection Mode (FA, FB)
The LTC2494 includes a high accuracy on-chip oscillator
with no required external components. Coupled with an
integrated 4th order digital low pass filter, the LTC2494
rejects line frequency noise. In the default mode, the
LTC2494 simultaneously rejects 50Hz and 60Hz by at least
87dB. If more rejection is required, the LTC2494 can be
configured to reject 50Hz or 60Hz to better than 110dB.
Speed Mode (SPD)
Every conversion cycle, two conversions are combined to
remove the offset (default mode). This result is free from
offset and drift. In applications where the offset is not
critical, the auto-calibration feature can be disabled with
the benefit of twice the output rate. While operating in the
2x mode (SPD = 1), the linearity and full-scale errors are
unchanged from the 1x mode performance. In both the 1x
and 2x mode there is no latency. This enables input steps
or multiplexer changes to settle in a single conversion
cycle easing system overhead and increasing the effective
conversion rate. During temperature measurements, the
1x mode is always used independent of the value of SPD.
applications inForMation
Table 4. Converter Configuration
1 0 EN SGL ODD A2 A1 A0 EN2 IM FA FB SPD GS2 GS1 GS0 CONVERTER CONFIGURATION
1 0 0
Any
Input
Channel
X X X X X X X X Keep Previous
1 0 1 0 X X X X X X X Keep Previous
1 0 1 1 0
Any
Rejection
Mode
0 0 0 0 External Input, Gain = 1, Auto-Calibration
1 0 1 1 0 0 0 0 1 External Input, Gain = 4, Auto-Calibration
1 0 1 1 0 0 0 1 0 External Input, Gain = 8, Auto-Calibration
1 0 1 1 0 0 0 1 1 External Input, Gain = 16, Auto-Calibration
1 0 1 1 0 0 1 0 0 External Input, Gain = 32, Auto-Calibration
1 0 1 1 0 0 1 0 1 External Input, Gain = 64, Auto-Calibration
1 0 1 1 0 0 1 1 0 External Input, Gain = 128, Auto-Calibration
1 0 1 1 0 0 1 1 1 External Input, Gain = 256, Auto-Calibration
1 0 1 1 0 1 0 0 0 External Input, Gain = 1, 2x Speed
1 0 1 1 0 1 0 0 1 External Input, Gain = 2, 2x Speed
1 0 1 1 0 1 0 1 0 External Input, Gain = 4, 2x Speed
1 0 1 1 0 1 0 1 1 External Input, Gain = 8, 2x Speed
1 0 1 1 0 1 1 0 0 External Input, Gain = 16, 2x Speed
1 0 1 1 0 1 1 0 1 External Input, Gain = 32, 2x Speed
1 0 1 1 0 1 1 1 0 External Input, Gain = 64, 2x Speed
1 0 1 1 0 1 1 1 1 External Input, Gain = 128, 2x Speed
1 0 1 1 0 0 0
Any
Speed
Any
Gain
External Input, Simultaneous 50Hz/60Hz Rejection
1 0 1 1 0 0 1 External Input, 50Hz Rejection
1 0 1 1 0 1 0 External Input, 60Hz Rejection
1 0 1 1 0 1 1 Reserved, Do Not Use
10 1 1 1 0 0 X X X X Temperature Input, Simultaneous 50Hz/60Hz Rejection
1 0 1 1 1 0 1 X X X X Temperature Input, 50Hz Rejection
1 0 1 1 1 1 0 X X X X Temperature Input, 60Hz Rejection
1 0 1 1 1 1 1 X X X X Reserved, Do Not Use
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GAIN (GS2, GS1, GS0)
The input referred gain of the LTC2494 is adjustable
from 1 to 256 (see Tables 5a and 5b). With a gain of 1,
the differential input range is ±VREF/2 and the common
mode input range is rail-to-rail. As the gain is increased,
the differential input range is reduced to ±0.5 • VREF/Gain
but the common mode input range remains rail-to-rail.
As the differential gain is increased, low level voltages
are digitized with greater resolution. At a gain of 256, the
LTC2494 digitizes an input signal range of ±9.76mV with
over 16,000 counts.
Temperature Sensor
The LTC2494 includes an integrated temperature sensor.
The temperature sensor is selected by setting IM = 1.
During temperature readings, MUXOUTN/MUXOUTP
remains connected to the selected input channel. The
ADC internally connects to the temperature sensor and
performs a conversion.
The digital output is proportional to the absolute tem-
perature of the device. This feature allows the converter
to perform cold junction compensation for external
thermocouples or continuously remove the temperature
effects of external sensors.
The internal temperature sensor output is 28mV at 27°C
(300°K), with a slope of 93.5µV/°C independent of VREF.
Slope calibration is not required if the reference voltage
(VREF) is known. A 5V reference has a slope of 2.45
LSBs16/°C. The temperature is calculated from the output
code (where DATAOUT16 is the decimal representation of
the 16-bit result) for a 5V reference using the following
formula:
TK = DATAOUT16/2.45 in Kelvin
If a different value of VREF is used, the temperature output is:
TK = DATAOUT16 • VREF/12.25 in Kelvin
If the value of VREF is not known, the slope is determined by
measuring the temperature sensor at a known temperature
TN (in °K) and using the following formula:
SLOPE = DATAOUT16/TN
This value of slope can be used to calculate further tem-
perature readings using:
TK = DATAOUT16/SLOPE
All Kelvin temperature readings can be converted to TC
(°C) using the fundamental equation:
TC = TK – 273
Table 5a. Performance vs Gain in Normal Speed Mode (VCC = 5V, VREF = 5V)
GAIN 1 4 8 16 32 64 128 256 UNIT
Input Span ±2.5 ±0.625 ±0.312 ±0.156 ±78m ±39m ±19.5m ±9.76m V
LSB 38.1 9.54 4.77 2.38 1.19 0.596 0.298 0.149 µV
Noise Free Resolution* 65536 65536 65536 65536 65536 65536 32768 16384 Counts
Gain Error 5 5 5 5 5 5 5 8 ppm of FS
Offset Error 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 µV
Table 5b. Performance vs Gain in 2x Speed Mode (VCC = 5V, VREF = 5V)
GAIN 1 2 4 8 16 32 64 128 UNIT
Input Span ±2.5 ±1.25 ±0.625 ±0.312 ±0.156 ±78m ±39m ±19.5m V
LSB 38.1 19.1 9.54 4.77 2.38 1.19 0.596 0.298 µV
Noise Free Resolution* 65536 65536 65536 65536 65536 65536 45875 22937 Counts
Gain Error 5 5 5 5 5 5 5 5 ppm of FS
Offset Error 200 200 200 200 200 200 200 200 µV
*The resolution in counts is calculated as the FS divided by LSB or the RMS noise value, whichever is larger.
LTC2494
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Figure 4. Internal PTAT Digital Output vs Temperature Figure 5. Absolute Temperature Error
Table 6. LTC2494 Interface Timing Modes
CONFIGURATION
SCK
SOURCE
CONVERSION
CYCLE CONTROL
DATA OUTPUT
CONTROL
CONNECTION AND
WAVEFORMS
External SCK, Single Cycle
Conversion
External CS and SCK CS and SCK Figures 6, 7
External SCK, 3-Wire I/O External SCK SCK Figure 8
Internal SCK, Single Cycle
Conversion
Internal CS↓CS↓Figures 9, 10
Internal SCK, 3-Wire I/O,
Continuous Conversion
Internal Continuous Internal Figure 11
SERIAL INTERFACE TIMING MODES
The LTC2494’s 4-wire interface is SPI and MICROWIRE
compatible. This interface offers several flexible modes
of operation. These include internal/external serial clock,
3- or 4-wire I/O, single cycle or continuous conversion. The
following sections describe each of these timing modes
in detail. In all cases, the converter can use the internal
oscillator (fO = LOW) or an external oscillator connected to
the fO pin. For each mode, the operating cycle, data input
format, data output format and performance remain the
same. Refer to Table 6 for a summary.
External Serial Clock, Single Cycle Operation
This timing mode uses an external serial clock to shift out
the conversion result and CS to monitor and control the
state of the conversion cycle (see Figure 6).
The external serial clock mode is selected during the pow-
er-up sequence and on each falling edge of CS. In order to
enter and remain in the external SCK mode of operation,
SCK must be driven LOW both at power-up and on each
CS falling edge. If SCK is HIGH on the falling edge of CS,
the device will switch to the internal SCK mode.
The serial data output pin (SDO) is Hi-Z as long as CS is
HIGH. At any time during the conversion cycle, CS may be
pulled LOW in order to monitor the state of the converter.
While CS is LOW, EOC is output to the SDO pin.
EOC = 1 while a conversion is in progress and EOC = 0 if
the conversion is complete and the device is in the sleep
state. Independent of CS, the device automatically enters
the sleep state once the conversion is complete; however,
in order to reduce the power, CS must be HIGH.
When the device is in the sleep state, its conversion result
is held in an internal static shift register. The device remains
in the sleep state until the first rising edge of SCK is seen
while CS is LOW. The input data is then shifted in via the
SDI pin on each rising edge of SCK (including the first rising
applications inForMation
TEMPERATURE (K)
0
DATAOUT16
480
640
800
960
1020
400
2494 F04
320
0300200100
160
VCC = 5V
VREF = 5V
SLOPE = 2.45 LSB16/K
TEMPERATURE (°C)
–55 –30 –5
ABSOLUTE ERROR (°C)
5
4
3
2
1
–4
–3
–2
–1
0
12095704520
2494 F05
–5
LTC2494
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edge). The channel selection and converter configuration
mode will be used for the following conversion cycle. If
the input channel or converter configuration is changed
during this I/O cycle, the new settings take effect on the
conversion cycle following the data input/output cycle.
The output data is shifted out the SDO pin on each falling
edge of SCK. This enables external circuitry to latch the
output on the rising edge of SCK. EOC can be latched on
the first rising edge of SCK and the last bit of the conver-
sion result can be latched on the 24th rising edge of SCK.
On the 24th falling edge of SCK, the device begins a new
conversion and SDO goes HIGH (EOC = 1) indicating a
conversion is in progress.
At the conclusion of the data cycle, CS may remain LOW
and EOC monitored as an end-of-conversion interrupt.
Typically, CS remains LOW during the data output/input
state. However, the data output state may be aborted by
pulling CS HIGH any time between the 1st falling edge
and the 24th falling edge of SCK (see Figure 7). On the
rising edge of CS, the device aborts the data output state
and immediately initiates a new conversion. In order to
program a new input channel, 8 SCK clock pulses are
required. If the data output sequence is aborted prior to
the 8th falling edge of SCK, the new input data is ignored
and the previously selected input channel remains valid.
If the rising edge of CS occurs after the 8th falling edge
of SCK, the new input channel is loaded and valid for the
next conversion cycle. If CS goes HIGH between the 8th
falling edge and the 16th falling edge of SCK, the new
channel is still loaded, but the converter configuration
remains unchanged. In order to program both the input
channel and converter configuration, CS must go HIGH
after the 16th falling edge of SCK (at this point all data
has been shifted into the device).
Figure 6. External Serial Clock, Single Cycle Operation
Hi-Z
2494 F06
Hi-Z
CS
SCK
(EXTERNAL)
SDI
SDO
CONVERSION SLEEP DATA INPUT/OUTPUT CONVERSION
VCC fO
REF+
REF–
CH0
CH7
CH8
CH15
COM
SCK
SDI
SDO
CS
GND
28 35
29
30
8
15
16
23
7
38
37
1,3,4,5,6,31,32,33,39
36
34
REFERENCE
VOLTAGE
0.1V TO VCC
ANALOG
INPUTS
= EXTERNAL OSCILLATOR
= INTERNAL OSCILLATOR
10µF
0.1µF LTC2494
2.7V TO 5.5V
4-WIRE
SPI INTERFACE
•
•
•
•
•
•
•
•
•
•
•
•
EOC
BIT 20 BIT 19 BIT 18 BIT 17 BIT 16 BIT 15 BIT 14 BIT 13 BIT 12 BIT 11BIT 21BIT 22BIT 23 BIT 10 BIT 9 BIT 0
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 24
1 0 EN SGL A2 A1 A0 EN2 IM FA FB SPD GS2 GS1 GS0ODD DON'T CAREDON'T CARE
MSBSIG“0”
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Figure 7. External Serial Clock, Reduced Output Data Length and Valid Channel Selection
applications inForMation
Figure 8. External Serial Clock, 3-Wire Operation (CS = 0)
Hi-Z
2494 F07
CS
SCK
(EXTERNAL)
SDI
SDO
CONVERSION SLEEP DATA INPUT/OUTPUT SLEEPCONVERSION
VCC fO
REF+
REF–
CH0
CH7
CH8
CH15
COM
SCK
SDI
SDO
CS
GND
28 35
29
30
8
15
16
23
7
38
37
1,3,4,5,6,31,32,33,39
36
34
REFERENCE
VOLTAGE
0.1V TO VCC
ANALOG
INPUTS
= EXTERNAL OSCILLATOR
= INTERNAL OSCILLATOR
LTC2494
4-WIRE
SPI INTERFACE
•
•
•
•
•
•
•
•
•
•
•
•
EOC
BIT 20 BIT 19 BIT 18 BIT 17 BIT 16 BIT 15BIT 21BIT 22BIT 23
1 2 3 4 5 6 7 8
1 0 EN SGL A2 A1 A0ODD DON'T CAREDON'T CARE
MSBSIG“0”
10µF
0.1µF
2.7V TO 5.5V
VCC fO
REF+
REF–
CH0
CH7
CH8
CH15
COM
SCK
SDI
SDO
CS
GND
28 35
29
30
8
15
16
23
7
38
37
1,3,4,5,6,31,32,33,39
36
34
REFERENCE
VOLTAGE
0.1V TO VCC
ANALOG
INPUTS
= EXTERNAL OSCILLATOR
= INTERNAL OSCILLATOR
LTC2494
3-WIRE
SPI INTERFACE
•
•
•
•
•
•
•
•
•
•
•
•
EOC
CS
SCK
(EXTERNAL)
SDI
SDO 2494 F08
CONVERSION SLEEP DATA INPUT/OUTPUT CONVERSION
BIT 20 BIT 19 BIT 18 BIT 17 BIT 16 BIT 15 BIT 14 BIT 13 BIT 12 BIT 11BIT 21BIT 22BIT 23
1 0 EN SGL A2 A1 A0 EN2 IM FA FB SPD GS2 GS1 GS0ODD
BIT 10 BIT 9 BIT 0
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 24
DON'T CAREDON'T CARE
MSBSIG“0”
10µF
0.1µF
2.7V TO 5.5V
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applications inForMation
External Serial Clock, 3-Wire I/O
This timing mode uses a 3-wire serial I/O interface. The
conversion result is shifted out of the device by an exter-
nally generated serial clock (SCK) signal (see Figure 8).
CS is permanently tied to ground, simplifying the user
interface or isolation barrier.
The external serial clock mode is selected at the end of
the power-on reset (POR) cycle. The POR cycle is typically
concluded 4ms after VCC exceeds 2V. The level applied to
SCK at this time determines if SCK is internally generated
or externally applied. In order to enter the external SCK
mode, SCK must be driven LOW prior to the end of the
POR cycle.
Since CS is tied LOW, the end-of-conversion (EOC) can
be continuously monitored at the SDO pin during the
convert and sleep states. EOC may be used as an interrupt
to an external controller. EOC = 1 while the conversion is
in progress and EOC = 0 once the conversion is com-
plete. On the falling edge of EOC, the conversion result
is loading into an internal static shift register
. The output
data can now be shifted out the SDO pin under control
of the externally applied SCK signal. Data is updated on
the falling edge of SCK. The input data is shifted into the
device through the SDI pin on the rising edge of SCK. On
the 24th falling edge of SCK, SDO goes HIGH, indicating a
new conversion has begun. This data now serves as EOC
for the next conversion.
Internal Serial Clock, Single Cycle Operation
This timing mode uses the internal serial clock to shift out
the conversion result and CS to monitor and control the
state of the conversion cycle (see Figure 9).
In order to select the internal serial clock timing mode,
the serial clock pin (SCK) must be floating or pulled HIGH
before the conclusion of the POR cycle and prior to each
falling edge of CS. An internal weak pull-up resistor is active
on the SCK pin during the falling edge of CS; therefore,
the internal SCK mode is automatically selected if SCK is
not externally driven.
Figure 9. Internal Serial Clock, Single Cycle Operation
10µF
0.1µF
2.7V TO 5.5V
Hi-Z
2494 F09
CS
SCK
(INTERNAL)
SDI
SDO
CONVERSION SLEEP DATA INPUT/OUTPUT CONVERSION
VCC fO
REF+
REF–
CH0
CH7
CH8
CH15
COM
SCK
SDI
SDO
CS
GND
28 35
29
30
8
15
16
23
7
38
37
1,3,4,5,6,31,32,33,39
36
34
REFERENCE
VOLTAGE
0.1V TO VCC
ANALOG
INPUTS
= EXTERNAL OSCILLATOR
= INTERNAL OSCILLATOR
LTC2494
4-WIRE
SPI INTERFACE
•
•
•
•
•
•
•
•
•
•
•
•
EOC
BIT 20 BIT 19 BIT 18 BIT 17 BIT 16 BIT 15 BIT 14 BIT 13 BIT 12 BIT 11BIT 21BIT 22BIT 23 BIT 10 BIT 9 BIT 0
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 24
1 0 EN SGL A2 A1 A0 EN2 IM FA FB SPD GS2 GS1 GS0ODD DON'T CAREDON'T CARE
MSBSIG“0”
OPTIONAL
10k
VCC
<tEOCTEST
LTC2494
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applications inForMation
Figure 10. Internal Serial Clock, Reduced Data Output Length with Valid Channel and Configuration Selection
The serial data output pin (SDO) is Hi-Z as long as CS is
HIGH. At any time during the conversion cycle, CS may be
pulled LOW in order to monitor the state of the converter.
Once CS is pulled LOW, SCK goes LOW and EOC is output
to the SDO pin. EOC= 1 while the conversion is in progress
and EOC = 0 if the device is in the sleep state.
When testing EOC, if the conversion is complete (EOC = 0),
the device will exit sleep state. In order to return to the
sleep state and reduce the power consumption, CS must be
pulled HIGH before the device pulls SCK HIGH. When the
device is using its own internal oscillator (fO is tied LOW),
the first rising edge of SCK occurs 12µs (tEOCTEST = 12µs)
after the falling edge of CS. If fO is driven by an external
oscillator of frequency fEOSC, then tEOCTEST = 3.6/fEOSC.
If CS remains LOW longer than tEOCTEST, the first rising
edge of SCK will occur and the conversion result is shifted
out the SDO pin on the falling edge of SCK. The serial
input word (SDI) is shifted into the device on the rising
edge of SCK.
After the 24th rising edge of SCK a new conversion au-
tomatically begins. SDO goes HIGH (EOC = 1) and SCK
remains HIGH for the duration of the conversion cycle.
Once the conversion is complete, the cycle repeats.
Typically, CS remains LOW during the data output state.
However, the data output state may be aborted by pulling
CS HIGH any time between the 1st rising edge and the 24th
falling edge of SCK (see Figure 10). On the rising edge of
CS, the device aborts the data output state and immediately
initiates a new conversion. In order to program a new input
channel, 8 SCK clock pulses are required. If the data output
sequence is aborted prior to the 8th falling edge of SCK,
the new input data is ignored and the previously selected
input channel remains valid. If the rising edge of CS occurs
after the 8th falling edge of SCK, the new input channel is
loaded and valid for the next conversion cycle. If CS goes
HIGH between the 8th falling edge and the 16th falling edge
of SCK, the new channel is still loaded, but the converter
configuration remains unchanged. In order to program
Hi-Z
2494 F10
CS
SCK
(INTERNAL)
SDI
SDO
CONVERSION SLEEP DATA INPUT/OUTPUT
EOC
BIT 20 BIT 19 BIT 18 BIT 17 BIT 16 BIT 15 BIT 14 BIT 13 BIT 12 BIT 11BIT 21BIT 22BIT 23 BIT 10 BIT 9 BIT 8 BIT 7
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
1 0 EN SGL A2 A1 A0 EN2 IM FA FB SPD GS2 GS1 GS0ODD DON'T CAREDON'T CARE
MSBSIG“0”
<tEOCTEST
CONVERSION
10µF
0.1µF
2.7V TO 5.5V
VCC fO
REF+
REF–
CH0
CH7
CH8
CH15
COM
SCK
SDI
SDO
CS
GND
28 35
29
30
8
15
16
23
7
38
37
1,3,4,5,6,31,32,33,39
36
34
REFERENCE
VOLTAGE
0.1V TO VCC
ANALOG
INPUTS
= EXTERNAL OSCILLATOR
= INTERNAL OSCILLATOR
LTC2494
4-WIRE
SPI INTERFACE
•
•
•
•
•
•
•
•
•
•
•
•
OPTIONAL
10k
VCC
LTC2494
26
2494fe
For more information www.linear.com/LTC2494
both the input channel and converter configuration, CS
must go HIGH after the 16th falling edge of SCK (at this
point all data has been shifted into the device).
Internal Serial Clock, 3-Wire I/O, Continuous
Conversion.
This timing mode uses a 3-wire interface. The conversion
result is shifted out of the device by an internally generated
serial clock (SCK) signal (see Figure 11). In this case, CS is
permanently tied to ground, simplifying the user interface
or transmission over an isolation barrier.
The internal serial clock mode is selected at the end of the
power-on reset (POR) cycle. The POR cycle is concluded
approximately 4ms after VCC exceeds 2V. An internal weak
pull-up is active during the POR cycle; therefore, the internal
serial clock timing mode is automatically selected if SCK
is floating or driven HIGH.
During the conversion, the SCK and the serial data output
pin (SDO) are HIGH (EOC = 1). Once the conversion is
complete, SCK and SDO go LOW (EOC = 0) indicating
the conversion has finished and the device has entered
the sleep state. The device remains in the sleep state a
minimum amount of time (1/2 the internal SCK period)
then immediately begins outputting and inputting data.
The input data is shifted through the SDI pin on the ris-
ing edge of SCK (including the first rising edge) and the
output data is shifted out the SDO pin on the falling edge
of SCK. The data input/output cycle is concluded and a
new conversion automatically begins after the 24th rising
edge of SCK. During the next conversion, SCK and SDO
remain HIGH until the conversion is complete.
The Use of a 10k Pull-Up on SCK for Internal SCK
Selection
If CS is pulled HIGH while the converter is driving SCK
LOW
, the internal pull-up is not available to restore SCK
to a logic HIGH state if SCK is floating. This will cause the
device to exit the internal SCK mode on the next falling
edge of CS. This can be avoided by adding an external 10k
pull-up resistor to the SCK pin.
applications inForMation
Figure 11. Internal Serial Clock, Continuous Operation
10µF
0.1µF
2.7V TO 5.5V
EOC
CS
SCK
(INTERNAL)
SDI
SDO 2494 F11
CONVERSION DATA INPUT/OUTPUT CONVERSION
BIT 20 BIT 19 BIT 18 BIT 17 BIT 16 BIT 15 BIT 14 BIT 13 BIT 12 BIT 11BIT 21BIT 22BIT 23
1 0 EN SGL A2 A1 A0 EN2 IM FA FB SPD GS2 GS1 GS0ODD
BIT 10 BIT 9 BIT 0
2 31 4 5 6 7 8 9 10 11 12 13 14 15 16 24
DON'T CAREDON'T CARE
MSBSIG“0”
VCC fO
REF+
REF–
CH0
CH7
CH8
CH15
COM
SCK
SDI
SDO
CS
GND
28 35
29
30
8
15
16
23
7
38
37
1,3,4,5,6,31,32,33,39
36
34
REFERENCE
VOLTAGE
0.1V TO VCC
ANALOG
INPUTS
= EXTERNAL OSCILLATOR
= INTERNAL OSCILLATOR
LTC2494
3-WIRE
SPI INTERFACE
•
•
•
•
•
•
•
•
•
•
•
•
OPTIONAL
10k
VCC
LTC2494
27
2494fe
For more information www.linear.com/LTC2494
applications inForMation
Whenever SCK is LOW, the LTC2494’s internal pull-up at
SCK is disabled. Normally, SCK is not externally driven if
the device is operating in the internal SCK timing mode.
However, certain applications may require an external
driver on SCK. If the driver goes Hi-Z after outputting a
LOW signal, the internal pull-up is disabled. An external
10k pull-up resistor prevents the device from exiting the
internal SCK mode under this condition.
A similar situation may occur during the sleep state when
CS is pulsed HIGH-LOW-HIGH in order to test the conver-
sion status. If the device is in the sleep state (EOC = 0),
SCK will go LOW. If CS goes HIGH before the time tEOCtest,
the internal pull-up is activated. If SCK is heavily loaded,
the internal pull-up may not restore SCK to a HIGH state
before the next falling edge of CS. The external 10k pull-up
resistor prevents the device from exiting the internal SCK
mode under this condition.
PRESERVING THE CONVERTER ACCURACY
The LTC2494 is designed to reduce as much as possible
sensitivity to device decoupling, PCB layout, anti-aliasing
circuits, line frequency perturbations and temperature
sensitivity. In order to achieve maximum performance a
few simple precautions should be observed.
Digital Signal Levels
The LTC2494’s digital interface is easy to use. Its digital
inputs SDI, fO, CS and SCK (in external serial clock mode)
accept standard CMOS logic levels. Internal hysteresis
circuits can tolerate edge transition times as slow as 100µs.
The digital input signal range is 0.5V to VCC – 0.5V. During
transitions, the CMOS input circuits draw dynamic current.
For optimal performance, application of signals to the
serial data interface should be reserved for the sleep and
data output periods.
During the conversion period, overshoot and undershoot
of fast digital signals applied to both the serial digital
interface and the external oscillator pin (fO) may degrade
the converter performance. Undershoot and overshoot
occur due to impedance mismatch of the circuit board
trace at the converter pin when the transition time of an
external control signal is less than twice the propagation
delay from the driver to the input pin. For reference, on a
regular FR-4 board, the propagation delay is approximately
183ps/inch. In order to prevent overshoot, a driver with
a 1ns transition time must be connected to the converter
through a trace shorter than 2.5 inches. This becomes
difficult when shared control lines are used and multiple
reflections occur.
Parallel termination near the input pin of the LTC2494 will
eliminate this problem, but will increase the driver power
dissipation. A series resistor from 27Ω to 54Ω (depend-
ing on the trace impedance and connection) placed near
the driver will also eliminate over/under shoot without
additional driver power dissipation.
For many applications, the serial interface pins (SCK, SDI,
CS, fO) remain static during the conversion cycle and no
degradation occurs. On the other hand, if an external
oscillator is used (fO driven externally) it is active during
the conversion cycle. Moreover, the digital filter rejection
is minimal at the clock rate applied to fO. Care must be
taken to ensure external inputs and reference lines do not
cross this signal or run near it. These issues are avoided
when using the internal oscillator.
Driving the Input and Reference
The input and reference pins of the LTC2494 are connected
directly to a switched capacitor network. Depending on
the relationship between the differential input voltage and
the differential reference voltage, these capacitors are
switched between these four pins. Each time a capacitor
is switched between two of these pins, a small amount
of charge is transferred. A simplified equivalent circuit is
shown in Figure 12.
When using the LTC2494’s internal oscillator, the input
capacitor array is switched at 123kHz. The effect of the
charge transfer depends on the circuitry driving the input/
reference pins. If the total external RC time constant is less
then 580ns the errors introduced by the sampling process
are negligible since complete settling occurs.
Typically, the reference inputs are driven from a low imped-
ance source. In this case, complete settling occurs even
with large external bypass capacitors. The inputs (CH0 to
CH15, COM), on the other hand, are typically driven from
larger source resistances. Source resistances up to 10k
LTC2494
28
2494fe
For more information www.linear.com/LTC2494
applications inForMation
may interface directly to the LTC2494 and settle completely;
however, the addition of external capacitors at the input
terminals in order to filter unwanted noise (anti-aliasing)
results in incomplete settling.
The LTC2494 offers two methods of removing these errors.
The first is automatic differential input current cancellation
(Easy Drive) and the second is the insertion of buffer
between the MUXOUT and ADCIN pins, thus isolating the
input switching from the source resistance.
Automatic Differential Input Current Cancellation
In applications where the sensor output impedance is
low (up to 10kΩ with no external bypass capacitor or up
to 500Ω with 0.001µF bypass), complete settling of the
input occurs. In this case, no errors are introduced and
direct digitization is possible.
For many applications, the sensor output impedance
combined with external input bypass capacitors produces
RC time constants much greater than the 580ns required
for 1ppm accuracy. For example, a 10k bridge driving a
0.1µF capacitor has a time constant an order of magnitude
greater than the required maximum.
The LTC2494 uses a proprietary switching algorithm
that forces the average differential input current to zero
independent of external settling errors. This allows direct
digitization of high impedance sensors without the need
of buffers.
The switching algorithm forces the average input current
on the positive input (IIN+) to be equal to the average input
current in the negative input (IIN–). Over the complete
conversion cycle, the average input current (IIN+ – IIN–)
is zero. While the differential input current is zero, the
common mode input current (IIN+ + IIN–)/2 is proportional
to the difference between the common mode input volt-
age (VIN(CM)) and the common mode reference voltage
(VREF(CM)).
In applications where the input common mode voltage is
equal to the reference common mode voltage, as in the
case of a balanced bridge, both the differential and common
mode input current are zero. The accuracy of the converter
is not compromised by settling errors.
In applications where the input common mode voltage is
constant but different from the reference common mode
voltage, the differential input current remains zero while
the common mode input current is proportional to the
Figure 12. LTC2494 Equivalent Analog Input Circuit
IN+
IN–
10k
INTERNAL
SWITCH
NETWORK
10k
CEQ
12pF
10k
IIN–
REF+
IREF+
IIN+
IREF–
2494 F12
SWITCHING FREQUENCY
fSW = 123kHz INTERNAL OSCILLATOR
f
SW
= 0.4 • f
EOSC
EXTERNAL OSCILLATOR
REF–
10k
100Ω
INPUT
MULTIPLEXER EXTERNAL
CONNECTION
100Ω
MUXOUTP ADCINP
EXTERNAL
CONNECTION
MUXOUTN ADCINN
I IN+
( )
AVG =I IN–
( )
AVG =V
IN(CM) −VREF(CM)
0.5•REQ
I REF+
( )
AVG ≈1.5VREF +VREF(CM) – V
IN(CM)
( )
0.5 •REQ
–V
IN
2
VREF •REQ
where:
VREF =REF+−REF−
VREF(CM) =REF+– REF−
2
V
IN =IN+−IN−, WHERE IN+AND IN−ARE THE SELECTEDINPUT CHANNELS
VIN(CM) =IN+–IN−
2
REQ =2.71MΩINTERNAL OSCILLATOR 60Hz MODE
REQ =2.98MΩINTERNAL OSCILLATOR 50Hz/60Hz MODE
REQ =0.833•1012
( )
/fEOSC EXTERNAL OSCILLATOR
LTC2494
29
2494fe
For more information www.linear.com/LTC2494
Figure 13. External Buffers Provide High Impedance Inputs and
Amplifier Offsets are Automatically Cancelled.
applications inForMation
difference between VIN(CM) and VREF(CM). For a reference
common mode voltage of 2.5V and an input common mode
of 1.5V, the common mode input current is approximately
0.74µA (in simultaneous 50Hz/60Hz rejection mode). This
common mode input current does not degrade the accuracy
if the source impedances tied to IN+ and IN– are matched.
Mismatches in source impedance lead to a fixed offset
error but do not effect the linearity or full-scale reading.
A 1% mismatch in a 1k source resistance leads to a 74µV
shift in offset voltage.
In applications where the common mode input voltage
varies as a function of the input signal level (single-ended
type sensors), the common mode input current varies
proportionally with input voltage. For the case of balanced
input impedances, the common mode input current effects
are rejected by the large CMRR of the LTC2494, leading
to little degradation in accuracy. Mismatches in source
impedances lead to gain errors proportional to the dif-
ference between the common mode input and common
mode reference. 1% mismatches in 1k source resistanc-
es lead to gain errors on the order of 15ppm. Based on
the stability of the internal sampling capacitors and the
accuracy of the internal oscillator
, a one-time calibration
will remove this error
.
–
+
–
+
1/2 LTC6078
1/2 LTC6078
1
2
3
5
6
7
∆Σ ADC
WITH
EASY DRIVE
INPUTS
INPUT
MUX
MUXOUTP
MUXOUTN
17
2494 F13
LTC2494
ANALOG
INPUTS SDI
SCK
SDO
CS
1k
1k
0.1µF
0.1µF
In addition to the input sampling current, the input ESD
protection diodes have a temperature dependent leakage
current. This current, nominally 1nA (±10nA max) results
in a small offset shift. A 1k source resistance will create a
1µV typical and a 10µV maximum offset voltage.
Automatic Offset Calibration of External Buffers/
Amplifiers
In addition to the Easy Drive input current cancellation,
the LTC2494 enables an external amplifier to be inserted
between the multiplexer output and the ADC input (see
Figure 13). This is useful in applications where balanced
source impedances are not possible. One pair of external
buffers/amplifiers can be shared between all 17 analog
inputs. The LTC2494 performs an internal offset calibration
every conversion cycle in order to remove the offset and
drift of the ADC. This calibration is performed through a
combination of front end switching and digital process-
ing. Since the external amplifier is placed between the
multiplexer and the ADC, it is inside this correction loop.
This results in automatic offset correction and offset drift
removal of the external amplifier.
The LTC6078 is an excellent amplifier for this function.
It operates with supply voltages as low as 2.7V and its
noise level is 18nV/√Hz. The Easy Drive input technology
of the LTC2494 enables an RC network to be added directly
to the output of the LTC6078. The capacitor reduces the
magnitude of the current spikes seen at the input to the
ADC and the resistor isolates the capacitor load from the
op-amp output enabling stable operation.
Reference Current
Similar to the analog inputs, the LTC2494 samples the
differential reference pins (REF+ and REF–) transferring
small amounts of charge to and from these pins, thus pro-
ducing a dynamic reference current. If incomplete settling
occurs (as a function the reference source resistance and
reference bypass capacitance) linearity and gain errors
are introduced.
For relatively small values of external reference capaci-
tance (CREF < 1nF), the voltage on the sampling capacitor
settles for reference impedances of many kΩ (if CREF =
LTC2494
30
2494fe
For more information www.linear.com/LTC2494
applications inForMation
100pF up to 10k will not degrade the performance) (see
Figures 14, 15).
In cases where large bypass capacitors are required
on the reference inputs (CREF > 0.01µF) full-scale and
linearity errors are proportional to the value of the refer-
ence resistance. Every ohm of reference resistance pro-
duces a full-scale error of approximately 0.5ppm (while
operating in simultaneous 50Hz/60Hz mode) (see Figures
16 and 17). If the input common mode voltage is equal to
the reference common mode voltage, a linearity error of
approximately 0.67ppm per 100Ω of reference resistance
results (see Figure 18). In applications where the input
and reference common mode voltages are different, the
errors increase. A 1V difference in between common mode
input and common mode reference results in a 6.7ppm
INL error for every 100Ω of reference resistance.
Figure 16. +FS Error vs RSOURCE at VREF (Large CREF)
Figure 17. –FS Error vs RSOURCE at VREF (Large CREF)
Figure 18. INL vs Differential Input Voltage and
Reference Source Resistance for CREF > 1µF
Figure 14. +FS Error vs RSOURCE at VREF (Small CREF)
Figure 15. –FS Error vs RSOURCE at VREF (Small CREF)
RSOURCE (Ω)
0
+FS ERROR (ppm)
50
70
90
10k
2494 F14
30
10
40
60
80
20
0
–10 10 100 1k 100k
VCC = 5V
VREF = 5V
VIN+ = 3.75V
VIN– = 1.25V
fO = GND
TA = 25°C
CREF = 0.01µF
CREF = 0.001µF
CREF = 100pF
CREF = 0pF
RSOURCE (Ω)
0
–FS ERROR (ppm)
–30
–10
10
10k
2494 F15
–50
–70
–40
–20
0
–60
–80
–90 10 100 1k 100k
VCC = 5V
VREF = 5V
VIN+ = 1.25V
VIN– = 3.75V
fO = GND
TA = 25°C
CREF = 0.01µF
CREF = 0.001µF
CREF = 100pF
CREF = 0pF
RSOURCE (Ω)
0
+FS ERROR (ppm)
300
400
500
800
2494 F16
200
100
0200 400 600 1000
VCC = 5V
VREF = 5V
VIN+ = 3.75V
VIN– = 1.25V
fO = GND
TA = 25°C
CREF = 1µF, 10µF
CREF = 0.1µF
CREF = 0.01µF
RSOURCE (Ω)
0
–FS ERROR (ppm)
–200
–100
0
800
2494 F17
–300
–400
–500 200 400 600 1000
VCC = 5V
VREF = 5V
VIN+ = 1.25V
VIN– = 3.75V
fO = GND
TA = 25°C
CREF = 1µF, 10µF
CREF = 0.1µF
CREF = 0.01µF
VIN/VREF (V)
–0.5
INL (ppm OF V
REF
)
2
6
10
0.3
2494 F18
–2
–6
0
4
8
–4
–8
–10 –0.3 –0.1 0.1 0.5
VCC = 5V
VREF = 5V
VIN(CM) = 2.5V
TA = 25°C
CREF = 10µF
R = 1k
R = 100Ω
R = 500Ω
LTC2494
31
2494fe
For more information www.linear.com/LTC2494
Figure 19. Input Normal Mode Rejection, Internal
Oscillator and 50Hz Rejection Mode
Figure 20. Input Normal Mode Rejection, Internal
Oscillator and 60Hz Rejection Mode
applications inForMation
In addition to the reference sampling charge, the reference
ESD projection diodes have a temperature dependent leak-
age current. This leakage current, nominally 1nA (±10nA
max) results in a small gain error. A 100Ω reference
resistance will create a 0.5µV full-scale error.
Normal Mode Rejection and Anti-Aliasing
One of the advantages delta-sigma ADCs offer over
conventional ADCs is on-chip digital filtering. Combined
with a large oversample ratio, the LTC2494 significantly
simplifies anti-aliasing filter requirements. Additionally,
the input current cancellation feature allows external low
pass filtering without degrading the DC performance of
the device.
The SINC4 digital filter provides excellent normal mode
rejection at all frequencies except DC and integer multiples
of the modulator sampling frequency (fS) (see Figures
19 and 20). The modulator sampling frequency is fS =
15,360Hz while operating with its internal oscillator and
fS = FEOSC/20 when operating with an external oscillator
of frequency FEOSC.
When using the internal oscillator, the LTC2494 is designed
to reject line frequencies. As shown in Figure 21, rejection
nulls occur at multiples of frequency fN, where fN is deter-
mined by the input control bits FA and FB (fN = 50Hz or
60Hz or 55Hz for simultaneous rejection). Multiples of the
modulator sampling rate (fS = fN • 256) only reject noise
to 15dB (see Figure 22), if noise sources are present at
these frequencies anti-aliasing will reduce their effects.
Figure 21. Input Normal Mode Rejection at DC
Figure 22. Input Normal Mode Rejection at fS = 256 • fN
DIFFERENTIAL INPUT SIGNAL FREQUENCY (Hz)
0 fS2fS3fS4fS5fS6fS7fS8fS9fS10fS
11fS
12fS
INPUT NORMAL MODE REJECTION (dB)
2494 F19
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
DIFFERENTIAL INPUT SIGNAL FREQUENCY (Hz)
0 fS
INPUT NORMAL MODE REJECTION (dB)
2494 F20
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120 2fS3fS4fS5fS6fS7fS8fS9fS10fS
INPUT SIGNAL FREQUENCY (Hz)
INPUT NORMAL MODE REJECTION (dB)
2494 F21
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120 fN
0 2fN3fN4fN5fN6fN7fN8fN
fN = fEOSC/5120
INPUT SIGNAL FREQUENCY (Hz)
250fN252fN254fN256fN258fN260fN262fN
INPUT NORMAL MODE REJECTION (dB)
2494 F22
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
LTC2494
32
2494fe
For more information www.linear.com/LTC2494
applications inForMation
The user can expect to achieve this level of performance
using the internal oscillator, as shown in Figures 23, 24
and 25. Measured values of normal mode rejection are
shown superimposed over the theoretical values in all
three rejection modes.
Traditional high order delta-sigma modulators suffer from
potential instabilities at large input signal levels. The
proprietary architecture used for the LTC2494 third order
modulator resolves this problem and guarantees stability
with input signals 150% of full-scale. In many industrial
applications, it is not uncommon to have microvolt level
signals superimposed over unwanted volt level error
sources with several volts of peak-to-peak noise. Figures
26 and 27 show measurement results for the rejection
of a 7.5V peak-to-peak noise source (150% of full-scale)
applied to the LTC2494. From these curves, it is shown that
the rejection performance is maintained even in extremely
noisy environments.
Using the 2x speed mode of the LTC2494 alters the re-
jection characteristics around DC and multiples of fS. The
device bypasses the offset calibration in order to increase
the output rate. The resulting rejection plots are shown
in Figures 28 and 29. 1x type frequency rejection can be
achieved using the 2x mode by performing a running
average of the conversion results (see Figure 30).
Output Data Rate
When using its internal oscillator, the LTC2494 produces up
to 15 samples per second (sps) with a notch frequency of
60Hz. The actual output data rate depends upon the length
of the sleep and data output cycles which are controlled
by the user and can be made insignificantly short. When
operating with an external conversion clock (fO connected
to an external oscillator), the LTC2494 output data rate
can be increased. The duration of the conversion cycle is
41036/fEOSC. If fEOSC = 307.2kHz, the converter behaves
as if the internal oscillator is used.
An increase in fEOSC over the nominal 307.2kHz will translate
into a proportional increase in the maximum output data
rate (up to a maximum of 100sps). The increase in output
rate leads to degradation in offset, full-scale error, and ef-
fective resolution as well as a shift in frequency rejection.
When using the integrated temperature sensor, the internal
Figure 23. Input Normal Mode Rejection vs Input Frequency with
Input Perturbation of 100% (60Hz Notch)
Figure 24. Input Normal Mode Rejection vs Input Frequency with
Input Perturbation of 100% (50Hz Notch)
Figure 25. Input Normal Mode Rejection vs Input Frequency with
Input Perturbation of 100% (50Hz/60Hz Notch)
INPUT FREQUENCY (Hz)
015 30 45 60 75 90 105 120 135 150 165 180 195 210 225 240
NORMAL MODE REJECTION (dB)
2494 F23
0
–20
–40
–60
–80
–100
–120
VCC = 5V
VREF = 5V
VIN(CM) = 2.5V
VIN(P-P) = 5V
TA = 25°C
MEASURED DATA
CALCULATED DATA
INPUT FREQUENCY (Hz)
012.5 25 37.5 50 62.5 75 87.5 100 112.5 125 137.5 150 162.5 175 187.5 200
NORMAL MODE REJECTION (dB)
2494 F24
0
–20
–40
–60
–80
–100
–120
VCC = 5V
VREF = 5V
VIN(CM) = 2.5V
VIN(P-P) = 5V
TA = 25°C
MEASURED DATA
CALCULATED DATA
INPUT FREQUENCY (Hz)
020 40 60 80 100 120 140 160 180 200 220
NORMAL MODE REJECTION (dB)
2494 F25
0
–20
–40
–60
–80
–100
–120
VCC = 5V
VREF = 5V
VIN(CM) = 2.5V
VIN(P-P) = 5V
TA = 25°C
MEASURED DATA
CALCULATED DATA
oscillator should be used (fO = 0) or an external oscillator
applied to fO, fEOSC, should be set to 307.2kHz Max.
A change in fEOSC results in a proportional change in the
internal notch position. This leads to reduced differential
mode rejection of line frequencies. The common mode
LTC2494
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For more information www.linear.com/LTC2494
Figure 26. Measure Input Normal Mode Rejection vs Input
Frequency with Input Perturbation of 150% (60Hz Notch)
Figure 27. Measure Input Normal Mode Rejection vs Input
Frequency With input Perturbation of 150% (50Hz Notch)
Figure 28. Input Normal Mode Rejection 2x Speed Mode
Figure 29. Input Normal Mode Rejection 2x Speed Mode
applications inForMation
rejection of line frequencies remains unchanged, thus fully
differential input signals with a high degree of symmetry
on both the IN+ and IN– pins will continue to reject line
frequency noise.
An increase in fEOSC also increases the effective dynamic
input and reference current. External RC networks will
continue to have zero differential input current, but the
time required for complete settling (580ns for fEOSC =
307.2kHz) is reduced, proportionally.
Once the external oscillator frequency is increased above
1MHz (a more than 3x increase in output rate) the ef-
fectiveness of internal auto calibration circuits begins
to degrade. This results in larger offset errors, full-scale
errors and decreased resolution (see Figures 31 to 38).
INPUT FREQUENCY (Hz)
015 30 45 60 75 90 105 120 135 150 165 180 195 210 225 240
NORMAL MODE REJECTION (dB)
2494 F26
0
–20
–40
–60
–80
–100
–120
VCC = 5V
VREF = 5V
VIN(CM) = 2.5V
TA = 25°C
VIN(P-P) = 5V
VIN(P-P) = 7.5V
(150% OF FULL SCALE)
INPUT FREQUENCY (Hz)
0
NORMAL MODE REJECTION (dB)
2494 F27
0
–20
–40
–60
–80
–100
–120
VCC = 5V
VREF = 5V
VIN(CM) = 2.5V
TA = 25°C
VIN(P-P) = 5V
VIN(P-P) = 7.5V
(150% OF FULL SCALE)
12.5 25 37.5 50 62.5 75 87.5 100 112.5 125 137.5 150 162.5 175 187.5 200
INPUT SIGNAL FREQUENCY (fN)
INPUT NORMAL REJECTION (dB)
2494 F28
0
–20
–40
–60
–80
–100
–120 0fN2fN3fN4fN5fN6fN7fN8fN
INPUT SIGNAL FREQUENCY (fN)
INPUT NORMAL REJECTION (dB)
2494 F29
0
–20
–40
–60
–80
–100
–120 250248 252 254 256 258 260 262 264
Figure 30. Input Normal Mode Rejection 2x Speed Mode
with and Without Running Averaging
DIFFERENTIAL INPUT SIGNAL FREQUENCY (Hz)
48
–70
–80
–90
–100
–110
–120
–130
–140 54 58
2494 F30
50 52 56 60 62
NORMAL MODE REJECTION (dB)
NO AVERAGE
WITH
RUNNING
AVERAGE
LTC2494
34
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For more information www.linear.com/LTC2494
applications inForMation
Figure 37. Resolution (NoiseRMS ≤ 1LSB)
vs Output Data Rate and Reference Voltage
Figure 38. Resolution (INLMAX ≤ 1LSB) vs
Output Data Rate and Reference Voltage
Figure 36. Offset Error vs Output Data
Rate and Reference Voltage
Figure 33.–FS Error vs Output Data
Rate and Temperature
Figure 34. Resolution (NoiseRMS ≤ 1LSB)
vs Output Data Rate and Temperature
Figure 35. Resolution (INLMAX ≤ 1LSB)
vs Output Data Rate and Temperature
Figure 31. Offset Error vs Output Data
Rate and Temperature
Figure 32. +FS Error vs Output Data
Rate and Temperature
–10
OFFSET ERROR (ppm OF VREF)
10
30
50
0
20
40
OUTPUT DATA RATE (READINGS/SEC) 2494 F31
0 20 3010
VIN(CM) = VREF(CM)
VCC = VREF = 5V
VIN = 0V
fO = EXT CLOCK
TA = 25°C
TA = 85°C
OUTPUT DATA RATE (READINGS/SEC)
0
+FS ERROR (ppm OF VREF)
500
1500
2000
2500
3500
2494 F32
1000
3000
0 20 3010
TA = 25°C
TA = 85°C
VIN(CM) = VREF(CM)
VCC = VREF = 5V
fO = EXT CLOCK
OUTPUT DATA RATE (READINGS/SEC)
–3500
–FS ERROR (ppm OF VREF)
–3000
–2000
–1500
–1000
0
2494 F33
–2500
–500
0 20 3010
VIN(CM) = VREF(CM)
VCC = VREF = 5V
fO = EXT CLOCK
TA = 25°C
TA = 85°C
OUTPUT DATA RATE (READINGS/SEC)
–10
OFFSET ERROR (ppm OF VREF)
–5
5
10
20
2494 F36
0
15
0 20 3010
VCC = 5V, VREF = 2.5V
VCC = VREF = 5V
VIN(CM) = VREF(CM)
VIN = 0V
fO = EXT CLOCK
TA = 25°C
OUTPUT DATA RATE (READINGS/SEC)
10
RESOLUTION (BITS)
12
16
18
2494 F34
14
0 20 3010
VIN(CM) = VREF(CM)
VCC = VREF = 5V
VIN = 0V
fO = EXT CLOCK
RES = LOG 2 (VREF/NOISERMS)
TA = 25°C, 85°C
OUTPUT DATA RATE (READINGS/SEC)
10
RESOLUTION (BITS)
12
16
18
14
2494 F35
0 20 3010
VIN(CM) = VREF(CM)
VCC = VREF = 5V
fO = EXT CLOCK
RES = LOG 2 (VREF/INLMAX)
TA = 25°C, 85°C
OUTPUT DATA RATE (READINGS/SEC)
10
RESOLUTION (BITS)
12
16
18
2494 F37
14
0 20 3010
VIN(CM) = VREF(CM)
VIN = 0V
fO = EXT CLOCK
TA = 25°C
RES = LOG 2 (VREF/NOISERMS)
VCC = 5V, VREF = 2.5V, 5V
OUTPUT DATA RATE (READINGS/SEC)
10
RESOLUTION (BITS)
12
16
18
14
2494 F38
0 20 3010
VIN(CM) = VREF(CM)
VIN = 0V
REF– = GND
fO = EXT CLOCK
TA = 25°C
RES = LOG 2 (VREF/INLMAX)
VCC = 5V, VREF = 2.5V, 5V
LTC2494
35
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For more information www.linear.com/LTC2494
applications inForMation
Figure 39. Input Range
VCC + 0.3V
GND GND
GND
–0.3V
GND
–0.3V
–0.3V
(a) Arbitrary (b) Fully Differential
(d) Pseudo-Differential Unipolar
IN– or COM Grounded
(c) Pseudo Differential Bipolar
IN– or COM Biased
VREF
2
VREF
2
VREF
2
VREF
2
VREF
2
–VREF
2
–VREF
2
–VREF
2
Selected IN+ Ch
Selected IN
–
Ch or COM
VCC
VCC
VCC
VCC
2494 F39
LTC2494
36
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For more information www.linear.com/LTC2494
5.00 ± 0.10
NOTE:
1. DRAWING CONFORMS TO JEDEC PACKAGE
OUTLINE M0-220 VARIATION WHKD
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
PIN 1
TOP MARK
(SEE NOTE 6)
37
1
2
38
BOTTOM VIEW—EXPOSED PAD
5.50 REF 5.15 ± 0.10
7.00 ± 0.10
0.75 ± 0.05
R = 0.125
TYP
R = 0.10
TYP
0.25 ± 0.05
(UH) QFN REF C 1107
0.50 BSC
0.200 REF
0.00 – 0.05
RECOMMENDED SOLDER PAD LAYOUT
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
3.00 REF
3.15 ± 0.10
0.40 ±0.10
0.70 ± 0.05
0.50 BSC
5.5 REF
3.00 REF 3.15 ± 0.05
4.10 ± 0.05
5.50 ± 0.05 5.15 ± 0.05
6.10 ± 0.05
7.50 ± 0.05
0.25 ± 0.05
PACKAGE
OUTLINE
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
PIN 1 NOTCH
R = 0.30 TYP OR
0.35 × 45° CHAMFER
package Description
UHF Package
38-Lead Plastic QFN (5mm × 7mm)
(Reference LTC DWG # 05-08-1701 Rev C)
LTC2494
37
2494fe
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation
that the interconnection of its circuits as described herein will not infringe on existing patent rights.
revision history
REV DATE DESCRIPTION PAGE NUMBER
C 11/09 Update Tables 1 and 2 17, 18
D 07/10 Revised Typical Application drawing 1
Added Note 18 4, 5
E 11/14 Clarify performance vs f0 frequency, reduced external oscillator max frequency to 1MHz
Clarify Input Voltage Range
Fixed External Input, Gain = 256, Auto-Calibration in Table 4
5, 8, 34
4, 14, 35
19
(Revision history begins at Rev C)
LTC2494
38
2494fe
LINEAR TECHNOLOGY CORPORATION 2007
LT 1114 REV E • PRINTED IN USA
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com/LTC2494
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LTC2400 24-Bit, No Latency DS ADC in SO-8 0.3ppm Noise, 4ppm INL, 10ppm Total Unadjusted Error, 200µA
LTC2410 24-Bit, No Latency DS ADC with Differential Inputs 0.8µVRMS Noise, 2ppm INL
LTC2413 24-Bit, No Latency DS ADC with Differential Inputs Simultaneous 50Hz/60Hz Rejection, 800nVRMS Noise
LTC2415/LTC2415-1 24-Bit, No Latency DS ADCs with 15Hz Output Rate Pin Compatible with the LTC2410
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LTC2440 High Speed, Low Noise 24-Bit DS ADC 3.5kHz Output Rate, 200nVRMS Noise, 24.6 ENOBs
LTC2480 16-Bit DS ADC with Easy Drive Inputs, 600nVRMS Noise,
Programmable Gain, and Temperature Sensor
Pin Compatible with LTC2482/LTC2484
LTC2481 16-Bit DS ADC with Easy Drive Inputs, 600nVRMS Noise, I2C
Interface, Programmable Gain, and Temperature Sensor
Pin Compatible with LTC2483/LTC2485
LTC2482 16-Bit DS ADC with Easy Drive Inputs Pin Compatible with LTC2480/LTC2484
LTC2483 16-Bit DS ADC with Easy Drive Inputs, and I2C Interface Pin Compatible with LTC2481/LTC2485
LTC2484 24-Bit DS ADC with Easy Drive Inputs Pin Compatible with LTC2480/LTC2482
LTC2485 24-Bit DS ADC with Easy Drive Inputs, I2C Interface, and
Temperature Sensor
Pin Compatible with LTC2481/LTC2483
LTC2486 16-Bit 2-/4-Channel DS ADC with PGA and Temperature Sensor Pin Compatible with LTC2492/LTC2488
LTC2496 16-Bit 8-/16-Channel DS ADC with Easy Drive Input Current
Cancellation
Pin Compatible with LTC2494/LTC2449/LTC2498
LTC2498 24-Bit DS ADC with SPI Interface and Temperature Sensor Pin Compatible with LTC2494/LTC2496/LTC2449
typical application
External Buffers Provide High Impedance Inputs and Amplifier Offsets Are Automatically Cancelled
–
+
–
+
1/2 LTC6078
1/2 LTC6078
1
2
3
5
6
7
ΔΣ ADC
WITH
EASY DRIVE
INPUTS
INPUT
MUX
MUXOUTP
MUXOUTN
17
2494 TA02
LTC2494
ANALOG
INPUTS
SDI
SCK
SDO
CS
1k
1k
0.1µF
0.1µF