Burr-BrownAudio
OPA1652
OPA1654
www.ti.com
SBOS477 –DECEMBER 2011
™
Low Noise and Distortion, General-Purpose, FET-Input
AUDIO OPERATIONAL AMPLIFIERS
Check for Samples: OPA1652,OPA1654
1FEATURES DESCRIPTION
The OPA1652 (dual) and OPA1654 (quad) FET-input
234•Low Noise: 4.5 nV/√Hz at 1 kHz operational amplifiers achieve a low 4.5 nV/√Hz noise
•Low Distortion: 0.00005% at 1 kHz density with an ultralow distortion of 0.00005% at 1
•Low Quiescent Current: kHz. The OPA1652 and OPA1654 op amps offer
2 mA Per Channel rail-to-rail output swing to within 800 mV with 2-kΩ
load, which increases headroom and maximizes
•Low Input Bias Current: 10 pA dynamic range. These devices also have a high
•Slew Rate: 10 V/μsoutput drive capability of ±30 mA.
•Wide Gain Bandwidth: 18 MHz (G = +1) These devices operate over a very wide supply range
•Unity Gain Stable of ±2.25 V to ±18 V, or +4.5 V to +36 V, on only 2 mA
•Rail-to-Rail Output of supply current per channel. The OPA1652 and
OPA1654 op amps are unity-gain stable and provide
•Wide Supply Range: excellent dynamic behavior over a wide range of load
±2.25 V to ±18 V, or +4.5 V to +36 V conditions.
•Dual and Quad Versions Available These devices also feature completely independent
•Small Package Sizes: circuitry for lowest crosstalk and freedom from
DUAL: SO-8 and MSOP-8 interactions between channels, even when overdriven
QUAD: SO-14 and TSSOP-14 or overloaded.
The OPA1652 and OPA1654 temperature ranges are
APPLICATIONS specified from –40°C to +85°C. SoundPlus™
•Analog and Digital Mixers
•Audio Effects Processors
•Musical Instruments
•A/V Receivers
•DVD and Blu-Ray™Players
•Car Audio Systems
1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2SoundPlus is a trademark of Texas Instruments Incorporated.
3Blu-Ray is a trademark of Blu-Ray Disc Association.
4All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date. Copyright ©2011, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
1
2
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8
7
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5
V+
OUTB
-INB
+INB
OUTA
-INA
+INA
V-
A
B
OutA
-InA
+InA
V+
+InB
-InB
OutB
1
2
3
4
5
6
7
14
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10
9
8
DA
B C
OutD
-InD
+InD
V-
+InC
-InC
OutC
OPA1652
OPA1654
SBOS477 –DECEMBER 2011
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
PACKAGE INFORMATION(1)
PRODUCT PACKAGE-LEAD PACKAGE DESIGNATOR PACKAGE MARKING
SO-8 D OP1652
OPA1652 MSOP-8 DGK OUPI
SO-14 D OP1654
OPA1654 TSSOP-14 PW OP1654
(1) For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
ABSOLUTE MAXIMUM RATINGS(1)
Over operating free-air temperature range (unless otherwise noted). OPA1652, OPA1654 UNIT
Supply Voltage VS= (V+) –(V–) 40 V
Input Voltage (V–)–0.5 to (V+) + 0.5 V
Input Current (All pins except power-supply pins) ±10 mA
Output Short-Circuit(2) Continuous
Operating Temperature –55 to +125 °C
Storage Temperature –65 to +150 °C
Junction Temperature 200 °C
Human Body Model (HBM) 2 kV
ESD Ratings Charged Device Model (CDM) 1 kV
Machine Model (MM) 200 V
(1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may
degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond
those specified is not supported.
(2) Short-circuit to VS/2 (ground in symmetrical dual supply setups), one amplifier per package.
PIN CONFIGURATIONS
OPA1652: D AND DGK PACKAGES OPA1654: D AND PW PACAKGES
SO-8 AND MSOP-8 SO-14 AND TSSOP-14
(TOP VIEW) (TOP VIEW)
2Copyright ©2011, Texas Instruments Incorporated
Product Folder Link(s): OPA1652 OPA1654
OPA1652
OPA1654
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SBOS477 –DECEMBER 2011
ELECTRICAL CHARACTERISTICS: VS=±15 V
At TA= +25°C, RL= 2 kΩ, and VCM = VOUT = midsupply, unless otherwise noted. OPA1652, OPA1654
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
AUDIO PERFORMANCE
0.00005 %
THD+N Total harmonic distortion + noise G = +1, f = 1 kHz, VO= 3 VRMS –126 dB
0.00005 %
SMPTE/DIN Two-Tone, 4:1
(60 Hz and 7 kHz) –126 dB
0.00005 %
G = +1, DIM 30 (3-kHz square wave
IMD Intermodulation distortion VO= 3 VRMS and 15-kHz sine wave) –126 dB
0.00005 %
CCIF Twin-Tone
(19 kHz and 20 kHz) –126 dB
FREQUENCY RESPONSE
GBW Gain-bandwidth product G = +1 18 MHz
SR Slew rate G = –1 10 V/μs
Full power bandwidth(1) VO= 1 VP1.6 MHz
Overload recovery time G = –10 1 μs
Channel separation (dual and quad) f = 1 kHz –120 dB
NOISE
enInput voltage noise f = 20 Hz to 20 kHz 5.4 μVPP
Input voltage noise density f = 1 kHz 4.5 nV/√Hz
InInput current noise density f = 1 kHz 0.5 pA/√Hz
OFFSET VOLTAGE
VS=±2.25 V to ±18 V ±0.5 ±1.5 mV
VOS Input offset voltage VS=±2.25 V to ±18 V, TA=–40°C to +85°C(2) 2 8 μV/°C
PSRR Power-supply rejection ratio VS=±2..25 V to ±18 V 3 8 μV/V
INPUT BIAS CURRENT
IBInput bias current VCM = 0 V ±10 ±100 pA
IOS Input offset current VCM = 0 V ±10 ±100 pA
INPUT VOLTAGE RANGE
VCM Common-mode voltage range (V–) + 0.5 (V+) –2 V
CMRR Common-mode rejection ratio 100 110 dB
INPUT IMPEDANCE
Differential 100 || 6 MΩ|| pF
Common-mode 6000 || 2 GΩ|| pF
OPEN-LOOP GAIN
AOL Open-loop voltage gain (V–) + 0.8 V ≤VO≤(V+) –0.8 V, RL= 2 kΩ106 114 dB
OUTPUT
VOUT Voltage output RL= 2 kΩ(V–) + 0.8 (V+) –0.8 V
IOUT Output current See Typical Characteristics mA
ZOOpen-loop output impedance f = 1 MHz See Typical Characteristics Ω
ISC Short-circuit current(3) ±50 mA
CLOAD Capacitive load drive 100 pF
POWER SUPPLY
VSSpecified voltage ±2.25 ±18 V
IOUT = 0 A 2.0 2.5 mA
Quiescent current
IQ(per channel) IOUT = 0 A, TA=–40°C to +85°C(2) 2.8 mA
(1) Full-power bandwidth = SR/(2π × VP), where SR = slew rate.
(2) Specified by design and characterization.
(3) One channel at a time.
Copyright ©2011, Texas Instruments Incorporated 3
Product Folder Link(s): OPA1652 OPA1654
OPA1652
OPA1654
SBOS477 –DECEMBER 2011
www.ti.com
ELECTRICAL CHARACTERISTICS: VS=±15 V (continued)
At TA= +25°C, RL= 2 kΩ, and VCM = VOUT = midsupply, unless otherwise noted. OPA1652, OPA1654
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
TEMPERATURE
Specified range –40 +85 °C
Operating range –55 +125 °C
THERMAL INFORMATION: OPA1652 OPA1652
THERMAL METRIC(1) D (SO) DGK (MSOP) UNITS
8 PINS 8 PINS
θJA Junction-to-ambient thermal resistance 143.6 218.9
θJCtop Junction-to-case (top) thermal resistance 76.9 78.6
θJB Junction-to-board thermal resistance 61.8 103.7 °C/W
ψJT Junction-to-top characterization parameter 27.8 14.6
ψJB Junction-to-board characterization parameter 61.3 101.8
θJCbot Junction-to-case (bottom) thermal resistance N/A N/A
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
THERMAL INFORMATION: OPA1654 OPA1654
THERMAL METRIC(1) D (SO) PW (TSSOP) UNITS
14 PINS 14 PINS
θJA Junction-to-ambient thermal resistance 90.1 126.9
θJCtop Junction-to-case (top) thermal resistance 54.8 46.6
θJB Junction-to-board thermal resistance 44.4 58.6 °C/W
ψJT Junction-to-top characterization parameter 19.9 5.5
ψJB Junction-to-board characterization parameter 44.2 57.8
θJCbot Junction-to-case (bottom) thermal resistance N/A N/A
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
4Copyright ©2011, Texas Instruments Incorporated
Product Folder Link(s): OPA1652 OPA1654
Time (1 s/div)
Voltage Noise (500 nV/div)
G002
1
10
100
1 10 100 1k 10k 100k
Frequency (Hz)
Voltage Noise (nV/ Hz)
G001
0
2
5
8
10
12
15
18
20
10k 100k 1M 10M
Frequency (Hz)
Output Voltage (V)
VS = ±15 V
VS = ±2.25 V
G004
1
10
100
1k
10k
100 1k 10k 100k 1M
Resistor Noise
OPA166x
OPA165x
Source Resistance ( )W
Voltage Noise (nV/ Hz)
Eo
2= en
2+ (inRS)2+ 4KTRS
G003
RS
EO
10 100 1k 10k 100k 1M 10M 100M
−20
0
20
40
60
80
100
120
140
0
45
90
135
180
Frequency (Hz)
Gain (dB)
Phase (°)
Gain
Phase
CL = 10 pF
G005
−20
0
20
40
100k 1M 10M 100M
Frequency (Hz)
Gain (dB)
Gain = −1 V/V
Gain = +1 V/V
Gain = +10 V/V
CL = 10 pF
G006
OPA1652
OPA1654
www.ti.com
SBOS477 –DECEMBER 2011
TYPICAL CHARACTERISTICS
At TA= +25°C, VS=±15 V, and RL= 2 kΩ, unless otherwise noted.
INPUT VOLTAGE NOISE DENSITY
vs FREQUENCY 0.1Hz TO 10Hz NOISE
Figure 1. Figure 2.
VOLTAGE NOISE vs SOURCE RESISTANCE MAXIMUM OUTPUT VOLTAGE vs FREQUENCY
Figure 3. Figure 4.
GAIN AND PHASE vs FREQUENCY CLOSED-LOOP GAIN vs FREQUENCY
Figure 5. Figure 6.
Copyright ©2011, Texas Instruments Incorporated 5
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0.00001
0.0001
0.001
0.01
20 100 1k 10k 20k
Frequency (Hz)
THD+N (%)
G = 10 V/V, RL = 600 Ω
G = 10 V/V, RL = 2 kΩ
G = +1 V/V, RL = 600 Ω
G = +1 V/V, RL = 2 kΩ
G = −1 V/V, RL = 600 Ω
G = −1 V/V, RL = 2 kΩ
VOUT = 3 VRMS
BW = 80 kHz
G007
0.00001
0.0001
0.001
0.01
20 100 1k 10k 20k
Frequency (Hz)
THD+N (%)
RS= 0 W
RS= 30 W
RS= 60 W
RS= 1 kW
VOUT = 3 VRMS
BW = 80 kHz
G008
OPA1652
+15V
-15V RL
RSOURCE
0.00001
0.0001
0.001
0.01
20 100 1k 10k 100k
Frequency (Hz)
THD+N (%)
G = 10 V/V, RL = 600 Ω
G = 10 V/V, RL = 2 kΩ
G = +1 V/V, RL = 600 Ω
G = +1 V/V, RL = 2 kΩ
G = −1 V/V, RL = 600 Ω
G = −1 V/V, RL = 2 kΩ
VOUT = 3 VRMS
BW = 500 kHz
G009
0.00001
0.0001
0.001
0.01
20 100 1k 10k 100k
Frequency (Hz)
THD+N (%)
RS= 0 W
RS= 30 W
RS= 60 W
RS= 1 kW
VOUT = 3 VRMS
BW = 500 kHz
G010
OPA1652
+15V
-15V RL
RSOURCE
0.00001
0.0001
0.001
0.01
1m 10m 100m 1 10 20
Output Amplitude (Vrms)
THD+N (%)
G = 10 V/V, RL = 600 Ω
G = 10 V/V, RL = 2 kΩ
G = +1 V/V, RL = 600 Ω
G = +1 V/V, RL = 2 kΩ
G = −1 V/V, RL = 600 Ω
G = −1 V/V, RL = 2 kΩ
f = 1 kHz
BW = 80 kHz
RS = 0 Ω
G011
0.00001
0.0001
0.001
0.01
100m 1 10 20
Output Amplitude (Vrms)
THD+N (%)
DIM 30: 3 kHz − Square Wave, 15 kHz Sine Wave
CCIF Twin Tone: 19 kHz and 20 kHz
SMPTE / DIN: Two −Tone 4:1, 60 Hz and 7 KHz
G = +1 V/V
G012
OPA1652
OPA1654
SBOS477 –DECEMBER 2011
www.ti.com
TYPICAL CHARACTERISTICS (continued)
At TA= +25°C, VS=±15 V, and RL= 2 kΩ, unless otherwise noted.
THD+N RATIO vs FREQUENCY THD+N RATIO vs FREQUENCY
Figure 7. Figure 8.
THD+N RATIO vs FREQUENCY THD+N RATIO vs FREQUENCY
Figure 9. Figure 10.
INTERMODULATION DISTORTION vs
THD+N RATIO vs OUTPUT AMPLITUDE OUTPUT AMPLITUDE
Figure 11. Figure 12.
6Copyright ©2011, Texas Instruments Incorporated
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−160
−140
−120
−100
−80
100 1k 10k 100k
Frequency (Hz)
Crosstalk (dB)
VOUT = 3 VRMS
Gain = +1 V/V
G013
0
20
40
60
80
100
120
140
100 1k 10k 100k 1M 10M 100M
Frequency (Hz)
CMRR, PSRR (dB)
+PSRR
−PSRR
CMRR
G014
Time (0.2 s/div)m
Voltage (25 mV/div)
VIN
VOUT
G = −1 V/V
CL= 100 pF
G016
Time (1 s/div)m
Voltage (2.5 V/div)
VIN
VOUT
G = + 1V/V
RF= 2 kW
CL= 100 pF
G017
OPA1652
OPA1654
www.ti.com
SBOS477 –DECEMBER 2011
TYPICAL CHARACTERISTICS (continued)
At TA= +25°C, VS=±15 V, and RL= 2 kΩ, unless otherwise noted.
CHANNEL SEPARATION vs FREQUENCY CMRR AND PSRR vs FREQUENCY (Referred to Input)
Figure 13. Figure 14.
SMALL-SIGNAL STEP RESPONSE SMALL-SIGNAL STEP RESPONSE
(100mV) (100mV)
Figure 15. Figure 16.
LARGE-SIGNAL STEP RESPONSE LARGE-SIGNAL STEP RESPONSE
Figure 17. Figure 18.
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0
5
10
15
20
25
30
35
40
45
50
0 50 100 150 200 250 300 350 400
Capacitance (pF)
Overshoot (%)
RS= 0 W
RS= 25 W
RS= 50 W
VOUT = 100 mVPP
G = +1 V/V
G019
+15 V
-15 V
RS
CL
OPA1652
RL
0
5
10
15
20
25
30
35
40
45
50
0 50 100 150 200 250 300 350 400
Capacitance (pF)
Overshoot (%)
RS= 0 W
RS= 25 W
RS= 50 W
VOUT = 100 mVPP
G = −1 V/V
G020
OPA1652
R =
I2 kW
RS
CL
RF= 2 kW
+15 V
-15 V
−1
0
1
2
3
4
−40 −15 10 35 60 85 110 135
Temperature (°C)
AOL (µV)
RL = 2 kΩ
G022
0
5
10
15
20
25
0 1 2 3 4 5
Capacitance (pF)
Overshoot (%)
VOUT = 100 mVPP
G = −1 V/V
RS= 0 W
G021
OPA1652
R =
I2 kW
RS
CL
CF
RF= 2 kW
+15 V
-15 V
−2000
−1600
−1200
−800
−400
0
400
800
1200
−40 −15 10 35 60 85 110 135
Temperature (°C)
Ib and Ios Current (pA)
Ibn
Ibp
Ios
G023
−8
−6
−4
−2
0
2
4
6
8
−18 −15 −12 −9 −6 −3 0 3 6 9 12 15 18
Common − Mode Voltage (V)
Ib and Ios Current (pA)
Ibp
Ibn
Ios
G024
OPA1652
OPA1654
SBOS477 –DECEMBER 2011
www.ti.com
TYPICAL CHARACTERISTICS (continued)
At TA= +25°C, VS=±15 V, and RL= 2 kΩ, unless otherwise noted.
SMALL-SIGNAL OVERSHOOT SMALL-SIGNAL OVERSHOOT
vs CAPACITIVE LOAD vs CAPACITIVE LOAD
Figure 19. Figure 20.
SMALL-SIGNAL OVERSHOOT
vs FEEDBACK CAPACITOR (100mV Output Step) OPEN-LOOP GAIN vs TEMPERATURE
Figure 21. Figure 22.
IBAND IOS vs TEMPERATURE IBAND IOS vs COMMON-MODE VOLTAGE
Figure 23. Figure 24.
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0
0.5
1
1.5
2
2.5
3
−40 −15 10 35 60 85 110 135
Temperature (°C)
Supply Current (mA)
G025
0
0.5
1
1.5
2
2.5
3
0 4 8 12 16 20 24 28 32 36
Supply Voltage (V)
Supply Current (mA)
G026
−40
−30
−20
−10
0
10
20
30
40
0 5 10 15 20 25 30 35 40 45 50 55 60
Output Current (mA)
Output Volage Swing (V)
−40 C
−25 C
0 C
25 C
85 C
125 C
G029
−100
−80
−60
−40
−20
0
20
40
60
80
100
−40 −15 10 35 60 85 110 135
Temperature (°C)
Isc (mA)
+Isc
−Isc
G028
0
10
20
30
40
50
60
70
80
90
0 50 100 150 200 250 300 350 400
Capacitance (pF)
Phase Margin (°)
G = +1 V/V
G031
0
10
20
30
40
50
0 50 100 150 200 250 300 350 400
Capacitance (pF)
Overshoot (%)
VS = ±2.25 V
VS = ±18 V
G = +1 V/V
VIN = 100 mVPP
G032
OPA1652
OPA1654
www.ti.com
SBOS477 –DECEMBER 2011
TYPICAL CHARACTERISTICS (continued)
At TA= +25°C, VS=±15 V, and RL= 2 kΩ, unless otherwise noted.
SUPPLY CURRENT vs TEMPERATURE SUPPLY CURRENT vs SUPPLY VOLTAGE
Figure 25. Figure 26.
OUTPUT VOLTAGE vs OUTPUT CURRENT SHORT-CIRCUIT CURRENT vs TEMPERATURE
Figure 27. Figure 28.
PHASE MARGIN vs CAPACITIVE LOAD PERCENT OVERSHOOT vs CAPACITIVE LOAD
Figure 29. Figure 30.
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Time (0.4 s/div)m
Output Voltage (5 V/div)
VIN
VOUT
G = −10 V/V
G033
2 kW
20 kW
VIN
VOUT
OPA1652
G = 10-
+18 V
-18 V
Time (0.4 s/div)m
Output Voltage (5 V/div)
VIN
VOUT
G = −10 V/V
G027
2 kW
20 kW
VIN
VOUT
OPA1652
G = 10-
+18 V
-18 V
G = +1 V/V
−20
−15
−10
−5
0
5
10
15
20
Time (125 s/div)m
Voltage (V)
VIN
VOUT
G034
+18 V
-18 V
37VPP
Sine Wave
( 18.5 V)±
OPA1652
10
100
1k
10 100 1k 10k 100k 1M 10M 100M
Frequency (Hz)
Impedance (Ω)
G030
OPA1652
OPA1654
SBOS477 –DECEMBER 2011
www.ti.com
TYPICAL CHARACTERISTICS (continued)
At TA= +25°C, VS=±15 V, and RL= 2 kΩ, unless otherwise noted.
NEGATIVE OVERLOAD RECOVERY POSITIVE OVERLOAD RECOVERY
Figure 31. Figure 32.
OPEN-LOOP OUTPUT IMPEDANCE vs
FREQUENCY NO PHASE REVERSAL
Figure 33. Figure 34.
10 Copyright ©2011, Texas Instruments Incorporated
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VBIAS1
Class AB
Control
Circuitry
VBIAS2
V +
IN
V+
V-
V-
IN
VO
Tail
Current
OPA1652
OPA1654
www.ti.com
SBOS477 –DECEMBER 2011
APPLICATION INFORMATION
applications do not require equal positive and
The OPA1652 and OPA1654 are unity-gain stable, negative output voltage swing. With the OPA165x
precision dual and quad op amps with very low noise. series, power-supply voltages do not need to be
Applications with noisy or high-impedance power equal. For example, the positive supply could be set
supplies require decoupling capacitors close to the to +25 V with the negative supply at –5 V.
device pins. In most cases, 0.1-μF capacitors are
adequate. Figure 35 shows a simplified schematic of In all cases, the common-mode voltage must be
the OPA165x (one channel shown). maintained within the specified range. In addition, key
parameters are assured over the specified
temperature range of TA=–40°C to +85°C.
OPERATING VOLTAGE Parameters that vary significantly with operating
The OPA165x series op amps operate from ±2.25 V voltage or temperature are shown in the Typical
to ±18 V supplies while maintaining excellent Characteristics.
performance. The OPA165x series can operate with
as little as +4.5V between the supplies and with up to
+36 V between the supplies. However, some
Figure 35. OPA165x Simplified Schematic
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1
10
100
1k
10k
100 1k 10k 100k 1M
Resistor Noise
OPA166X
OPA165X
Source Resistance (Ω)
Voltage Noise (nV/ Hz )
Eo
2 = en
2 + (inRS)2 + 4KTRS
G003
OPA165x Output
RF
Input
-
+
RI
OPA1652
OPA1654
SBOS477 –DECEMBER 2011
www.ti.com
INPUT PROTECTION The equation in Figure 37 shows the calculation of
the total circuit noise, with these parameters:
The input terminals of the OPA1652 and OPA1654 •en= Voltage noise
are protected from excessive differential voltage with •in= Current noise
back-to-back diodes, as Figure 36 illustrates. In most
circuit applications, the input protection circuitry has •RS= Source impedance
no consequence. However, in low-gain or G = +1 •k = Boltzmann’s constant = 1.38 ×10–23 J/K
circuits, fast ramping input signals can forward bias •T = Temperature in Kelvins (K)
these diodes because the output of the amplifier
cannot respond rapidly enough to the input ramp. If
the input signal is fast enough to create this forward
bias condition, the input signal current must be limited
to 10 mA or less. If the input signal current is not
inherently limited, an input series resistor (RI) and/or
a feedback resistor (RF) can be used to limit the
signal input current. This resistor degrades the
low-noise performance of the OPA165x and is
examined in the following Noise Performance section.
Figure 36 shows an example configuration when both
current-limiting input and feeback resistors are used.
Figure 37. Noise Performance of the OPA165x in
Unity-Gain Buffer Configuration
BASIC NOISE CALCULATIONS
Design of low-noise op amp circuits requires careful
consideration of a variety of possible noise
contributors: noise from the signal source, noise
generated in the op amp, and noise from the
Figure 36. Pulsed Operation feedback network resistors. The total noise of the
circuit is the root-sum-square combination of all noise
components.
NOISE PERFORMANCE The resistive portion of the source impedance
Figure 37 shows the total circuit noise for varying produces thermal noise proportional to the square
source impedances with the op amp in a unity-gain root of the resistance. Figure 37 plots this equation.
configuration (no feedback resistor network, and The source impedance is usually fixed; consequently,
therefore no additional noise contributions). select the op amp and the feedback resistors to
The OPA165x (GBW = 18 MHz, G = +1) is shown minimize the respective contributions to the total
with total circuit noise calculated. The op amp itself noise.
contributes both a voltage noise component and a Figure 38 illustrates both inverting and noninverting
current noise component. The voltage noise is op amp circuit configurations with gain. In circuit
commonly modeled as a time-varying component of configurations with gain, the feedback network
the offset voltage. The current noise is modeled as resistors also contribute noise. The current noise of
the time-varying component of the input bias current the op amp reacts with the feedback resistors to
and reacts with the source resistance to create a create additional noise components. The feedback
voltage component of noise. Therefore, the lowest resistor values can generally be chosen to make
noise op amp for a given application depends on the these noise sources negligible. The equations for
source impedance. For low source impedance, total noise are shown for both configurations.
current noise is negligible, and voltage noise
generally dominates. The voltage noise of the
OPA165x series op amps makes them a better
choice for source impedances greater than or equal
to 1 kΩ.
12 Copyright ©2011, Texas Instruments Incorporated
Product Folder Link(s): OPA1652 OPA1654
R1
R2
EO
R1
R2
EO
RS
VS
RS
VS
A)NoiseinNoninvertingGainConfiguration
B)NoiseinInvertingGainConfiguration
Noiseattheoutput:
Wheree =
S4kTRS
4kTR1
4kTR2
=thermalnoiseofRS
=thermalnoiseofR1
=thermalnoiseofR2
e =
1
e =
2
Noiseattheoutput:
E =
O
21+ R2
R +R
1 S
R2
R +R
1 S
2 22
Wheree =
S4kTRS
4kTR1
4kTR2
=thermalnoiseofRS
=thermalnoiseofR1
=thermalnoiseofR2
e =
1
e =
2
R2
R +R
1 S
2
1+ R2
R1
1+ R2
R1
2
R2
R1
2
e +e +
1 2
2 2
E =
O
2e +
n
2es
2
e +e +
1 2
2 2 es
2
e +
n
2
OPA1652
OPA1654
www.ti.com
SBOS477 –DECEMBER 2011
Note: For the OPA165x series of op amps at 1kHz, en= 4.5nV/√Hz.
Figure 38. Noise Calculation in Gain Configurations
Copyright ©2011, Texas Instruments Incorporated 13
Product Folder Link(s): OPA1652 OPA1654
R2
OPA165x
R1
Signal Gain = 1+
Distortion Gain = 1+
R3V = 3 V
O RMS
Generator
Output
Analyzer
Input
Audio Precision
System Two(1)
with PC Controller
SIGNAL
GAIN
DISTORTION
GAIN R1R2R3
¥
4.99 kW
1 kW
4.99 kW
10 W
49.9 W
+1
-1
101
549 W4.99 kW49.9 W+10 110
101
R2
R1
R2
R II R
1 3
Load
OPA1652
OPA1654
SBOS477 –DECEMBER 2011
www.ti.com
TOTAL HARMONIC DISTORTION The validity of this technique can be verified by
MEASUREMENTS duplicating measurements at high gain and/or high
frequency where the distortion is within the
The OPA165x series op amps have excellent measurement capability of the test equipment.
distortion characteristics. THD + noise is below Measurements for this data sheet were made with an
0.0002% (G = +1, VO=3VRMS, BW = 80 kHz) Audio Precision System Two distortion/noise
throughout the audio frequency range, 20 Hz to 20 analyzer, which greatly simplifies such repetitive
kHz, with a 2-kΩload (see Figure 7 for characteristic measurements. The measurement technique can,
performance). however, be performed with manual distortion
measurement instruments.
The distortion produced by the OPA165x series op
amps is below the measurement limit of many
commercially available distortion analyzers. However, CAPACITIVE LOADS
a special test circuit (such as Figure 39 shows) can The dynamic characteristics of the OPA1652 and
be used to extend the measurement capabilities. OPA1654 have been optimized for commonly
Op amp distortion can be considered an internal error encountered gains, loads, and operating conditions.
source that can be referred to the input. Figure 39 The combination of low closed-loop gain and high
shows a circuit that causes the op amp distortion to capacitive loads decreases the phase margin of the
be gained up (refer to the table in Figure 39 for the amplifier and can lead to gain peaking or oscillations.
distortion gain factor for various signal gains). The As a result, heavier capacitive loads must be isolated
addition of R3to the otherwise standard noninverting from the output. The simplest way to achieve this
amplifier configuration alters the feedback factor or isolation is to add a small resistor (RSequal to 50 Ω,
noise gain of the circuit. The closed-loop gain is for example) in series with the output.
unchanged, but the feedback available for error This small series resistor also prevents excess power
correction is reduced by the distortion gain factor, dissipation if the output of the device becomes
thus extending the resolution by the same amount. shorted. Figure 19 illustrates a graph of Small-Signal
Note that the input signal and load applied to the op Overshoot vs Capacitive Load for several values of
amp are the same as with conventional feedback RS. Also, refer to Applications Bulletin AB-028
without R3. The value of R3should be kept small to (literature number SBOA015, available for download
minimize its effect on the distortion measurements. from the TI web site) for details of analysis
techniques and application circuits.
(1) For measurement bandwidth, see Figure 7 through Figure 12.
Figure 39. Distortion Test Circuit
14 Copyright ©2011, Texas Instruments Incorporated
Product Folder Link(s): OPA1652 OPA1654
5kW
Device
10mAmax
V+
VIN
VOUT
IOVERLOAD
OPA1652
OPA1654
www.ti.com
SBOS477 –DECEMBER 2011
POWER DISSIPATION
The OPA1652 and OPA1654 series op amps are
capable of driving 2-kΩloads with a power-supply
voltage up to ±18V and full operating temperature
range. Internal power dissipation increases when
operating at high supply voltages. Copper leadframe
construction used in the OPA165x series op amps
improves heat dissipation compared to conventional
materials. Circuit board layout can also help minimize Figure 40. Input Current Protection
junction temperature rise. Wide copper traces help
dissipate the heat by acting as an additional heat An ESD event produces a short duration,
sink. Temperature rise can be further minimized by high-voltage pulse that is transformed into a short
soldering the devices to the circuit board rather than duration, high-current pulse as it discharges through
using a socket. a semiconductor device. The ESD protection circuits
are designed to provide a current path around the
ELECTRICAL OVERSTRESS operational amplifier core to prevent it from being
damaged. The energy absorbed by the protection
Designers often ask questions about the capability of circuitry is then dissipated as heat.
an operational amplifier to withstand electrical
overstress. These questions tend to focus on the When the operational amplifier connects into a circuit,
device inputs, but may involve the supply voltage pins the ESD protection components are intended to
or even the output pin. Each of these different pin remain inactive and not become involved in the
functions have electrical stress limits determined by application circuit operation. However, circumstances
the voltage breakdown characteristics of the may arise where an applied voltage exceeds the
particular semiconductor fabrication process and operating voltage range of a given pin. Should this
specific circuits connected to the pin. Additionally, condition occur, there is a risk that some of the
internal electrostatic discharge (ESD) protection is internal ESD protection circuits may be biased on,
built into these circuits to protect them from and conduct current. Any such current flow occurs
accidental ESD events both before and during through ESD cells and rarely involves the absorption
product assembly. device.
These ESD protection diodes also provide in-circuit, If there is an uncertainty about the ability of the
input overdrive protection, as long as the current is supply to absorb this current, external zener diodes
limited to 10 mA as stated in the Absolute Maximum may be added to the supply pins. The zener voltage
Ratings.Figure 40 shows how a series input resistor must be selected such that the diode does not turn
may be added to the driven input to limit the input on during normal operation.
current. The added resistor contributes thermal noise However, its zener voltage should be low enough so
at the amplifier input and its value should be kept to a that the zener diode conducts if the supply pin begins
minimum in noise-sensitive applications. to rise above the safe operating supply voltage level.
Copyright ©2011, Texas Instruments Incorporated 15
Product Folder Link(s): OPA1652 OPA1654
I L+
OUT
Audio DAC
with Differential
Current
Outputs OPA165x
8200 pF
100 W
I L-
OUT
OPA165x
0.1 Fm
2200 pF
820 W
0.1 Fm
2700 pF
-VA
( 15 V)-
+VA
(+15 V)
680 W620 W
330 W
-VA
( 15 V)-
+VA
(+15 V)
0.1 Fm
0.1 Fm
330 W2700 pF
OPA165x
0.1 Fm
2200 pF
820 W
0.1 Fm
-VA
( 15 V)-
+VA
(+15 V) 680 W620 W
L Ch
Output
OPA1652
OPA1654
SBOS477 –DECEMBER 2011
www.ti.com
APPLICATION CIRCUIT
An additional application idea is shown in Figure 41.
Figure 41. Audio DAC I/V Converter and Output Filter
16 Copyright ©2011, Texas Instruments Incorporated
Product Folder Link(s): OPA1652 OPA1654
PACKAGE OPTION ADDENDUM
www.ti.com 16-Aug-2012
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
OPA1652AID ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
OPA1652AIDGK ACTIVE VSSOP DGK 8 80 Green (RoHS
& no Sb/Br) CU NIPDAUAGLevel-1-260C-UNLIM
OPA1652AIDGKR ACTIVE VSSOP DGK 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAUAGLevel-1-260C-UNLIM
OPA1652AIDR ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
OPA1654AID ACTIVE SOIC D 14 50 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
OPA1654AIDR ACTIVE SOIC D 14 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
OPA1654AIPW ACTIVE TSSOP PW 14 90 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
OPA1654AIPWR ACTIVE TSSOP PW 14 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
PACKAGE OPTION ADDENDUM
www.ti.com 16-Aug-2012
Addendum-Page 2
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
OPA1652AIDGKR VSSOP DGK 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
OPA1652AIDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
OPA1654AIDR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
OPA1654AIPWR TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 16-Aug-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
OPA1652AIDGKR VSSOP DGK 8 2500 364.0 364.0 27.0
OPA1652AIDR SOIC D 8 2500 367.0 367.0 35.0
OPA1654AIDR SOIC D 14 2500 367.0 367.0 38.0
OPA1654AIPWR TSSOP PW 14 2000 367.0 367.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 16-Aug-2012
Pack Materials-Page 2
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