W9412FASA
128MB (16M
×
64) DDR SDRAM SO-DIMM
Publication Release Date: March 15, 2002
- 1 - Revision A1
1. GENERAL DESCRIPTION
The W9412FASA is a 128MB Double Data Rate Synchronous Dynamic RAM (DDR SDRAM) memory
modules. It is organized in a 16M x 64 bit configuration using four pieces of Winbond W942516AH
(16M x 16 bits) DDR SDRAMs and assembled on a JEDEC standard 200-pin SO-DIMM PCB.
To provide high data bandwidth, W9412FASA uses a double data rate architecture to transfer two
data words per clock cycle and delivers a data bandwidth of up to 2.1G (DDR266) bytes per second. It
is ideal for high performance systems that require small form factor memory modules.
By reading the Serial Presence-Detect (SPD), the system can identify the module type, DDR SDRAM
timing parameters and other necessary information to optimize system setting and maximize its
performance.
2. FEATURES
• JEDEC standard 200-pin, Small-Outline, Dual In-Line Memory Module (SO-DIMM)
• Comply to DDR266 and DDR200 specification
• One memory row on this module
• Differential clock inputs (CLK and CLK )
• Double Data Rate architecture, two data transfers per clock cycle
• CAS Latency: 2 and 2.5
• Burst Lengths: 2, 4, 8
• Auto Refresh and Self Refresh
• 8K refresh cycles / 64 ms
• Serial Presence Detect with EEPROM
• Interface: SSTL-2
• Power supply: 2.5V ±0.2V
• PCB height: 1.25 inches
3. AVAILABLE PART NUMBERS
MODULE PART NUMBER SPEED
W9412FASA-7 DDR266/CL2
W9412FASA-75 DDR266/CL2.5
W9412FASA
- 2 -
4. PIN ASSIGNMENT
PIN
NAME
PIN
NAME
PIN
NAME
PIN NAME
PIN
NAME
PIN
NAME
1 VREF 67
DQ27 135
DQ34 2 VREF 68
DQ31 136
DQ38
3 VSS 69
VDD 137
VSS 4 VSS 70
VDD 138
VSS
5 DQ0 71
CB0* 139
DQ35 6 DQ4 72
CB4* 140
DQ39
7 DQ1 73
CB1* 141
DQ40 8 DQ5 74
CB5* 142
DQ44
9 VDD 75
VSS 143
VDD 10 VDD 76
VSS 144
VDD
11 DQS0 77
DQS8 145
DQ41 12 DM0 78
DM8 146
DQ45
13 DQ2 79
CB2* 147
DQS5 14 DQ6 80
CB6* 148
DM5
15 VSS 81
VDD 149
VSS 16 VSS 82
VDD 150
VSS
17 DQ3 83
CB3* 151
DQ42 18 DQ7 84
CB7* 152
DQ46
19 DQ8 85
NC 153
DQ43 20 DQ12 86
NC 154
DQ47
21 VDD 87
VSS 155
VDD 22 VDD 88
VSS 156
VDD
23 DQ9 89
CLK2* 157
VDD 24 DQ13 90
VSS 158
CLK1
25 DQS1 91
CLK2 *
159
VSS 26 DM1 92
VDD 160
CLK1
27 VSS 93
VDD 161
VSS 28 VSS 94
VDD 162
VSS
29 DQ10 95
CKE1* 163
DQ48 30 DQ14 96
CKE0 164
DQ52
31 DQ11 97
A13* 165
DQ49 32 DQ15 98
BA2* 166
DQ53
33 VDD 99
A12 167
VDD 34 VDD 100
A11 168
VDD
35 CLK0 101
A9 169
DQS6 36 VDD 102
A8 170
DM6
37 CLK0
103
VSS 171
DQ50 38 VSS 104
VSS 172
DQ54
39 VSS 105
A7 173
VSS 40 VSS 106
A6 174
VSS
KEY 107
A5 175
DQ51 KEY 108
A4 176
DQ55
41 DQ16 109
A3 177
DQ56 42 DQ20 110
A2 178
DQ60
43 DQ17 111
A1 179
VDD 44 DQ21 112
A0 180
VDD
45 VDD 113
VDD 181
DQ57 46 VDD 114
VDD 182
DQ61
47 DQS2 115
A10/AP
183
DQS7 48 DM2 116
BA1 184
DM7
49 DQ18 117
BA0 185
VSS 50 DQ22 118
RAS 186
VSS
51 VSS 119
WE 187
DQ58 52 VSS 120
CAS 188
DQ62
53 DQ19 121
CS0 189
DQ59 54 DQ23 122
CS1* 190
DQ63
55 DQ24 123
NC 191
VDD 56 DQ28 124
NC 192
VDD
57 VDD 125
VSS 193
SDA 58 VDD 126
VSS 194
SA0
59 DQ25 127
DQ32 195
SCL 60 DQ29 128
DQ36 196
SA1
61 DQS3 129
DQ33 197
VDDSPD 62 DM3 130
DQ37 198
SA2
63 VSS 131
VDD 199
VDDID 64 VSS 132
VDD 200
NC
65 DQ26 133
DQS4 66 DQ30 134
DM4
* These pins are not used in this module.
W9412FASA
Publication Release Date: March 15, 2002
- 3 - Revision A1
5. PIN DESCRIPTIONS
PIN NAME FUNCTION DESCRIPTION
CLKn, CLKn Clock Input CLKn and CLKn are differential clock inputs. All input command signals
are sampled at the positive edge of CLK (except for DQ, DM and CKE).
CSn Chip Select Disable or enable the command decoder. When command
decoder is disabled, new command is ignored and previous
operation continues.
CKEn Clock Enable CKE controls the clock activation and deactivation. When CKE is low,
Power Down mode, Suspend mode, or Self-Refresh mode is entered.
A0 − A12 Address Multiplexed pins for row and column address.
Row address: A0 − A12. Column address: A0 − A8.
BA0 − BA1 Bank Select
Address Selects bank to be activated during row address latch time.
Selects bank for read/write during column address latch time.
RAS Row Address
Strobe Command input. When sampled at the rising edge of the clock, RAS ,
CAS and WE define the operation to be executed.
CAS Column
Address Strobe
Referred to RAS
WE Write Enable Referred to RAS
DM0 − DM7 Input/Output
Mask The output buffer is placed at Hi-Z when DM is sampled high in read
cycle. In write cycle, sampling DM high will block the write data.
DQ0 − DQ63 Data
Input/Output Multiplexed pins for data output and input
DQS0 − DQS7 Data Strobe
Input/Output Output with read data, input with write data. DQS is edge-aligned with
read data, centered in write data.
VDD Power (+2.5V) Power supply (2.5V).
VSS Ground Ground
VREF Reference
Voltage SSTL-2 Reference voltage
VDDSPD SPD Power Separated power supply for SPD EEPROM (2.3V − 3.6V)
SCL Serial Clock Clock for serial presence detection
SDA Serial Data I/O Data line for serial presence detection
SAn SPD Address
Line System assigned address (SA0 − SA2) to identify different memory
module in a system board.
NC No Connection No connection
W9412FASA
- 4 -
6. BLOCK DIAGRAM
LDQS
LDM
I/O0-7
UDQS
UDM
I/O8-15
CS
U1
CS0
DQS0
DM0
DQ0 - DQ7
DQS1
DM1
DQ8 - DQ15
LDQS
LDM
I/O0-7
UDQS
UDM
I/O8-15
CS
U3
DQS4
DM4
DQ32 - DQ39
DQS5
DM5
DQ40 - DQ47
LDQS
LDM
I/O0-7
UDQS
UDM
I/O8-15
CS
U2
DQS2
DM2
DQ16 - DQ23
DQS3
DM3
DQ24 - DQ31
LDQS
LDM
I/O0-7
UDQS
UDM
I/O8-15
CS
U4
DQS6
DM6
DQ48 - DQ55
DQS7
DM7
DQ56 - DQ63
CKE0
RAS
CAS
WE
A(0:12)
BA(0:1)
DDR SDRAMs U1 - U4
DDR SDRAMs U1 - U4
DDR SDRAMs U1 - U4
DDR SDRAMs U1 - U4
DDR SDRAMs U1 - U4
DDR SDRAMs U1 - U4
VDDSPD
VDD
VREF
VSS
SPD EEPROM
DDR SDRAMs U1 - U4
DDR SDRAMs U1 - U4
DDR SDRAMs U1 - U4
VDDID
Notes:
1. Damping resistors for DQ/DQS/DM signals are 22 Ohms.
2. VDDID open denotes that the VDD and VDDQ pins of DDR SDRAMs are connected together. (VDD=VDDQ)
SDA
SCL
SA(0:2)
SPD EEPROM
SCL
A0 - A2
WP
SDA
NC
CLK0
CLK0
CLK1
CLK1
CLK2
CLK2
2 SDRAMs
2 SDRAMs
120 Ohm
120 Ohm
W9412FASA
Publication Release Date: March 15, 2002
- 5 - Revision A1
7. ABSOLUTE MAXIMUM RATINGS
PARAMETER SYMBOL RATING UNIT
Input, Output Voltage VIN, VOUT -0.3 − VDDQ +0.3 V
Power Supply Voltage VDD, VDDQ -0.3 − 3.6 V
Operating Temperature TOPR 0 − 70 °C
Storage Temperature TSTG -55 − 150 °C
Soldering Temperature (10s) TSOLDER 260 °C
Power Dissipation for Each Component PD 4 W
Short Circuit Output Current IOUT 50 mA
Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability
of the device.
8. RECOMMENDED DC OPERATING CONDITIONS
(TA = 0 to 70°C)
PARAMETER SYMBOL
MIN. TYP. MAX. UNIT
NOTES
Power Supply Voltage VDD 2.3 2.5 2.7 V 2
Power Supply Voltage (for I/O Buffer) VDDQ 2.3 2.5 VDD V 2
Input reference Voltage VREF 0.49 x VDDQ
0.50 x VDDQ
0.51 x VDDQ
V 2,3
Termination Voltage (System) VTT VREF - 0.04
VREF VREF + 0.04
V 2,8
Input High Voltage (DC) VIH (DC) VREF + 0.15
- VDDQ + 0.3 V 2
Input Low Voltage (DC) VIL (DC) -0.3 - VREF - 0.15
V 2
Differential Clock DC Input Voltage VICK (DC) -0.3 - VDDQ + 0.3 V 15
Input Differential Voltage. CLK and
CLK inputs (DC) VID (DC) 0.36 - VDDQ + 0.6 V 13,15
Input High Voltage (AC) VIH (AC) VREF + 0.31
- - V 2
Input Low Voltage (AC) VIL (AC) - - VREF - 0.31
V 2
Input Differential Voltage. CLK and
CLK inputs (AC) VID (AC) 0.7 - VDDQ + 0.6 V 13,15
Differential AC input Cross Point Voltage
VX (AC) VDDQ/2 - 0.2
- VDDQ/2 + 0.2
V 12, 15
Differential Clock AC Middle Point VISO (AC) VDDQ/2 - 0.2
- VDDQ/2 + 0.2
V 14, 15
Note: Undershoot limit: VIL (min.) = -0.9V with a pulse width < 5 nS
Overshoot limit: VIH (max.) = VDDQ +0.9V with a pulse width < 5 nS
VIH (DC) and VIL (DC) are levels to maintain the current logic state, VIH (AC) and VIL (AC) are levels to change to the new logic
state.
W9412FASA
- 6 -
9. CAPACITANCE
(VDD = VDDQ = 2.5V ±0.2V, f = 1 MHz, TA = 25°C, VOUT (DC) = VDDQ/2, VOUT (Peak to Peak) = 0.2V)
PARAMETER SYMBOL MIN. MAX. UNIT
Address Input Capacitance (A0 − A12, BA0, BA1) Cadd-IN 12 pF
Command Input Capacitance (RAS ,CAS , WE ) CCMD-IN 12 pF
CS signals Input Capacitance (CS0 ) CCS-IN 12 pF
CKE signal Input Capacitance (CKE0) CCKE-IN 12 pF
CLK signals Input Capacitance (CLKn,CLKn ) CCLK-IN 6 pF
DM/DQS/DQ Input capacitance (DM0 − DM7, DQS0 − 7, DQ0 − 63) CI/O 5 pF
10. DC CHARACTERISTICS
MAX. UNIT
NOTES
PARAMETER SYM.
-7 -75
OPERATING CURRENT: One Bank Active-Precharge; tRC = tRC min; tCK =
tCK min; DQ, DM and DQS inputs changing twice per clock cycle; Address
and control inputs changing once per clock cycle IDD0 440 440 7
OPERATING CURRENT: One Bank Active-Read-Precharge; Burst = 2; tRC
= tRC min; CL=2.5; tCK = tCK min; IOUT=0mA; Address and control inputs
changing once per clock cycle. IDD1 440 440 7, 9
PRECHARGE-POWER-DOWN STANDBY CURRENT: All Banks Idle;
Power down mode; CKE < VIL max; tCK = tCK min; Vin = VREF for DQ, DQS
and DM IDD2P 8 8
IDLE FLOATING STANDBY CURRENT: CS > VIH min; All Banks Idle; CKE
> VIH min; Address and other control inputs changing once per clock cycle;
Vin = Vref for DQ, DQS and DM IDD2F 180 160 7
IDLE STANDBY CURRENT: CS > VIH min; All Banks Idle; CKE > VIH min;
tCK = tCK min; Address and other control inputs changing once per clock
cycle; Vin > VIH min or Vin < VIL max for DQ, DQS and DM IDD2N 180 160 7
IDLE QUIET STANDBY CURRENT: CS > VIH min; All Banks Idle; CKE >
VIH min; tCK = tCK min; Address and other control inputs stable; Vin > VREF
for DQ, DQS and DM IDD2Q 160 140 mA
7
ACTIVE POWER-DOWN STANDBY CURRENT: One Bank Active; Power
down mode; CKE < VIL max; tCK = tCK min IDD3P 80 80
ACTIVE STANDBY CURRENT: CS > VIH min; CKE > VIH min; One Bank
Active-Precharge; tRC = tRAS max; tCK = tCK min; DQ, DM and DQS inputs
changing twice per clock cycle; Address and other control inputs changing
once per clock cycle
IDD3N 280 260 7
OPERATING CURRENT: Burst = 2; Reads; Continuous burst; One Bank
Active; Address and control inputs changing once per clock cycle; CL = 2.5;
tCK = tCK min; IOUT = 0 mA IDD4R 660 620 7, 9
OPERATING CURRENT: Burst = 2; Write; Continuous burst; One Bank
Active; Address and control inputs changing once per clock cycle; CL=2.5;
tCK = tCK min; DQ, DM and DQS inputs changing twice per clock cycle IDD4W 660 620 7
AUTO REFRESH CURRENT: tRC = tRFC min IDD5 760 760 7
SELF REFRESH CURRENT: CKE < 0.2V IDD6 12 12
RANDOM READ CURRENT: 4 Banks Active Read with activate every 20
nS, Auto-Precharge Read every 20ns; Burst = 4; Trcd = 3; IOUT = 0 mA; DQ,
DM and DQS inputs changing twice per clock cycle; Address changing once
per clock cycle
IDD7 1080
1080
W9412FASA
Publication Release Date: March 15, 2002
- 7 - Revision A1
11. AC CHARACTERISTICS OF SDRAM COMPONENTS (Notes: 10, 12)
SYMBOL
PARAMETER -7 -75 UNITS
NOTES
MIN.
MAX.
MIN.
MAX.
tRC Active to Ref/Active Command Period 65 65
tRFC Ref to Ref/Active Command Period 75 75
tRAS Active to Precharge Command Period 45 100000
45 100000
tRCD Active to Read/Write Command Delay Time 15 15
tRAP Active to Read with Auto Precharge enable 15 15
nS
tCCD Read/Write (a) to Read/Write (b) Command Period
1 1 tCK
tRP Precharge to Active Command Period 20 20
tRRD Active (a) to Active (b) Command Period 15 15
tWR Write Recovery time 15 15
tDAL Auto Precharge Write Recovery + Precharge time 30 30
tCK CL = 2 7.5 15 8 15
CLK Cycle Time CL = 2.5 7 15 7.5 15
tAC Data Access time from CLK, CLK -0.75
0.75
-0.75
0.75
tDQSCK DQS output access time from CLK, CLK -0.75
0.75
-0.75
0.75 16
tDQSQ Data Strobe Edge to Output Data Edge Skew 0.5 0.5
ns
tCH CLk High Level Width 0.45
0.55
0.45
0.55
tCL CLK Low Level Width 0.45
0.55
0.45
0.55 tCK 11
tHP CLK Half Period (minimum of actual tCH, tCL) Min.
(tCL,tCH)
Min.
(tCL,tCH)
tQH DQ Output Data Hold Time from DQS tHP
-0.75
tHP
-0.75
nS
tRPRE DQS Read Preamble Time 0.9 1.1 0.9 1.1
tRPST DQS Read Postamble Time 0.4 0.6 0.4 0.6 tCK 11
tDS DQ and DM Setup Time 0.5 0.5
tDH DQ and DM Hold Time 0.5 0.5
tDIPW DQ and DM Input Pulse Width (for each input) 1.75
1.75
nS
tDQSH DQS Input High Pulse Width 0.35
0.35
tDQSL DQS Input Low Pulse Width 0.35
0.35
tDSS DQS Falling Edge to CLK Setup Time 0.2 0.2
tDSH DQS Falling Edge Hold Time from CLK 0.2 0.2
tCK 11
tWPRES Clock to DQS Write Preamble Set-up Time 0 0 nS
tWPRE DQS Write Preamble Time 0.25
0.25
tWPST DQS Write Postamble Time 0.4 0.4
tDQSS Write Command to First DQS Latching Transition 0.75
1.25
0.75
1.25 11
tDSSK UDQS – LDQS Skew (x 16) -0.25
0.25
-0.25
0.25
tCK
tIS Input Setup Time 0.9 0.9
tIH Input Hold Time 0.9 0.9
tIPW Control & Address Input Pulse Width (for each input)
2.2 2.2
tHZ Data-out High-impedance Time from CLK, CLK -0.75
0.75
-0.75
0.75
tLZ Data-out Low-impedance Time from CLK,CLK -0.75
0.75
-0.75
0.75
tT(SS) SSTL Input Transition 0.5 1.5 0.5 1.5
nS
tWTR Internal Write to Read Command Delay 1 1 tCK
tXSNR Exit Self Refresh to Non-read Command 75 75 nS
tXSRD Exit Self Refresh to Read Command 10 10 tCK
tREF Refresh Time (8K) 64 64 mS
tMRD Mode Register Set Cycle Time 15 15 nS
W9412FASA
- 8 -
12. AC TEST CONDITION OF SDRAM COMPONENTS
PARAMETER SYM. VALUE UNIT NOTE
Input High Voltage (AC) VIH VREF +0.31 V
Input Low Voltage (AC) VIL V REF -0.31 V
Input Reference Voltage VREF 0.5 x VDDQ V
Termination Voltage VTT 0.5 x VDDQ V
Input Signal Peak to Peak Swing VSWING
1.0 V
Differential Clock Input Reference Voltage VR Vx (AC) V
Input Difference Voltage. CLK and CLK inputs (AC)
VID (AC)
1.5 V
Input Signal Minimum Slew Rate SLEW 1.0 V/nS
Output Timing Measurement Reference Voltage VOTR 0.5 x VDDQ V
V SWING (MAX)
VDDQ
VSS
TT
VIH min (AC)
VREF
VIL max (AC)
SLEW = (VIH min (AC) - VILmax (AC)) / T
RT= 50 ohms
VTT
A.C. TEST LOAD (A)
Z = 50 ohms
output 30pF
Notes:
(1) Conditions outside the limits listed under “ABSOLUTE MAXIMUM RATINGS” may cause permanent damage to the
device.
(2) All voltages are referenced to VSS, VSSQ.
(3) Peak to peak AC noise on VREF may not exceed ±2% of VREF(DC).
(4) VOH = 1.95V, VOL = 0.35V
(5) VOH = 1.9V, VOL = 0.4V
(6) The values of IOH (DC) is based on VDDQ = 2.3V and VTT = 1.19V. The values of IOL (DC) is based on VDDQ =2.3V and
VTT = 1.11V.
(7) These parameters depend on the cycle rate and these values are measured at a cycle rate with the minimum values
of tCK and tRC.
(8) VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set
equal to VREF and must track variations in the DC level of VREF.
W9412FASA
Publication Release Date: March 15, 2002
- 9 - Revision A1
(9) These parameters depend on the output loading. Specified values are obtained with the output open.
(10) Transition times are measured between VIH min.(AC) and VIL max.(AC).Transition (rise and fall) of input signals have a
fixed slope.
(11) If the result of nominal calculation with regard to tCK contains more than one decimal place, the result is rounded up to
the nearest decimal place. i.e., tDQSS = 0.75 × tCK, tCK = 7.5 nS, 0.75 × 7.5 nS = 5.625 nS is rounded up to 5.6 nS.
(12) VX is the differential clock cross point voltage where input timing measurement is referenced.
(13) VID is magnitude of the difference between CLK input level and CLK input level.
(14) VISO means {VICK(CLK) + VICK(CLK )}/2.
(15) Refer to the figure below.
CLK
CLK
VSS
V
ICK
V
X
V
X
V
X
V
X
V
X
V
ICK
V
ICK
V
ICK
V
ID(AC)
V
ID(AC)
0 V Differential
V
ISO
V
ISO(min)
V
ISO(max)
V
SS
(16) tAC and tDQSCK depend on the clock jitter. These timing are measured at stable clock.
W9412FASA
- 10 -
13. OPERATION MODES
The following Simplified Truth Table illustrates the operation modes of DDR SDRAM. For more
detailed information please refer to the DDR SDRAM datasheet.
Simplified Truth Table
COMMAND DEVICE
STATE
CKEN-1
CKEN
DMN BS0,
BS1
A10
A12,
A11,
A9-A0
CS
RAS
CAS
WE
Bank Active Idle H X X V V V L L H H
Bank Precharge Any H X X V L X L L H L
Precharge All Any H X X X H X L L H L
Write Active(3) H X X V L V L H L L
Write with
Autoprecharge Active(3)
H X X V H V L H L L
Read Active(3)
H X X V L V L H L H
Read with
Autoprecharge Active(3)
H X X V H V L H L H
Mode Register Set Idle H X X L, L C C L L L L
Extended Mode Register
Set Idle H X X H, L V V L L L L
No Operation Any H X X X X X L H H H
Burst Read Stop Active H X X X X X L H H L
Device Deselect Any H X X X X X H X X X
Auto Refresh Idle H H X X X X L L L H
Self Refresh Entry Idle H L X X X X L L L H
H X X X Self Refresh Exit Idle (Self
Refresh)
L H X X X X
L H H X
H X X X Power Down Mode
Entry Idle/
Active(5) H L X X X X
L H H X
H X X X Power Down Mode Exit Any
(Power
Down)
L H X X X X
L H H X
Data Write Enable Active H X L X X X X X X X
Data Write Disable Active H X H X X X X X X X
Notes:
1. V = Valid X = Don’t Care L = Low level H = High level
2. CKEn signal is input level when commands are issued.
3. CKEn-1 signal is input level one clock cycle before the commands are issued.
4. These are state designated by the BS0, BS1 signals.
5. Power Down Mode can not entry in the burst cycle.
W9412FASA
Publication Release Date: March 15, 2002
- 11 - Revision A1
14. SERIAL PRESENCE DETECT EEPROM
The Serial Presence Detect (SPD) function is implemented by using a 2,408-bit EEPROM component.
This nonvolatile storage device contains those data for identifying the module type and various
SDRAM organizations and timing parameters. System read operations to the EEPROM device occur
using the DIMM SCL (clock) and SDA (data) signals, together with SA(2:0) which provide the
EEPROM Device Address.
SPD EEPROM DC Operating Conditions
(VCC = 2.3V − 3.6V)
PARAMETER/CONDITION SYM. MIN. MAX. UNIT
NOTES
Supply Voltage VCC 2.3 3.6 V
Input High (Logic 1) Voltage, all inputs VIH VCC x 0.7 VCC +0.5 V
Input Low (Logic 0) Voltage, all inputs VIL -0.3 VCC x 0.3 V
Output Low Voltage, lout = 3 mA VOL 0.4 V IOL = 3 mA
Input Leakage Current, VIN = GND to VCC ILI 2 uA
Output Leakage Current, VOUT = GND to VCC ILO 2 uA
Power Supply Current
SCL Clock Frequency = 100 KHz ICC 1 mA
SPD AC Operating Conditions
(VCC = 2.3V − 3.6V)
PARAMETER SYM. MIN. MAX. UNIT
SCL clock frequency fSCL 100 KHz
Noise Suppression Time Constant at SCL, SDA Inputs tI 100 nS
SCL Low to SDA Data Out Valid tAA 0.2 3.5 µS
Time the bus must be free before a new transition can start tBUF 4.7 µS
Start Condition Hold Time tHD:STA 4.0 µS
Clock Low Period tLOW 4.7 µS
Clock High Period tHIGH 4.0 µS
Start Condition Setup Time tSU:STA 4.7 µS
Data in Hold Time tHD:DAT 0 µS
Data in Setup Time tSU:DAT 250 nS
SDA and SCL Rise time tR 1 µS
SDA and SCL Fall Time tF 300 nS
Stop Condition Setup Time tSU:STO 4 µS
Data Out Hold Time tDH 200 nS
Write Cycle Time tWR 10 mS
Note: The write cycle time (tWR) is the time from a valid stop condition of a write sequence to the end of the internal
erase/program cycle. During the write cycle the EEPROM bus interface circuits are disabled, SDA is allowed to remain
high the bus level pull-up resistor, and the device does not respond to its slave address.
W9412FASA
- 12 -
15. SPD DATA
FUNCTION SUPPORTED HEX VALUE
BYTE NO. FUNCTION DESCRIBED -7 -75 -7 -75
0 Defines # bytes written into serial memory at
module manufacturer 128 bytes 80h
1 Total # bytes of SPD memory device 256 bytes (2K-bit) 08h
2 Fundamental memory type (FPM, EDO, DRAM..)
DDR SDRAM 07h
3 # Row Addresses on this assembly 13 0Dh
4 # Column Addresses on this assembly 09 09h
5 # Module Rows on this assembly 1 row 01h
6 Data Width of this assembly. 64 bits 40h
7 Data Width continuation - 00h
8 Voltage interface standard of this assembly SSTL 2.5V 04h
9 SDRAM Cycle time @CAS latency of 2.5 7 nS 7.5 nS 70h 75h
10 SDRAM Access time @CAS latency of 2.5 +/-0.75 nS +/-0.75 nS 75h 75h
11 DIMM Configuration type (Non-parity, Parity ECC)
Non parity 00h
12 Refresh Rate/Type 7.8 µS, support self refresh 82h
13 SDRAM width, Primary DRAM X 16 10h
14 Error Checking SDRAM data width None 00h
15 Minimum Clock Delay, Back Random Column
Addresses TCCD = 1 CLK 01h
16 Burst Lengths supported 2, 4, 8 0Eh
17 #Bank on Each SDRAM device 4 banks 04h
18 CAS# Latencies Supported 2 & 2.5 0Ch
19 CS# Latency 0 CLK 01h
20 Write Latency 1 CLK 02h
21 SDRAM Module Attributes Differential Clock, Non-
buffered Non–registered &
redundant addressing 20h
22 SDRAM Device Attributes: General 2.5V+/-10% voltage
tolerance, Burst Read, Write,
precharge all, auto precharge
00h
23 SDRAM cycle time @ CAS latency of 2 7.5 nS 10 nS 75h A0h
24 SDRAM access time @CAS latency of 2 +/-0.75 nS +/-0.75 nS 75h 75h
25 SDRAM cycle time @ CAS latency of 1.5 - - 00h 00h
26 SDRAM access time @CAS latency of 1.5 - - 00h 00h
27 Precharge to active command period (tRP) 20 nS 20 nS 50h 50h
28 Active to Active command period (tRRD) 15 nS 15 nS 3Ch 3Ch
29 Active to Read/Write command delay time (tRCD)
20 nS 20 nS 50h 50h
30 Minimum Active to precharge period (tRAS) 45 nS 45 nS 2Dh 2Dh
31 Density of each Row on Module Each row of 128 MB 20h
32 Command and Address signal input setup time 0.9 nS 0.9 nS 90h 90h
33 Command and Address signal input hold time 0.9 nS 0.9 nS 90h 90h
34 Data signal input setup time 0.5 nS 0.5 nS 50h 50h
35 Data signal input hold time 0.5 nS 0.5 nS 50h 50h
36 - 61 Superset Information (may be used in future) - 00h
62 SPD data specification revision Initial release revision 00h
63 Checksum for Bytes 0 - 62 - - 76h A6h
64 - 128 Unused storage locations - 00h
W9412FASA
Publication Release Date: March 15, 2002
- 13 - Revision A1
16. LABELING INFORMATION
There is a product description sticker stuck on each module to fully describe the information of the
module. The following are examples of the product description sticker.
Examples:
MODULE P/N EXAMPLE OF STICKER
W9412FASA-7
(DDR266/CL2 SO-DIMM)
W9412FASA-7
128MB DDR266/CL2 SO-DIMM
TAIWAN 126K264896
W9412FASA-75
(DDR266/CL2.5 SO-DIMM)
W9412FASA-75
128MB DDR266/CL2.5 SO-DIMM
TAIWAN 126K264896
The content of this product description sticker is described as below:
1. MODULE PART NUMBER W9412FASA-7/-75
DIMM Module Part Number Informatoin
W94
Winbond Product Line
W94:
DDR SDRAM
Memory Size
12:
128Mbytes
DDR SDRAM Type
F:
16M x 16
Speed Grade
-7:
DDR266 CL2
-75:
DDR266 CL2.5
Module Version
A:
A Version
Module Type
S:
DDR SO-DIMM
DDR SDRAM Version
A:
A Version
12 FASA-7/-75
1. Total Memory Size: 128Mbytes
2. Compliant Industry Spec: DDR266/CL2, DDR266/CL2.5
3. Module Type: SO-DIMM
4. Manufacturing Location: TAIWAN
5. Tracking Number: 126K264896
(The number “126K264896” is for reference only. It is changed according to assembly date,
assembly site, and serial lot number.)
W9412FASA
- 14 -
17. PACKAGE DIMENSION
Units:Inches
Tolerances : 0.005 unless otherwise specified
Component P/N: W942516AH-7/-75 (16M x 16 DDR SDRAM,TSOP-66)
0.24
1.250
0.16
Rear View
Front View
2.7
2- 0.07
1199
4139
0.79
200 2
4042
SPD
0.04 0.004
0.0040.07
0.0040.16
0.001
0.01
0.024 TYP
0.120 Min
0.018
0.04 0.004
0.100 Max
Side View
W9412FASA
Publication Release Date: March 15, 2002
- 15 - Revision A1
Headquarters
No. 4, Creation Rd. III,
Science-Based Industrial Park,
Hsinchu, Taiwan
TEL: 886-3-5770066
FAX: 886-3-5665577
http://www.winbond.com.tw/
Taipei Office
TEL: 886-2-8177-7168
FAX: 886-2-8751-3579
Winbond Electronics Corporation America
2727 North First Street, San Jose,
CA 95134, U.S.A.
TEL: 1-408-9436666
FAX: 1-408-5441798
Winbond Electronics (H.K.) Ltd.
No. 378 Kwun Tong Rd.,
Kowloon, Hong Kong
FAX: 852-27552064
Unit 9-15, 22F, Millennium City,
TEL: 852-27513100
Please note that all data and specifications are subject to change without notice.
All the trade marks of products and companies mentioned in this data sheet belong to their respective owners.
Winbond Electronics (Shanghai) Ltd.
200336 China
FAX: 86-21-62365998
27F, 2299 Yan An W. Rd. Shanghai,
TEL: 86-21-62365999
Winbond Electronics Corporation Japan
Shinyokohama Kohoku-ku,
Yokohama, 222-0033
FAX: 81-45-4781800
7F Daini-ueno BLDG, 3-7-18
TEL: 81-45-4781881
9F, No.480, Rueiguang Rd.,
Neihu Chiu, Taipei, 114,
Taiwan, R.O.C.
