Features * * * * * * * * * * * * * * * * * * * * * * * * * * * * 80C52 Compatible 8051 pin and instruction compatible Four 8-bit I/O ports Three 16-bit timer/counters 256 bytes scratchpad RAM High-Speed Architecture 40 MHz @ 5V, 30MHz @ 3V X2 Speed Improvement capability (6 clocks/machine cycle) - 30 MHz @ 5V, 20 MHz @ 3V (Equivalent to - 60 MHz @ 5V, 40 MHz @ 3V) Dual Data Pointer On-chip ROM/EPROM (16K-bytes, 32K-bytes) Programmable Clock Out and Up/Down Timer/Counter 2 Hardware Watchdog Timer (One-time enabled with Reset-Out) Asynchronous port reset Interrupt Structure with 6 Interrupt sources 4 level priority interrupt system Full duplex Enhanced UART Framing error detection Automatic address recognition Low EMI (inhibit ALE) Power Control modes Idle mode Power-down mode Power-off Flag Once mode (On-chip Emulation) Power supply: 4.5-5.5V, 2.7-5.5V Temperature ranges: Commercial (0 to 70oC) and Industrial (-40 to 85 oC) Packages: PDIL40, PLCC44, VQFP44 1.4, PQFP44 F1, CQPJ44 (window), CDIL40 (window) 8-bit CMOS Microcontroller 16/32 Kbytes ROM/OTP TS80C54/58X2 TS87C54/58X2 AT80C54/58X2 AT87C54/58X2 1. Description TS80C54/58X2 is high performance CMOS ROM, OTP and EPROM versions of the 80C51 CMOS single chip 8-bit microcontroller. The TS8 0C54/58X2 retains a ll fe atures of the Atmel 80 C51 with e xtend ed ROM/EPROM capacity (16/32 Kbytes), 256 bytes of internal RAM, a 6-source , 4-level interrupt system, an on-chip oscilator and three timer/counters. In addition, the TS80C54/58X2 a Hardware Watchdog Timer, a more versatile serial channel that facilitates multiprocessor communication (EUART) and a X2 speed improvement mechanism. The fully static design of the TS80C54/58X2 allows to reduce system power consumption by bringing the clock frequency down to any value, even DC, without loss of data. Rev. 4431E-8051-04/06 The TS80C54/58X2 has 2 software-selectable modes of reduced activity for further reduction in power consumption. In the idle mode the CPU is frozen while the timers, the serial port and the interrupt system are still operating. In the power-down mode the RAM is saved and all other functions are inoperative. PDIL40 PLCC44 PQFP44 F1 VQFP44 1.4 ROM (bytes) EPROM (bytes) TS80C54X2 16k 0 TS80C58X2 32k 0 TS87C54X2 0 16k TS87C58X2 0 32k (2) (2) (1) XTAL1 EUART XTAL2 ALE/ PROG C51 CORE PSEN ROM /EPROM 16/32Kx8 RAM 256x8 T2 T2EX Vss Vcc TxD RxD 2. Block Diagram (1) Timer2 IB-bus CPU EA/VPP Timer 0 Timer 1 (2) Parallel I/O Ports INT Ctrl Watch Dog P3 P2 P1 P0 INT1 (2) (2) T1 (2) (2) INT0 Port 0 Port 1 Port 2 Port 3 RESET WR (2) T0 RD (1): Alternate function of Port 1 (2): Alternate function of Port 3 2 AT/TS8xC54/8X2 4431E-8051-04/06 AT/TS8xC54/8X2 4. SFR Mapping The Special Function Registers (SFRs) of the TS80C54/58X2 fall into the following categories: * C51 core registers: ACC, B, DPH, DPL, PSW, SP, AUXR1 * I/O port registers: P0, P1, P2, P3 * Timer registers: T2CON, T2MOD, TCON, TH0, TH1, TH2, TMOD, TL0, TL1, TL2, RCAP2L, RCAP2H * Serial I/O port registers: SADDR, SADEN, SBUF, SCON * Power and clock control registers: PCON * HDW Watchdog Timer Reset: WDTRST, WDTPRG * Interrupt system registers: IE, IP, IPH * Others: AUXR, CKCON 3 4431E-8051-04/06 Table 4-1. All SFRs with their address and their reset value Bit addressable 0/8 Non Bit addressable 1/9 2/A 3/B 4/C 5/D 6/E 7/F F8h F0h FFh B 0000 0000 F7h E8h E0h EFh ACC 0000 0000 E7h D8h DFh D0h PSW 0000 0000 C8h T2CON 0000 0000 D7h T2MOD XXXX XX00 RCAP2L 0000 0000 RCAP2H 0000 0000 TL2 0000 0000 TH2 0000 0000 CFh C0h B8h B0h C7h IP SADEN XX00 0000 0000 0000 BFh P3 IPH XX00 0000 1111 1111 A8h A0h 98h 90h IE SADDR 0X00 0000 0000 0000 AFh P2 AUXR1 WDTRST WDTPRG 1111 1111 XXXX 0XX0 XXXX XXXX XXXX X000 SCON SBUF 0000 0000 XXXX XXXX B7h A7h 9Fh P1 97h 1111 1111 88h 80h TCON TMOD TL0 TL1 TH0 TH1 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 P0 1111 1111 SP 0000 0111 DPL 0000 0000 DPH 0000 0000 0/8 1/9 2/A 3/B AUXR XXXX XXX0 CKCON 8Fh XXXX XXX0 PCON 87h 00X1 0000 4/C 5/D 6/E 7/F reserved 4 AT/TS8xC54/8X2 4431E-8051-04/06 AT/TS8xC54/8X2 31 30 EA/VPP ALE/PROG PSEN P2.7 / A15 P2.6 / A14 P2.5 / A13 P3.4/T0 P3.5/T1 P3.6/WR 14 15 26 16 25 P3.7/RD XTAL2 17 18 24 23 P2.2 / A10 XTAL1 19 20 22 21 P2.1 / A9 37 P0.6/AD6 RST 10 36 P0.7/AD7 P3.0/RxD 35 34 EA/VPP NIC* 11 12 P3.1/TxD 13 33 ALE/PROG P3.2/INT0 P3.3/INT1 14 15 32 31 PSEN P3.4/T0 P3.5/T1 16 30 P2.6/A14 17 29 P2.5/A13 PLCC/CQPJ 44 NIC* P2.7/A15 P2.3/A11 P2.4/A12 P2.2/A10 P2.1/A9 P3.6/WR P1.0/T2 P1.1/T2EX P1.2 P1.3 P0.5/AD5 18 19 20 21 22 23 24 25 26 27 28 P2.0 / A8 P1.4 VSS P2.4 / A12 P2.3 / A11 9 NIC* P2.0/A8 13 29 28 27 P1.7 VSS CDIL40 39 38 P0.4/AD4 P1.6 XTAL1 PDIL/ 6 5 4 3 2 1 44 43 42 41 40 7 8 P3.7/RD XTAL2 11 12 P0.2/AD2 P0.3/AD3 10 P0.1/AD1 P0.7 / A7 P0.0/AD0 32 VCC 9 VSS1/NIC* P1.5 P1.0/T2 P0.6 / A6 P0.5 / A5 P1.2 33 P1.4 P0.3 / A3 P0.4 / A4 7 8 36 35 34 5 6 P1.3 P0.1 / A1 P0.2 / A2 37 P0.3/AD3 P3.2/INT0 P3.3/INT1 3 4 P0.2/AD2 P3.0/RxD P3.1/TxD P0.0 / A0 P0.1/AD1 P1.7 RST VCC 39 38 P0.0/AD0 P1.6 40 2 VCC P1.4 P1.5 1 VSS1/NIC* P1.0 / T2 P1.1 / T2EX P1.2 P1.3 P1.1/T2EX 5. Pin Configuration 44 43 42 41 40 39 38 37 36 35 34 P1.5 33 32 P0.4/AD4 P1.6 1 2 P1.7 RST 3 4 31 P0.6/AD6 P0.7/AD7 P3.0/RxD NIC* P3.1/TxD P3.2/INT0 P3.3/INT1 P3.4/T0 P3.5/T1 30 5 6 7 8 29 28 27 PQFP44 F1 VQFP44 1.4 26 25 9 10 11 P0.5/AD5 EA/VPP NIC* ALE/PROG PSEN 24 P2.7/A15 P2.6/A14 23 P2.5/A13 P2.4/A12 P2.3/A11 P2.2/A10 P2.1/A9 P2.0/A8 NIC* VSS XTAL1 XTAL2 P3.7/RD P3.6/WR 12 13 14 15 16 17 18 19 20 21 22 *NIC: No Internal Connection 5 4431E-8051-04/06 Table 5-1. Pin Description for 40/44 pin packages PIN NUMBER TYPE MNEMONIC DIL LCC VQFP 1.4 VSS 20 22 16 I Ground: 0V reference 1 39 I Optional Ground: Contact the Sales Office for ground connection. Power Supply: This is the power supply voltage for normal, idle and power-down operation Vss1 Name And Function VCC 40 44 38 I P0.0-P0.7 39-32 43-36 37-30 I/O Port 0: Port 0 is an open-drain, bidirectional I/O port. Port 0 pins that have 1s written to them float and can be used as high impedance inputs. Port 0 pins must be polarized to Vcc or Vss in order to prevent any parasitic current consumption. Port 0 is also the multiplexed low-order address and data bus during access to external program and data memory. In this application, it uses strong internal pull-up when emitting 1s. Port 0 also inputs the code bytes during EPROM programming. External pull-ups are required during program verification during which P0 outputs the code bytes. P1.0-P1.7 1-8 2-9 40-44 1-3 I/O Port 1: Port 1 is an 8-bit bidirectional I/O port with internal pull-ups. Port 1 pins that have 1s written to them are pulled high by the internal pull-ups and can be used as inputs. As inputs, Port 1 pins that are externally pulled low will source current because of the internal pull-ups. Port 1 also receives the low-order address byte during memory programming and verification. Alternate functions for Port 1 include: P2.0-P2.7 1 2 40 I/O 2 3 41 I 21-28 24-31 18-25 I/O T2 (P1.0): Timer/Counter 2 external count input/Clockout T2EX (P1.1): Timer/Counter 2 Reload/Capture/Direction Control Port 2: Port 2 is an 8-bit bidirectional I/O port with internal pull-ups. Port 2 pins that have 1s written to them are pulled high by the internal pull-ups and can be used as inputs. As inputs, Port 2 pins that are externally pulled low will source current because of the internal pull-ups. Port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that use 16bit addresses (MOVX @DPTR).In this application, it uses strong internal pull-ups emitting 1s. During accesses to external data memory that use 8-bit addresses (MOVX @Ri), port 2 emits the contents of the P2 SFR. Some Port 2 pins receive the high order address bits during EPROM programming and verification: P2.0 to P2.5 for A8 to A13 P3.0-P3.7 10-17 11, 13-19 5, 7-13 I/O Port 3: Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. Port 3 pins that have 1s written to them are pulled high by the internal pull-ups and can be used as inputs. As inputs, Port 3 pins that are externally pulled low will source current because of the internal pull-ups. Some Port 3 pin P3.4 receive the high order address bits during EPROM programming and verification for TS8xC58X2 devices. Port 3 also serves the special features of the 80C51 family, as listed below. 10 11 5 I RXD (P3.0): Serial input port 11 13 7 O TXD (P3.1): Serial output port 12 14 8 I INT0 (P3.2): External interrupt 0 13 15 9 I INT1 (P3.3): External interrupt 1 14 16 10 I T0 (P3.4): Timer 0 external input 15 17 11 I T1 (P3.5): Timer 1 external input 16 18 12 O WR (P3.6): External data memory write strobe 17 19 13 O RD (P3.7): External data memory read strobe P3.4 also receives A14 during TS87C58X2 EPROM Programming. Reset 6 9 10 4 I Reset: A high on this pin for two machine cycles while the oscillator is running, resets the device. An internal diffused resistor to VSS permits a power-on reset using only an external capacitor to VCC. AT/TS8xC54/8X2 4431E-8051-04/06 AT/TS8xC54/8X2 Table 5-1. Pin Description for 40/44 pin packages PIN NUMBER TYPE MNEMONIC DIL MNEMONIC LCC VQFP 1.4 PIN NUMBER Name And Function TYPE NAME AND FUNCTION ALE/PROG 30 33 27 O (I) Address Latch Enable/Program Pulse: Output pulse for latching the low byte of the address during an access to external memory. In normal operation, ALE is emitted at a constant rate of 1/6 (1/3 in X2 mode) the oscillator frequency, and can be used for external timing or clocking. Note that one ALE pulse is skipped during each access to external data memory. This pin is also the program pulse input (PROG) during EPROM programming. ALE can be disabled by setting SFR's AUXR.0 bit. With this bit set, ALE will be inactive during internal fetches. PSEN 29 32 26 O Program Store ENable: The read strobe to external program memory. When executing code from the external program memory, PSEN is activated twice each machine cycle, except that two PSEN activations are skipped during each access to external data memory. PSEN is not activated during fetches from internal program memory. EA/VPP 31 35 29 I External Access Enable/Programming Supply Voltage: EA must be externally held low to enable the device to fetch code from external program memory locations 0000H and 3FFFH (54X2) or 7FFFH (58X2). If EA is held high, the device executes from internal program memory unless the program counter contains an address greater than 3FFFH (54X2) or 7FFFH (58X2). This pin also receives the 12.75V programming supply voltage (VPP) during EPROM programming. If security level 1 is programmed, EA will be internally latched on Reset. XTAL1 19 21 15 I Crystal 1: Input to the inverting oscillator amplifier and input to the internal clock generator circuits. XTAL2 18 20 14 O Crystal 2: Output from the inverting oscillator amplifier 7 4431E-8051-04/06 6. TS80C54/58X2 Enhanced Features In comparison to the original 80C52, the TS80C54/58X2 implements some new features, which are: * The X2 option. * The Dual Data Pointer. * The Watchdog. * The 4 level interrupt priority system. * The power-off flag. * The ONCE mode. * The ALE disabling. * Some enhanced features are also located in the UART and the timer 2. 6.1 X2 Feature The TS80C54/58X2 core needs only 6 clock periods per machine cycle. This feature called "X2" provides the following advantages: * Divide frequency crystals by 2 (cheaper crystals) while keeping same CPU power. * Save power consumption while keeping same CPU power (oscillator power saving). * Save power consumption by dividing dynamically operating frequency by 2 in operating and idle modes. * Increase CPU power by 2 while keeping same crystal frequency. In order to keep the original C51 compatibility, a divider by 2 is inserted between the XTAL1 signal and the main clock input of the core (phase generator). This divider may be disabled by software. 6.1.1 Description The clock for the whole circuit and peripheral is first divided by two before being used by the CPU core and peripherals. This allows any cyclic ratio to be accepted on XTAL1 input. In X2 mode, as this divider is bypassed, the signals on XTAL1 must have a cyclic ratio between 40 to 60%. Figure 6-2. shows the clock generation block diagram. X2 bit is validated on XTAL1/2 rising edge to avoid glitches when switching from X2 to STD mode. Figure 6-2. shows the mode switching waveforms. Figure 6-1. Clock Generation Diagram 2 XTAL1 FXTAL XTAL1:2 0 state machine: 6 clock cycles. 1 CPU control FOSC X2 CKCON reg 8 AT/TS8xC54/8X2 4431E-8051-04/06 AT/TS8xC54/8X2 Figure 6-2. Mode Switching Waveforms XTAL1 XTAL1:2 X2 bit CPU clock STD Mode X2 Mode STD Mode The X2 bit in the CKCON register (See Table 6-1.) allows to switch from 12 clock cycles per instruction to 6 clock cycles and vice versa. At reset, the standard speed is activated (STD mode). Setting this bit activates the X2 feature (X2 mode). CAUTION In order to prevent any incorrect operation while operating in X2 mode, user must be aware that all peripherals using clock frequency as time reference (UART, timers) will have their time reference divided by two. For example a free running timer generating an interrupt every 20 ms will then generate an interrupt every 10 ms. UART with 4800 baud rate will have 9600 baud rate. 9 4431E-8051-04/06 Table 6-1. CKCON Register CKCON - Clock Control Register (8Fh) 7 6 5 4 3 2 1 0 - - - - - - - X2 Bit Bit Number Mnemonic 7 - Reserved The value read from this bit is indeterminate. Do not set this bit. 6 - Reserved The value read from this bit is indeterminate. Do not set this bit. 5 - Reserved The value read from this bit is indeterminate. Do not set this bit. 4 - Reserved The value read from this bit is indeterminate. Do not set this bit. 3 - Reserved The value read from this bit is indeterminate. Do not set this bit. 2 - Reserved The value read from this bit is indeterminate. Do not set this bit. 1 - Reserved The value read from this bit is indeterminate. Do not set this bit. 0 X2 Description CPU and peripheral clock bit Clear to select 12 clock periods per machine cycle (STD mode, FOSC =FXTAL/2). Set to select 6 clock periods per machine cycle (X2 mode, FOSC =FXTAL). Reset Value = XXXX XXX0b Not bit addressable For further details on the X2 fe ature, please refer to ANM072 ava ilable on the web (http://www.atmel.com) 10 AT/TS8xC54/8X2 4431E-8051-04/06 AT/TS8xC54/8X2 7. Dual Data Pointer Register Ddptr The additional data pointer can be used to speed up code execution and reduce code size in a number of ways. The dual DPTR structure is a way by which the chip will specify the address of an external data memory location. There are two 16-bit DPTR registers that address the external memory, and a single bit called DPS = AUXR1/bit0 (See Table 7-1.) that allows the program code to switch between them (Refer to Figure 7-1). Figure 7-1. Use of Dual Pointer External Data Memory 7 0 DPS AUXR1(A2H) DPTR1 DPTR0 DPH(83H) DPL(82H) 11 4431E-8051-04/06 Table 7-1. AUXR1: Auxiliary Register 1 7 6 5 4 3 2 1 0 - - - - GF3 0 - DPS Bit Bit Number Mnemonic 7 - Reserved The value read from this bit is indeterminate. Do not set this bit. 6 - Reserved The value read from this bit is indeterminate. Do not set this bit. 5 - Reserved The value read from this bit is indeterminate. Do not set this bit. 4 - Reserved The value read from this bit is indeterminate. Do not set this bit. 3 GF3 2 0 Reserved Always stuck at 0. 1 - Reserved The value read from this bit is indeterminate. Do not set this bit. 0 DPS Description This bit is a general purpose user flag Data Pointer Selection Clear to select DPTR0. Set to select DPTR1. Reset Value = XXXX 00X0 Not bit addressable User software should not write 1s to reserved bits. These bits may be used in future 8051 family products to invoke new feature. In that case, the reset value of the new bit will be 0, and its active value will be 1. The value read from a reserved bit is indeterminate. 12 AT/TS8xC54/8X2 4431E-8051-04/06 AT/TS8xC54/8X2 7.1 Application Software can take advantage of the additional data pointers to both increase speed and reduce code size, for example, block operations (copy, compare, search ...) are well served by using one data pointer as a 'source' pointer and the other one as a "destination" pointer. ASSEMBLY LANGUAGE ; Block move using dual data pointers ; Destroys DPTR0, DPTR1, A and PSW ; note: DPS exits opposite of entry state ; unless an extra INC AUXR1 is added ; 00A2 AUXR1 EQU 0A2H ; 0000 909000 MOV DPTR,#SOURCE 0003 05A2 INC AUXR1 0005 90A000 MOV DPTR,#DEST 0008 LOOP: 0008 05A2 INC AUXR1 000A E0 MOVX A,@DPTR 000B A3 INC DPTR 000C 05A2 INC AUXR1 000E F0 MOVX @DPTR,A 000F A3 INC DPTR 0010 70F6 JNZ LOOP 0012 05A2 INC AUXR1 ; address of SOURCE ; switch data pointers ; address of DEST ; switch data pointers ; get a byte from SOURCE ; increment SOURCE address ; switch data pointers ; write the byte to DEST ; increment DEST address ; check for 0 terminator ; (optional) restore DPS INC is a short (2 bytes) and fast (12 clocks) way to manipulate the DPS bit in the AUXR1 SFR. However, note that the INC instruction does not directly force the DPS bit to a particular state, but simply toggles it. In simple routines, such as the block move example, only the fact that DPS is toggled in the proper sequence matters, not its actual value. In other words, the block move routine works the same whether DPS is '0' or '1' on entry. Observe that without the last instruction (INC AUXR1), the routine will exit with DPS in the opposite state. 13 4431E-8051-04/06 8. Timer 2 The timer 2 in the TS80C54/58X2 is compatible with the timer 2 in the 80C52. It is a 16-bit timer/counter: the count is maintained by two eight-bit timer registers, TH2 and TL2, connected in cascade. It is controlled by T2CON register (See Table 8-1) and T2MOD register (See Table 8-2). Timer 2 operation is similar to Timer 0 and Timer 1. C/T2 selects FOSC/12 (timer operation) or external pin T2 (counter operation) as the timer clock input. Setting TR2 allows TL2 to be incremented by the selected input. Timer 2 has 3 operating modes: capture, autoreload and Baud Rate Generator. These modes are selected by the combination of RCLK, TCLK and CP/RL2 (T2CON), as described in the Atmel Wireless & Microcontrollers 8-bit Microcontroller Hardware description. Refer to the Atmel Wireless & Microcontrollers 8-bit Microcontroller Hardware description for the description of Capture and Baud Rate Generator Modes. In TS80C54/58X2 Timer 2 includes the following enhancements: * Auto-reload mode with up or down counter * Programmable clock-output 8.1 Auto-Reload Mode The auto-reload mode configures timer 2 as a 16-bit timer or event counter with automatic reload. If DCEN bit in T2MOD is cleared, timer 2 behaves as in 80C52 (refer to the Atmel Wireless & Microcontrollers 8-bit Microcontroller Hardware description). If DCEN bit is set, timer 2 acts as an Up/down timer/counter as shown in Figure 8-1. In this mode the T2EX pin controls the direction of count. When T2EX is high, timer 2 counts up. Timer overflow occurs at FFFFh which sets the TF2 flag and generates an interrupt request. The overflow also causes the 16-bit value in RCAP2H and RCAP2L registers to be loaded into the timer registers TH2 and TL2. When T2EX is low, timer 2 counts down. Timer underflow occurs when the count in the timer registers TH2 and TL2 equals the value stored in RCAP2H and RCAP2L registers. The underflow sets TF2 flag and reloads FFFFh into the timer registers. The EXF2 bit toggles when timer 2 overflows or underflows according to the the direction of the count. EXF2 does not generate any interrupt. This bit can be used to provide 17-bit resolution 14 AT/TS8xC54/8X2 4431E-8051-04/06 AT/TS8xC54/8X2 Figure 8-1. Auto-Reload Mode Up/Down Counter (DCEN = 1) (:6 in X2 mode) XTAL1 FXTAL :12 0 FOSC 1 T2 TR2 C/T2 T2CONreg T2CONreg (DOWN COUNTING RELOAD VALUE) FFh FFh (8-bit) (8-bit) T2EX: if DCEN=1, 1=UP if DCEN=1, 0=DOWN TOG- T2CONreg EXF2 TL2 (8-bit) TH2 (8-bit) TF2 TIMER 2 INTERRUPT T2CONreg RCAP2L RCAP2H (8-bit) (8-bit) (UP COUNTING RELOAD VALUE) 8.1.1 Programmable Clock-Output In the clock-out mode, timer 2 operates as a 50%-duty-cycle, programmable clock generator (See Figure 8-2) . The input clock increments TL2 at frequency F OSC/2. The timer repeatedly counts to overflow from a loaded value. At overflow, the contents of RCAP2H and RCAP2L registers are loaded into TH2 and TL2. In this mode, timer 2 overflows do not generate interrupts. The formula gives the clock-out frequency as a function of the system oscillator frequency and the value in the RCAP2H and RCAP2L registers : Clock - OutFrequency F osc RCAP H RCAP L = ---------------------------------------------------------------------------------------4 x ( 65536 - 2 2 ) For a 16 MHz system clock, timer 2 has a programmable frequency range of 61 Hz (FOSC/216) to 4 MHz (FOSC/4). The generated clock signal is brought out to T2 pin (P1.0). Timer 2 is programmed for the clock-out mode as follows: * Set T2OE bit in T2MOD register. * Clear C/T2 bit in T2CON register. * Determine the 16-bit reload value from the formula and enter it in RCAP2H/RCAP2L registers. 15 4431E-8051-04/06 * Enter a 16-bit initial value in timer registers TH2/TL2. It can be the same as the reload value or a different one depending on the application. * To start the timer, set TR2 run control bit in T2CON register. It is possible to use timer 2 as a baud rate generator and a clock generator simultaneously. For this configuration, the baud rates and clock frequencies are not independent since both functions use the values in the RCAP2H and RCAP2L registers. Figure 8-2. Clock-Out Mode C/T2 = 0 :2 XTAL1 (:1 in X2 mode) TR2 T2CON reg TL2 (8-bit) TH2 (8-bit) OVERFLOW RCAP2L (8-bit) RCAP2H (8-bit) Toggle T2 Q D T2OE T2MOD reg T2EX EXF2 EXEN2 T2CON reg 16 TIMER 2 INTERRUPT T2CON reg AT/TS8xC54/8X2 4431E-8051-04/06 AT/TS8xC54/8X2 Table 8-1. T2CON Register T2CON - Timer 2 Control Register (C8h) 7 6 5 4 3 2 1 0 TF2 EXF2 RCLK TCLK EXEN2 TR2 C/T2# CP/RL2# Bit Bit Number Mnemonic 7 TF2 Description Timer 2 overflow Flag Must be cleared by software. Set by hardware on timer 2 overflow, if RCLK = 0 and TCLK = 0. 6 EXF2 Timer 2 External Flag Set when a capture or a reload is caused by a negative transition on T2EX pin if EXEN2=1. When set, causes the CPU to vector to timer 2 interrupt routine when timer 2 interrupt is enabled. Must be cleared by software. EXF2 doesn't cause an interrupt in Up/down counter mode (DCEN = 1) 5 RCLK Receive Clock bit Clear to use timer 1 overflow as receive clock for serial port in mode 1 or 3. Set to use timer 2 overflow as receive clock for serial port in mode 1 or 3. 4 TCLK Transmit Clock bit Clear to use timer 1 overflow as transmit clock for serial port in mode 1 or 3. Set to use timer 2 overflow as transmit clock for serial port in mode 1 or 3. Timer 2 External Enable bit Clear to ignore events on T2EX pin for timer 2 operation. Set to cause a capture or reload when a negative transition on T2EX pin is detected, if timer 2 is not used to clock the serial port. 3 EXEN2 2 TR2 1 C/T2# Timer/Counter 2 select bit Clear for timer operation (input from internal clock system: FOSC ). Set for counter operation (input from T2 input pin, falling edge trigger). Must be 0 for clock out mode. CP/RL2# Timer 2 Capture/Reload bit If RCLK=1 or TCLK=1, CP/RL2# is ignored and timer is forced to auto-reload on timer 2 overflow. Clear to auto-reload on timer 2 overflows or negative transitions on T2EX pin if EXEN2=1. Set to capture on negative transitions on T2EX pin if EXEN2=1. 0 Timer 2 Run control bit Clear to turn off timer 2. Set to turn on timer 2. Reset Value = 0000 0000b Bit addressable 17 4431E-8051-04/06 Table 8-2. T2MOD Register T2MOD - Timer 2 Mode Control Register (C9h) 7 6 5 4 3 2 1 0 - - - - - - T2OE DCEN Bit Bit Number Mnemonic 7 - Reserved The value read from this bit is indeterminate. Do not set this bit. 6 - Reserved The value read from this bit is indeterminate. Do not set this bit. 5 - Reserved The value read from this bit is indeterminate. Do not set this bit. 4 - Reserved The value read from this bit is indeterminate. Do not set this bit. 3 - Reserved The value read from this bit is indeterminate. Do not set this bit. 2 - Reserved The value read from this bit is indeterminate. Do not set this bit. 1 T2OE Timer 2 Output Enable bit Clear to program P1.0/T2 as clock input or I/O port. Set to program P1.0/T2 as clock output. 0 DCEN Down Counter Enable bit Clear to disable timer 2 as up/down counter. Set to enable timer 2 as up/down counter. Description Reset Value = XXXX XX00b Not bit addressable 18 AT/TS8xC54/8X2 4431E-8051-04/06 AT/TS8xC54/8X2 9. TS80C54/58X2 Serial I/O Port The serial I/O port in the TS80C54/58X2 is compatible with the serial I/O port in the 80C52. It provides both synchronous and asynchronous communication modes. It operates as an Universal Asynchronous Receiver and Transmitter (UART) in three full-duplex modes (Modes 1, 2 and 3). Asynchronous transmission and reception can occur simultaneously and at different baud rates Serial I/O port includes the following enhancements: * Framing error detection * Automatic address recognition 9.1 Framing Error Detection Framing bit error detection is provided for the three asynchronous modes (modes 1, 2 and 3). To enable the framing bit error detection feature, set SMOD0 bit in PCON register (See Figure 9-1). Figure 9-1. Framing Error Block Diagram SM0/FE SM1 SM2 REN TB8 RB8 TI RI SCON (98h) Set FE bit if stop bit is 0 (framing error) (SMOD0 = 1) SM0 to UART mode control (SMOD = 0) SMOD1SMOD0 - POF GF1 GF0 PD PCON (87h) IDL To UART framing error control When this feature is enabled, the receiver checks each incoming data frame for a valid stop bit. An invalid stop bit may result from noise on the serial lines or from simultaneous transmission by two CPUs. If a valid stop bit is not found, the Framing Error bit (FE) in SCON register (See Table 9-3.) bit is set. Software may examine FE bit after each reception to check for data errors. Once set, only software or a reset can clear FE bit. Subsequently received frames with valid stop bits cannot clear FE bit. When FE feature is enabled, RI rises on stop bit instead of the last data bit (See Figure 92. and Figure 9-3.). Figure 9-2. UART Timings in Mode 1 RXD D0 Start bit D1 D2 D3 D4 Data byte D5 D6 D7 Stop bit RI SMOD0=X FE SMOD0=1 19 4431E-8051-04/06 Figure 9-3. UART Timings in Modes 2 and 3 RXD D0 D1 D2 Start bit D3 D4 Data byte D5 D6 D7 D8 Ninth Stop bit bit RI SMOD0=0 RI SMOD0=1 FE SMOD0=1 9.1.1 Automatic Address Recognition The automatic address recognition feature is enabled when the multiprocessor communication feature is enabled (SM2 bit in SCON register is set). Implemented in hardware, automatic address recognition enhances the multiprocessor communication feature by allowing the serial port to examine the address of each incoming command frame. Only when the serial port recognizes its own address, the receiver sets RI bit in SCON register to generate an interrupt. This ensures that the CPU is not interrupted by command frames addressed to other devices. If desired, you may enable the automatic address recognition feature in mode 1. In this configuration, the stop bit takes the place of the ninth data bit. Bit RI is set only when the received command frame address matches the device's address and is terminated by a valid stop bit. To support automatic address recognition, a device is identified by a given address and a broadcast address. NOTE: The multiprocessor communication and automatic address recognition features cannot be enabled in mode 0 (i.e. setting SM2 bit in SCON register in mode 0 has no effect). 9.1.2 Given Address Each device has an individual address that is specified in SADDR register; the SADEN register is a mask byte that contains don't-care bits (defined by zeros) to form the device's given address. The don't-care bits provide the flexibility to address one or more slaves at a time. The following example illustrates how a given address is formed. To address a device by its individual address, the SADEN mask byte must be 1111 1111b. For example: SADDR SADEN Given 20 0101 0110b 1111 1100b 0101 01XXb AT/TS8xC54/8X2 4431E-8051-04/06 AT/TS8xC54/8X2 The following is an example of how to use given addresses to address different slaves: Slave A: SADDR SADEN Given 1111 0001b 1111 1010b 1111 0X0Xb Slave B: SADDR SADEN Given 1111 0011b 1111 1001b 1111 0XX1b Slave C: SADDR SADEN Given 1111 0010b 1111 1101b 1111 00X1b The SADEN byte is selected so that each slave may be addressed separately. For slave A, bit 0 (the LSB) is a don't-care bit; for slaves B and C, bit 0 is a 1. To communicate with slave A only, the master must send an address where bit 0 is clear (e.g. 1111 0000b). For slave A, bit 1 is a 1; for slaves B and C, bit 1 is a don't care bit. To communicate with slaves B and C, but not slave A, the master must send an address with bits 0 and 1 both set (e.g. 1111 0011b). To communicate with slaves A, B and C, the master must send an address with bit 0 set, bit 1 clear, and bit 2 clear (e.g. 1111 0001b). 9.1.3 Broadcast Address A broadcast address is formed from the logical OR of the SADDR and SADEN registers with zeros defined as don't-care bits, e.g.: SADDR SADEN Broadcast =SADDR OR SADEN 0101 0110b 1111 1100b 1111 111Xb The use of don't-care bits provides flexibility in defining the broadcast address, however in most applications, a broadcast address is FFh. The following is an example of using broadcast addresses: Slave A: SADDR 1111 0001b SADEN 1111 1010b Broadcast 1111 1X11b, Slave B: SADDR 1111 0011b SADEN 1111 1001b Broadcast 1111 1X11B, Slave C: SADDR= 1111 0010b SADEN 1111 1101b Broadcast 1111 1111b For slaves A and B, bit 2 is a don't care bit; for slave C, bit 2 is set. To communicate with all of the slaves, the master must send an address FFh. To communicate with slaves A and B, but not slave C, the master can send and address FBh. 9.1.4 Reset Addresses On reset, the SADDR and SADEN registers are initialized to 00h, i.e. the given and broadcast addresses are XXXX XXXXb (all don't-care bits). This ensures that the serial port will reply to any address, and so, that it is backwards compatible with the 80C51 microcontrollers that do not support automatic address recognition. 21 4431E-8051-04/06 Table 9-1. SADEN - Slave Address Mask Register (B9h) 7 6 5 4 3 2 1 0 2 1 0 Reset Value = 0000 0000b Not bit addressable Table 9-2. SADDR - Slave Address Register (A9h) 7 6 5 4 3 Reset Value = 0000 0000b Not bit addressable 22 AT/TS8xC54/8X2 4431E-8051-04/06 AT/TS8xC54/8X2 Table 9-3. SCON Register SCON - Serial Control Register (98h) 7 6 5 4 3 2 1 0 FE/SM0 SM1 SM2 REN TB8 RB8 TI RI Bit Bit Number Mnemonic 7 FE Description Framing Error bit (SMOD0=1) Clear to reset the error state, not cleared by a valid stop bit. Set by hardware when an invalid stop bit is detected. SMOD0 must be set to enable access to the FE bit SM0 Serial port Mode bit 0 Refer to SM1 for serial port mode selection. SMOD0 must be cleared to enable access to the SM0 bit 6 SM1 Serial port Mode bit 1 SM0 SM1Mode Description Baud Rate 0 0 1 1 Shift RegisterFXTAL/12 (/6 in X2 mode) 8-bit UARTVariable 9-bit UARTFXTAL/64 or FXTAL/32 (/32, /16 in X2 mode) 9-bit UARTVariable 0 1 0 1 0 1 2 3 5 SM2 Serial port Mode 2 bit / Multiprocessor Communication Enable bit Clear to disable multiprocessor communication feature. Set to enable multiprocessor communication feature in mode 2 and 3, and eventually mode 1. This bit should be cleared in mode 0. 4 REN Reception Enable bit Clear to disable serial reception. Set to enable serial reception. 3 TB8 Transmitter Bit 8 / Ninth bit to transmit in modes 2 and 3. 2 RB8 Clear to transmit a logic 0 in the 9th bit. Set to transmit a logic 1 in the 9th bit. Receiver Bit 8 / Ninth bit received in modes 2 and 3 Cleared by hardware if 9th bit received is a logic 0. Set by hardware if 9th bit received is a logic 1. In mode 1, if SM2 = 0, RB8 is the received stop bit. In mode 0 RB8 is not used. 1 TI Transmit Interrupt flag Clear to acknowledge interrupt. Set by hardware at the end of the 8th bit time in mode 0 or at the beginning of the stop bit in the other modes. 0 RI Receive Interrupt flag Clear to acknowledge interrupt. Set by hardware at the end of the 8th bit time in mode 0, see Figure 9-2. and Figure 9-3. in the other modes. Reset Value = 0000 0000b Bit addressable 23 4431E-8051-04/06 Table 9-4. PCON Register Table 9-5. PCON - Power Control Register (87h) 7 6 5 4 3 2 1 0 SMOD1 SMOD0 - POF GF1 GF0 PD IDL Bit Bit Number Mnemonic 7 SMOD1 Serial port Mode bit 1 Set to select double baud rate in mode 1, 2 or 3. 6 SMOD0 Serial port Mode bit 0 Clear to select SM0 bit in SCON register. Set to to select FE bit in SCON register. 5 - 4 POF Power-Off Flag Clear to recognize next reset type. Set by hardware when VCC rises from 0 to its nominal voltage. Can also be set by software. 3 GF1 General purpose Flag Cleared by user for general purpose usage. Set by user for general purpose usage. 2 GF0 General purpose Flag Cleared by user for general purpose usage. Set by user for general purpose usage. 1 PD Power-Down mode bit Cleared by hardware when reset occurs. Set to enter power-down mode. 0 IDL Idle mode bit Clear by hardware when interrupt or reset occurs. Set to enter idle mode. Description Reserved The value read from this bit is indeterminate. Do not set this bit. Reset Value = 00X1 0000b Not bit addressable Power-off flag reset value will be 1 only after a power on (cold reset). A warm reset doesn't affect the value of this bit. 24 AT/TS8xC54/8X2 4431E-8051-04/06 AT/TS8xC54/8X2 10. Interrupt System The TS80C54/58X2 has a total of 7 interrupt vectors: two external interrupts (INT0 and INT1), three timer interrupts (timers 0, 1 and 2) and the serial port interrupt. These interrupts are shown in Figure 10-1. Figure 10-1. Interrupt Control System High priority interrupt IPH, IP 3 INT0 IE0 0 3 TF0 0 Interrupt polling sequence, decreasing from high to low priority 3 INT1 IE1 0 3 TF1 0 RI TI 3 TF2 EXF2 3 0 0 Individual Enable Global Disable Low priority interrupt Each of the interrupt sources can be individually enabled or disabled by setting or clearing a bit in the Interrupt Enable register (See Table 10-2.). This register also contains a global disable bit, which must be cleared to disable all interrupts at once. Each interrupt source can also be individually programmed to one out of four priority levels by setting or clearing a bit in the Interrupt Priority register (See Table 10-3.) and in the Interrupt Priority High register (See Table 10-4.). shows the bit values and priority levels associated with each combination. Table 10-1. Priority Level Bit Values IPH.x IP.x Interrupt Level Priority 0 0 0 (Lowest) 0 1 1 1 0 2 1 1 3 (Highest) A low-priority interrupt can be interrupted by a high priority interrupt, but not by another low-priority interrupt. A high-priority interrupt can't be interrupted by any other interrupt source. 25 4431E-8051-04/06 If two interrupt requests of different priority levels are received simultaneously, the request of higher priority level is serviced. If interrupt requests of the same priority level are received simultaneously, an internal polling sequence determines which request is serviced. Thus within each priority level there is a second priority structure determined by the polling sequence. Table 10-2. IE Register IE - Interrupt Enable Register (A8h) 7 6 5 4 3 2 1 0 EA - ET2 ES ET1 EX1 ET0 EX0 Bit Bit Number Mnemonic Description Enable All interrupt bit Clear to disable all interrupts. Set to enable all interrupts. If EA=1, each interrupt source is individually enabled or disabled by setting or clearing its own interrupt enable bit. 7 EA 6 - 5 ET2 Timer 2 overflow interrupt Enable bit Clear to disable timer 2 overflow interrupt. Set to enable timer 2 overflow interrupt. 4 ES Serial port Enable bit Clear to disable serial port interrupt. Set to enable serial port interrupt. 3 ET1 Timer 1 overflow interrupt Enable bit Clear to disable timer 1 overflow interrupt. Set to enable timer 1 overflow interrupt. 2 EX1 External interrupt 1 Enable bit Clear to disable external interrupt 1. Set to enable external interrupt 1. 1 ET0 Timer 0 overflow interrupt Enable bit Clear to disable timer 0 overflow interrupt. Set to enable timer 0 overflow interrupt. 0 EX0 External interrupt 0 Enable bit Clear to disable external interrupt 0. Set to enable external interrupt 0. Reserved The value read from this bit is indeterminate. Do not set this bit. Reset Value = 0X00 0000b Bit addressable 26 AT/TS8xC54/8X2 4431E-8051-04/06 AT/TS8xC54/8X2 Table 10-3. IP Register IP - Interrupt Priority Register (B8h) 7 6 5 4 3 2 1 0 - - PT2 PS PT1 PX1 PT0 PX0 Bit Bit Number Mnemonic 7 - Reserved The value read from this bit is indeterminate. Do not set this bit. 6 - Reserved The value read from this bit is indeterminate. Do not set this bit. 5 PT2 Timer 2 overflow interrupt Priority bit Refer to PT2H for priority level. 4 PS Serial port Priority bit Refer to PSH for priority level. 3 PT1 Timer 1 overflow interrupt Priority bit Refer to PT1H for priority level. 2 PX1 External interrupt 1 Priority bit Refer to PX1H for priority level. 1 PT0 Timer 0 overflow interrupt Priority bit Refer to PT0H for priority level. 0 PX0 External interrupt 0 Priority bit Refer to PX0H for priority level. Description Reset Value = XX00 0000b Bit addressable 27 4431E-8051-04/06 Table 10-4. IPH Register IPH - Interrupt Priority High Register (B7h) 7 6 5 4 3 2 1 0 - - PT2H PSH PT1H PX1H PT0H PX0H Bit Bit Number Mnemonic 7 - Reserved The value read from this bit is indeterminate. Do not set this bit. 6 - Reserved The value read from this bit is indeterminate. Do not set this bit. 5 4 3 2 1 0 Description PT2H Timer 2 overflow interrupt Priority High bit PT2H PT2 Priority Level 0 0 Lowest 0 1 1 0 1 1 Highest PSH Serial port Priority High bit PSH PS Priority Level 0 0 Lowest 0 1 1 0 1 1 Highest PT1H Timer 1 overflow interrupt Priority High bit PT1H PT1 Priority Level 0 0 Lowest 0 1 1 0 1 1 Highest PX1H External interrupt 1 Priority High bit PX1H PX1 Priority Level 0 0 Lowest 0 1 1 0 1 1 Highest PT0H Timer 0 overflow interrupt Priority High bit PT0H PT0 Priority Level 0 0 Lowest 0 1 1 0 1 1 Highest PX0H External interrupt 0 Priority High bit PX0H PX0 Priority Level 0 0 Lowest 0 1 1 0 1 1 Highest Reset Value = XX00 0000b Not bit addressable 28 AT/TS8xC54/8X2 4431E-8051-04/06 AT/TS8xC54/8X2 11. Idle mode An instruction that sets PCON.0 causes that to be the last instruction executed before going into the Idle mode. In the Idle mode, the internal clock signal is gated off to the CPU, but not to the interrupt, Timer, and Serial Port functions. The CPU status is preserved in its entirely : the Stack Pointer, Program Counter, Program Status Word, Accumulator and all other registers maintain their data during Idle. The port pins hold the logical states they had at the time Idle was activated. ALE and PSEN hold at logic high levels. There are two ways to terminate the Idle. Activation of any enabled interrupt will cause PCON.0 to be cleared by hardware, terminating the Idle mode. The interrupt will be serviced, and following RETI the next instruction to be executed will be the one following the instruction that put the device into idle. The flag bits GF0 and GF1 can be used to give an indication if an interrupt occured during normal operation or during an Idle. For example, an instruction that activates Idle can also set one or both flag bits. When Idle is terminated by an interrupt, the interrupt service routine can examine the flag bits. The other way of terminating the Idle mode is with a hardware reset. Since the clock oscillator is still running, the hardware reset needs to be held active for only two machine cycles (24 oscillator periods) to complete the reset. 11.1 Power-Down Mode To save maximum power, a power-down mode can be invoked by software (Refer to Table 9-4., PCON register). In power-down mode, the oscillator is stopped and the instruction that invoked power-down mode is the last instruction executed. The internal RAM and SFRs retain their value until the power-down mode is terminated. VCC can be lowered to save further power. Either a hardware reset or an external interrupt can cause an exit from power-down. To properly terminate powerdown, the reset or external interrupt should not be executed before VCC is restored to its normal operating level and must be held active long enough for the oscillator to restart and stabilize. Only external interrupts INT0 and INT1 are useful to exit from power-down. For that, interrupt must be enabled and configured as level or edge sensitive interrupt input. Holding the pin low restarts the oscillator but bringing the pin high completes the exit as detailed in Figure 11-1. When both interrupts are enabled, the oscillator restarts as soon as one of the two inputs is held low and power down exit will be completed when the first input will be released. In this case the higher priority interrupt service routine is executed. Once the interrupt is serviced, the next instruction to be executed after RETI will be the one following the instruction that put TS80C54/58X2 into power-down mode. 29 4431E-8051-04/06 Figure 11-1. Power-Down Exit Waveform INT0 INT1 XTAL1 Active phase Power-down phase Oscillator restart phase Active phase Exit from power-down by reset redefines all the SFRs, exit from power-down by external interrupt does no affect the SFRs. Exit from power-down by either reset or external interrupt does not affect the internal RAM content. NOTE: If idle mode is activated with power-down mode (IDL and PD bits set), the exit sequence is unchanged, when execution is vectored to interrupt, PD and IDL bits are cleared and idle mode is not entered. Table 11-1. The state of ports during idle and power-down modes Mode Program Memory ALE PSEN PORT0 PORT1 PORT2 PORT3 Idle Internal 1 1 Port Data* Port Data Port Data Port Data Idle External 1 1 Floating Port Data Address Port Data Power Down Internal 0 0 Port Data* Port Data Port Data Port Data Power Down External 0 0 Floating Port Data Port Data Port Data * Port 0 can force a "zero" level. A "one" Level will leave port floating. 30 AT/TS8xC54/8X2 4431E-8051-04/06 AT/TS8xC54/8X2 12. Hardware Watchdog Timer The WDT is intended as a recovery method in situations where the CPU may be subjected to software upset. The WDT consists of a 14-bit counter and the WatchDog Timer ReSeT (WDTRST) SFR. The WDT is by default disabled from exiting reset. To enable the WDT, user must write 01EH and 0E1H in sequence to the WDTRST, SFR location 0A6H. When WDT is enabled, it will increment every machine cycle while the oscillator is running and there is no way to disable the WDT except through reset (either hardware reset or WDT overflow reset). When WDT overflows, it will drive an output RESET HIGH pulse at the RST-pin. 12.1 Using the WDT To enable the WDT, user must write 01EH and 0E1H in sequence to the WDTRST, SFR location 0A6H. When WDT is enabled, the user needs to service it by writing to 01EH and 0E1H to WDTRST to avoid WDT overflow. The 14-bit counter overflows when it reaches 16383 (3FFFH) and this will reset the device. When WDT is enabled, it will increment every machine cycle while the oscillator is running. This means the user must reset the WDT at least every 16383 machine cycle. To reset the WDT the user must write 01EH and 0E1H to WDTRST. WDTRST is a write only register. The WDT counter cannot be read or written. When WDT overflows, it will generate an output RESET pulse at the RST-pin. The RESET pulse duration is 96 x TOSC , where TOSC = 1/FOSC . To make the best use of the WDT, it should be serviced in those sections of code that will periodically be executed within the time required to prevent a WDT reset. To have a more powerful WDT, a 27 counter has been added to extend the Time-out capability, ranking from 16ms to 2s @ FOSC = 12MHz. To manage this feature, refer to WDTPRG register description, Table 12-2. (SFR0A7h). Table 12-1. Reset value WDTRST Register WDTRST Address (0A6h) 7 6 5 4 3 2 1 X X X X X X X Write only, this SFR is used to reset/enable the WDT by writing 01EH then 0E1H in sequence. 31 4431E-8051-04/06 Table 12-2. WDTPRG Register WDTPRG Address (0A7h) 7 6 5 4 3 2 1 0 T4 T3 T2 T1 T0 S2 S1 S0 Bit Bit Number Mnemonic 7 T4 6 T3 5 T2 4 T1 3 T0 2 S2 WDT Time-out select bit 2 1 S1 WDT Time-out select bit 1 0 S0 WDT Time-out select bit 0 Description Reserved Do not try to set or clear this bit. S2S1 0 0 0 0 1 1 1 1 S0 0 0 1 1 0 0 1 1 Selected Time-out 0 (214 - 1) machine cycles, 16.3 ms @ 12 MHz 1 (215 - 1) machine cycles, 32.7 ms @ 12 MHz 0 (216 - 1) machine cycles, 65.5 ms @ 12 MHz 1 (217 - 1) machine cycles, 131 ms @ 12 MHz 0 (218 - 1) machine cycles, 262 ms @ 12 MHz 1 (219 - 1) machine cycles, 542 ms @ 12 MHz 0 (220 - 1) machine cycles, 1.05 s @ 12 MHz 1 (221 - 1) machine cycles, 2.09 s @ 12 MHz Reset value XXXX X000 12.1.1 WDT during Power Down and Idle In Power Down mode the oscillator stops, which means the WDT also stops. While in Power Down mode the user does not need to service the WDT. There are 2 methods of exiting Power Down mode: by a hardware reset or via a level activated external interrupt which is enabled prior to entering Power Down mode. When Power Down is exited with hardware reset, servicing the WDT should occur as it normally should whenever the TS80C54/58X2 is reset. Exiting Power Down with an interrupt is significantly different. The interrupt is held low long enough for the oscillator to stabilize. When the interrupt is brought high, the interrupt is serviced. To prevent the WDT from resetting the device while the interrupt pin is held low, the WDT is not started until the interrupt is pulled high. It is suggested that the WDT be reset during the interrupt service routine. To ensure that the WDT does not overflow within a few states of exiting of powerdown, it is best to reset the WDT just before entering powerdown. In the Idle mode, the oscillator continues to run. To prevent the WDT from resetting the TS80C54/58X2 while in Idle mode, the user should always set up a timer that will periodically exit Idle, service the WDT, and re-enter Idle mode. 32 AT/TS8xC54/8X2 4431E-8051-04/06 AT/TS8xC54/8X2 13. ONCETM Mode (ON Chip Emulation) The ONCE mode facilitates testing and debugging of systems using TS80C54/58X2 without removing the circuit from the board. The ONCE mode is invoked by driving certain pins of the TS80C54/58X2; the following sequence must be exercised: * Pull ALE low while the device is in reset (RST high) and PSEN is high. * Hold ALE low as RST is deactivated. While the TS80C54/58X2 is in ONCE mode, an emulator or test CPU can be used to drive the circuit Table 13-1 shows the status of the port pins during ONCE mode. Normal operation is restored when normal reset is applied. Table 13-1. External Pin Status during ONCE Mode ALE PSEN Port 0 Port 1 Port 2 Port 3 XTAL1/2 Weak pull-up Weak pull-up Float Weak pull-up Weak pull-up Weak pull-up Active 33 4431E-8051-04/06 14. Power-Off Flag The power-off flag allows the user to distinguish between a "cold start" reset and a "warm start" reset. A cold start reset is the one induced by VCC switch-on. A warm start reset occurs while VCC is still applied to the device and could be generated for example by an exit from power-down. The power-off flag (POF) is located in PCON register (See Table 14-1.). POF is set by hardware when VCC rises from 0 to its nominal voltage. The POF can be set or cleared by software allowing the user to determine the type of reset. The POF value is only relevant with a Vcc range from 4.5V to 5.5V. For lower Vcc value, reading POF bit will return indeterminate value. Table 14-1. PCON Register PCON - Power Control Register (87h) 7 6 5 4 3 2 1 0 SMOD1 SMOD0 - POF GF1 GF0 PD IDL Bit Bit Number Mnemonic 7 SMOD1 Serial port Mode bit 1 Set to select double baud rate in mode 1, 2 or 3. 6 SMOD0 Serial port Mode bit 0 Clear to select SM0 bit in SCON register. Set to to select FE bit in SCON register. 5 - 4 POF Power-Off Flag Clear to recognize next reset type. Set by hardware when VCC rises from 0 to its nominal voltage. Can also be set by software. 3 GF1 General purpose Flag Cleared by user for general purpose usage. Set by user for general purpose usage. 2 GF0 General purpose Flag Cleared by user for general purpose usage. Set by user for general purpose usage. 1 PD Power-Down mode bit Cleared by hardware when reset occurs. Set to enter power-down mode. 0 IDL Idle mode bit Clear by hardware when interrupt or reset occurs. Set to enter idle mode. Description Reserved The value read from this bit is indeterminate. Do not set this bit. Reset Value = 00X1 0000b Not bit addressable 34 AT/TS8xC54/8X2 4431E-8051-04/06 AT/TS8xC54/8X2 15. Reduced EMI Mode The ALE signal is used to demultiplex address and data buses on port 0 when used with external program or data memory. Nevertheless, during internal code execution, ALE signal is still generated. In order to reduce EMI, ALE signal can be disabled by setting AO bit. The AO bit is located in AUXR register at bit location 0. As soon as AO is set, ALE is no longer output but remains active during MOVX and MOVC instructions and external fetches. During ALE disabling, ALE pin is weakly pulled high. Table 15-1. AUXR Register AUXR - Auxiliary Register (8Eh) 7 6 5 4 3 2 1 0 - - - - - - RESERVED AO Bit Bit Number Mnemonic 7 - Reserved The value read from this bit is indeterminate. Do not set this bit. 6 - Reserved The value read from this bit is indeterminate. Do not set this bit. 5 - Reserved The value read from this bit is indeterminate. Do not set this bit. 4 - Reserved The value read from this bit is indeterminate. Do not set this bit. 3 - Reserved The value read from this bit is indeterminate. Do not set this bit. 2 - Reserved The value read from this bit is indeterminate. Do not set this bit. 1 - Reserved The value read from this bit is indeterminate. Do not set this bit. 0 AO Description ALE Output bit Clear to restore ALE operation during internal fetches. Set to disable ALE operation during internal fetches. Reset Value = XXXX XXX0b Not bit addressable 35 4431E-8051-04/06 16. TS80C54/58X2 ROM 16.1 ROM Structure The TS80C54/58X2 ROM memory is in three different arrays: * the code array:16/32 Kbytes. * the encryption array:64 bytes. * the signature array:4 bytes. 16.2 ROM Lock System The program Lock system, when programmed, protects the on-chip program against software piracy. 16.2.1 Encryption Array Within the ROM array are 64 bytes of encryption array that are initially unprogrammed (all FF's). Every time a byte is addressed during program verify, 6 address lines are used to select a byte of the encryption array. This byte is then exclusive-NOR'ed (XNOR) with the code byte, creating an encrypted verify byte. The algorithm, with the encryption array in the unprogrammed state, will return the code in its original, unmodified form. When using the encryption array, one important factor needs to be considered. If a byte has the value FFh, verifying the byte will produce the encryption byte value. If a large block (>64 bytes) of code is left unprogrammed, a verification routine will display the content of the encryption array. For this reason all the unused code bytes should be programmed with random values. This will ensure program protection. 16.2.2 Program Lock Bits The lock bits when programmed according to Table 16-1. will provide different level of protection for the on-chip code and data. Table 16-1. Program Lock bits Program Lock Bits Security level LB1 LB2 LB3 1 U U U No program lock features enabled. Code verify will still be encrypted by the encryption array if programmed. MOVC instruction executed from external program memory returns non encrypted data. 2 P U U MOVC instruction executed from external program memory are disabled from fetching code bytes from internal memory, EA is sampled and latched on reset. Protection Description U: unprogrammed P: programmed 16.2.3 Signature bytes The TS80C54/58X2 contains 4 factory programmed signatures bytes. To read these bytes, perform the process described in section 8.3. 16.2.4 Verify Algorithm Refer to 17.3.4 36 AT/TS8xC54/8X2 4431E-8051-04/06 AT/TS8xC54/8X2 17. TS87C54/58X2 EPROM 17.1 EPROM Structure The TS87C54/58X2 EPROM is divided in two different arrays: * the code array:16/32 Kbytes. * the encryption array:64 bytes. * In addition a third non programmable array is implemented: * the signature array: 4 bytes. 17.2 EPROM Lock System The program Lock system, when programmed, protects the on-chip program against software piracy. 17.2.1 Encryption Array Within the EPROM array are 64 bytes of encryption array that are initially unprogrammed (all FF's). Every time a byte is addressed during program verify, 6 address lines are used to select a byte of the encryption array. This byte is then exclusive-NOR'ed (XNOR) with the code byte, creating an encrypted verify byte. The algorithm, with the encryption array in the unprogrammed state, will return the code in its original, unmodified form. When using the encryption array, one important factor needs to be considered. If a byte has the value FFh, verifying the byte will produce the encryption byte value. If a large block (>64 bytes) of code is left unprogrammed, a verification routine will display the content of the encryption array. For this reason all the unused code bytes should be programmed with random values. This will ensure program protection. 17.2.2 Program Lock Bits The three lock bits, when programmed according to Table 17-1., will provide different level of protection for the on-chip code and data. Table 17-1. Program Lock bits Program Lock Bits Security level LB1 LB2 LB3 Protection Description 1 U U U No program lock features enabled. Code verify will still be encrypted by the encryption array if programmed. MOVC instruction executed from external program memory returns non encrypted data. 2 P U U MOVC instruction executed from external program memory are disabled from fetching code bytes from internal memory, EA is sampled and latched on reset, and further programming of the EPROM is disabled. 3 U P U Same as 2, also verify is disabled. 4 U U P Same as 3, also external execution is disabled. U: unprogrammed, P: programmed WARNING: Security level 2 and 3 should only be programmed after EPROM and Core verification. 37 4431E-8051-04/06 17.2.3 17.3 17.3.1 Signature bytes The TS87C54/58X2 contains 4 factory programmed signatures bytes. To read these bytes, perform the process described in section 8.3. EPROM Programming Set-up modes In order to program and verify the EPROM or to read the signature bytes, the TS87C54/58X2 is placed in specific set-up modes (See Figure 17-1.). Control and program signals must be held at the levels indicated in Table 17-2. 17.3.2 Definition of terms Address Lines:P1.0-P1.7, P2.0-P2.5, P3.4 respectively TS87C54X2, P3.4 (A14) for TS87C58X2). for A0-A14 (P2.5 (A13) for Data Lines:P0.0-P0.7 for D0-D7 Control Signals:RST, PSEN, P2.6, P2.7, P3.3, P3.6, P3.7. Program Signals:ALE/PROG, EA/VPP. Table 17-2. EPROM Set-Up Modes Mode Program Code data Verify Code data Program Encryption Array Address 0-3Fh Read Signature Bytes Program Lock bit 1 Program Lock bit 2 Program Lock bit 3 38 RST PSEN 1 0 1 0 1 0 1 0 1 ALE/PR OG EA/VPP P2.6 P2.7 P3.3 P3.6 P3.7 12.75V 0 1 1 1 1 1 0 0 1 1 12.75V 0 1 0 1 1 0 0 0 0 0 12.75V 1 1 1 1 1 1 0 12.75V 1 1 1 0 0 1 0 12.75V 1 0 1 1 0 1 1 1 AT/TS8xC54/8X2 4431E-8051-04/06 AT/TS8xC54/8X2 Figure 17-1. Set-Up Modes Configuration +5V PROGRAM SIGNALS* EA/VPP VCC ALE/PROG CON TRO L SIGNALS* RST PSEN P2.6 P2.7 P3.3 P3.6 P3.7 4 to 6 MHz XTAL1 P0.0-P0.7 D0-D7 P1.0-P1.7 A0-A7 A8-A14 P2.0-P2.5, VSS GND * See Table 31. for proper value on these inputs 17.3.3 Programming Algorithm The Improved Quick Pulse algorithm is based on the Quick Pulse algorithm and decreases the number of pulses applied during byte programming from 25 to 1. To program the TS80C54/58X2 the following sequence must be exercised: * Step 1: Activate the combination of control signals. * Step 2: Input the valid address on the address lines. * Step 3: Input the appropriate data on the data lines. * Step 4: Raise EA/VPP from VCC to VPP (typical 12.75V). * Step 5: Pulse ALE/PROG once. * Step 6: Lower EA/VPP from VPP to VCC Repeat step 2 through 6 changing the address and data for the entire array or until the end of the object file is reached (See Figure 17-2.). 17.3.4 Verify algorithm Code array verify must be done after each byte or block of bytes is programmed. In either case, a complete verify of th e p rog ra mmed array will ensure reliable programming of the TS87C54/58X2. P 2.7 is used to enable data output. To verify the TS87C54/58X2 code the following sequence must be exercised: * Step 1: Activate the combination of program and control signals. * Step 2: Input the valid address on the address lines. * Step 3: Read data on the data lines. Repeat step 2 through 3 changing the address for the entire array verification (See Figure 17-2.) 39 4431E-8051-04/06 The encryption array cannot be directly verified. Verification of the encryption array is done by observing that the code array is well encrypted. Figure 17-2. Programming and Verification Signal's Waveform Programming Cycle Read/Verify Cycle A0-A12 Data In D0-D7 100 Data Out s ALE/PROG EA/VPP 12.75V 5V 0V C ont rol signals 17.4 EPROM Erasure (Windowed Packages Only) Erasing the EPROM erases the code array, the encryption array and the lock bits returning the parts to full functionality. Erasure leaves all the EPROM cells in a 1's state (FF). 17.4.1 Erasure Characteristics The recommended erasure procedure is exposure to ultraviolet light (at 2537 A) to an integrated dose at least 15 W-sec/cm2. Exposing the EPROM to an ultraviolet lamp of 12,000 W/cm2 rating for 30 minutes, at a distance of about 25 mm, should be sufficient. An exposure of 1 hour is recommended with most of standard erasers. Erasure of the EPROM begins to occur when the chip is exposed to light with wavelength shorter than approximately 4,000 A. Since sunlight and fluorescent lighting have wavelengths in this range, exposure to these light sources over an extended time (about 1 week in sunlight, or 3 years in room-level fluorescent lighting) could cause inadvertent erasure. If an application subjects the device to this type of exposure, it is suggested that an opaque label be placed over the window. 18. Signature Bytes The TS87C54/58X2 has four signature bytes in location 30h, 31h, 60h and 61h. To read these bytes follow the procedure for EPROM verify but activate the control lines provided in Table 31. for Read Signature Bytes. Table 18-1. shows the content of the signature byte for the TS80C54/58X2. 40 AT/TS8xC54/8X2 4431E-8051-04/06 AT/TS8xC54/8X2 Table 18-1. Signature Bytes Content Location Contents Comment 30h 58h Manufacturer Code: Atmel Wireless & Microcontrollers 31h 57h Family Code: C51 X2 60h 37h Product name: TS80C58X2 60h B7h Product name: TS87C58X2 60h 3Bh Product name: TS80C54X2 60h BBh Product name: TS87C54X2 61h FFh Product revision number 41 4431E-8051-04/06 19. Electrical Characteristics 19.1 Absolute Maximum Ratings (1) Ambiant Temperature Under Bias: C = commercial0C to 70C I = industrial -40C to 85C Storage Temperature-65C to + 150C Voltage on VCC to VSS-0.5 V to + 7 V Voltage on VPP to VSS-0.5 V to + 13 V Voltage on Any Pin to VSS-0.5 V to VCC + 0.5 V Power Dissipation1 W(2) 1. Stresses at or above those listed under " Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions may affect device reliability. 2. This value is based on the maximum allowable die temperature and the thermal resistance of the package. 19.2 Power consumption measurement Since the introduction of the first C51 devices, every manufacturer made operating Icc measurements under reset, which made sense for the designs were the CPU was running under reset. In Atmel new devices, the CPU is no more active during reset, so the power consumption is very low but is not really representative of what will happen in the customer system. That's why, while keeping measurements under Reset, Atmel presents a new way to measure the operating Icc: Using an internal test ROM, the following code is executed: Label: SJMP Label (80 FE) Ports 1, 2, 3 are disconnected, Port 0 is tied to FFh, EA = Vcc, RST = Vss, XTAL2 is not connected and XTAL1 is driven by the clock. This is much more representative of the real operating Icc. 19.3 DC Parameters for Standard Voltage TA = 0C to +70C; VSS = 0 V; VCC = 5 V 10%; F = 0 to 40 MHz. TA = -40C to +85C; VSS = 0 V; VCC = 5 V 10%; F = 0 to 40 MHz. Table 19-1. Symbol Parameter Min VIL Input Low Voltage VIH Input High Voltage except XTAL1, RST VIH1 Input High Voltage, XTAL1, RST VOL 42 DC Parameters in Standard Voltage Output Low Voltage, ports 1, 2, 3 (6) Typ Max Unit Test Conditions -0.5 0.2 VCC - 0.1 V 0.2 VCC + 0.9 VCC + 0.5 V 0.7 VCC VCC + 0.5 V 0.3 V IOL = 100 A(4) 0.45 V IOL = 1.6 mA(4) 1.0 V IOL = 3.5 mA(4) AT/TS8xC54/8X2 4431E-8051-04/06 AT/TS8xC54/8X2 Symbol VOL1 VOL2 VOH VOH1 VOH2 RRST Parameter Output Low Voltage, port 0 Min Typ (6) Output Low Voltage, ALE, PSEN Output High Voltage, ports 1, 2, 3 Output High Voltage, port 0 Output High Voltage,ALE, PSEN RST Pulldown Resistor Max Unit 0.3 V IOL = 200 A(4) 0.45 V IOL = 3.2 mA(4) 1.0 V IOL = 7.0 mA(4) 0.3 V IOL = 100 A(4) 0.45 V IOL = 1.6 mA(4) 1.0 V IOL = 3.5 mA(4) VCC - 0.3 V VCC - 0.7 V VCC - 1.5 V VCC - 0.3 V VCC - 0.7 V VCC - 1.5 V VCC - 0.3 V VCC - 0.7 V VCC - 1.5 V 50 90 (5) Test Conditions 200 k IOH = -10 A IOH = -30 A IOH = -60 A V CC = 5 V 10% IOH = -200 A IOH = -3.2 mA IOH = -7.0 mA VCC = 5 V 10% IOH = -100 A IOH = -1.6 mA IOH = -3.5 mA VCC = 5 V 10% IIL Logical 0 Input Current ports 1, 2 and 3 -50 A Vin = 0.45 V ILI Input Leakage Current 10 A 0.45 V < Vin < VCC ITL Logical 1 to 0 Transition Current, ports 1, 2, 3 -650 A Vin = 2.0 V CIO Capacitance of I/O Buffer 10 pF Fc = 1 MHz TA = 25C IPD Power Down Current 50 A 2.0 V < VCC < 5.5 V(3) ICC under RESET ICC operating Power Supply Current Maximum values, X1 mode: (7) 20 (5) 1 + 0.4 Freq (MHz) @12MHz 5.8 @16MHz 7.4 Power Supply Current Maximum values, X1 mode: (7) 3 + 0.6 Freq (MHz) @12MHz 10.2 mA mA V CC = 5.5 V(1) V CC = 5.5 V(8) @16MHz 12.6 ICC idle Power Supply Current Maximum values, X1 mode: (7) 0.25+0.3 Freq (MHz) @12MHz 3.9 mA V CC = 5.5 V(2) @16MHz 5.1 43 4431E-8051-04/06 19.4 DC Parameters for Low Voltage TA = 0C to +70C; VSS = 0 V; VCC = 2.7 V to 5.5 V 10%; F = 0 to 30 MHz. TA = -40C to +85C; VSS = 0 V; VCC = 2.7 V to 5.5 V 10%; F = 0 to 30 MHz. Table 19-2. Symbol DC Parameters for Low Voltage Parameter Min VIL Input Low Voltage VIH Input High Voltage except XTAL1, RST VIH1 Input High Voltage, XTAL1, RST Typ Max Unit -0.5 0.2 VCC - 0.1 V 0.2 VCC + 0.9 VCC + 0.5 V 0.7 VCC VCC + 0.5 V 0.45 V IOL = 0.8 mA(4) 0.45 V IOL = 1.6 mA(4) (6) VOL Output Low Voltage, ports 1, 2, 3 VOL1 Output Low Voltage, port 0, ALE, PSEN (6) Test Conditions VOH Output High Voltage, ports 1, 2, 3 0.9 VCC V IOH = -10 A VOH1 Output High Voltage, port 0, ALE, PSEN 0.9 VCC V IOH = -40 A IIL Logical 0 Input Current ports 1, 2 and 3 -50 A Vin = 0.45 V ILI Input Leakage Current 10 A 0.45 V < Vin < VCC ITL Logical 1 to 0 Transition Current, ports 1, 2, 3 -650 A Vin = 2.0 V 200 k 10 pF RRST RST Pulldown Resistor CIO Capacitance of I/O Buffer IPD Power Down Current ICC under RESET ICC operating Power Supply Current Maximum values, X1 mode: (7) 50 90 (5) 20 (5) 50 (5) 30 10 1 + 0.2 Freq (MHz) @12MHz 3.4 idle mA VCC = 2.0 V to 5.5 V(3) VCC = 2.0 V to 3.3 V(3) VCC = 3.3 V(1) @16MHz 4.2 Power Supply Current Maximum values, X1 mode: (7) 1 + 0.3 Freq (MHz) @12MHz 4.6 @16MHz 5.8 ICC A Fc = 1 MHz TA = 25C Power Supply Current Maximum values, X1 mode: (7) mA VCC = 3.3 V(8) 0.15 Freq (MHz) + 0.2 @12MHz 2 mA VCC = 3.3 V(2) @16MHz 2.6 1. ICC under reset is measured with all output pins disconnected; XTAL1 driven with TCLCH, TCHCL = 5 ns (see Figure 19-5.), VIL = V SS + 0.5 V, VIH = V CC - 0.5V; XTAL2 N.C.; EA = RST = Port 0 = VCC. ICC would be slightly higher if a crystal oscillator used.. 2. Idle ICC is measured with all output pins disconnected; XTAL1 driven with TCLCH, TCHCL = 5 ns, V IL = VSS + 0.5 V, VIH = V CC - 0.5 V; XTAL2 N.C; Port 0 = VCC; EA = RST = VSS (see Figure 19-3.). 3. Power Down I CC is measured with all output pins disconnected; EA = VSS, PORT 0 = VCC; XTAL2 NC.; RST = VSS (see Figure 19-4.). 4. Capacitance loading on Ports 0 and 2 may cause spurious noise pulses to be superimposed on the VOLs of ALE and Ports 1 and 3. The noise is due to external bus capacitance discharging into the Port 0 and Port 2 pins when these pins make 1 to 0 transitions during bus operation. In the worst cases (capacitive loading 100pF), the noise pulse on the ALE line may exceed 0.45V with maxi VOL peak 0.6V. A Schmitt Trigger use is not necessary. 44 AT/TS8xC54/8X2 4431E-8051-04/06 AT/TS8xC54/8X2 5. Typicals are based on a limited number of samples and are not guaranteed. The values listed are at room temperature and 5V. 6. Under steady state (non-transient) conditions, I OL must be externally limited as follows: Maximum IOL per port pin: 10 mA Maximum IOL per 8-bit port: Port 0: 26 mA Ports 1, 2 and 3: 15 mA Maximum total IOL for all output pins: 71 mA If I OL exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater than the listed test conditions. 7. For other values, please contact your sales office. 8. Operating I CC is measured with all output pins disconnected; XTAL1 driven with TCLCH, TCHCL = 5 ns (see Figure 19-5.), VIL = V SS + 0.5 V, VIH = V CC - 0.5V; XTAL2 N.C.; EA = Port 0 = VCC; RST = VSS. The internal ROM runs the code 80 FE (label: SJMP label). ICC would be slightly higher if a crystal oscillator is used. Measurements are made with OTP products when possible, which is the worst case. Figure 19-1. ICC Test Condition, under reset VCC ICC VCC P0 VCC RST (NC) C LOC K SIGNAL VCC EA XTAL2 XTAL1 VSS All other pins are disconnected. Figure 19-2. Operating ICC Test Condition VCC ICC VCC VCC P0 Reset = Vss after a high pulse during at least 24 clock cycles RST (NC) C LOC K SIGNAL EA XTAL2 XTAL1 VSS All other pins are disconnected. 45 4431E-8051-04/06 Figure 19-3. ICC Test Condition, Idle Mode VCC ICC VCC VCC P0 Reset = Vss after a high pulse during at least 24 clock cycles RST (NC) CLOCK SIGNAL EA XTAL2 XTAL1 All other pins are disconnected. VSS Figure 19-4. ICC Test Condition, Power-Down Mode VCC ICC VCC VCC P0 Reset = Vss after a high pulse during at least 24 clock cycles RST (NC) EA XTAL2 XTAL1 VSS All other pins are disconnected. Figure 19-5. Clock Signal Waveform for ICC Tests in Active and Idle Modes VCC-0.5V 0.45V TCLCH TCHCL TCLCH = TCHCL = 5ns. 46 0.7VCC 0.2VCC-0.1 AT/TS8xC54/8X2 4431E-8051-04/06 AT/TS8xC54/8X2 19.5 19.5.1 AC Parameters Explanation of the AC Symbols Each timing symbol has 5 characters. The first character is always a "T" (stands for time). The other characters, depending on their positions, stand for the name of a signal or the logical status of that signal. The following is a list of all the characters and what they stand for. Example:TAVLL = Time for Address Valid to ALE Low. TLLPL = Time for ALE Low to PSEN Low. TA = 0 to +70C (commercial temperature range); VSS = 0 V; VCC = 5 V 10%; -M and -V ranges. TA = -40C to +85C (industrial temperature range); VSS = 0 V; VCC = 5 V 10%; -M and -V ranges. TA = 0 to +70C (commercial temperature range); VSS = 0 V; 2.7 V < VCC < 5.5 V; -L range. TA = -40C to +85C (industrial temperature range); V SS = 0 V; 2.7 V < VCC < 5.5 V; -L range. Table 19-3. gives the maximum applicable load capacitance for Port 0, Port 1, 2 and 3, and ALE and PSEN signals. Timings will be guaranteed if these capacitances are respected. Higher capacitance values can be used, but timings will then be degraded. Table 19-3. Load Capacitance versus speed range, in pF -M -V -L Port 0 100 50 100 Port 1, 2, 3 80 50 80 ALE / PSEN 100 30 100 Table 19-5., Table 19-8. and Table 19-11. give the description of each AC symbols. Table 19-6., Table 19-9. and Table 19-12. give for each range the AC parameter. Table 19-7., Table 19-10. and Table 19-13. give the frequency derating formula of the AC parameter. To calculate each AC symbols, take the x value corresponding to the speed grade you need (-M, -V or -L) and replace this value in the formula. Values of the frequency must be limited to the corresponding speed grade: Table 19-4. Max frequency for derating formula regarding the speed grade -M X1 mode -M X2 mode -V X1 mode -V X2 mode -L X1 mode -L X2 mode Freq (MHz) 40 20 40 30 30 20 T (ns) 25 50 25 33.3 33.3 50 Example: TLLIV in X2 mode for a -V part at 20 MHz (T = 1/20E6 = 50 ns): x= 22 (Table 19-7.) T= 50ns TLLIV= 2T - x = 2 x 50 - 22 = 78ns 47 4431E-8051-04/06 19.5.2 External Program Memory Characteristics Table 19-5. Symbol Description Symbol Parameter T Table 19-6. Speed ALE pulse width TAVLL Address Valid to ALE TLLAX Address Hold After ALE TLLIV ALE to Valid Instruction In TLLPL ALE to PSEN TPLPH PSEN Pulse Width TPLIV PSEN to Valid Instruction In TPXIX Input Instruction Hold After PSEN TPXIZ Input Instruction FloatAfter PSEN TPXAV PSEN to Address Valid TAVIV Address to Valid Instruction In TPLAZ PSEN Low to Address Float AC Parameters for Fix Clock -V -V -L X2 mode standard mode 40 MHz X2 mode -L 20 MHz standard mode 40 MHz equiv. 30 MHz 30 MHz 40 MHz 60 MHz equiv. Min Min T 25 33 25 50 33 ns TLHLL 40 25 42 35 52 ns TAVLL 10 4 12 5 13 ns TLLAX 10 4 12 5 13 ns 70 Max Min 45 Max Min 78 Max Min Units Symbol TLLIV 65 Max 98 ns TLLPL 15 9 17 10 18 ns TPLPH 55 35 60 50 75 ns TPLIV TPXIX 48 TLHLL -M Max Oscillator clock period 35 0 25 0 50 0 30 0 55 0 ns ns TPXIZ 18 12 20 10 18 ns TAVIV 85 53 95 80 122 ns TPLAZ 10 10 10 10 10 ns AT/TS8xC54/8X2 4431E-8051-04/06 AT/TS8xC54/8X2 Table 19-7. 19.5.3 AC Parameters for a Variable Clock: derating formula Symbol Type Standard Clock X2 Clock -M -V -L Units TLHLL Min 2T-x T-x 10 8 15 ns TAVLL Min T-x 0.5 T - x 15 13 20 ns TLLAX Min T-x 0.5 T - x 15 13 20 ns TLLIV Max 4T-x 2T-x 30 22 35 ns TLLPL Min T-x 0.5 T - x 10 8 15 ns TPLPH Min 3T-x 1.5 T - x 20 15 25 ns TPLIV Max 3T-x 1.5 T - x 40 25 45 ns TPXIX Min x x 0 0 0 ns TPXIZ Max T-x 0.5 T - x 7 5 15 ns TAVIV Max 5T-x 2.5 T - x 40 30 45 ns TPLAZ Max x x 10 10 10 ns External Program Memory Read Cycle Figure 19-6. External Program Memory Read Cycle 12 TCLCL TLHLL TLLIV ALE TLLPL TPLPH PSEN TLLAX TAVLL PORT 0 INSTR IN TPLIV TPLAZ A0-A7 TPXAV TPXIZ TPXIX INSTR IN A0-A7 INSTR IN TAVIV PORT 2 ADDRESS OR SFR-P2 ADDRESS A8-A15 ADDRESS A8-A15 49 4431E-8051-04/06 19.5.4 External Data Memory Characteristics Table 19-8. Symbol Description Symbol Parameter TRLRH RD Pulse Width TWLWH WR Pulse Width TRLDV RD to Valid Data In TRHDX Data Hold After RD TRHDZ Data Float After RD TLLDV ALE to Valid Data In TAVDV Address to Valid Data In TLLWL ALE to WR or RD TAVWL Address to WR or RD TQVWX Data Valid to WR Transition TQVWH Data set-up to WR High TWHQX Data Hold After WR TRLAZ RD Low to Address Float TWHLH RD or WR High to ALE high Table 19-9. AC Parameters for a Fix Clock -V X2 mode Speed -M 30 MHz 40 MHz 60 MHz equiv. 20 MHz 30 MHz 40 MHz equiv. 85 135 125 175 ns TWLWH 130 85 135 125 175 ns 0 Min 60 0 Max Min 102 0 Max Units 130 Min 95 0 Max 137 0 ns ns TRHDZ 30 18 35 25 42 ns TLLDV 160 98 165 155 222 ns TAVDV 165 100 175 160 235 ns 130 ns TLLWL 50 TAVWL 75 47 80 70 103 ns TQVWX 10 7 15 5 13 ns TQVWH 160 107 165 155 213 ns TWHQX 15 9 17 10 18 ns TWHLH 100 30 0 TRLAZ 50 standard mode 40 MHz TRLRH 100 Max -L standard mode Min TRHDX Min -L X2 mode Symbol TRLDV Max -V 10 40 70 55 0 7 27 95 45 0 15 35 105 70 0 5 45 13 0 ns 53 ns AT/TS8xC54/8X2 4431E-8051-04/06 AT/TS8xC54/8X2 Table 19-10. AC Parameters for a Variable Clock: derating formula 19.5.5 Symbol Type Standard Clock X2 Clock -M -V -L Units TRLRH Min 6T-x 3T-x 20 15 25 ns TWLWH Min 6T-x 3T-x 20 15 25 ns TRLDV Max 5T-x 2.5 T - x 25 23 30 ns TRHDX Min x x 0 0 0 ns TRHDZ Max 2T-x T-x 20 15 25 ns TLLDV Max 8T-x 4T -x 40 35 45 ns TAVDV Max 9T-x 4.5 T - x 60 50 65 ns TLLWL Min 3T-x 1.5 T - x 25 20 30 ns TLLWL Max 3T+x 1.5 T + x 25 20 30 ns TAVWL Min 4T-x 2T-x 25 20 30 ns TQVWX Min T-x 0.5 T - x 15 10 20 ns TQVWH Min 7T-x 3.5 T - x 15 10 20 ns TWHQX Min T-x 0.5 T - x 10 8 15 ns TRLAZ Max x x 0 0 0 ns TWHLH Min T-x 0.5 T - x 15 10 20 ns TWHLH Max T+x 0.5 T + x 15 10 20 ns External Data Memory Write Cycle Figure 19-7. External Data Memory Write Cycle TWHLH ALE PSEN TLLWL TWLWH WR TLLAX PORT 0 A0-A7 TQVWX TQVWH TWHQX DATA OUT TAVWL PORT 2 ADDRESS OR SFR-P2 ADDRESS A8-A15 OR SFR P2 51 4431E-8051-04/06 19.5.6 External Data Memory Read Cycle Figure 19-8. External Data Memory Read Cycle TWHLH TLLDV ALE PSEN TLLWL TRLRH RLDV T RD TLLAX PORT 0 TRHDZ TAVDV TRHDX A0-A7 DATA IN TRLAZ TAVWL ADDRESS OR SFR-P2 PORT 2 19.5.7 ADDRESS A8-A15 OR SFR P2 Serial Port Timing - Shift Register Mode Table 19-11. Symbol Description Symbol Parameter TXLXL Serial port clock cycle time TQVHX Output data set-up to clock rising edge TXHQX Output data hold after clock rising edge TXHDX Input data hold after clock rising edge TXHDV Clock rising edge to input data valid Table 19-12. AC Parameters for a Fix Clock Speed -V -L -L standard mode 40 MHz X2 mode standard mode 20 MHz 30 MHz -M 30 MHz 40 MHz 60 MHz equiv. Max Min TXLXL 300 200 300 300 400 ns TQVHX 200 117 200 200 283 ns TXHQX 30 13 30 30 47 ns TXHDX 0 0 0 0 0 ns 34 Min Max 117 Min Max Units Min 117 Max 40 MHz equiv. Symbol TXHDV 52 -V X2 mode 117 Min Max 200 ns AT/TS8xC54/8X2 4431E-8051-04/06 AT/TS8xC54/8X2 Table 19-13. AC Parameters for a Variable Clock: derating formula 19.5.8 Symbol Type Standard Clock X2 Clock TXLXL Min 12 T 6T TQVHX Min 10 T - x 5T-x 50 50 50 ns TXHQX Min 2T-x T-x 20 20 20 ns TXHDX Min x x 0 0 0 ns TXHDV Max 10 T - x 5 T- x 133 133 133 ns -M -V -L Units ns Shift Register Timing Waveforms Figure 19-9. Shift Register Timing Waveforms INSTRUCTION 0 1 2 3 4 5 6 7 8 ALE TXLXL CLOCK TXHQX TQVXH OUTPUT DATA WRITE to SBUF INPUT DATA CLEAR RI 0 1 2 3 4 5 6 7 TXHDX TXHDV VALID VALID VALID SET TI VALID VALID VALID VALID VALID SET RI 53 4431E-8051-04/06 19.5.9 EPROM Programming and Verification Characteristics TA = 21C to 27C; VSS = 0V; VCC = 5V 10% while programming. VCC = operating range while verifying. Table 19-14. EPROM Programming Parameters Symbol VPP Programming Supply Voltage IPP Programming Supply Current 1/TCLCL 19.5.10 Parameter Oscillator Frquency Min Max Units 12.5 13 V 75 mA 6 MHz 4 TAVGL Address Setup to PROG Low 48 TCLCL TGHAX Adress Hold after PROG 48 TCLCL TDVGL Data Setup to PROG Low 48 TCLCL TGHDX Data Hold after PROG 48 TCLCL TEHSH (Enable) High to VPP 48 TCLCL TSHGL VPP Setup to PROG Low 10 s TGHSL VPP Hold after PROG 10 s TGLGH PROG Width 90 TAVQV Address to Valid Data 48 TCLCL TELQV ENABLE Low to Data Valid 48 TCLCL TEHQZ Data Float after ENABLE 110 0 s 48 TCLCL EPROM Programming and Verification Waveforms Figure 19-10. EPROM Programming and Verification Waveforms PROGRAMMING VERIFICATION ADDRESS ADDRESS P1.0-P1.7 P2.0-P2.5 P3.4-P3.5* P TAVQV P0 DATA OUT DATA IN TGHDX TGHAX TDVGL TAVGL ALE/PROG TSHGL TGLGH EA/VPP VPP VCC CONTROL SIGNALS (ENABLE) TGHSL TEHSH VCC TELQV TEHQZ * 8KB: up to P2.4, 16KB: up to P2.5, 32KB: up to P3.4, 64KB: up to P3.5 54 AT/TS8xC54/8X2 4431E-8051-04/06 AT/TS8xC54/8X2 19.5.11 External Clock Drive Characteristics (XTAL1) Table 19-15. AC Parameters Symbol Parameter TCLCL Oscillator Period TCHCX Max Units 25 ns High Time 5 ns TCLCX Low Time 5 ns TCLCH Rise Time 5 ns TCHCL Fall Time 5 ns 60 % TCHCX/TCLCX 19.5.12 Min Cyclic ratio in X2 mode 40 External Clock Drive Waveforms Figure 19-11. External Clock Drive Waveforms V CC-0.5 V 0.45 V CC CC-0.1 V 0.7V 0.2V T CHCL T CLCX T T CLCL T CHCX CLCH 55 4431E-8051-04/06 19.5.13 AC Testing Input/Output Waveforms Figure 19-12. AC Testing Input/Output Waveforms V CC-0.5 V INPUT/OUTPUT 0.45 V 0.2V CC+0.9 0.2V CC-0.1 AC inputs during testing are driven at VCC - 0.5 for a logic "1" and 0.45V for a logic "0". Timing measurement are made at VIH min for a logic "1" and VIL max for a logic "0". 19.5.14 Float Waveforms Figure 19-13. Float Waveforms FLOAT V OH-0.1 V V OL+0.1 V V LOAD V LOAD+0.1 V LOAD-0.1 V V For timing purposes a port pin is no longer floating when a 100 mV change from load voltage occurs and begins to float when a 100 mV change from the loaded VOH/VOL level occurs. IOL/IOH 20mA. 19.5.15 56 Clock Waveforms Valid in normal clock mode. In X2 mode XTAL2 signal must be changed to XTAL2 divided by two. AT/TS8xC54/8X2 4431E-8051-04/06 AT/TS8xC54/8X2 Figure 19-14. Clock Waveforms INTERNAL CLOCK STATE4 STATE5 STATE6 STATE1 STATE2 P1P2 P1P2 P1P2 P1P2 P1P2 STATE3 P1P2 STATE4 P1P2 STATE5 P1P2 XTAL2 ALE THESE SIGNALS ARE NOT ACTIVATED DURING THE EXECUTION OF A MOVX INSTRUCTION EXTERNAL PROGRAM MEMORY FETCH PSEN P0 DATA SAMPLED FLOAT PCL OUT DATA SAMPLED FLOAT PCL OUT DATA SAMPLED FLOAT PCL OUT INDICATES ADDRESS P2 (EXT) READ CYCLE RD PCL OUT (IF PROGRAM MEMORY IS EXTERNAL) P0 DPL OR Rt FLOAT INDICATES DPH OR P2 SFR TO PCH TRANSITION P2 WRITE CYCLE WR PCL OUT (EVEN IF PROGRAM MEMORY IS INTERNAL) P0 DPL OR Rt OUT DATA OUT PCL OUT (IF PROGRAM MEMORY IS EXTERNAL) INDICATES DPH OR P2 SFR TO PCH TRANSITION P2 PORT OPERATION OLD DATA P0 PINS SAMPLED NEW DATA P0 PINS SAMPLED MOV DEST P0 MOV DEST PORT (P1, P2, P3) (INCLUDES INT0, INT1, TO, T1) P1, P2, P3 PINS SAMPLED SERIAL PORT SHIFT CLOCK RXD SAMPLED P1, P2, P3 PINS SAMPLED RXD SAMPLED TXD (MODE 0) This diagram indicates when signals are clocked internally. The time it takes the signals to propagate to the pins, however, ranges from 25 to 125 ns. This propagation delay is dependent on variables such as temperature and pin loading. Propagation also varies from output to output and component. Typically though (TA=25C fully loaded) RD and WR propagation delays are approximately 50ns. The other signals are typically 85 ns. Propagation delays are incorporated in the AC specifications. 57 4431E-8051-04/06 20. Ordering Information Table 20-1. 58 Possible Ordering Entries Part Number Supply Voltage Temperature Range Package Packing TS80C54X2xxx-MCA -5 to +/-10% Commercial PDIL40 Stick TS80C54X2xxx-MCB -5 to +/-10% Commercial PLCC44 Stick TS80C54X2xxx-MCC -5 to +/-10% Commercial PQFP44 Tray TS80C54X2xxx-MCE -5 to +/-10% Commercial VQFP44 Tray TS80C54X2xxx-VCA -5 to +/-10% Commercial PDIL40 Stick TS80C54X2xxx-VCB -5 to +/-10% Commercial PLCC44 Stick TS80C54X2xxx-VCC -5 to +/-10% Commercial PQFP44 Tray TS80C54X2xxx-VCE -5 to +/-10% Commercial VQFP44 Tray TS80C54X2xxx-LCA -5 to +/-10% Commercial PDIL40 Stick TS80C54X2xxx-LCB -5 to +/-10% Commercial PLCC44 Stick TS80C54X2xxx-LCC -5 to +/-10% Commercial PQFP44 Tray TS80C54X2xxx-LCE -5 to +/-10% Commercial VQFP44 Tray TS80C54X2xxx-MIA -5 to +/-10% Industrial PDIL40 Stick TS80C54X2xxx-MIB -5 to +/-10% Industrial PLCC44 Stick TS80C54X2xxx-MIC -5 to +/-10% Industrial PQFP44 Tray TS80C54X2xxx-MIE -5 to +/-10% Industrial VQFP44 Tray TS80C54X2xxx-VIA -5 to +/-10% Industrial PDIL40 Stick TS80C54X2xxx-VIB -5 to +/-10% Industrial PLCC44 Stick TS80C54X2xxx-VIC -5 to +/-10% Industrial PQFP44 Tray TS80C54X2xxx-VIE -5 to +/-10% Industrial VQFP44 Tray TS80C54X2xxx-LIA -5 to +/-10% Industrial PDIL40 Stick TS80C54X2xxx-LIB -5 to +/-10% Industrial PLCC44 Stick TS80C54X2xxx-LIC -5 to +/-10% Industrial PQFP44 Tray TS80C54X2xxx-LIE -5 to +/-10% Industrial VQFP44 Tray AT80C54X2zzz-3CSUM -5 to +/-10% Industrial & Green PDIL40 Stick AT80C54X2zzz-SLSUM -5 to +/-10% Industrial & Green PLCC44 Stick AT80C54X2zzz-RLTUM -5 to +/-10% Industrial & Green VQFP44 Tray AT80C54X2zzz-3CSUL -5 to +/-10% Industrial & Green PDIL40 Stick AT80C54X2zzz-SLSUL -5 to +/-10% Industrial & Green PLCC44 Stick AT80C54X2zzz-RLTUL -5 to +/-10% Industrial & Green VQFP44 Tray AT80C54X2zzz-3CSUV -5 to +/-10% Industrial & Green PDIL40 Stick AT80C54X2zzz-SLSUV -5 to +/-10% Industrial & Green PLCC44 Stick AT80C54X2zzz-RLTUV -5 to +/-10% Industrial & Green VQFP44 Tray TS87C54X2-MCA 5V 10% Commercial PDIL40 Stick TS87C54X2-MCB 5V 10% Commercial PLCC44 Stick AT/TS8xC54/8X2 4431E-8051-04/06 AT/TS8xC54/8X2 Part Number Supply Voltage Temperature Range Package Packing TS87C54X2-MCC 5V 10% Commercial PQFP44 Tray TS87C54X2-MCE 5V 10% Commercial VQFP44 Tray TS87C54X2-VCA 5V 10% Commercial PDIL40 Stick TS87C54X2-VCB 5V 10% Commercial PLCC44 Stick TS87C54X2-VCC 5V 10% Commercial PQFP44 Tray TS87C54X2-VCE 5V 10% Commercial VQFP44 Tray TS87C54X2-LCA 2.7 to 5.5V Commercial PDIL40 Stick TS87C54X2-LCB 2.7 to 5.5V Commercial PLCC44 Stick TS87C54X2-LCC 2.7 to 5.5V Commercial PQFP44 Tray TS87C54X2-LCE 2.7 to 5.5V Commercial VQFP44 Tray TS87C54X2-MIA 5V 10% Industrial PDIL40 Stick TS87C54X2-MIB 5V 10% Industrial PLCC44 Stick TS87C54X2-MIC 5V 10% Industrial PQFP44 Tray TS87C54X2-MIE 5V 10% Industrial VQFP44 Tray TS87C54X2-VIA 5V 10% Industrial PDIL40 Stick TS87C54X2-VIB 5V 10% Industrial PLCC44 Stick TS87C54X2-VIC 5V 10% Industrial PQFP44 Tray TS87C54X2-VIE 5V 10% Industrial VQFP44 Tray TS87C54X2-LIA 2.7 to 5.5V Industrial PDIL40 Stick TS87C54X2-LIB 2.7 to 5.5V Industrial PLCC44 Stick TS87C54X2-LIC 2.7 to 5.5V Industrial PQFP44 Tray TS87C54X2-LIE 2.7 to 5.5V Industrial VQFP44 Tray AT87C54X2-3CSUM 5V 10% Industrial & Green PDIL40 Stick AT87C54X2-SLSUM 5V 10% Industrial & Green PLCC44 Stick AT87C54X2-RLTUM 5V 10% Industrial & Green VQFP44 Tray AT87C54X2-3CSUL 2.7 to 5.5V Industrial & Green PDIL40 Stick AT87C54X2-SLSUL 2.7 to 5.5V Industrial & Green PLCC44 Stick AT87C54X2-RLTUL 2.7 to 5.5V Industrial & Green VQFP44 Tray AT87C54X2-3CSUV 5V 10% Industrial & Green PDIL40 Stick AT87C54X2-SLSUV 5V 10% Industrial & Green PLCC44 Stick AT87C54X2-RLTUV 5V 10% Industrial & Green VQFP44 Tray 59 4431E-8051-04/06 60 Part Number Supply Voltage Temperature Range Package Packing TS80C58X2xxx-MCA -5 to +/-10% Commercial PDIL40 Stick TS80C58X2xxx-MCB -5 to +/-10% Commercial PLCC44 Stick TS80C58X2xxx-MCC -5 to +/-10% Commercial PQFP44 Tray TS80C58X2xxx-MCE -5 to +/-10% Commercial VQFP44 Tray TS80C58X2xxx-VCA -5 to +/-10% Commercial PDIL40 Stick TS80C58X2xxx-VCB -5 to +/-10% Commercial PLCC44 Stick TS80C58X2xxx-VCC -5 to +/-10% Commercial PQFP44 Tray TS80C58X2xxx-VCE -5 to +/-10% Commercial VQFP44 Tray TS80C58X2xxx-LCA -5 to +/-10% Commercial PDIL40 Stick TS80C58X2xxx-LCB -5 to +/-10% Commercial PLCC44 Stick TS80C58X2xxx-LCC -5 to +/-10% Commercial PQFP44 Tray TS80C58X2xxx-LCE -5 to +/-10% Commercial VQFP44 Tray TS80C58X2xxx-MIA -5 to +/-10% Industrial PDIL40 Stick TS80C58X2xxx-MIB -5 to +/-10% Industrial PLCC44 Stick TS80C58X2xxx-MIC -5 to +/-10% Industrial PQFP44 Tray TS80C58X2xxx-MIE -5 to +/-10% Industrial VQFP44 Tray TS80C58X2xxx-VIA -5 to +/-10% Industrial PDIL40 Stick TS80C58X2xxx-VIB -5 to +/-10% Industrial PLCC44 Stick TS80C58X2xxx-VIC -5 to +/-10% Industrial PQFP44 Tray TS80C58X2xxx-VIE -5 to +/-10% Industrial VQFP44 Tray TS80C58X2xxx-LIA -5 to +/-10% Industrial PDIL40 Stick TS80C58X2xxx-LIB -5 to +/-10% Industrial PLCC44 Stick TS80C58X2xxx-LIC -5 to +/-10% Industrial PQFP44 Tray TS80C58X2xxx-LIE -5 to +/-10% Industrial VQFP44 Tray AT80C58X2zzz-3CSUM -5 to +/-10% Industrial & Green PDIL40 Stick AT80C58X2zzz-SLSUM -5 to +/-10% Industrial & Green PLCC44 Stick AT80C58X2zzz-RLTUM -5 to +/-10% Industrial & Green VQFP44 Tray AT80C58X2zzz-3CSUL -5 to +/-10% Industrial & Green PDIL40 Stick AT80C58X2zzz-SLSUL -5 to +/-10% Industrial & Green PLCC44 Stick AT80C58X2zzz-RLTUL -5 to +/-10% Industrial & Green VQFP44 Tray AT80C58X2zzz-3CSUV -5 to +/-10% Industrial & Green PDIL40 Stick AT80C58X2zzz-SLSUV -5 to +/-10% Industrial & Green PLCC44 Stick AT80C58X2zzz-RLTUV -5 to +/-10% Industrial & Green VQFP44 Tray TS87C58X2-MCA 5V 10% Commercial PDIL40 Stick TS87C58X2-MCB 5V 10% Commercial PLCC44 Stick TS87C58X2-MCC 5V 10% Commercial PQFP44 Tray AT/TS8xC54/8X2 4431E-8051-04/06 AT/TS8xC54/8X2 Part Number Supply Voltage Temperature Range Package Packing TS87C58X2-MCE 5V 10% Commercial VQFP44 Tray TS87C58X2-VCA 5V 10% Commercial PDIL40 Stick TS87C58X2-VCB 5V 10% Commercial PLCC44 Stick TS87C58X2-VCC 5V 10% Commercial PQFP44 Tray TS87C58X2-VCE 5V 10% Commercial VQFP44 Tray TS87C58X2-LCA 2.7 to 5.5V Commercial PDIL40 Stick TS87C58X2-LCB 2.7 to 5.5V Commercial PLCC44 Stick TS87C58X2-LCC 2.7 to 5.5V Commercial PQFP44 Tray TS87C58X2-LCE 2.7 to 5.5V Commercial VQFP44 Tray TS87C58X2-MIA 5V 10% Industrial PDIL40 Stick TS87C58X2-MIB 5V 10% Industrial PLCC44 Stick TS87C58X2-MIC 5V 10% Industrial PQFP44 Tray TS87C58X2-MIE 5V 10% Industrial VQFP44 Tray TS87C58X2-VIA 5V 10% Industrial PDIL40 Stick TS87C58X2-VIB 5V 10% Industrial PLCC44 Stick TS87C58X2-VIC 5V 10% Industrial PQFP44 Tray TS87C58X2-VIE 5V 10% Industrial VQFP44 Tray TS87C58X2-LIA 2.7 to 5.5V Industrial PDIL40 Stick TS87C58X2-LIB 2.7 to 5.5V Industrial PLCC44 Stick TS87C58X2-LIC 2.7 to 5.5V Industrial PQFP44 Tray TS87C58X2-LIE 2.7 to 5.5V Industrial VQFP44 Tray AT87C58X2-3CSUM 5V 10% Industrial & Green PDIL40 Stick AT87C58X2-SLSUM 5V 10% Industrial & Green PLCC44 Stick AT87C58X2-RLTUM 5V 10% Industrial & Green VQFP44 Tray AT87C58X2-3CSUL 2.7 to 5.5V Industrial & Green PDIL40 Stick AT87C58X2-SLSUL 2.7 to 5.5V Industrial & Green PLCC44 Stick AT87C58X2-RLTUL 2.7 to 5.5V Industrial & Green VQFP44 Tray AT87C58X2-3CSUV 5V 10% Industrial & Green PDIL40 Stick AT87C58X2-SLSUV 5V 10% Industrial & Green PLCC44 Stick AT87C58X2-RLTUV 5V 10% Industrial & Green VQFP44 Tray 21. Datasheet Revision History 21.1 Changes from Rev. C 01/01 to Rev. D 11/05 1. Added green product Ordering Information. 21.2 Changes from Rev. D 11/05 to Rev. E 04/06 1. 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