PF990-02 SRM2AW416LLBT1/7 4M-bit Static RAM Super Low Voltage Operation and Low Current Consumption Access Time 100ns (1.8V) / 70ns (2.2V) 262,144 Words x 16-bit Asynchtonous Wide Temperature Range e tag Vol ow L r e n Sup eratio ts Op oduc Pr DESCRIPTION The SRM2AW416LLBT1/7 is a 262,144words x 16-bit asynchronous, random access memory on a monolithic CMOS chip. Its very low standby power requirement makes it ideat for applications requiring non-volatile syorage with back-up batteries. The asynchronous and static nature of the memory requires no external clock or refreshing circuit. It is possible to contorol the date width by the data byte control. Both the Input and output ports are TTL compatible and 3-state output allows easy expansion of memory capacity. The temperature range of the SRM2AW416LLBT1/7 is from -40 to 85C, and it is suitable for the industrial products. FEATURES Fast Access time ........................ 100ns (at 1.8V) / 70ns (at 2.2V) Low supply current ..................... LL Version Completely static ........................ No clock required Supply voltage ............................ 1.8V to 2.85V TTL compatible inputs and outputs 3-state output with wired-OR capability Non-volatile storage with back-up batteries Package ..................................... SRM2AW416LLBT TFBGA-48 pin (Tape CSP) OE WE X Decoder 1024 Memory Cell Array 1024 x 256 x 16 8 Y Decoder 256x16 256 Column Gate CS,LB,UB Control Logic CS LB UB 10 16 OE, WE Control Logic A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 Address Buffer BLOCK DIAGRAM I/O Buffer I/O1 I/O16 SRM2AW416LLBT1/7 PIN CONFIGURATION TFBGA-48 pin SRM2AW416LLBT 1 2 3 4 5 6 A LB OE A0 A1 A2 NC B I/O9 UB A3 A4 CS I/O1 C I/O10 I/O11 A5 A6 I/O2 I/O3 D VSS I/O12 A17 A7 I/O4 VDD E VDD I/O13 NC A16 I/O5 VSS F I/O15 I/O14 A14 A15 I/O6 I/O7 G I/O16 NC H NC A8 A12 A13 A9 WE I/O8 A10 A11 NC Top view (Looking through part) PIN DESCRIPTION A0 to A17 WE OE CS LB UB I/O1 to 16 VDD VSS NC 2 Address Input Write Enable Output Enable Chip Select LOWER Byte Enable UPPER Byte Enable Data I/O Power Supply (1.8V to 2.85V) Power Supply (0V) No connection SRM2AW416LLBT1/7 ABSOLUTE MAXIMUM RATINGS Parameter Supply voltage Input voltage Input/Output voltage Power dissipation Operating temperature Storage temperature Soldering temperature and time * VI,VI/O Symbol VDD VI VI/O PD Topr Tstg Tsol (Min.) = -3.0V (Pulse width is 50ns) DC RECOMMENDED OPERATING CONDITIONS Parameter Symbol VDD VSS VIH VIL Supply voltage Input voltege * if (VSS=0V) Unit V V V W C -- Ratings - 0.5 * to 3.6 - 0.5 * to VDD + 0.3 - 0.5 * to VDD + 0.3 0.5 - 40 to 85 - 65 to 150 260C, 10s (at lead) (Ta = -40 to 85 C) VDD = 2.2 to 2.85V Unit Max. Min. Typ. 2.85 2.2 2.5 V 0.0 0.0 0.0 V VDD+0.3 2.0 - V - 0.3 * - 0.3 V VDD = 1.8 to 2.2V Max. Min. Typ. 2.2 1.8 2.0 0.0 0.0 0.0 VDD+0.3 0.8VDD - - 0.3 - 0.3* pulse width is less than 50ns it is - 3.0V ELECTRICAL CHARACTERISTICS DC Electrical Characteristics Parameter Symbol (VSS =0V, Ta = -40 to 85 C) Conditions Input leakage current ILI VI = 0 to VDD Output leakage current ILO LB and UB = VIH or CS = VIH or WE = VIL or OE = VIH, VI/O = 0 to VDD High level output voltage VOH IOH Low level output voltage VOL IOL IDDS -0.5mA,VDD 2.2V -100A 0.5mA,VDD 2.2V 100A CS = VIH Standby supply current CS VDD - 0.2V IDDS1 IDDA Average operating current IDDA1 Operating Supply Current IDDO -40 to 85 C -40 to 70 C LL -40 to 40 C 25 C VI = VIL or VIH II/O = 0mA, tcyc = Min. VI = VIL or VIH II/O = 0mA, tcyc = 1s VI = VIL or VIH II/O = 0mA VDD = 2.2 to 2.85V VDD = 1.8 to 2.2V Min. Typ. *1 Max. Min. Typ.*2 Max. Unit - 1.0 -1.0 - 1.0 A -1.0 -1.0 - 1.0 - VDD-0.2 - - - - - - - -1.0 A - 1.0 1.8 - - VDD-0.2 - - 0.2 - - - - - - - 0.4 0.2 - 0.8 - - 1.0 mA - - - - - - - 0.15 30 20 6.0 0.6 - - - - - - - 0.2 40 27 8.0 0.8 A - 20 35 - 35 45 mA - 2.5 4 - 3 5 mA - 2.5 4 - 3 5 mA V V *1 : Typical values are measured at Ta = 25C and VDD = 2.0V *2 : Typical values are measured at Ta = 25C and VDD = 2.5V Terminal Capacitance Parameter Address Capacitance Input Capacitance I/O Capacitance (Ta = 25C, f = 1MHz) Symbol Conditions Min. CADD CI CI/O VI = 0V VI = 0V VI/O = 0V - - - Typ. - - - Max. Unit 8 8 10 pF pF pF Note : This parameter is made by the inspection data of sample, not of all products 3 SRM2AW416LLBT1/7 AC Electrical Characteristics Read Cycle (VSS = 0V, Ta = -40 to 85C) SRM2AW416LLBT1 Parameter Symbol Conditions SRM2AW416LLBT7 1.8 to 2.2V Min. Unit 2.2 to 2.85V Max. Min. Max. Read cycle time tRC 1 100 - 70 - ns Address access time tACC 1 - 100 - 70 ns CS access time tACS 1 - 100 - 70 ns OE access time tOE 1 - 60 - 40 ns LB, UB access time tAB 1 - 60 - 40 ns CS output set time tCLZ 2 10 - 5 - ns CS output floating tCHZ 2 - 40 - 30 ns LB, UB output set time tBLZ 2 5 - 0 - ns LB, UB output floating tBHZ 2 - 40 - 30 ns OE output set time tOLZ 2 5 - 0 - ns OE output floating tOHZ 2 - - tOH 1 10 30 - ns Output hold time 40 - 10 Write Cycle (VSS = 0V, Ta = -40 to 85C) Parameter Symbol Conditions SRM2AW416LLTT1 1.8 to 2.2V SRM2AW416LLBT7 2.2 to 2.85V Max. - Min. 70 Max. - ns Unit Write cycle time tWC 1 Min. 100 Chip select time (CS) tCW 1 85 - 60 - ns Address enable time tAW 1 85 - 60 - ns Address setup time tAS 1 0 - 0 - ns Write pulse width tWP 1 80 - 55 - ns LB, UB select time tBW 1 85 - 60 - ns Address hold time tWR 1 0 - 0 - ns Data setup time tDW 1 50 - 35 - ns Data hold time tDH 1 0 - 0 - ns WE output floating tWHZ 2 - - tOW 2 5 30 - ns WE output set time 40 - 5 ns *2 Test Conditions *1 Test Conditions 1. Input pulse level : 0.3V to 2.2V (2.2V to 2.85V) 1. Input pulse level : 0.3V to 0.8VDD (1.8V to 2.2V) 2. tr = tf = 5ns 0.3V to 2.2V (2.2V to 2.85V) 0.3V to 0.8VDD (1.8V to 2.2V) 2. tr = tf = 5ns 3. Input and output timing reference levels :1.1V (2.2V to 2.85V) 3. Input timing reference levels :1.1V (2.2V to 2.85V) :1/2VDD (1.8V to 2.2V) 4. Output load : CL =50pF (Includes Jig Capacitance) :1/2VDD (1.8V to 2.2V) 4. Output timing reference levels : 200mV (the level displaced from stable output voltage level) 1TTL 5. Output load :CL = 5pF (Includes Jig Capacitance) I/O 1TTL CL I/O CL 4 ns SRM2AW416LLBT1/7 Timing Chart Read Cycle*1 Write Cycle 1 (CS Control) *2, *3 tWC tRC A0 to 16 A0 to 16 tACC tAS tOH tACS CS tCLZ tAB LB, UB tBLZ OE tOE tOLZ I/O1 to 16 (Dout) tCHZ LB, UB tBHZ WE tOHZ I/O1 to 16 (Dout) tWR tCW tWHZ tDW tDH (Din) Write Cycle 2 (WE Control) *3 Write Cycle 3 (UB, LB Control)*3 tWC tWC A0 to 16 A0 to 16 tCW CS CS LB, UB tWR LB, UB tAS tWP tWR WE tWHZ I/O1 to 16 (Dout) tBW tAS tBW I/O1 to 16 (Dout) tOW tDW tWP WE tDH (Din) Note : tAW CS tDW tDH (Din) *1 During read cycle time, WE is to be "High" level. In write cycle time that is controlled by CS, output buffer is to be "Hi-Z" state if OE is "Low" level. *3 When output buffer is in output state, be careful that do not input the opposite signals to the output data. *2 DATA RETENTION CHARACTERISTIC WITH LOW VOLTAGE POWER SUPPLY (for just 3.0V operation) (VSS = 0V, Ta = -40 to 85C) Parameter Symbol Data retention supply voltage VDDR IDDR Data retention curren Data hold time Operation recovery time Conditions -40 to 85C -40 to 70C VDDR = 2.5V, CS VDD - 0.2V LL -40 to 40C +25C tCDR tR Min. 1.5 - - - - Typ. - - - - 0.2 Max. 2.85 35 24 7.0 0.7 Unit V 0 5 - - - - ns ms A Data retention timing (CS Control) VDD 1.8V tCDR VDDR 1.5V Data hold time 1.8V tR CS VDD - 0.2V CS 0.8xVDD VIL 0.8xVDD VIL 5 SRM2AW416LLBT1/7 FUNCTIONS Truth Table CS H L L L L L L L L LB X H L H L L H L X UB X H H L L H L L X OE X X X X X L L L H WE X X L L L H H H H I/O1 to 8 High-Z High-Z Data In High-Z Data In DataOut High-Z Data Out High-Z I/O9 to 16 High-Z High-Z High-Z Data In Data In High-Z DataOut Data Out High-Z MODE Not Selected Output disable Lower Byte Write Upper Byte Write All Byte Write Lower Byte Read Upper Byte Read All Byte Read Output disable IDD IDDS, IDDS1 IDDA, IDDA1 IDDA, IDDA1 IDDA, IDDA1 IDDA, IDDA1 IDDA, IDDA1 IDDA, IDDA1 IDDA, IDDA1 IDDA, IDDA1 X : High or Low Reading data It is possible to control the data width by LB and UB pins. (1) Reading data from lower byte Data is able to be read when the address is set while holding CS ="Low", OE= "Low", LB ="Low" and WE = "High". (2) Reading data from upper byte Data is able to be read when the address is set while holding CS = "Low", OE = "Low", UB = "Low" and WE ="High". (3) Reading data from both bytes Data is able to be read when the address is set while holding CS = "Low", OE ="Low", UB ="Low", LB = "Low", and WE = "High" Since I/O pins are in "Hi-Z" state when OE = "High", the data bus line can be used for any other objective, then access time apparently is able to be cut down. Writing data (1) Writing data into lower byte There are the following three ways of writing data into memory. i) Hold WE = "Low", UB = "High" and LB = "Low", set address and give "Low" pulse to CS. ii) Hold CS = "Low", UB = "High" and LB = "Low", set address and give "Low" pulse to WE. iii) Set address and give "Low" pulse to CS, UB = "High" and "Low" pulse to WE, LB. Anyway, data on I/O pins are latched up into the memory cell during CS ="Low", WE ="Low", and LB = "Low". (2) Writing data into upper byre There are the following three ways of writing data into the memory. i) Hold WE = "Low", LB = "High" and UB = "Low", set address and give "Low" pulse to CS. ii) Hold CS = "Low", LB = "High" and UB = "Low", set address and give "Low" pulse to WE. iii) Set address and give "Low" pulse to CS, LB = "High" and "Low" pulse to WE, UB. Anyway, data on I/O pins are latched up into the memory cell during CS = "Low", WE = "Low", and UB = "Low". (3)Writing data into both bytes There are the following three ways of writing data into the memory. i) Hold WE = "Low", LB and UB = "Low", set address and give "Low" pulse to CS. ii) Hold CS = "Low", LB and UB = "Low", set address and give "Low" pulse to WE. iii) Set address give "Low" pulse to both pins of LB and UB, "Low" pulse to CS and "Low" pulse to WE. 6 SRM2AW416LLBT1/7 Anyway, data on I/O pins are latched up into the memory cell during CS = "Low" , WE = "Low", UB and LB = "Low". As DATA I/O pins are in "Hi-Z" when any of CS is "High", OE or LB, UB are "High" level, the contention on the data bus can be avoided. But during I/O pins are in the output state, the data that is opposite to the output data should not be given. Standby mode When CS "High" or LB, UB = "High" level. the chip is in the standby mode which has rataining data operation. In this case data I/O pins are Hi-Z, and all inputs of addresses, WE, OE and all input data are inhibited. When CS, LB and UB level are in the range over VDD-0.2V, there is almost no current flow except through the high resistance parts of the memory. Data retention at low voltage In case of the data retention in the stadby mode, the power supply can be gone down till the specified voltage. But it is impossible to write or read in this mode. 7 SRM2AW416LLBT1/7 PACKAGE DIMENSIONS TFBGA-48 pin BOTTOM VIEW 6 5 4 3 2 1 A 0.75 Typ. C D E F 8.0 0.2 B G H 0.350.05 0.75 Typ. 1.0 Max. 10.0 0.2 SIDE VIEW TOP VIEW 1 2 3 4 5 6 A B INDEX C D E F G H SRAM Die Base Tape Unit : mm 8 SRM2AW416LLBT1/7 CHARACTERISTICS CURVES t n e m e ur s a e M r e d n U 9 SRM2AW416LLBT1/7 NOTICE: No part of this material may be reproduced or duplicated in any form or by any means without the written permission of Seiko Epson. Seiko Epson reserves the right to make changes to this material without notice. Seiko Epson does not assume any liability of any kind arising out of any inaccuracies contained in this material or due to its application or use in any product or circuit and, further, there is no representation that this material is applicable to products requiring high level reliability, such as, medical products. Moreover, no license to any intellectual property rights is granted by implication or otherwise, and there is no representation or warranty that anything made in accordance with this material will be free from any patent or copyright infringement of a third party. This material or portions thereof may contain technology or the subject relating to strategic products under the control of the Foreign Exchange and Foreign Trade Control Law of Japan and may require an export license from the Ministry of International Trade and Industry or other approval from another government agency. (c) Seiko Epson Corporation 1999 All right reserved. ELECTRONIC DEVICES MARKETING DIVISION IC Marketing & Engineering Group ED International Marketing Department I (Europe & U.S.A.) 421-8, Hino, Hino-shi, Tokyo 191-8501, JAPAN Phone : 042-587-5812 FAX : 042-587-5564 ED International Marketing Department II (Asia) 421-8, Hino, Hino-shi, Tokyo 191-8501, JAPAN Phone : 042-587-5814 FAX : 042-587-5110