DIC) ILC DATA DEVICE CORPORATION? BU-65170/61580 and BU-61585 MIL-STD-1553A/B NOTICE 2 RT and BC/RT/MT, ADVANCED COMMUNICATION ENGINE (ACE) ACE Users Guide Also Available FEATURES DESCRIPTION DDCs BU-65170, BU-61580 and BU-61585 BC/RT/MT Advanced Com- munication Engine (ACE) terminal comprises a complete integrated interface between a host processor and a MIL-STD- 1553 A and B or STANAG 3838 bus. The ACE series is packaged in a 1.9 square inch 70-pin, low-profile, cofired MCM ceramic package that is well suited for applications with stringent height requirements. The BU-61585 ACE integrates dual transceiver, protocol, memory man- agement, processor interface logic, and a total of 12K words of RAM in a choice of DIP or flat pack packages. The BU-61585 requires +5 V power and either -15 V or -12 V power. The BU-61585 internal RAM can be configured as 12K x 16 or 8K x 17. The 8K x17 RAM feature provides capability for memory integrity checking by implementing RAM parity genera- tion and verification on all accesses. To minimize board space and glue logic, the ACE provides ultimate flexibility in interfacing to a host processor and internal/external RAM. The advanced functional architecture of the ACE terminals provides soft- ware compatibility to DDCs AIM series hybrids, while incorporating a multiplicity of architectural enhance- ments. It allows flexible operation while off-loading the host processor, ensuring data sample consistency, and supporting buik data transfers. The ACE hybrids may be operated at either 12 or 16 MHz. Wire bond op- tions allow for programmable RT address (hardwired is standard) and external transmitter inhibit inputs. Fully Integrated Bus Interface Terminal @ Flexible Processor/Memory Interface Standard 4K x 16 RAM and Optional 12K x 16 or 8K x 17 RAM Available Optional RAM Parity Generation/Checking Automatic BC Retries Programmable BC Gap Times @ BC Frame Auto-Repeat Flexible RT Data Buffering Programmable Iilegalization Selective Message Monitor @ Simultaneous RT/Monitor Mode i t SHARED * ' XARA RAM 1 1 t ' RANSCE:VER |, cH A n ~2 1 PROCESSOR OATA BUS BUereRS DATA BUS DUAL THR A ENCOOERMDECQDER : ' MULTIPROTOCOL i : BC/RT/MONITOR ' 1 PROTOCOL t ' "AND. ' ? MEMORY, ' ~<eRX 8 MANAGEMENT iA iM PROCESSOR < ADDRESS BUS > bones AODRESS BUS t + ' cu | RANSCE VER |,__ gl + i" 1 ' ' 1 , ' AT ACDAESS: INC MO MSCE_ANEOUS Cum IN TAG_CL. SF RTADSATADO RTADP PROCESSOR ANI MEMORY ' INTERFACE LOGIC. t + 1OEN, MEMENA-OUT, READYD: iNT 1 ____ 1 TRANSPARENT/QUFFERED, STABD, SELECT. 'RDAVA, MEMAEG, TRIGGER _SELIMEMENA.N, SBA SEVOTGAT PROCESSOR AND MEMORY CONTROL {ADOR_LATIMEMOE, ZERO_WAITMEMWA, 118/16-BiT;OTAEQ, POLARITY SEL/OTACK . INTERAUPT REQUEST i+ SEE ORDERING INFORMATION FOR AVAILABLE MEMORY FIGURE 1. ACE BLOCK DIAGRAM ViI-51BOG ILC DATA DEVICE BU-65170/61580 and BU-61585 CORPORATION. . - CATI " PARAMETER MIN | TYP | MAX [UNITS PARAMETER MIN | TYP | MAX [UNITS ABSOLUTE MAXIMUM RATINGS mINCMD, INT, MEMENA_OUT, 3.2 mA Supply Voltage READYD, IOEN, 8D16-BDo, mw Logic +5V 0.3 7.0 Vv BA15-BAO, TXA, TXA , TXB, TXB, m Transceiver +5V -0.3 7.0 v TX_INH_OUT_A, TX_INH_OUT_B, w-15V -18.0 0.3 v CLOCK _OUT, LATCH BRO, M a-12V 18.0 0.3 v RT_FAIL, HS FAIL, TX DTA STR, Logic RX_DTA_STR, SOM, BR_CS a in 0.3 10.3] V BR_OE, BR WR, BC_FRAME, RECEIVER low SMN_ACTIVE Differential Input Resistance # (BU-65170/61580/61585x1, 1 K ohm # OBE BETS, AO ATS. 6.4 | mA BU-65170/61580/61585X2) MEMWRUZEROWAIT : (Notes 1-7) DTREQ/6/8, # (BU-65170/61580/61585X3, 25 Kohm DTACK/POLARITY SEL (Note ye UetSBExS) mINGMD, INT, MEMENA OUT, 3.2 | mA Differential Input Capacitance READ YD, IOEN, BD16_BD0___ , BA15-BAO, TXA, TXA, TXB, TXB, @ (BU-65170/61580/61585xX1, 10 pF TX_INH_ OUT A OUT A TX IN INH OUT B BU-65170/61580/61586X2) CLOCK OUT. LATCH BRO. ME Cl ME, (Notes 1-7) RT_FAIL, HS FAIL, TX DTA STR, (BU-65170/61580/61585X3, 5 pF AX DTA STR SOM. BR CS Nea ee BR OE, BR WA, BC FRAME, - SMM_FR, SMM_ACTIVE Threshold Voltage, Transformer 0.200 0.860 | Ve-p CI (Input Capacitance) 50 pt Coupled, Measured on Stub Clo (Bi-directional signal input 50 pt M 7) 10 Voeak capacitance) TRANSMITTER POWER SUPPLY REQUIREMENTS Differential Output Voltage Voltages/Tolerances wg Direct Coupled Across 35 ohms, 6 7 9 Ve.p @ BU-65170/61580/61585X1 Measured on Bus +5 V (Logic) 45/50] 55 Vv = Transformer Coupled Across 70 * +5 V (CH. A, CH. B} 45 | 50 55 Vv ohms . A, CH. . : 5. -15V |. |. -15.75} -15.0 | -14.2: Vv * BU-65170/61580/61585S1 20 | 22 | 27 | Vee e AU eS wei etoniElsxe 18.75) -15.0| -14.25 BU-65170/61580/61585V1 18 21 27 Vp-p 45 V (Logic) 45 ) 5.0 65 Vy * BU-65170/61580/61585X2 18 | 21 | 27 | Vpp +5 V (CH. A, CH. B) 45 | 5.0] 65 v BU-65170/61580/61585X3, o-12V (CH. A CH. B) 4126 12.0 11.4 Vv BU-65170/61580/61585X6 18 | 21 | 27 | Vee BU-65170/61580/61585X3, Differential Output Noise (Direct 10 mv BU-65170/61580/61585X6 Coupled) P-P. diff * +5 V (Logic) 45/50] $5 v Output Offset Voltage, Transformer -250 250 |mVpeak 0 +5 V (Cr A. HP) 4.75 | 5.0 | 5.25 v led A 70 ohms Current Drain (Total Hybrid) Seaaiae Time m @ BU-65170/61580X1 @ BU-65170/61580/61585X1, 100 | 150 | 300 | nsec e +5 V (Logic, CH.A, CH.B) 95 190 mA BU-65170/61580/61585X2, * wv, iM (CH. A, CH. B) 30 | 60 | mA BU-65170/61580/61585X3, BU-65170/61580/61585X6 25% Transmitter Duty Cycle 68 108 mA LOGIC 50% Transmitter Duty Cycle 105 | 160 mA Vin 2.0 v * 100% Transmitter Duty Cycle 180 | 255 mA Vit 0.8 v m BU-65170/61580X2 ti (Voc=5.5 V, ViN=Vcc) -10 10 pA e +5 V (Logic, CH. A, CH. B) 95 190 mA tH (Voc=5.5 V, VIN=2.7 V) * -12 V (CH. A, CH. B) ; mSSFLAG*/EXT_TRIG -692 -84 HA Idle ; 30 60 mA @AIl other inputs -346 -42 BA * 25% Transmitter Duty Cycle 80 120 mA ln. (Voc=5.5 V, Vin=0.4 V) * 50% Transmitter Duty Cycle 130 | 185 mA | @ SSFLAG*/EXT_TRIG -794 -100 pA 100% Transmitter Duty Cycle 230 | 30S mA | @ All other inputs -397 -50 pA w BU-65170/61580X3; VoH (Voc=4.5 V, Vin=2.7 V, ViL=0.2 24 v ey ego CHA CH.8) * . A, . v Oot sv Vine=2.7 V, Vits0.2 V 04] Vv * Idle 95 ) 200 | mA OL WWEC=S.9 Vs VIE 1M IL=0.2 Vi . 25% Transmitter Duty Cycle 245 | 350 mA jot=max) * 50% Transmitter Duty Cycle 360 | 500 | mA OL. 100% Ti itter Duty Cycl 590 | 800 | mA DBO-DBI15, AO-AI5, 6.4 mA * 100% Transmitter Duty Cycle MEMOE/ADDR_LAT, MEMWR/ZEROWAIT, DTREQ/16/8, DTACK/POLARITY_SEL VII-52OOe ILC DATA DEVICE BU-65170/61580 and BU-61585 CORPORATIONS ACE IFICATIONS TABLE 1, ACE SERIES SPECIFICATIONS PARAMETER MIN _| TYP | MAX [UNITS PARAMETER MIN | TYP | MAX [UNITS mBU-61585X1 mBU-61585xX1 +5 V (Logic, CH.A, CH.B) 105 ; 240 mA Idle 0.335) 0.68 Ww -15 V (CH. A, CH. B) 25% Duty Cycle 0.600] 1.06 Ww Idle 30 | 60 | mA 50% Duty Cycle 0.860] 1.45 | W 25% Transmitter Duty Cycle 68 108 mA * 100% Duty Cycle 1.385) 2.23 Ww * 50% Transmitter Duty Cycle 105 | 160 mA i BU-61585X2 * 100% Transmitter Duty Cycle 180 | 255 mA Idle 0.290] 0.59 Ww w BU-61585X2 25% Duty Cycle 0.590) 0.92 Ww * +5 V (Logic, CH.A, CH.B) 405] 240 | mA * 50% Duty Cycle 0.890] 1.36 | W -12 V (CH. A, CH. B) 100% Duty Cycle 1.490) 2.16 Ww Idle 30 60 mA m BU-61585X3, 25% Transmitter Duty Cycle 80 | 120 | mA BU-61585X6 50% Transmitter Duty Cycle 130 | 185 | mA e Idle 0.200] 0.25 WwW * 100% Transmitter Duty Cycle 230 | 305 mA 25% Duty Cycle 0.630] (.68 WwW @BU-61585X3, 50% Duty Cycle 0.885| 1.11 | W BU-61585X6 100% Duty Cycle 1.395] 1.97 | Ww +5 V (Logic, GH.A, CH.B) CLOCK INPUT Idle 105 | 250 mA Frequency 25% Transmitter Duty Cycle 255 | 400 mA Nominal Value (programmable) 50% Transmitter Duty Cycle 370 | 550 mA Default Mode 16.0 MHz . itter i 600 | 850 mA * Software Programmable Option 12.0 MHz POWER DISSIPATION w Long Term Tolerance Total Hybrid 1553A Mode 0.01 % @ BU-65170/61580X1 1553B Mode ot % Idle 0.850] 1.85 w Short Term Tolerance, 1 second 25% Duty Cycle 1.195] 2.25 Ww e 1553A Mode 0.001 % 50% Duty Cycle 1.450] 2.72 Ww 1553B Mode 0.01 % * 100% Duty Cycle 1.975] 352 | W w Duty Cycle @ BU-65170/61580X2 16MHz 33 67 % * Idie 0,835) 1.67 Ww 12MHz 40 60 % * 25% Duty Cycle 1.135] 2.10 Ww 1553 MESSAGE TIMING 50% Duty Cycle 1.435| 2.59 Ww Completion of CPU Write (BC Start)-to- 2.5 Bs * 100% Duty Cycle 2.035| 3.46 | W Start of First BC Message @ BU-65170/61580X3, BC Intermessage Gap(Note 8) 9.5 us BU-65170/61580X6 BC/RT/MT Response Timeout(Note 9) Idle 0.475) 1.00 | W m 18.5 nominal 175 |185| 195 | ps * 25% Duty Cycle 0.905) 1.43 | W = 22.5 nominal 215/225! 23.5 | us * 50% Duty Cycle 1.160) 1.86 | W 50.5 nominal 49.5 |50.5) 51.5 | ps * 100% Duty Cycle 1.670) 2.72 | W @ 128.0 nominal 127 |129.5| 131 qs @ BU-61585xX1 RT Response Timeout (Note 11} 4 7 us * dle 9.900) 2.10 ) W |_Transmitter Watchdog Timeout _ 668 us * 25% Duty Cycle 1.245] 2.50 Ww THERMAL . 50% Duty cycle 1.500] 2.97 | W Thermal Resistance, Junction-to-Case, . BU eieeee ycle 2.025) 3.77 Ww Hottest Die (ac) m BU-65170/61580/61585X1, 6.99 | C/W * Idle 0.885) 1.92 | W BU-65170/61580/61585X2 * 25% Duty Cycle 1.185) 2.35 | W m BU-65170/61580/61585X3, 6a | CW * 50% Duty Cycle 1.485) 2.84 | W BU-65170/61580/61585X6 * 100% Duty Cycle 2.085] 3.71 | W Operating Junction Temperature -55 150) C s Bue oeexe Storage Temperature -65 150 C * Idle 0.525] 1.25 W ead Temperature (soldering, +300 Cc * 25% Duty Cycle 0.955| 1.68 | W |_10 seconds), + 50% Duty Cycle 1240] 2.11 Ww PHYSICAL CHARACTERISTICS Hottest oe Duy Cycle 1-720) 2.97 | W m BU-65170/61580/61585 S 19X1.0X0165 | in mBU-65170/61580X1 (48.26 X 25.4 X 4.19), (mm) @ BU-65170/61580/61585 V 1.9 X 1.0 X 0.150 in * Idle 0.335] 0.68 | W 48.26 X 25.4 X 3.81)| (mm * 25% Duty Cycle 0.600} 1.06 | W Weight (48. 4X3. ) * 50% Duty Cycle 0.860] 1.45 WwW |S t00% Doty Cycle ves] 223 | W @ BU-65170/61580/61585 S/V 08 oz | m BU-65470/61580X2 2 { e i . ieee Duty Cycle oe00 Dee w Notes: Notes 1 through 6 are applicable ta the Receiver Differential Resis- * 50% Duty Cycle 0.390] 1.36 | W tance and Differential Capacitance specifications: | * 100% Duty Cycle 1.490] 2.16 Ww (1) Specifications include both transmitter and receiver (tied together @ BU-65170/61580X3, internally). ; . / BU-65170/61580X6 (2) Measurement of impedance is directly between pins TX/RX A(B) and | * idle 0200] 025 | w TX/RX A(B) of the BU-65170/61580XX hybrid. | * 25% Duty Cycle 0.630 0.68 Ww (3) pssuring we connection oa power ane ground aed ro the nypne 50% Duty Cycle 0.885| 1.11 Ww (4) The specifications are applicable for both unpowered and powere' 100% 1395! 1,97 W conditions. Notes continued on next page. ViI-53[p10] C) ILC DATA DEVICE CORPORATIONS (5) The specifications assume a 2 volt rms balanced, differential, sinusoidal input. The applicable frequency range is 75 kHz to 1 MHz. (6) Minimum resistance and maximum capacitance parameters are guaranteed,but not tested, over the operating range. (7) Assumes a common mode voltage within the frequency range of dc to 2MHz, applied to pins of the isolation transformer on the stub side (either direct or transformer coupled), referenced to hybrid ground. Use a DDC recommended transformer or other transformer that provides an equivalent minimum CMRR. (8) Typical vaiue for minimum interressage gap time. Under software control, may be lengthened to (65,535us minus message time), in increments of tps. (8) Software programmable (4 options). includes RT-to-RT Timeout (Mid-Parity of Transmit Comrnand to Mid-Sync of Transmitting RT Status). (10) For both +5V logic and transceiver. +5V for channels A and B. (11) Measured from mid-parity crossing of Command Word to mid-sync crossing of RT's Status Word. (12) Specifications for BU-65171, BU-61581, and BU-61586 are identical to the specifications for the BU-65170, BU-61580, and BU-61585 respectively. INTRODUCTION DDC's ACE series of Integrated BC/RT/MT hybrids provide a complete, flexible interface between a microprocessor and a MIL-STD-1553A, B Notice 2, McAir, or STANAG 3838 bus, implementing Bus Controller, Remote Terminal (RT) and Monitor Terminal (MT) modes. Packaged in a single 1.9 square inch 70-pin DIP or surface mountable flatpack or J-lead package, the ACE series contains dual low-power transceivers and en- coder/decoders, complete BC/AT/MT multi-protocol logic, mem- ory management and interrupt logic, 4K x 16 of shared static RAM and a direct, buffered interface to a host processor bus. The BU-65170/61580 contains internal address latches and bidi- rectional data buffers to provide a direct interface to a host processor bus. The BU-65170/61580 may be interfaced directly to both 16-bit and 8-bit microprocessors in a buffered shared RAM configuration. In addition, the ACE may connect to a 16-bit processor bus via a Direct Memory Access (DMA) interface. The BU-65170/61580 includes 4K words of buffered RAM. Alterna- tively, the ACE may be interfaced to as much as 64K words of external RAM in either the shared RAM or DMA configurations. The ACE RT mode is multiprotocol, supporting MIL-STD-1553A, MIL-STD-1553B Notice 2, STANAG 3838 (including EFAbus), and the McAir A3818, A5232, and A5690 protocols. Full compli- ance to the McAir specs, however, requires the use of a sinusoi- dal transceiver (transceiver option 5). Refer to the BU-61590 data sheet for additional information on McAir terminals. The memory management scheme for RT mode provides an option for separation of broadcast data, in compliance with 1553B Notice 2. Both double buffer and circular buffer options are programmable by subaddress. These features serve to en- sure data consistency and to off-load the host processor for bulk data transfer applications. The ACE series implements three monitor modes: a word monitor, a selective message monitor, and a combined RT/selective monitor. Other features include options for automatic retries and program- BU-65170/61580 and BU-61585 mable intermessage gap for BC mode, an internal Time Tag Register, an Interrupt Status Register and internal command illegatization for RT mode. FUNCTIONAL OVERVIEW TRANSCEIVERS The transceivers in the BU-65170/61580X3(X6) are fully mono- lithic, requiring only a +5 volt power input. Besides eliminating the need for an additional power supply, the use of a 5 volt (only) transceiver requires the use of step-up, rather than step-down, isolation transformers. This provides the advantage of a higher terminal input impedance than is possible for a 15 volt or 12 volt transmitter. As a result, there is greater margin for the input impedance test, mandated for 1553 validation testing. This al- lows for longer cable lengths between an LRUs system connec- tor and the isolation transformers of an embedded 1553 terminal. For the +5 V and -15 V/-12 V front end, the BU-65170/61580X1(X2) uses low-power bipolar analog monolithic and thick-film hybrid tech- nology. The transceiver requires +5 V and -15 V (-12 V) only {requiring no +15 V/+12 V) and includes voltage source transmit- ters. The voltage source transmitters provide superior line driving capability for long cables and heavy amounts of bus loading. In addition, the monolithic transceivers in the BU-65170/61580X1 provide a minimum stub voltage level of 20 volts peak-to-peak transformer coupled, making them suitable for MIL-STD-1760 applications. The receiver sections of the BU-65170/61580 are fully compliant with MIL-STD-1553B in terms of front end overvoltage protection, threshold, common mode rejection, and word error rate. In addi- tion, the receiver filters have been designed for optimal operation with the J chip's Manchester Il decoders. J DIGITAL MONOLITHIC The J digital monolithic represents the cornerstone element of the ACE family of terminals. The development of the J chip represented the fifth generation of 1553 protocol and interface design for DDC. Over the years, DDC's 1553 protocol and interface design has evolved from: (1) discrete component sets, consisting of multiple hybrids (with large numbers of chips inside the individual hybrids) and programmable logic devices, to (2) multiple custom ASICs to perform the functions of encoder/de- coder and RT protocol within a single hybrid, to (3) the BUS- 61553 Advanced Integrated Mux Hybrid (AIM-HY) series, containing, in addition to a dual monolithic/thick-film transceiver and discrete RAM chips, a custom protocol chip and a separate custom memory management/processor interface chip, to (4) the BUS-61559 Advanced Integrated Mux Hybrids with Enhanced RT Features (AIM-HYer the AIM-HYer series includes mem- ory management and processor interface functions beyond those of the AIM-HY series) , to (5) the full integration of the J chip.BOC ILC DATA DEVICE CORPORATION: The J chip consists of a dual encoder/decoder, complete proto- col for Bus Controller (BC), 1553A/B/McAir Remote Terminal (RT), and Monitor (MT) modes; memory management and inter- rupt logic; a flexibie, buffered interface to a host processor bus and optional external RAM; and 4K words of on-chip RAM. Reference the region within the dotted line of FIGURE 1. Besides realizing all the protocol, memory management, and interface functions of the earlier AIM-HYer series, the J chip includes a large number of enhancements to facilitate hardware and soft- ware design, and to further off-load the 1553 terminals host processor. DECODERS The default mode of operation for the BU-65170 RT and BU- 61580 BC/RT/MT requires a 16 MHz clock input. If needed, a software programmable option allows the device to be operated from a 12 MHz clock input. Most current 1553 decoders sample using a 10 MHz or 12 MHz clock. in the 16 MHz mode (default following a hardware or software reset), the ACE decoders sam- ple 1553 serial data using the 16 MHz clock. In the 12 MHz mode (or 16 MHz mode), the decoders sample using both clock edges; this provides a sampling rate of 24 MHz (or 32 MHz). The faster sampling rate for the J-primes Manchester lf decoders provides superior performance in terms of bit error rate and zero-crossing distortion tolerance. For interfacing to fiber optic transceivers for MIL-STD-1773 appli- cations, a transceiverless version of the J chip, the BU-65620, can be used. These versions provide a pin programmable option for a direct interface to the single-ended outputs of a fiber optic receiver. No external logic is needed. TIME TAGGING The ACE includes an internal read/writable Time Tag Register. This register is a CPU read/writable 16-bit counter with a pro- grammable resolution of either 2, 4, 8, 16, 32, or 64 us per LSB. Also, the Time Tag Register may be clocked from an external oscillator. Another option allows software controlled increment- ing of the Time Tag Register. This supports self-test for the Time Tag Register. For each message processed, the value of the Time Tag register is loaded into the second location of the respective descriptor stack entry (TIME TAG WORD) for both BC and RT modes. Additional provided options will: clear the Time Tag Register fallowing a Synchronize (without data} mode command or load the Time Tag Register following a Synchronize (with data) mode command; enable an interrupt request and a bit setting in the Interrupt Status Register when the Time Tag Register rolls over from FFFF to 0000. Assuming the Time Tag Register is not loaded or reset, this will occur at approximately 4-second time intervals, for 64 us/LSB resolution, down to 131 ms intervals, for 2 us/LSB resolution. Another programmable option for RT mode is the automatic clearing of the Service Request Status Word bit following the ACEs response to a Transmit Vector Word mode command. BU-65170/61580 and BU-61585 INTERRUPTS The ACE series components provide many programmable op- tions for interrupt generation and handling. The interrupt output pin (INT) has three software programmable modes of operation: a pulse, a level output cleared under software control, or a tevel output automatically cleared following a read of the Interrupt Status Register. Individual interrupts are enabled by the Interrupt Mask Register. The host processor may easily determine the cause of the inter- rupt by using the Interrupt Status Register. The Interrupt Status Register provides the current state of the interrupt conditions. The Interrupt Status Register may be updated in two ways. In the standard interrupt handling mode, a particular bit in the Interrupt Status Register will be updated only if the condition exists and the corresponding bit in the Interrupt Mask Register is enabled. In the enhanced interrupt handling mode, a particular bit in the Interrupt Status Register will be updated if the condition exists regardless of the contents of the corresponding Interrupt Mask Register bit. in any case, the respective Interrupt Mask Register bit enables an interrupt for a particular condition. ADDRESSING, INTERNAL REGISTERS, AND MEMORY MANAGEMENT The software interface of the BU-65170/61580 to the host proces- sor consists of 17 internal operational registers for normal opera- tion, an additional 8 test registers, plus 64K x 16 of shared memory address space. The BU-65170/61580's 4K x 16 of inter- nal RAM resides in this address space. Reference TABLE 2 and FIGURES 2-23. Definition of the address mapping and accessibility for the ACEs 17 non-test registers, and the test registers, is as follows:. Interrupt Mask Register is used to enable and disable interrupt requests for various conditions. Configuration Registers #1 and #2 are used to select the BU- 61580s mode of operation, and for software control of RT Status Word bits, Active Memory Area, BC Stop-on-Error, RT Memory Management mode selection, and control of the Time Tag opera- tion. Start/Reset Register is used for command type functions, such as software reset, BC/MT Start, Interrupt Reset, Time Tag Reset, and Time Tag Register Test. The Start/Reset Register includes provisions for stopping the BC in its auto-repeat mode, either at the end of the current message or at the end of the current BC frame. BC/RT Command Stack Pointer Register allows the host CPU to determine the pointer location for the current or most recent message when the BU-61580 is in BC or RT modes. BC Control Word/RT Subaddress Control Word Register: In BC mode, allows host access to the current or most recent BC Control Word. The BC Control Word contains bits that select the active bus and message format, enable off-line self-test, masking of Status Word bits, enable retries and interrupts, and specify MIL-STD-1553A or -1553B error handling. In RT mode, VII-55OOG _... BU-65170/61580 and BU-61585 CORPORATION? T. REGISTER ADDRESS LINES Command Stack Pointer Register Control Word*/RT Subaddress Control 1_'BC Frame Time Remaining Register (R 0 BC Time Remaining to Next Message {RD _ of Frame Time*/RT Last Command/MT 1 (RD) Lae L testi ti * Not applicable to BU-65170/61571 this register allows host access to the current or most receni Subaddress Control Word. The Subaddress Control Word is used to select the memory management scheme and enable interrupts for the current message. The read/write accessibility can be used as an aid for testing the ACE. Time Tag Register maintains the value of a real-time clock. The resolution of this register is programmable from among 2. 4, 8, 16, 32, and 64 us/LSB. The TAG_CLK input signal also may cause an external oscillator to clock the Time Tag Register. Start-of-Message (SOM) and End-of-Message (EOM) se- quences in BC, RT, and Message Monitor modes cause a write of the current vatue of the Time Tag Register to the stack area of RAM. Interrupt Status Register mirrors the Interrupt Mask Register and contains a Master Interrupt bit. tt allows the host processor to determine the cause of an interrupt request by means of a single READ operation. Configuration Registers #3, #4, and #5 are used to enable many of the BU-61580's advanced features. These include all the enhanced mode features; that is, ail the functionality beyond that of the previous generation product, the BUS-61559 Ad- vanced Integrated Mux Hybrid with Enhanced RT Features (AIM- VII-56 HY'er). For all three modes, use of the Enhanced Mode enables the various read-only bits in Configuration Register #1. For BC mode, the enhanced mode features include the expanded BC Control Word and BC Block Status Word, additional Stop-On- Error and Stop-On-Status Set functions, frame auto-repeat, programmable intermessage gap times, automatic retries, ex- panded Status Word Masking, and the capability to generate interrupts following the completion of any selected message. For RT mode, the enhanced mode features include the ex- panded RT Block Status Word, the combined AT/Selective Message Monitor mode, internal wrapping of the ATFAIL out- put signal (from the J chip) to the RTFLAG RT Status Word bit, the double buffering scheme for individual receive (broadcast) subaddresses, and the alternate (fully software programmable) RT Status Word. For MT mode, use of the enhanced mode enables use of the Selective Message Monitor, the combined RT/Selective Monitor modes, and the monitor triggering capa- bility. Data Stack Address Register is used to point to the current address location in shared RAM used for storing message words (second Command Words, Data Words, RT Status Words) in the Selective Word Monitor mode. Frame Time Remaining Register provides a read only indica- tion of the time remaining in the current BC frame. The resolu- tion of this register is 100 ps/LSB. Message Time Remaining Register provides a read only indication of the time remaining before the start of the next message in a BC frame. The resolution of this register is 1 us/LSB. BC Frame/RT Last Command/MT Trigger Word Register: In BC mode, it programs the BC frame time, for use in the frame auto-repeat mode. The resolution of this register is 100 j1s/LSB, with a range of 6.55 seconds; in RT mode, this register stores the current {or most previous) 1553 Command Word processed by the ACE RT; in the Word Monitor mode, this register speci- fies a 16-bit Trigger (Command) Word. The Trigger Word may be used to start or stop the monitor, or to generate interrupts. Status Word Register and BIT Word Registers provide read- only indications of the BU-65170/61580's RT Status and BIT Words. Test Mode Registers 0-7: These registers may be used to facilitate production or maintenance testing of the BU- 65170/61580 and systems incorporating the BU-65170/61580.OOG BU-65170/61580 and BU-61585 CORPORATIONS 8C STATUS SET/RT MODE CODE/MT PATTERN FIGURE 2. INTERRUPT MASK REGISTER BC FUNCTION (bits 11-0 Enhanced Mode RT WITH ALTERNATE STATUS (Enhanced Mode MONITOR FUNCTION {Enhanced Mode Only, RT WITHOUT ALTERNATE STATUS (logic 1) (logic 1 {logic SSAGE STOP MONITOR ENABLED MONITOR E STOP-ON-ERROR WORD ATUS SET STOP-ON- ART-ON-TRIGGER (enhanced made only) TRIGGER E GAP TIMER USED ENABLED (Read Only) USED ENABLED TRIGGERED USED FRAME IN PROGRESS ACTIVE Only) MESSAGE IN PROGRESS Only) MESSAGE iN PROGRESS only) MESSAGE IN PROGRESS Mode only) (Read ENHANCED INTERAUPTS FIGURE 4. CONFIGURATION REGISTER #2 VII-57BOG BU-65170/61580 and BU-61585 ILC DATA DEVICE CORPORATION 2 RX DOUBLE BUFFER ENABLE RESERVED TX: INT FIGURE 5. START/RESET REGISTER FIGURE 8. RT SUBADDRESS CONTROL WORD COMMAND STACK POINTER 15 TIME TAG 15 FIGURE 6. BC/RT COMMAND STACK POINTER 5 RESERVED FIGURE 9. TIME TAG REGISTER MASTER INTERRUPT FIGURE 7. BC CONTROL WORD REGISTER BU-61580 BC STATUS SET/RT MODE CODE/MT PATTERN FIGURE 10. INTERRUPT STATUS REGISTER Vil-58OOG .. _ BU-65170/61580 and BU-61585 CORPORATION. 15 ENHANCED MODE ENABLE MONITOR DATA STACK ADDRESS 15 FIGURE 14. MONITOR DATA STACK ADDRESS 8C FRAME TIME REMAINING 15 FIGURE 11. CONFIGURATION REGISTER #3 FIGURE 15. BC FRAME TIME REMAINING EXTERNAL BIT WORD ENABLE BC MESSAGE TIME REMAINING 15 FIGURE 16. BC MESSAGE TIME REMAINING Bir DESCRIPTION 15 BIT 15 L(MSB) FIGURE 12. CONFIGURATION REGISTER #4 ; ; 0 (LSB) BIT 0 FIGURE 17. BC FRAME TIME/RT LAST COMMANDIMT TRIGGER REGISTER 12MHZ CLOCK SELECT (READ/WRITE ODh) Note: read only, logic O" for 65170/61580, logic "1" for FIGURE 13. CONFIGURATION REGISTER #5 VII-59OG... BU-65170/61580 and BU-61585 CORPORATION: LOGIC o FIGURE 18. RT STATUS WORD REGISTER GAP TIME TRANSMITTER TIMEOUT FIGURE 22. WORD MONITOR IDENTIFICATION FIGURE 19. RT BIT WORD REGISTER FIGURE 23. MESSAGE MONITOR MODE BLOCK Note: FIGURES 20 to 23 are not reigisters, but they are WORDS stored in RAM. Vil-60OOG ILG DATA DEVICE CORPORATIONS BC CONTROLLER (BC) ARCHITECTURE The BC protocol of the BU-61580 implements al! MIL-STD- 1553B message formats. Message format is programmable on a message-by-message basis by means of bits in the BC Control Word and the T/R bit of the Command Word for the respective message. The BC Control Word allows 1553 message format, 1553A/B type RT, bus channel, self-test, and Status Word mask- ing to be specified on an tndividual message basis. In addition, automatic retries and/or interrupt requests may be enabled or disabled for individual messages. The BC performs al! error checking required by MIL-STD-1553B. This includes validation of response time, sync type and sync encoding, Manchester I! encoding, parity, bit count, word count, Status Word RT Address tield, and various RT-to-RT transfer errors. The BU-61580s BC response timeout value is programmable with choices of 18, 22, 50, and 130 ps. The longer response timeout values allow for operation over long buses and/or the use of repeaters. FIGURE 24 illustrates BC intermessage gap and frame timing. The BU-61580 may be pregrammed to process BC frames of up to 512 messages with no processor intervention. It is possible to program for either single frame or frame auto-repeat operation. In the auto-repeat mode, the frame repetition rate may be con- trolled either internally, using a programmable BC frame timer, or from an external trigger input. The internai BC frame time is programmable up to 6.55 seconds in increments of 100 us. In addition to BC frame time, intermessage gap time, defined as the start of the current message to the start of the subsequent message, is programmable on an individual message basis. The time between individual successive messages is programmable up to 65.5 ms, in increments of 1 us. BC MEMORY ORGANIZATION TABLE 3 illustrates a typical memory map for BC mode. It is important to note that the only fixed locations for the BU-61580 in the Standard BC mode are for the two Stack Pointers (address locations 0100 (hex) and 0104) and for the two Message Count locations (0101 and 0105}. Enabling the Frame Auto-Repeat mode will reserve four more memory locations for use in the BU-65170/61580 and BU-61585 TABLE 3. TYPICAL BC MEMORY ORGANIZATION ADDRESS DESCRIPTION Initial Stack Pointer A (see note)(Auto-Frame Repeat Initial Message Count A (see note) Initial Stack Pointer B (see note) Initial Message Count B (see note) Note: Used only in the abled. BC mode with Auto-Repeat en- Enhanced BC mode; these locations are for the two Initial Stack Pointers (address locations 102 (hex) and 106) and for the Initial Message Count locations (103 and 107). The user is free to locate the Stack and BC Message Blocks anywhere else within the 64K (4K internal) shared RAM address space. For simplicity of illustration, assume the allocation of the maxi- mum length of a BC message for each message block in the typical BC memory map of TABLE 3. The maximum size of a BC message block is 38 words, for an RT-to-RT transter of 32 Data Words (Control + 2 Commands + Loopback + 2 Status Words + 32 Data Words). Note, however, that this example assumes the disabling of the 256-word boundaries. INTERMESSAGE ______- AP TIME ___-+ FOR MESSAGE NO. 1 J wT MESSAGE NO. 1 8C FRAME TIME MESSAGE NO. 2 Vv / __ MESSAGE NO. 1 FIGURE 24. BC INTERMESSAGE GAP AND FRAME TIMING Vil-611D] D]C) ILC DATA DEVICE CORPORATIONS BC MEMORY MANAGEMENT FIGURE 25 illustrates the BU-61580s BC memory management scheme. One of the BC memory management features is the global double buffering mechanism. This provides for two sets of the various BC mode data structures: Stack Pointer and Mes- sage Counter locations, Descriptor Stack areas, and BC mes- sage blocks. Bit 13 of Configuration Register #1 selects the Current active area. At any point in time, the BU-61580s internal 1553 memory management logic may access only the various data structures within the active area. FIGURE 25 delineates the active and inactive areas by the nonshaded and shaded areas, respectively; however, at any point in time, both the active and nonactive areas are accessible by the host processor. In most applications, the host processor will access the nonactive area, while the 1553 bus processes the active area messages. The BC may be programmed to transmit multimessage trames ot up to 512 messages. The number of messages to be processed is programmable by the Active Area Message Count location in the shared RAM, initialized by the host processor. In addition, the host processor must initialize another location, the Active Area Stack Pointer. The Stack Pointer references the four-word mes- sage block descriptor in the Stack area of shared RAM for each message to be processed. The BC Stack size is programmable with choices of 256, 512, 1024, and 2048 words. In the BC Frame Auto-Repeal mode, the Initial Stack Pointer and Initial Message Counter locations must be loaded by the host BU-65170/61580 and BU-61585 prior to the processing of the first frame. The single frame mode does not use these two locations. The third and fourth words of the BC block descriptor are the Intermessage Gap Time and the Message Block Address for the respective message. These two memory locations must be writ- ten by the host processor prior to the start of message process- ing. Use of the Intermessage Gap Time is optional. The Block Address pointer specifies the starting location for each message block. The first word of each BC message block is the BC Control Word. At the start and end of each message, the Block Status and Time Tag Words write to the message block descriptor in the stack. The Block Status Word includes indications of message in proc- ess of message completion, bus channel, status set, response timeout, retry count, status address mismatch, loop test (on-line self-test) failure, and other error conditions. FIGURE 20 illus- trates the bit mapping of the BC Block Status word. The 16-bit Time Tag Word will reflect the current contents of the internal Time Tag Register. This read/writable register, which operates for all three modes, has programmable resolution of from 2 to 64 ps/LSB. In addition, the Time Tag register may be clocked from an external source. BC Message Block Formats and BC Control Word In BC mode, the BU-61580 supports all MIL-STD-1553 message formats. For each 1553 message format, the BU-61580 man- dates a specific sequence of words within the BC Message INITIAL STACK POINTERS (NOTE) CONFIGURATION REGISTER STACK POINTERS CURRENT AREA BA INITIAL MESSAGE COUNTERS (NOTE) MESSAGE COUNTERS peepee nwnenns NOTE: INITIAL STACK POINTERS AND INITIAL MESSAGE COUNTERS USED ONLY IN BC FRAME AUTO-REPEAT MODE. DESCRIPTOR MESSAGE STACKS BLOCKS BLOCK STATUS WORD TIME TAG WORD: . ' ' ' 1 1 ' ' ' ' t INTERMESSAGE ' GAP TIME WORD ' P BLOCK ADDA BLOCK MESSAGE BLOCK FIGURE 25. BC MODE MEMORY MANAGEMENT Vi-62OG ILC DATA DEVICE CORPORATIONS BU-65170/61580 and BU-61585 Block. This includes locations for the Control, Command and (transmitted) Data Words that are to be read from RAM by the BC protocol logic. In addition, subsequent contiguous locations must be allocated for storage of received Loopback, RT Status and Data Words. FIGURE 26 illustrates the organization of the BC message blocks for the various MIL-STD-1553 message formats. Note that for all of the message formats, the BC Control Word is located in the first location of the message block. Mode Code; conta Wert Tx Mode Code M Transmit Command | [Mode Command Jommnan |__Looped Back _| |_Status Received _| Made Command Rx Mode Code | | Broadcast | | RT-to-ATs (Broadcast) With Data | Control Word Control Word Broadcast Rx Mode Command | Data#i | |_Data Word _} | Data #2) |"7, Command Looped Data Word : |_ Looped Back _| Status Received | Last Data | Last Data Looped Back Broadcast Mode Code; Broadcast Mode Code No Data With Data Control Word Controt Word Broadcast Mode Command | Br Broadcast Mode Command Data Word Looped Back Data Word Looped Back FIGURE 26. BC MESSAGE BLOCK FORMATS For each of the BC Message Block formats, the first word in the block is the BC Control Word. The BC Control Word is not transmitted on the 1553 bus. instead, it contains bits that select the active bus and message format, enable off-line self-test, masking of Status Word bits, enable retries and interrupts, and specify MIL-STD-1553A or -1553B error handling. The bit map- ping and definitions of the BC Control Word are illustrated in FIGURE 7. The BC Controt Word is follawed by the Command Word to be transmitted, and subsequently by a second Command Word (for an RT-to-RT transfer), followed by Data Words to be transmitted (for Receive commands). The location after the last word to be transmitted is reserved for the Loopback Word. The Loopback Word is an on-line self-test feature. The subsequent locations after the Loopback Word are reserved for received Status Words and Data Words (for Transmit commands). AUTOMATIC RETRIES The BU-61580 BC implements automatic message retries. When enabled, retries will occur, following response timeout or format error conditions. As additional options, retries may be enabled when the Message Error Status Word bit is set by a 1553A RT or following a Status Set condition. For a failed message, either one or two message retries will occur, the bus channel (same or alternate) is independently programmable for the first and second retry attempts. Retries may be enabled or disabled on an individ- ual message basis. BC INTERRUPTS BC interrupts may be enabled by the Interrupt Mask Register for Stack Rollover, Retry, End-of-Message (global), End-of-Message (in conjunction with the BC Control Word for individual messages), response timeout, message error, end of BC frame, and Status Set conditions. The definition of Status Set is programmable on an individual message basis by means of the BC Control Word. This allows for masking (care/dont care) for the individual RT Status Word bits. REMOTE TERMINAL (RT) ARCHITECTURE The RT protocol design of the BU-65170/61580 represents DDC's fifth generation implementation of a 1553 RT. One of the salient features of the ACEs RT architecture is its true multiprotocol functionality. This includes programmable options for support of MIL-STD-1553A, the various McAir protocols, and MIL-STD- 1553B Notice 2. The BU-65170/61580 RT response time is 2 to 5 us dead time (4 to 7 1s per 1553B), providing compliance to all the 1553 protocols. Additional multiprotocol features of the BU- 65170/61580 include options for full software control of RT Status and Built-in-Test (BIT) words. Alternatively, for 1553B applica- tions, these words may be formulated in real time by the BU- 65170/61580 protocol logic. The BU-65170/61580 RT protocol design implements ail the MIL- STD-1553B message formats and dual redundant mode codes. This design is based largely on previous generation products that Vil-63OOe 1L.C OATA DEVICE CORPORATION? have passed SEAFAC testing for MIL-STD-15538 compliance. The ACE RT performs comprehensive error checking, word and format validation, and checks for various RT-to-RT transfer er- rors. Other key features of the BU-65170/61580 RT include a set of interrupt conditions, internal command illegalization, and pro- grammable busy by subaddress RT MEMORY ORGANIZATION TABLE 4 illustrates a typical memory map for the BU-61580 in RT mode. As in BC mode, the two Stack Pointers reside in fixed locations in the shared RAM address space: address 0100 (hex) for the Area A Stack Pointer and address 0104 for the Area B Stack Pointer. Besides the Stack Pointer, for RT mode there are several other areas of the ACE address space designated as fixed locations. All RT modes of operation require the Area A and Area B Lookup Tables. Also allocated, are several fixed locations for optional features: Command Illegalization Lookup Table, Mode Cade Selective Interrupt Table, Mode Code Data Table, and Busy Bit Lookup Table. It should be noted that any unen- abled optional fixed locations may be used for general purpose storage (data blocks). The RT Lookup tables, which provide a mechanism for mapping data blocks for individual Tx/Rx/Best-subaddresses to areas in the RAM, occupy address range locations are 0140 to 01BF for Area A and 01C0 to 023F for Area B. The RT lookup tables include Subaddress Control Words and the individual Data Block Pointers. If used, address range 0300-03FF will be dedicated as the illegalizing section of RAM. The actual Stack RAM area and the individual data blocks may be located in any of the nonfixed areas in the shared RAM address space. RT MEMORY MANAGEMENT One of the salient features of the ACE series products is the flexibility of its RT memory management architecture. The RT architecture allows the memory management scheme for each transmit, receive, or broadcast subaddress to be programmable on a subaddress basis. Also, in compliance with MIL-STD-1553B Notice 2, the BU-65170/61580 provides an option to separate data received from broadcast messages from nonbroadcast re- ceived data. Besides supporting a global double buffering scheme (as in BC mode), the ACE RT provides a pair of 128-word Lookup Tables for memory management control, programmable on a subad- dress basis (refer to TABLE 5). The 128-word tables include 32-word tables for transmit message pointers and receive mes- sage pointers. There is also a third, optional Lookup Table for broadcast message pointers, providing Notice 2 compliance, if necessary. The fourth section of each of the RT Lookup Tables stores the 32 Subaddress Control Words (refer to FIGURE 8 and TABLE 6). The individual Subaddress Control Words may be used to select the RT memory management option and interrupt scheme for each transmit, receive, and (optionally) broadcast subaddress. VIl-64 T, ADDRESS BU-65170/61580 and BU-61585 DESCRIPTION 100 TABLE 5. RT LOOK-UP TABLES AREA A_| AREAB DESCRIPTION COMMENT. 0140 01C0 Rx(/Best)_ SAO Receive . . . ({Broadcast) Lookup Table O15F O1DF | _Rx(/Best)_SA31 0160 01E0 Tx_SAO Transmit . : . Lookup Table O17F O1FF Tx_SA31 07180 0200 Best_SAO Broadcast : : . Lookup Table (Optional) O19F O21F Best_SA31 01A0 0220 SACW_SAO Subaddress Contro} . : : Word Lookup Table (Optional) O1BF 023F SACW_SA31 TABLE 6. SUBADDRESS CONTROL WORD Circular Buffer of Specified SizeOG ILC DATA DEVICE CORPORATION? For each transmit subaddress, there are two possible memory management schemes: (1) single message; and (2) circular buffer. For each receive (and optionally broadcast) subaddress, there are three possible memory management schemes: (1) single message; (2) double buffered; and (3) circular buffer. For each transmit, receive and broadcast subaddress, there are two interrupt conditions programmable by the respective Subaddress Control Word: (1) after every message to the subaddress; (2) after a circular buffer rollover. An additional table in RAM may be used to enable interrupts following selected mode code mes- sages. When using the circular buffer scheme for a given subaddress, the size of the circular buffer is programmable by three bits of the Subaddress Control Word (see TABLE 6). The options for circu- lar buffer size are 128, 256, 512, 1024, 2048, 4096, and 8192 Data Words. SINGLE MESSAGE MODE FIGURE 27 illustrates the RT Single Message memory manage- ment scheme. When operating the BU-65170/61580 in its AiM- HY (default) mode, the Single Message scheme is implemented for all transmit, receive, and broadcast subaddresses. In the Single Message mode (aiso in the Double Buffer and Circular Buffer modes), there is a global double buffering scheme, con- trolled by bit 13 of Configuration Register #1. This selects from between the two sets of the various data structures shown in the figure: the Stack Pointers (fixed addresses), Descriptor Stacks (user defined addresses), F1T Lookup Tables (fixed addresses), and RT Data Word blocks (user defined addresses). FIGURES 27, 28, and 29 delineate the active and nonactive areas by the nonshaded and shaded areas, respectively. As shown, the ACE stores the Command Word from each mes- sage received, in the fourth location within the message descrip- tor {in the stack) for the respective message. The T/R bit, subaddress field, and (optionally) broadcast/own address, index into the active area Lookup Table, to locate the data block pointer for the current message. The BU-65170/61580 RT memory man- agement logic then accesses the data block pointer to locate the starting address for the Data Word block for the current message. The maximum size for an RT Data Word block is 32 words. For a particular subaddress in the Single Message mode, there is overwriting of the contents of the data blocks for receive/broad- cast subaddresses or overreading, for transmit subaddresses. In the single message mode, it is possible to access multiple data blocks for the same subaddress. This, however, requires the intervention of the host processor to update the respective Lookup Table pointer. To implement a data wraparound subaddress, as required by Notice 2 of MIL-STD-1553B, the Single Message scheme should be used for the wraparound subaddress. Notice 2 recommends subaddress 30 as the wraparound subaddress. BU-65170/61580 and BU-61585 CIRCULAR BUFFER MODE FIGURE 28 illustrates the RT circular buffer memory manage- ment scheme. The circular buffer mode facilitates bulk data transfers. The size of the RT circular buffer, shown on the right side of the figure, is programmable from 128 to 8192 words (in even powers of 2) by the respective Subaddress Control Word. As in the single message mode, the host processor initially loads the individual Lookup Table entries. At the start of each mes- sage, the ACE stores the Lookup Table entry in the third position of the respective message block descriptor in the stack area of RAM, as in the Single Message mode. The ACE transfers Re- ceive or Transmit Data Words to (from) the circular buffer, start- ing at the location referenced by the Lookup Table pointer. At the end of a valid (or, optionally invalid) message, the value of the Lookup Table entry updates to the next location after the last address accessed for the current message. As a result, Data Words for the next message directed to the same Tx/RX(/Bcst) subaddress will be accessed from the next contiguous block of address locations within the circular buffer. As a recommended option, the Lookup Table pointers may be programmed to not update following an invalid receive (or broadcast) message. This allows the 1553 bus controller to retry the failed message, result- ing in the valid (retried) data overwriting the invalid data. This eliminates overhead for the RT's host processor. When the pointer reaches the lower boundary of the circular buffer (located at 128, 256, .. . 8192-word boundaries in the BU-65170/61580 address space), the pointer moves to the top boundary of the circular buffer, as FIGURE 28 shows. Implementing Bulk Data Transfers The use of the Circular Buffer scheme is ideal for bulk data transfers; that is, multiple messages to/from the same subad- dress. The recommendation for such applications is to enable the circular buffer interrupt request. By so doing, the routine transfer of multiple messages to the selected subaddress, including errors and retries, is transparent to the RTs host processor. By strategically initializing the subaddressess Lookup Table pointer prior to the start of the bulk transfer, the BU-65170/61580 may be configured to issue an interrupt request only after it has received the anticipated number of valid Data Words to the designated subaddress. SUBADDRESS DOUBLE BUFFERING MODE For receive (and broadcast) subaddresses, the BU-65170/61580 FT offers a third memory management option, Subaddress Dou- ble Buffering. Subaddress Double Buffering provides a means of ensuring data consistency. FIGURE 29 illustrates the RT Subad- dress Doubie Buffering scheme. Like the Single Message and Circular Buffer modes, the Double Buffering mode may be se- lected on a subaddress basis by means of the Subaddress Control Word. The purpose of the Double Buffering mode is to provide the host processor a convenient means of accessing the most recent, valid data received to a given subaddress. This serves to ensure the highest possible degree of data consistency by allocating two 32-bit Data Word blocks for each individual receive (and/or broadcast) subaddress. VH-65OOG BU-65170/61580 and BU-61585 CORPORATIONS CONFIGURATION STACK DESCRIPTOR LOOK-UP TABLE Dara REGISTER PO;TERS STACKS IDATA BLOCK ADORT LOCKS BLOCK STATUS WORD TIME TAG WORD DATA BLOCK POINTER OR MODE CODE DATA WORD FIGURE 27. RT MEMORY MANAGEMENT: SINGLE MESSAGE MODE CONFIGURATION STACK DESCRIPTOR IACULAA AEGISTER POINTERS STACK LOOK-UP FABLES ore 1a a BUFFER, CURRENT eS AREA AB ES - /ecocx status word L TIME TAG WORD, aro LOOK-UP PONTE: Sch] pata eLocx powren TABLE on nock RECEIVED COMMA ADDRESS | LOOR ue TARE | Pe ORO RANSMATTED) POINTERTO Lb NEXT DATA oo S00" een | ow * TYRS/RCST_SA COK-UP TABLE ENTRY IS UPDATED FOLLOWING VALIO RECEIVE (BROADCAST) MESSAGE OF FOLLOWING COMPLETION OF TRANSMIT MESBAGE, FIGURE 28. RT MEMORY MANAGEMENT: CIRCULAR BUFFER MODE CONFIGURATION REGISTER NO * STACK 5 13 Q POINTERS CURRENT AREA BA LOOK-UP TABLES. DESCRIPTOR STACKS: eeeees BLOCK STATUS WORD TIME TAG WORD DATA BLOCK POINTER BATA SLOCK POINTER RECEIVE DOUBLE BUFFER ENABLE FIGURE 29. RT MEMORY MANAGEMENT: SUBADDRESS DOUBLE BUFFERING MODE ViI-66BOE ILC DATA DEVICE CORPORATION. At a given point in time, one of the two blocks will be designated as the active 1553 data block while the other will be designated as the inactive block. The Data Words from the next receive message to that subaddress will be stored in the active block. Upon completion of the message, provided that the message was valid and Subaddress Double Buffering is enabled, the BU-65170/61580 will autornatically switch the active and inac- tive blocks for the respective subaddress. The ACE accom- plishes this by toggling bit 5 of the subaddresss Lookup Table Pointer and rewriting the pointer. As a result, the most recent valid block of received Data Words will always be readily acces- sible to the host processor. As a means of ensuring data consistency, the host processor is able to reliably access the most recent valid, received Data Word block by performing the following sequence: (1) Disable the double buffering for the respective subaddress by the Subaddress Control Word. That is, temporarily switch the subaddresss memory management scheme to the Single Message mode. (2) Read the current value of the receive (or broadcast) subad- dresss Lookup Table pointer. This points to the current active Data Word block. By inverting bit 5 of this pointer value, it is possible to locate the start of the inactive Data Word block. This block will contain the Data Words received during the most recent valid message to the subaddress. (3) Read out the words from the inactive (most recent) Data Word Block. (4) Re-enable the Double Buffering mode for the respective subaddress by the Subaddress Control Word. RT INTERRUPTS As in BC mode, the BU-65170/61580 RT provides many mask- able interrupts. RT interrupt conditions include End of (every) Message, Message Error, Selected Subaddress (Subaddress Contro! Word) interrupt, Circular Buffer Rollover, Selected Mode Code Interrupt, and Stack Rollover. DESCRIPTOR STACK At the beginning and end of each message, the BU-65170/61580 RT stores a four-word message descriptor in the active area stack. The RT stack size is programmable, with choices of 256, 512, 1024, and 2048 words. FIGURES 27, 28, and 29 show the four words: Block Status Word, Time Tag Word, Data Block Pointer, and the 1553 received Command Word. The RT Block Status Word includes indications of message in-progress or message complete, bus channel, RT-to-RT transfer and RT-to- RT transfer errors, message format error, loop test (self-test) failure, circular buffer rollover, illegal command, and other error conditions. FIGURE 21 shows the bit mapping of the RT Block Status Word. As in BC mode, the Time Tag Word stores the current contents of the BU-65170/61580's read/writable Time Tag Register. The resolution of the Time Tag Register is programmable from among 2, 4, 8, 16, 32, and 64 ys/LSB. Also, incrementing of the BU-65170/61580 and BU-61585 Time Tag counter may be from an external clock source or via software command. The ACE stores the contents of the accessed Lookup Table location for the current message, indicating the starting location of the Data Word block, as the Data Block Pointer. This serves as a convenience in locating stored message data blocks. The ACE stores the full 16-bit 1553 Command Word in the fourth location of the RT message descriptor. RT COMMAND ILLEGALIZATION The BU-65170/61580 provides an internal mechanism for RT com- mand illegalization. In addition, there is a means for allowing the setting of the Busy Status Word bit to be only for a programmed subset of the transmit/receive/broadcast subaddresses. The illegalization scheme uses a 256-word area in the BU- 65170/61580's address space. A benefit of this feature is the reduction of printed circuit board requirements, by eliminating the need for an external PROM, PLD, or RAM device that does the legalizing function. The BU-65170/61580's illegalization scheme provides maximum flexibility, allowing any subset of the 4096 possible combinations of broadcast/own address, T/R bit, subaddress, and word count/mode code to be itlegalized. An- other advantage of the RAM-based illegalization technique is that it provides for a high degree of self-testability. Addressing the Iilegalization Table. FIGURE 30 illustrates the addressing scheme of the illegalization RAM . As shown, the base address of the illegalizing RAM is 0300 (hex). The ACE formulates the index into the Illegalizing Table based on the values of BROADCAST(OWN ADDRESS, T/R bit, Subaddress, and the MSB of the Word Count/Mode Code field (WC/MC4) of the current Command Word. The internal RAM has 256 words reserved for command illegali- zation. Broadcast commands may be illegalized separately from nonbroadcast receive commands and mode commands. Commands may be illegalized down to the word count level. For example, a one-word receive command to subaddress 1 may be legal, while a two-word receive command to subaddress 1 may be iltegalized. The first 64 words of the Illegalization Table refer to broadcast teceive commands (two words per subaddress). The next 64 words refer to broadcast transmit commands. Since nonmode code broadcast transmit commands are by definition invalid, this section of the table (except for subaddresses 0 and 31) does not need to be initialized by the user. The next 64 words correspond to nonbroadcast receive commands. The final 64 words refer to nonbroadcast transmit commands. Messages with Word Count/ Mode Code (WC/MC) fields between 0 and 15 may be illegalized by setting the corresponding data bits for the respective even-num- bered address focations in the illegalization table. Likewise, mes- sages with WC/MC fields between 16 and 31 may be illegalized by setting the corresponding data bits for the respective odd-num- bered address locations in the illegalization table. VIl-67BOG ILC DATA DEVICE CORPORATIONS FIGURE 30. ILLEGALIZING RAM ADDRESS The following should be noted with regards to command illegaliza- tion: (1) To illegalize a particular word count for a given broad- cast/own address-T/A subaddress, the appropriate bit po- sition in the respective illegalization word should be set to logic 1. A bit value of logic 0 designates the respective Command Word as a legal command. The ACE will re- spond to an_ illegalized nonbroadcast command with the Message Error bit set in its RT Status Word, For subaddresses 00001 through 11110, the "WC/MC field specities the Word Count field of the respective Command Word. For subaddresses 00000 and 11111, the WC/MC field specifies the Mode Code field of the respective Com- mand Word. (3) Since nonmode code broadcast transmit messages are not defined by MIL-STO-15538, the sixty (60) words in the illegalization RAM, addresses 0342 through 037D, corre- sponding to these commands do not need to be initialized. The ACE will not respond to a nonmode code broadcast transmit command, but will automatically set the Message Error bit in its internal Status Register, regardiess of whether or not corresponding bit in the iflegalization RAM has been set. If the next message is a Transmit Status or Transmit Last Command mode code, the ACE will respond with its Message Error bit set. (2 PROGRAMMABLE BUSY As a means of providing compliance with Notice 2 of MIL-STD- 1553B, the BU-65170/61580 RT provides a software controllable means for setting the Busy Status Word bit as a function of subad- dress. By a Busy Lookup Table in the BU-65170/61580 address space, it is possible to set the Busy bit based on command broad- cast/own address, T/R bit, and subaddress. Another programmabie option, allows received Data Words to be either stored or not stored for messages, when the Busy bit is set. VIl-68 BU-65170/61580 and BU-61585 OTHER RT FUNCTIONS The BU-65170/61580 allows the hardwired RT Address to be read by the host processor. Also, there are options for the RT FLAG Status Word bit to be set under software contro! and/or automatically following a failure of the loopback self-test. Other software controllable RT options include software programmable RT Status and RT BIT words, automatic clearing of the Service Request Status Word bit following a Transmit Vector Word mode command, capabilities to clear and/or load the Time Tag Register following receipt of Synchronize mode commands, options re- garding Data Word transfers for the Busy and/or Message Error (legal) Status Word bits, and for handling of 1553A and re- served mode codes. MONITOR (MT) ARCHITECTURE The BU-61580 provides three bus monitor (MT) modes: (1) The AIM-HY (default) or AIM-HY'er Word Monitor mode. (2) A Selective Message Monitor mode. (3) A Simultaneous Remote Terminal/Selective Message Moni- tor mode. The strong recommendation for new applications is the use of the Selective Message Monitor, rather than the Word Monitor. Be- sides providing monitor filtering based on RT Address, T/R bit, and Subaddress, the Message Monitor eliminates the need to determine the start and end of messages by software. The development of such software tends to be a tedious task. More- over, at run time, it tends to entail a high degree of CPU over- head. WORD MONITOR In the Word Monitor mode, the BU-61580 monitors both 1553 buses. After initializing the Word Monitor and putting it on-line the BU-61580 stores all Command, Status, and Data Words received from both buses. For each word received from either bus, the BU-61580 stores a pair of words in RAM. The first word is the 16 bits of data from the received word. The second word is the Monitor Identification (ID), or Tag word. The ID Word con- tains information relating to bus channel, sync type, word validity, and interword time gaps. The BU-61580 stores data and ID words in a circular buffer in the shared RAM address space. FIGURE 22 shows the bit mapping for the Monitor ID word. MONITOR TRIGGER WORD There is a Trigger Word Register that provides additional flexibil- ity for the Word Monitor mode. The BU-61580 stores the value of the 16-bit Trigger Word in the MT Trigger Word Register. The contents of this register represent the value of the Trigger Com- mand Word. The BU-61580 has programmable options to start or stop the Word Monitor, and/or to issue an interrupt request following receipt of the Trigger Command Word from the 1553 bus.OOG _.. BU-65170/61580 and BU-61585 CORPORATION? SELECTIVE MESSAGE MONITOR MODE Message Monitor mode. Refer to TABLE 7 for an example of a typical Selective Message Monitor Memory Map. The fixed mem- ory map consists of two Monitor Command Stack Pointers (loca- tion 102h and 106h), two Monitor Data Stack Pointers (locations 103h and 107h), and a Selective Message Monitor Lookup Table (0280-02FFh) based on RT Address, T/R, and subaddress. As- sume a Monitor Command Stack size of 1K words, and a Monitor Data Stack size of 2K words. The BU-61580 Selective Message Monitor provides features to greatly reduce the software and processing burden of the host CPU. The Selective Message Monitor implements selective monitoring of messages from a dual_1553 bus, with the monitor filtering based on the RT Address, T/R bit, and Subaddress fields of received 1553 Command Words. The Selective Message Monitor mode greatly simplifies the host processor software by distinguishing between Command and Status Words. The Selec- tive Message Monitor maintains two stacks in the BU-61580 RAM: a Command Stack and a Data Stack. Refer to FIGURE 31 for an illustration of the Selective Message Monitor operation. Upon receipt of a valid Command Word, the BU-61580 will reference the Selective Monitor Lookup Table (a fixed block of addresses) to check for the condition (disabled/en- Simultaneous RT/Message Monitor Mode abled) of the current command. If disabled, the BU-61580 will ignore (and not store) the current message; if enabled, the The Selective Message Monitor may function as a purely passive BU-61580 will create an entry in the Monitor Command Stack at monitor or may be programmed to function as a simultaneous the address location referenced by the Monitor Command Stack RT/Monitor. The RT/Monitor mode provides complete Remote Pointer. Terminal (RT) operation for the BU-61580's strapped RT address and bus monitor capability for the other 30 nonbroadcast RT Similar to RT mode, The ACE stores a Block Status Word, 16-bit addresses. This allows the BU-61580 to simultaneously operate Time Tag Word, and Data Block Pointer in the Message Descrip- as a full function RT and snoop on ail or a subset of the bus tor, along with the received 1553 Command Word following activity involving the other RTs on a bus. This type of operation reception of the Command Word. The ACE writes the Block is sometimes needed to implement a backup bus controller. The Status and Time Tag Words at both the start and end of the combined RT/Selective Monitor maintains three stack areas in message. The Monitor Block Status Word contains indications of the BU-61580 address space: an RT Command Stack, a Monitor message in-progress or message complete, bus channel, Moni- Command Stack, and a Monitor Data Stack. The pointers for the tor Data Stack Rollover, RT-to-AT transfer and RT-to-RT transfer various stacks have fixed locations in the BU-61580 address errors, message format error, and other error conditions. FIG- space. URE 23 shows the Message Monitor Block Status Word. The Data Block Pointer references the first word stored in the Monitor . . oe Data Stack (the first word following the Command Word) for the Selective Message Monitor Memory Organization current message. The BU-61580 will then proceed to store the i ic. ; lbsequent words from the message (possible second Com- TABLE 7 illustrates a typical memory map for the ACE in the su : : Selective Message Monitor mode. This mode of operation de- mand Word, Data Word(s), Status Word(s)) into consecutive fines several fixed locations in the RAM. These locations allocate locations in the Monitor Data Stack. in a manner that is compatible with the combined RT/Selective MONITOR. COMMAND STACKS CONFIGURATION MONITOR COMMAND: REGISTER MO + STACK POINTERS 15 1a 6 MONITOR DATA STACKS BLOCK STATUS WORD CURRENT y a TIME TAG WORD Zz CURRENT. oe AREA Bik COMMAND WORD DATA BLOCK POINTER: AECEIVED COMMAND WORD. MONITOR DATA BLOCK #N MONITOR DATA BLOCK @N + 1 MONITOR CATA STACK POINTERS NOTE IF THIS BIT IS O (NOT SELECTEC), NO IOS ARE STORED IN EITHER THE COMMANDO STACK OR DATA STACK, DDITION, TH in STACK POINTERS WiLL NOT BE UPDATED SELECTIVE MONITOR LOOKUP TABLES 4 TION zs aI BASED ON SA3-SAO OFFSET BASED ON TI ATAS-ATAQ, TA Sad [ I SELECTIVE MONITOR t y {SEE NOTE) FIGURE 31. SELECTIVE MESSAGE MONITOR MEMORY MANAGEMENT Vil-69Oc ILC OATA DEVICE CORPORATION: TABLE 7. TYPICAL SELECTIVE MESSAGE MONITOR MEMORY ADDRESS OESCRIPTION The size of the Monitor Command Stack is programmable to 256, 1K, 4K, or 16K words. The Monitor Data Stack size is program- mable to 512, 1K, 2K, 4K, &K, 16K, 32K, or 64K words. Monitor interrupts may be enabled for Monitor Command Stack Rollover, Monitor Data Stack Rollover, and/or End-of-Message conditions. In addition, in the Word Monitor mode there may be an interrupt enabled for a Monitor Trigger condition. PROCESSOR AND MEMORY INTERFACE The ACE terminals provide much flexibility for interfacing to a host processor and optional external memory. FIGURE 1 shows that there are 14 control signals, 6 of which are dual purpose, for the processor/memory interface. FIGURES 32 through 37 illus- trate six of the configurations that may be used for interfacing a BU-65170 or BU-61580 to a host processor bus. The various possible configurations serve to reduce to an absolute minimum the amount of glue logic required to interface to 8-, 16-, and 32-bit processor buses. Also included are features to facilitate interfac- ing to processors that do not have a wait state type of hand- shake acknowledgement. Finally, the ACE supports a reliable interface to an external dual port RAM. This type of interface minimizes the portion of the available processor bandwidth re- quired to access the 1553 RAM. The 16-bit buffered mode (FIGURE 32) is the most common configuration used. it provicles a direct, shared RAM interface to a 16-bit or 32-bit microprocessor. In this mode, the ACE's internal address and data buffers provide the necessary isolation be- tween the host processor's address and data buses and the corresponding internal memory buses. In the buffered mode, the 1553 shared RAM address space limit is the BU-65170/61580's 4K words of internal RAM. The 16-bit buffered mode provides a pair of pin-programmable options: (1) The logic sense of the RD/WR control input is selectable by the POLARITY_SEL input: For example, write when RD/WR is low for Motorola 680X0 processors; write when RD/WR is high for the Intel i960 series microprocessors. (2) By strapping the input signal ZERO_WAIT to logic "1," the ACE terminals may interface to processors that have an acknow- BU-65170/61580 and BU-61585 ledge type of handshake input to accommodate hardware control- led wait states; most current processor chips have such an input. In this case, the BU-65170/61580 will assert its READYD output low only after it has latched WRITE data internally or has pre- sented READ data on D15-Do. By strapping ZERO_WAIT to logic "0," it is possible to easily interface the BU-65170/61580 to processors that do not have an acknowledge type of handshake input. An example of such a processor is Analog Devices ADSP2101 DSP chip. In this con- figuration, the processor can clear its strobe output before the completion of access to the BU-65170/61580 internal RAM or register. In this case, READYD will go high fotiowing the rising edge of STRBD and will stay high until completion of the transfer. READYD will normally be iow when ZERO_WAIT is low. Similar to the 16-bit buffered mode, the 16-bit transparent mode (FIGURE 33) supports a shared RAM interface to a host CPU. The transparent mode offers the advantage of allowing the buffer RAM size to be expanded to up to 64K words, using extemal RAM. A disadvantage of the transparent mode is that it requires external address and data buffers to isolate the processor buses from the memory/BU-65170/61580 buses. A modified version of the transparent mode involves the use of dual port RAM, rather than conventional static RAM. Refer to FIGURE 34. This allows the host to access RAM very quickly, the only limitation being the access time of the dual port RAM. This configuration eliminates the BU-65170/61580 arbitration delays for memory ac- cesses. The worst case delay time occurs only during a simultaneous access by the host and the BU-65170/61580 1553 logic to the same memory address. In general, this will occur very rarely and the ACE limits the delay to approximately 250 ns. FIGURE 335 illustrates the connections for the 16-bit Direct Mem- ory Access (DMA) mode. In this configuration the host processor, rather than the ACE terminal, arbitrates the use of the address and data buses. The arbitration involves the two DMA output signals Request (DTREQ) and Acknowledge (DTACK), and the input signal Grant (DTGRT}. The DMA interface allows the ACE components to interface to large amounts of system RAM while eliminating the need for external buffers. For system address spaces larger than 64K words, itis necessary for the host proces- sor to provide a page register for the upper address bits (above A15) when the BU-65170/61580 accesses the RAM (while assert- ing DTACK low). The internal RAM is accessible through the standard ACE inter- face (SELECT, STRBD, READYD, etc). The host CPU may ac- cess external RAM by the ACE's arbitration logic and output control signals, as illustrated in FIGURE 35. Alternatively, control of the RAM may be shared by both the host processor and the ACE, as illustrated in FIGURE 36. The latter requires the use of external logic, but allows the processor to access the RAM directly at the full access speed of the RAM, rather than waiting for the ACE handshake acknowledge output (READYD). FIGURE 37 illustrates the 8-bit buffered mode. This interface allows a direct connection to 8-bit microprocessors and 8-bit microcontrol- lers. As in the 16-bit buffered configuration, the buffer RAM limit is the BU-65170/61580's 4K words of internal RAM. In the 8-bit mode, theBOE ILC DATA DEVICE CORPORATION? host CPU accesses the BU-65170/61580's internal registers and RAM by a pair of 8-bit registers embedded in the ACE interface. The 8-bit interface may be further configured by three strappable inputs: ZERO_WAIT, POLARITY_SEL, and TRIGGER_SEL. By connecting ZERO_WAIT to logic "0," the BU-65170/61580 may be interfaced with minimal "glue" logic to 8-bit microcontrollers, such as the Intel 8051 series, that do not have an Acknowledge type of handshake input. The programmable inputs POLARITY_SEL and TRIGGER_SEL allow the BU-65170/61580 to accommodate the different byte ordering conventions and "AO" logic sense utilized by different 8-bit processor families. PROCESSOR INTERFACE TIMING FIGURES 38 and 339 illustrate the timing for the host processor to access the ACEs intemal RAM or registers in the 16-bit, non-zero wait buffered mode. FIGURE 38 illustrates the 16-bit buffered, nonzero wait state mode read cycle timing while FIGURE 39 shows the 16-bit, buffered, nonzero wait state mode write cycle timing. During a CPU transfer cycle, the signals STRBD and SELECT must be sampled low on the rising edge of the system clock to request access to the BU-65170/61580's internal shared RAM. The transfer will begin on the first rising system clock edge when (SELECT and STRBD) is low and the 1553 protocol/memory management unit is not accessing the internal RAM. The falling edge of the output signal IOEN indicates the start of the transfer. The ACE latches the signals MEM/REG and RD/WR internally on the first falling clock edge after the start of the transfer cycle. The address inputs latch internally on the first rising clock edge after the signal IOEN goes tow. Note that the address lines may be latched at any time using the ADDR_LAT input signal. The output signal READYD will be asserted low on the third rising system clock edge after IOEN goes low. The assertion of READYD low indicates to the host processor that read data is available on the parallel data bus, or that write data has been stored. At this time, the CPU should bring the signal STRBD high, completing the transfer cycle. Address Latch Timing FIGURE 40 illustrates the operation and timing of the address input latches for the buffered interface mode. In the transparent mode, the address buffers are always transparent. Since the transparent mode requires the use of extemal buffers, extemal address latches would be required to demultiplex a multiplexed address bus. In the buffered mode however, the ACE's internal address latches may be used to perform the demultiplexing function. The ADDR_LAT input signal controls address latch operation. When ADDR_LAT is high, the outputs of the latch (which drive the ACEs intemal memory bus) track the state of address inputs A15 AQO. When low, the intemal memory bus remains latched at the state of A15 A00 just prior to the falling edge of ADDR_LAT. BU-65170/61580 and BU-61585 MISCELLANEOUS SELF-TEST The BU-65170/61580 products incorporate several self-test fea- tures. These features include an on-line wraparound self-test for all messages in BC and RT modes, an off-line wraparound self-test for BC mode, and several other intemal self-test features. The BC/RT on-ine loop test involves a wraparound test of the en- coder/decoder and transceiver. The BC off-line self-test involves the encoder/decoder, but not the transceiver. These tests entail checking the received version of every transmitted word for validity (sync, encod- ing, bit count, parity) and checking the received version of the last transmitted word for a bit-by-bit comparison with the encoded word. The loopback test also fails if there is a timeout of the intemal transmitter watchdog timer. A failure of the loop test results in setting a bit in the message's Block Status Word and, if enabled, will result in an interrupt Tequest. With appropriate host processor software, the BC off-line test is able to exercise the parallel and serial data paths, encoder, decoder, and a substantial portion of the BC protocal and memory management logic. There are additional built-in self-test features, involving the use of three configuration register bits and the eight test registers. This allows a test of approximately 99% of the J chip's internal logic. These tests include an encoder test, a decoder test, a register test, a protocol test, and a test of the fail-safe (transmitter timeout) timer. There is also a test mode. In the test mode, the host processor can emulate arbitrary activity on the 1553 buses by writing to a pair of test registers. The test mode can be operated in conjunction with the Word Monitor mode to facilitate end-to-end self-tests. RAM PARITY GENERATION AND CHECKING The architecture of the J monolithic is such that the amount of buffered RAM may be extended beyond the 4K words of on-chip J RAM. For this off-chip buffered RAM, the J chip includes provisions to implement parity generation and checking. Parity generation and checking provides a mechanism for checking the data integrity of the internal, buffered memory. Furthermore, 17-bit, rather than 16-bit, wide buffered RAM would be used. For this RAM, the J chip will generate the 17th bit (parity bit) for all (host and 1553) write accesses and check the parity bit for all read accesses. !f a parity error occurs, an interrupt request may be issued, and the corresponding bit in the Interrupt Status Register would be set. The BU-61585 incorporates an additional 8K x 17 RAM chip. Vil-71OOS ILG DATA DEVICE CORPORATIONS BU-65170/61580 and BU-61585 CLOCK OSCILLATOR -15V+5V 16 MRZ CLK IN 4 x we [asa D15-D0 CH.A * AT1-A0 CPU ADDRESS LATCH (NOTE 1) ADDR-LAT +5V Nw Wwe -. . (NOTE 2) +... (NOTE 3) HOST = ADDRESS DECODER RD/WR TRANSPARENT/BUFFERED +5V 16/8_BIT TRIGGER_SEL 1 MSB/LSB TXVAXB POLARITY_SEL = ZERO_WAIT BUS-61580 SELECT MEM/REG ADWA CPU STROBE STRBO CPU ACKNOWLEDGE (NOTE 4) Hd neocsenences me NA +5V RESET | READYD RTAD4-RTADO AT TAG_CLK ADDRESS. ATADP MSTCLR a x CPU INTERRUPT REQUEST SSFLAGEXT_TRIG iNT NOTES: 1. CPU ADORESS LATCH SIGNAL PROVIDED BY PROCESSORS WITH MULTIPLEXED ADDAESS/DATA 3. ZERO_WAIT SHOULD BE STRAPPED TO LOGIC "1" FOR NON-ZERO WAIT, INTERFACE BUSES. AND TO LOGIC 0 FOR ZEAO WAIT INTERFACE. 2. IF POL_SEL = 1, RD/WR IS HIGH TO READ, 4. CPU ACKNOWLEDGE PROCESSOR INPUT ONLY LOW TO WRITE. FOR NON-ZERO WAIT TYPE OF INTERFACE. IF POL_SEL = "0" RD/WR IS LOW TO READ, HIGH TO WRITE. * Additional address lines A12 and A13 are required with the BU-61585. FIGURE 32. 16-BIT BUFFERED MODEOOG ._... BU-65170/61580 and BU-61585 CORPORATION? -15V +5V 16 MHZ CLOCK OSCILLATOR al | y TXRXA S52 015-00 1 8 245 IR EN 2 7 ROWR b 5 CH.A I a = be = MEMWR WR = 3 4 552 RAM MEMOE 64K X16 MAX OE = as TXIRKA ZN en DTREQ a / OTGAT EN CPU A15-A0 > A15-A0 "244 ADDRESS THIRKB 552 DECODER | MEMENA-IN EN 1 8 HOST + _______ ] 8US-61580 , 7 2 PROCESSOR MEMENA-OUT . 5 CH.8 _____ PA TRANSPARENT/BUFFERED = e +5V 3 4 552 SELECT ADDRES: TX/AXB BeORESs b MEM/REG ROWA CPU STROBE STRBO CPU ACKNOWLEDGE READYD ATAD4-ATADO AT TAG_CLK ADORESS, PARITY +5V RTADP _ _ fn _ RESET MSTCLA Le Tr SSFLAG/EXT_TRIG CPU INTERRUPT REQUEST iNT FIGURE 33. 16-BIT TRANSPARENT MODE VII-73OG... BU-65170/61580 and BU-61585 CORPORATION? HOST BUS- PROCESSOR 65170/ ADDRESS 61580 DECODER FIGURE 34, 16-BIT TRANSPARENT MODE USING DUAL PORT RAM VII-74O8G __... BU-65170/61580 and BU-61585 CORPORATION: -15V +5V 16 MHZ CLOCK OSCILLATOR IN CPU 015-00 RO;WR CH. A CH. B CPU A1S-A0 AODRESS OECODER BUS-81586 EN TXIAXB MEMENA-OUT SELECT MEM/REG TRANSPARENT/BUFFERED STRBO REAOYD RTAD4-RTADO RT U ADDRESS, TAG_CLK PARITY RTADP MSTCLR TRIG =x CPU INTERRUPT REQUEST iNT FIGURE 35. 16-BIT DIRECT MEMORY ACCESS (DMA) MODEBOG ILC DATA DEVICE CORPORA |ON HOST PROCESSOR 18V +5V rl I BU-65170/61580 and BU-61585 16 MHZ CLOCK OSCILLATOR CPU 015-D0 D15-DO ROMWR ROAWR \7 MEMWR RAM Wa 64K X16MAX OE cs MEMOE DTREO OTGRT DTACK CPU A15-A0 A15-A0 > r MEMENA- IN > y MEMENA-OUT 1553 RAM MEM/AEG p> = } ADDRESS = DECODER 1553 REG SELECT 1 e TRANSPARENT/BUFFERED +5V CPU STROBE STABD CPU ACKNOWLEDGE READYD TAG_CLK +5V RESET MSTCLA ae = CPu INTERRUPT REQUEST SSFLAG/EXT_TRIG INT Vil-76 BUS-61580 CHA Crh.B K RTAD4-RTADO RT ADDRESS, PARITY RTADP FIGURE 36. 16-BIT DMA MODE WITH EXTERNAL LOGIC TO REDUCE PROCESSOR ACCESS TIME TO EXTERNAL RAMHOC ILC DATA DEVICE BU-651 70/61 580 and B U-61 585 CORPORATION. -15V +5V 16 MHZ CLOCK CLK OSCILLATOR IN 4 55Q CPU 07-00 D15-Da, D7-00 (NOTE 1) AAA . . 7 * el NC A15-A12 s CH. A CET CPU A12-A0 CPU A12-A1 *A1T-A0 [2 GPU ADDRESS LATCH (NOTE 2) ADDA-LAT Ks GPU AO MSB/LSB 8/16-BIT +5V <= TRANSPARENT/BUFFERED TX/AXB 552 . < = 1 8 o-.,_ (NOTES) POLARITY_SEL 2 ae ae CH. 8 +. (NOTE 4) ZERO WAIT 3 4 382 -_" Ee HOST Bus-61580 AXB PROCESSOR +... (NOTE 5) TRIGGER_SEL US-6 tc" SELECT ARORESS MEM/REG ROWR RDWA CPU STROBE. STRED |, .. CPU ACKNOWLEDGE | (NOTE 6) READYD RTAD4-RTADO at ADDRESS, TAG_CLK | DORES: +5V ATADP RESET MSTCLR ok _ x SSFLAG/EXT_TRIG CPU INTERRUPT REQUEST INT NOTES: 1. CPU D7 CONNECTS TO D15 ANO D7... CPU 00 CONNECTS TO D8 AND DO. 2. CPU ADDRESS LATCH SIGNAL PROVIDED BY PROCESSORS WITH MULTIPLEXED ADDRESS/DATA BUFFERS. 3. IF POLARITY SEL IS CONNECTED TO LOGIC "1", THEN MS8/ LSB SELECTS THE MOST SIGNIFICANT BYTE WHEN LOW, ANDO THE LEAST SIGNIFICANT BYTE WHEN HIGH IF POLARITY_SEL IS CONNECTED TO LOGIC "0", THEN MSB/ LSB SELECTS THE LEAST SIGNIFICANT BYTE WHEN LOW, AND THE MOST SIGNIFICANT BYTE WHEN HIGH. 4. ZERO WAIT SHOULO BE STRAPPED TO LOGIC "1" FOR NON-ZERO WAIT INTERFACE AND TO LOGIC "0" FOR ZERO WAIT INTERFACE 5. OPERATION OF TRIGGER_SELECT INPUTS AS FOLLOWS: FOR NON-ZERO WAIT INTERFACE (ZERO WAIT = 1"): IF TRIGGER_SEL = "1", THEN INTERNAL 16-BiT TRANSFERS ARE TRIGGERED BY THE Most SIGHIEICANT BYTE TRANSFER FOR READ ACCESSES ANI LEAST T SIGNIFICANT BYTE TRANSFER FOR WAITE A ACCESSES. IF TRIGGER_SEL = 0, THEN INTERNAL 16-B/T TRANSFERS ARE TRIGGERED BY THE LEAST SIGNIFICANT SYTE TRANSFER FOR READ ACCESSES AND BY THE MOST SIGNIFICANT BYTE TRANSFER FOR WRITE ACCESSES. FOR ZERO WAIT INTEREACE = ZERO WAIT = Tent IF TRIGGER_SEL = N INTERNAL 16-8!T TRANSFERS ARE TRIGGERED BY THE LEAST SIGNIFICANT BYTE TRANSFER, FOR BOTH READ AND WRITE ACCESSES. lf TRIGGER_SEL = 0", THEN INTERNAL 16-8!T. TRANSFERS ARE TRIGGERED BY THE MOST SIGNIFICANT BYTE TRANSFER, FOR BOTH READ AND WRITE ACCESSES. 6. CPU ACKNOWLEDGE PROCESSOR INPUT ONLY FOR NON-ZERO WAIT TYPE OF INTERFACE. * Additional address lines A12 and A13 are required with the BU-61585. FIGURE 37. 8-BIT BUFFERED MODE VII-77OG ILC DATA DEVICE CORPORATION? BU-65170/61580 and BU-61585 CLK IN SELECT (Note 2) STRBD {Note 2) MEM/REG (Notes 3, 4) AD/WR (Notes 3, 4) IGEN {Note 6) READYD (Note 6) A1S-AO {Notes 7, 8, 9) D1i5-D0 (Note 6) SYMBOL t2 {3 1 I" gc ff OS a foo" a ! / \ : ta : ' \ SSSA o Tae ETE TELE EDL LEE EEE I ' a \ oy : +13 # tii eti5 ' : ' C > | RS ae corre ween / 1 ' ' ' ' v ' ' ' t O ' ' 1 1 4 i t Ty aw----R---- I OTOP LV FU MOOT OTRO PIII Tn CET OEE, a TLL LLL, teste | : " ST ets! i ! ee ' tt { i Sees SSSA LLL, SELELLL LLL, LES, OPT OT, Ts : ' a mt ' ! iu tt eorye te Md as i tice if : 1 7 rt \ t10oae- t et12 5 1 i pa 4 ' \ ct if 1 ' : _ tt 9 tt ' ' t7 : C 4 aot Se vaL TO LEE ELE LEE t . 023 45 ! VALIO : : > * ' NOTE DESCRIPTION MIN | TYP UNITS | REFERENCE 10 ns note 2 low setup time prior ta CLOCK IN rising low delay to low (uncontended notes 2,6 low delay to tow (contended access notes 2,6 FIGURE 38. CPU READING RAM (SHOWN FOR 16-BIT, BUFFERED, NONZERO WAIT MODE) Vil-78Lc eat DEVICE CORPORATION BU-65170/61580 and BU-61585 Notes for FIGURE 38: 1. For the 16-bit buffered configuration, the inputs TRIGGER_SEL and MSB/LSB may be left unconnected (N/C). For the nonzero wait inter- face, ZERO_WAIT must be connected to logic "1." 2. SELECT and STRBD may be tied together. IOEN goes low on the first rising CLK edge when SELECT*STRBD is sampled low (satisfy- ing tz) and the BU-65170/61580's protocol/memory management logic is not accessing the internal RAM. When this occurs, IOEN goes low, starting the transfer cycle. After IOEN goes low, SELECT may be released high. 3. MEM/REG must be presented high for memory access, low for regis- ter access. 4. MEM/REG and ROWER are are buffered transparently until the first fall- ing edge of CLK after IC IGEN goes tow. After this CLK edge, MEM/REG and RD/WR become latched internally. aw . The logic sense for RDAWR in the diagram assumes that POLAR- ITY. SEL is connected to logic 1." If POLARITY _SEL is connected tu logic "0," RDAWR must be asserted low to read. . The timing for IOEN, READYD and 015-D0 assumes a 50pF load. For toading above 50pF, the validity of (OEN, READYD, and D15-00 is delayed by an additional 0.14ns/pF typ, 0.28ns/pF max. . Timing for A15-A0 assumes ADDR-LAT is connected to logic "1." Re- fer to Address Latch timing for additional details. . internal RAM is accessed by A11 through AO. Registers are ac- cessed by A4 through AO. _ The address bus A15-A0 is internally buffered transparently until the first rising edge of CLK after IOEN goes low. After this CLK edge, A15-A0 become latched internally. 10. Setup time given for use in worst case timing calculations. None of the ACE input signals are required to be synchronized to the systam clock. VII-79OOG BU-65170/61580 and BU-61585 CORPORATIONS CLK IN Legg OO ON EY F*F Nf Fe tees SELECT SEN ce AEE TLL TEE DEEL Zr Z Parl L . (Note 2) : Ho&ta ! ta : ' ' #e10 # H t124 __ ' : ' i . : STABO eee on a (Note 2) . ' ' : ros : ! | | MEM/REG SE SE Cem ON Te Zan DLA TEL a t > ? at - = ' t if ry {Notes 3, 4) i ts ts Weta rt | I ttt : tot i RD/WA SSMS SEM | AXE z LER Tr . v tT (Notes 3, 4) ' { it it : kee Pi Anes TOEN vor-~ ; Liege A (Note 6) ted say eS CO , : READYEC F a, (Note 6) : h ht? #- +1. + | i p! A1S5~AO WX VALIO EEE: OTE. (Notes 7,8, 9) : th "n 015-00 WT VALTS EEE EEEEEEZZEEZoEKAaa0a0E0EZEZEUEaoaxxc (Note 6) , Het? CPU WRITING RAM OR REGISTERS (SHOWN FOR 16-BIT, BUFFERED, NONZERO WAIT MODE) low delay to low (uncontended access notes 2,6 low delay to low (uncontended access notes 2,6 low delay to low (contended access @ . notes 2,6 tow delay to low (contended access @ - notes 2,6 from FIGURE 39. CPU WRITING RAM (SHOWN FOR 16-BiT, NONZERO WAIT STATE, BUFFERED MODE)OoG ILC DATA DEVICE CORPORATION? Notes for FIGURE 39: 1. For the 16-bit buffered contiguration, the inputs TRIGGER_SEL and MSB/LSB may be left unconnected (N/C). For the nonzero wait in- terface, ZERO_WAIT must be connected to logic "1." . SELECT and STRBD may be tied together. IOEN goes low on the first rising CLK edge when SELECTsSTRBD is sampied low (satisfy- ing te) and the BU-65170/61580's protocol/memory management logic is not accessing the internal RAM. When this occurs, IOEN goes fow, starting the transfer cycle. After IOEN goes low, SELECT may be released high. . MEM/REG must be presented high for memory access, low for reg- ister access. . MEM/REG and AD/WR are buffered transparently until the first fall- ing edge of CLK after |OEN goes low. After this CLK edge, MEM/REG and RD/WR become latched internally. . The logic sense for RO/WA in the diagram assumes that POLAR- {TY_SEL is connected to logic "1." if POLARITY SEL is connected to logic "0," RO/WR must be asserted high to write. BU-65170/61580 and BU-61585 . The timing for IOEN and READYD outputs assumes a 50pF load. For loading above 50pF, the validity of IOEN and READYD is de- layed by an additional 0.14ns/pF typ, 0.28 s/pF max. . Timing for A15-A0 assumes ADDR-LAT is connected to logic "1." Refer to Address Latch timing for additional details. . Internal RAM is accessed by A11 through AO. Registers are ac- cessed by A4 through AO. . The address bus A15-A0 and data bus D15-D0 are internally buff- ered transparently until the first rising edge of CLK after IOEN goes low. After this CLK edge, A15-A0 become latched internally. 10. Setup time given for use in worst case timing calculations. None of the ACE input signals are required to be synchronized to the sys- tem clock. Vil-84OOG a. BU-65170/61580 and BU-61585 CORPORATIONS SELECT INPUT SIGNALS A15-A0 ADDRESS_LAT /. 4 a{\ Pow oe s | SELECT Nf __ MSB/LSB INTERNAL a VALUES ; MEM/REG Nf A15-A0 (1) Xx (2) x (3) x (4) ADDRESS LATCH TIMING tt width t2 ADDR_LAT to internal to internal 3 from external to 14 to of ADDR_LAT 10 tS hold time of ADDR_LAT 10 Notes: ___ ___ 1. Applicable to Buffered Mode only. Address, SELECT, MSB/LSB, and MEM/REG latches are always transparent in the Transparent Mode of op- eration. 2. Latches are transparent when ADDR_LAT is high. internal values to no update when ADDR_LAT is low. 3. MSB/LSB input signal is applicable to 8-bit mode only (16/8 input = logic 0"). MSB/L SB input is a "dont care" for 16-bit operation. FIGURE 40. ADDRESS LATCH TIMING Vil-82BOG ILC DATA DEVICE CORPORATION? BU-65170/61580 and BU-61585 INTERFACE TO MIL-STD-1553 BUS FIGURE 41 illustrates the interface from the various versions of the ACE series terminals to a 1553 bus. The figure also indicates connections for both direct (short stub) and transformer (long stub) coupling, plus the peak-to-peak voltage levels that appear at various points (when transmitting). TABLE 8 lists the characteristics of the required isolation trans- formers for the various ACE terminals, the DDC and Beta Trans- former Technology Corporation corresponding part number, and the MIL (DESC) drawing number (if applicable). Beta Trans- former Technology is a direct subsidiary of DDC. For both coupling configurations, the isolation transformer is the transformer that interfaces. directly to the ACE component. For the transformer (long stub) coupling configuration, the trans- former that interfaces the stub to the bus is the coupling trans- former. The turns ratio of the isolation transformer varies, depending upon the peak-to-peak output voltage of the specific ACE terminal. The transmitter voltage of each model of the BU-65170/61580 varies directly as a function of the power supply voltage. The turns ratios of the respective transformers will yield a secondary voltage of approximately 28 volts peak-to-peak on the outer taps (used for direct coupling) and 20 volts peak-to-peak on the inner taps (used for stub coupling). In accordance with MIL-STD-15538B, the turns ratio of the cou- pling transformer is 1.0 to 1.4. Both coupling configurations require an isolation resistor to be in series with each leg connect- ing ta the 1553 bus; this protects the bus against short circuit conditions in the transformers, stubs, or terminal components. TABLE 8. ISOLATION TRANSFORMER GUIDE TURNS RATIO | RECOMENDED XFORMER ACE PART | DIRECT KFORMER SURFACE NUMBER COUPLEDCOUPLED| PLUG-IN MOUNT BU-85170X1 | 1.414:1 2:1 |BUS-25679, |B-2387, Sue saont B-2203, M21038/27-12, BU61s81xX1 M21038/27-02/B-2343, BU-61585X1 M21038/27-17, BU-61586X1 LPB-5002, LPB-5009, HLP-6002, HLP-6009 BU-65170X2} 1.20:1 1:0.6 |BUS-29854 |LPB-5001 BU-65171X2 LPB-5008 BU-61580X2 BU-61581X2 HIP-6001 BU-61585X2 HiP-6008 BU-61586X2| 1.25:1 B-2204, B-2388, (Note 5) M21038/27- 1M21038/27-13, 03 B-2344, M21038/27-18 BU-65170X3} 1:2.5 1:1.79 |B-3067 B-3072 BU-65171X3 BU-61580X3 BU-61581X3 BU-61585X3 BU-61586X3 BU-65170X6 BU-65171X6 BU-61580X6 BU-61581X6 BU-61585X6 BU-61586X6 Notes for TABLE 8 and FIGURE 41: (1) Shown for one of two redundant buses that interface to the BU- 65170 or BU-61580. (2) Transmitted voltage fevel on 1553 bus is 6 Vp-p min, 7 Vp-p nomi- nal, 9 Vp-p max. (3) Required tolerance on isolation resistors is 2%, Instantaneous power dissipation (when transmitting) is approximately 0.5 W (typ), 0.8 W (max). (4) Transformer pin numbering is correct for the DDC (e.g., BUS- 25679) transformers. For the Beta transformers (e.g., B-2203) or the QPL-21038-31 transformers (e.g., M21038/27-02), the winding sense and tums ratio are mechanically the same, but with reversed pin numbering; therefore, it is necessary to reverse pins 8 and 4 or pins 7 and 5 for the Beta or QPL transformers (Note: DDC trans- former part numbers begin with a BUS- prefix, while Beta trans- former part numbers begin with a B- prefix). (5)The B-2204, B-2388, and B-2344 transformers have a slightly differ- ent turns ratio on the direct coup!ed taps then the tums ratio of the BUS-29854 direct coupled taps. They do, however, have the same transformer coupled ratio. For transformer coupled applications, either transformer may be used. The transcevier in the BU- 65170X2 and the BU-61580X2 was designed to work with a 1:0.83 ratio for direct coupled applications. For direct coupled applica- tions, the 1.20:1 turns ration is recommended, but the 1.25:1 may be used. The 1.25:1 turns ratio will result in a slightly lower transmit- ter amplitude. (Approximateley 3.6% lower) and a slight shift in the ACEs receiver threshold. VH-83OG ILC DATA DEVICE BU-65170/61580 and BU-61585 CORPORATIONS DIRECT COUPLED (SHORT STUB) 20 78 Ne 259) 1.44 _ Ii | $5 7 TRI 14 WW | SOS 4 | | 1 FT MAX > BU-61580X1 | oy . VPP Te 38 isoLation 28 VPP TRANSFORMER oR TRANSFORMER COUPLED (LONG STUB) 24 11.4 ~ 2b, ta ' by ppt 20 FT MAX lg gy (9-75 Zo J c wy f ' E Te ( { r 51 y | 3 3 7 ! | i | 0.75 Z = lL . 39 VPP - 20 VPI ~ ISOLATION P COUPLING TRANSFORMER TRANSFORMER DIRECT COUPLED (SHORT STUB) 1:0.83 ~ ot 14 8 | 55 2 rae WW 2 IF = 1 FT MAX> BU-61580X2 a 1 oh . 33 VPP ~~ 28 VPP ISOLATION vp TRANSFORMER OR TRANSFORMER COUPLED {LONG STUB) 1:0.6 14 _ 1 14 7 | 20 FT MAX* 1g 4 _ BU-61580X3 BU-61580X6 ae TED Le eee oe oe 0.75 Zg 33 VPP 20 VPP ISOLATION COUPLING TRANSFORMER TRANSFORMER DIRECT COUPLED (SHORT STUB) 1:2.5 aS | 1 a} $5 2 . TRS Ww 1 Se 1 FT MAX > attest 4 MA: t Wy 1 ___! 52 11.6 VPP 28 VPP ISOLATION TRANSFORMER OR TRANSFORMER COUPLED (LONG STUB) 1:1.79 1:1.4 rn 4 =o . 14 7 | 20 FT MAX lg 4 5 7 lo f T T 3 >) 4 Fa3iits | | sits J | 1 T 0.75 Z 11.6 VPP 7 20 VPP bn ISOLATION COUPLING TRANSFORMER TRANSFORMER Z(70 to 850) Note: The BU-65170XX, BU-65171XX, BU-61581XX, BU-61585XX and BU-61586XX models are interfaced the same as the corresponding GU-61580XX model is shown (i.e. The BU-65170X1 is interfaced the same as the BU-61580X1). FIGURE 41. BU-65170/61580 INTERFACE TO A 1553 BUS ViH-84OOG ILC DATA OEVICE BU-65170/61580 and BU-61585 CORPORATION. TABLE 9. SIGNAL DESCRIPTIONS FOR BU-65170/61571, BU-61580/61585, BU-61586 (S OR V PACKAGE) PROCESSOR/MEMORY INTERFACE AND CONTROL (15) SIGNAL NAME PIN DESCRIPTION TRANSPARENT/ BUFFERED (I) 64 Used to select between the Transparent/(DMA mode (when strapped to logic 1) and the Buffered mode (when strapped to logic 0) for the host processor interface. STRBD (I) Strobe Data. Used with SELECT to initiate and contro! the data transfer cycle between the host processor and the BU- 65170/61580. SELECT (I) Generally connected to a CPU address decoder output to select the BU-65170/61580 for a transfer to/from either RAM or register. May be tied to STRBD. MEM/REG (I) Memory/Register. Generally connected to either a CPU address line or address decoder output. Selects between memory access (MEM/REG = 1) or register access (MEM/REG = 0). RD/WR (1) Read/Write. For a host processor access, selects between reading and writing. In the 16-bit buffered mode, if polarity selact is logic 0, them RD/WR is tow (logic 0) for read accesses and high (logic 1) for write accesses. If polarity select is logic 1 or the configuration of the interface is a mode other than 16-bit buffered mode, then RD/WR is high (logic 1) for read accesses and low (logic 0) for write accesses. TOEN (0) 67 Tri-state control for externa! address and data buffers. Generally not needed in the buffered mode. When low, external buffers should be enabled to allow the host processor access to the BU-65170/61580s RAM and registers. | READYD (0) 66 Handshake output to host processor. For a nonzero wait state read access, signals that data is available to be read on D15 through DO. For a nonzero wait state write cycle, signals the completion of data transfer to a register or RAM location. In the buffered zero wait state mode, active high output signal (following the rising edge of STRBD} used to indicate the latching of address and data (write only) and that an internal transfer between the address/data latches and the RAM/registers is on-going. INT (0) 65 Interrupt request output. If the LEVEL/PULSE interrupt bit (bit 3) of Configuration Register #2 is low, a negative pulse of approximately 500 ns in width is output on INT. If bit 3 is high, a low level interrupt request output will be asserted on iNT. BTREQ (0) N68 () 31 Data Transfer Request or 16-bit/8-bit Transter Mode Select. in transparent mode, active low output signal used to request access to the processor interface bus (address,data, and contro} buses). in buffered mode, input signal used to select between the 16-bit data transfer mode (16/8 = logic 1) and the 8 bit data transfer mode (16/8 = logic 0). DTGRT (1) /MSB/LSB (1) Data Transfer Grant or Most Significant Byte/Least Significant Byte. In transparent mode, active low input signal asserted, in response to the DTREQ output, to indicate that access to the processor buses has been granted to the BU- 65170/61580. In 8-bit buffered mode, input signal used to indicate which byte is being transferred (MSB or LSB). The POLARITY_SEL input controls the logic sense of MSB/LSB. (Note: only the 8-bit buffered mode uses MSB/LSB.) See description of POLARITY _SEL signal. N/C in 16-bit buffered mode. BTACK (O)/ POLARITY_SEL (1) 32 Data Transfer Acknowledge or Polarity Select. In transparent mode, active low output signal used to indicate acceptance of the processor interface bus in response to a data transfer grant (OTGRT). In 16-bit buffered mode (TRANSPARENT/ BUFFERED = logic 0 and 16/8 = logic 1), input signal used to control the logic sense of the RD/AWR signal. When POLARITY_SEL is logic 1, ROAWR must be asserted high (logic 1) for a read operation and low (logic 0) for a write operation. When POLARITY_SEL is lagic 0, RD/WR must be asserted low (logic 0) for a read operation and high (logic 1) for a write operation. In &-bit buffered mode (TRANSPARENT/BUFFERED = logic 0 and 16/8 = logic 0), input signal used to control the logic sense of the MSB/LSB signal. When POLARITY_SEL is logic 0, MSB/LSB must be asserted low (logic 0) to indicate the transfer of the least significant byte and high (logic 1) to indicate the transfer of the most significant byte. When POLARITY_SEL is Sogic 1, MSB/LSB must be asserted high (logic 1) to indicate the transfer of the least significant byte and low (logic 0) to indicate the transter of the most significant byte. MEMENA-OUT Memory Enable Output. Asserted low during both host processor and 1553 protocol/memory management memory trarisfer cycles. Usad as a memory chip select (C5) signal for external RAM in the transparent mode. {Od __ MEMENA-IN (|) /TRIGGER_SEL (1) Memory Enable Input or Trigger Select. In transparent mode, MEMENA-IN is an active low Chip Select (CS} input to the 4K x 16 of internal shared RAM. When only using internal RAM, connect directly to MEMENA-OUT. In &-bit buffered mode, the input signal (TRIGGER_SEL) indicates the order of byte pairs transfer to or from the BU- 65170/61580 by the host processor. This signal has no operation (can be N/C) in the 16-bit buffered mode. In the 8-bit buffered mode, TRIGGER_SEL should be asserted high (logic 1) if the byte order for both read operations and write operations is MSB followed by LSB. TRIGGER_SEL should be asserted low (logic 0) if the byte order for both read operations and write operations is LSB followed by MSB. MEMOE (0)/ ADDR_LAT (I) 29 Memory Output Enable or Address Latch. In transparent mode, MEMOE output will be used to enable data outputs for external RAM read cycles (normally connected to the OE signal on external RAM chips). In buffered mode, ADDR_LAT input will be used to configure the internal address latches in latched mode (when low) or transparent mode (when high). MEMWR (0) fZERO_WATT (I) 30 Memory Write or Zero Wait State. In trans-parent mode, active low output signal (MEMWR ) will be asserted low during memory write transfers to strobe data into internal or external RAM (normally connected to the WR signal on external RAM chips). In buffered mode, input signal (ZERO_WAIT) will be used to select between the zero wait mode (ZERO, WAIT = logic 0) and the nonzero wait mode (ZERO_WAIT = logic 1). VIl-85OG ILC DATA DEVICE CORPORATION 2 TABLE 9. (continued) BU-65170/61580 and BU-61585 AND ADDRESS BUS (16) SIGNAL +5V LOGIC +5V NAME PIN DESCRIPTION GND A15(MSB) [8 16-bit bidirectional address bus. In both -15(-12)VA CH. A -15V(-1 Ai4 9 the buffered and transparent modes, the A CH. A+5V A13 19 {host CPU accesses the BU-65170/61580 GNDA CH. AT A? 14 registers and 4K words of internal RAM by 15(- -15V(-1 All 12 A11 through AO (BU-61585 uses A13 +5VB CH. B +5V AiO 13 through AO). The host CPU performs GNDB 37. |CH. B Transceiver Ground register selection by A4 through A0.In the : A0g 14__|buffered mode, A15-A0 are inputs only. In for BU-65170/61580X6. A08 15 __|the transparent mode, A15-A0 are inputs AO7 16 _|during CPU accesses and drive outward DATA BUS (16) A06 17. |(towards the CPU} when the 1553 | SIGNAL NAME | PIN DESCRIPTION AOS 29 |protocol/memory management logic Di5 (MSB) 62 [16-bit bidirectional data bus. This bus A04 31. |accesses up to 64K x 16 of external RAM. 014 61_|interfaces the host processor to the internal A083 99 |The address bus drives outward only in D413 60 |registers and 4K words of RAM(12K of A02 23 me transparent mode nen re signe Di2 59 _|RAM for the BU-61585). In addition, in the A01 24 In fe omen icating t at ne a D114 58 |\transparent mode, this bus allows data 7A00 35 as contro! of the processor interlace us) D10 57 | transfers to take place between the internal and IOEN is high {indicating that this is not Dog 56 Protocol/memory management logic and up a CPU access). Most of the time, including DOs 55 |to 64K x 16 of external RAM. Most of the immediately after power turn-on RESET, DOT 5g |time, the outputs for 016 through DO are in ne viene peels will be in their DOE 52 |their high impedance state. They drive isabled (high impedance) state. Dos 54 outward in the buffered or transparent Do4 50 mode when the hast CPU reads the D03 49 internal RAM or registers. Or, in the Do2 48 trasparent mode, when the protocol/memory management logic is Dot 47 accessing (either reading or writing) DOO (LSB) 46 |. nternal RAM or writing to external RAM. 1553 ISOLATION TRANSFORMER INTERFACE (4) SIGNAL NAME PIN DESCRIPTION TX/AX-A_{I/O) 1__|Analog Transmit/Receive Input/Outputs. TX/RX-A (I/O) 2 |Connect directly to 1553 isolation TX/AX-B (1/0) | 34 |}transformers. TX/RX-B (I/O) | 35 RT ADDRESS (6) SIGNAL NAME | PIN DESCRIPTION [RTAD4 (MSB) | 43 [Remote Terminal Address Inputs () ATADS (}) 42 ATAD2 (i) 41 ATAD1 (1) 40 RTADO (LSB) | 39 () RTADP (I) 44 |Remote Terminal Address Parity. Must provide odd parity sum with RTAD4-RTADO in order for the RT to respond to non- broadcast commands. VII-86BOC ILC DATA DEVICE CORPORATION BU-65170/61580 and BU-61585 TABLE 9. (continued) MISCELLANEOUS (7) DESCRIPTION SIGNAL NAME | PIN CLOCK IN (I) 19 |16MHz (or 12MHz) clock input. MSTCLR (1) 7 |Master Clear. Negative true Reset input, normally asserted low following power turn-on. Requires a minimum 100ns negative pulse to reset all internal logic to its power turn-on state. In Command. In BC mode, asserted low throughout processing cycle for each message. In RT mode or Message Monitor mode, asserted low following receipt of Command Word and kept low until completion of current message sequence. In Word Monitor mode, goes low following MONITOR START command, kept low while monitor is on-line, goes high following RESET command. SSFLAG (i)/ 27 | Subsystem Flag or External Trigger input. In the Remote Terminal mode, asserting this input , will set the Subsystem EXT_TRIG (1) Flag bit in the BU-65170/61580s RT Status Word. A iow on the SSFLAG input overrides a logic 1 of the respective bit (bit 8) of Configuration Register #1. In the Bus Controller mode, an enabled external BC Start option (bit 7 of Configuration Register #1) and a iow-to-high transition on this input will issue a BC Start command, starting execution of the current BC frame. In the Word Monitor mode, an enabled external trigger (bit 7 of Configuration Register #1) and a low-to-high transition on this input will issue a monitor trigger. TAG_CLK (I) 63 | External Time Tag Clock input. Use may be designated by bits 7, 8, and 9 of Configuration Register #2. When used it increments the internal Time Tag Register/Counter. If not used, should be connected to +5V or ground. TX_INH_A (I) 70 _|Option for BU-65170/61580X6 and the BU-61585X6. Inhibits (disables) the respective (A/B) MIL-STD-1553 transmitter TX_INH_B (I) 36 |when asserted to logic 1. INCMD {O) 45 TABLE 10. BU-65170/65171, TABLE 10, BU-65170/65171, TABLE 10. BU-65170/65171, BU-61580/61581/61585/61586 BU-61580/61581/61585/61586 BU-61580/61581/61585/61586 PIN LISTINGS PIN LISTINGS PIN LISTINGS _{(S or V package) (S or V package) orv PIN NAME PIN NAME 1 TX/RX-A 28 _|MEMENA_OUT 2 | TX/RAX-A 29 _|MEMOE/ADDR_LAT 3. |SELECT 30 _|MEMWR/ZERO_WAIT 4 __|STRBD 31 [DTREQ/16/8 5 _|MEM/REG 32__ |DTACK/POLARITY_SEL 6 _|RDWR 33. |MEMENA_IN/TRIGGER_SEL 7__|MSTCLR 34 _ | TX/RX-B 8 _|A15 35 | TX/RX-B 9 A14 36 -VB (see note) 10 _|A13 37__|GNDB 11 |A12 38 __|+5VB 12 |A14 39 _{RTADO 13. |A10 40 _|RTAD1 67 14 |Ao9 41__ |RTAD2 68 |[45VA 15 _|A08 42 __|RTAD3 69 |GNDA 16 __|A07 43 |RTAD4 70__|-VA note 17 |A06 44 _{RTADP 18 GND 45 INCMD -15V for BU-65170/61580X1. -12V for BU-65170/61580X2. 19 |CLK 46 __|D00 NG for BU-85170/61580X3. 20 |A05 47__|D01 21 |A04 48 |D02 For BU-65170/61580X6: 22_|{ao3 49_|Dos Fin 70 ie CINHLA 23 |Ao2 50 |D04 24 _|A01 51 [DOS 25 [Aco 52 _|D06 26 _|DTGRT/MSB/LSB : 53 __|D07 27__ | SSFLAG/EXT_TRIG 54 _|+5V LOGIC VU-87OOG BU-65170/61580 and BU-61585 CORPORATION? ~~ ww 0.165 MAX (4.191) ' : 0.180 +0.010 TYP I reer ' ooo wx TOT a ne i O57 20.28) i (48.26) * NOTE 3 9.100 (2.54) i. , pt | OVP VOOGDO OO OOO9O0O, ay @OOODOOHOOOOOOOOS, | 0.400 asoo | 1.000 MAX (10.16) (18.24) (25.4) SEENOTE2 SEENOTE2 pt ~DDOOHOGO9DOOOOOOOE, =$-__1_|*SO@OOO0OO8O0000000q) 0.018 +0.002 DIA TYP | |, i (0.46 40.05) ot ot | he 0.100 TYP (254) | 0.050 TYP-= ti N\ (27) | be. 4.600 (40.64) SEE NOTE 2 a | peNoES we 1,700 (49.18) SEE NOTE 2 PIN NOTES: 1. DIMENSIONS ARE IN INCHES (MILLIMETERS). 2. LEAD CLUSTER TO BE CENTRALIZED WITH 10.010 (0.25) OF CASE CENTER LINE 9. PIN NUMBERS ARE FOR REFERENCE ONLY FIGURE 42. BU-65170/65171SX, BU-65180/61581SX, BU-61585/61586SX MECHANICAL OUTLINE \ 1.900 MAX Cr 43.26) ~ 0.010 26.002 TYP | (0.25 +0.05) | i oetate) rt 1 wo MAX (25.4) 7 | SEE NOTE 3 | fe-0.050 TYP (1.27) alh Wi | | oo gnene we-= == 1.700 (43.18) SEE NOTE 2 --~l ae 0.550 MAX _rseeeseaunassnecovesonnenscsean 1 an INDEX DENOTES PIN + i NOTES 1. DIMENSIONS ARE IN INCHES (MILLIMETERS) 2. LEAO CLUSTER TO BE CENTAALIZED WITH +0.010 (10.25) OF CASE CENTER LINE 3 PIN NUM@EAS ARE FOR REFERENCE ONLY FIGURE 43. BU-65170/65171VX, BU-65180/61581VX, BU-61585/61586VX MECHANICAL OUTLINE Vil-88OOG BU-65170/61580 and BU-61585 CORPORATIONS ORDERING INFORMATION BU-61580 $ 3 - 1 7 L Test Criteria: Q = None Screening: Commercial Screening Fully compliant to MIL-STD-883 and DESC Screened to MIL-STD-883 but without QCI testing 883B and DESC and PIND testing 883B and DESC and Solder Dip 883B and DESC and PIND and Solder Dip Temperature Range: 1 = 55 to +125C 1 3 4 5 3 = Oto +70C Voltage/Transceiver Option: 0 = Transceiverless 1 = +5/-15 V (1760 compliant)* 2 = +5/-12V 3 = +5 V only 6 = +5 V only with Tx Inhibits brought out on negative supply pins Package: S= Dip V= Flat Pack Product Type: 65170 = 70-pin RT 66171 = 70-pin RT with latched RT address option 61580 = 70-pin BC/RT/MT 61581 = 70-pin BC/RT/MT with latchable RT address option 61585 = 70-pin BC/RT/MT with 8K x 17 RAM 61586 = 70-pin BC/RT/MT with 8K x 17 RAM and RT address option * Contact factory about 1760 compliance. Note: The ACE series is also available to DESC drawing number 5962-93065. VII-89