1
©2004 Integrated Device Technology, Inc.
APRIL 2004
DSC-5675/4
I/O
Control
Address
Decoder
A
12L
(1)
A
0L
MEMORY
ARRAY
ARBITRATION
INTERRUPT
SEMAPHORE
LOGIC
OE
L
R/W
L
CE
L
5675 drw 01
OE
R
R/W
R
CE
R
SEM
L
INT
L
M/S
SEM
R
INT
R
(3) (3)
13 13
A
12R
(1)
A
0R
Address
Decoder
I/O
Control
BUSY
L
I/O
8L
-I/O
15L
I/O
0L
-I/O
7L
BUSY
R
I/O
8R
-I/O
15R
I/O
0R
-I/O
7R
(2,3) (2,3)
,
INPUT
READ REGISTER
AND
OUTPUT
DRIVE REGISTER
OE
L
R/W
L
CE
L
OE
R
R/W
R
CE
R
IRR
0
,IRR
1
ODR
0
-
ODR
4
R/W
L
UB
L
LB
L
CE
L
OE
L
R/W
R
UB
R
LB
R
CE
R
OE
R
SFEN
IDT70P258/248L
VERY LOW POWER 1.8V
8K/4K x 16 DUAL-PORT
STATIC RAM
Features
◆◆
◆◆
◆True Dual-Ported memory cells which allow simultaneous
reads of the same memory location
◆◆
◆◆
◆High-speed access
– Industrial: 55ns (max.)
◆◆
◆◆
◆Low-power operation
IDT70P258/248L
Active: 27mW (typ.)
Standby: 3.6
µ
W (typ.)
◆◆
◆◆
◆Separate upper-byte and lower-byte control for multiplexed
bus compatibility
◆◆
◆◆
◆IDT70P258/248 easily expands data bus width to 32 bits or
more using the Master/Slave select when cascading more
than one device
◆◆
◆◆
◆M/S = VDD for BUSY output flag on Master
M/S = VSS for BUSY input on Slave
◆◆
◆◆
◆Input Read Register
◆◆
◆◆
◆Output Drive Register
◆◆
◆◆
◆BUSY and Interrupt Flag
◆◆
◆◆
◆On-chip port arbitration logic
◆◆
◆◆
◆Full on-chip hardware support of semaphore signaling
between ports
◆◆
◆◆
◆Fully asynchronous operation from either port
◆◆
◆◆
◆LVTTL-compatible, single 1.8V (±100mV) power supply
◆◆
◆◆
◆Available in 100 Ball 0.5mm-pitch BGA
◆◆
◆◆
◆Industrial temperature range (-40°C to +85°C)
Functional Block Diagram
NOTES:
1. A12X is a NC for IDT70P248.
2. (MASTER): BUSY is output; (SLAVE): BUSY is input.
3. BUSY outputs and INT outputs are non-tri-stated push-pull.
◆◆
◆◆
◆Supports 3.0V, 2.5V and 1.8V I/O's
6.42
IDT70P258/248L
Low Power 1.8V 8K/4K x 16 Dual-Port Static RAM Industrial Temperature Range
2
Description
The IDT70P258/248 is a very low power 8K/4K x 16 Dual-Port
Static RAM. The IDT70P258/248 is designed to be used as a stand-alone
128/64K-bit Dual-Port SRAM or as a combination MASTER/SLAVE Dual-
Port SRAM for 32-bit-or-more word systems. Using the IDT MASTER/
SLAVE Dual-Port SRAM approach in 32-bit or wider memory system
applications results in full-speed, error-free operation without the need for
additional discrete logic.
This device provides two independent ports with separate control,
address, and I/O pins that permit independent, asynchronous access for
reads or writes to any location in memory. An automatic power down
feature controlled by CE permits the on-chip circuitry of each port to enter
a very low standby power mode.
Fabricated using IDT’s CMOS high-performance technology,
these devices typically operate on only 27mW of power.
The IDT70P258/248 is packaged in a 100 ball 0.5mm- pitch Ball
Grid Array. The package is a 1mm thick and designed to fit in wireless
handset applications.
Pin Configurations(2,3,4)
C10
D8
C8
A9
D9
C9
B9
D10
C7
B8
A8 A10
D7
B7
A7
B6
C6
D6
A5
B5
C5
D5
A4
B4
C4
D4
A3
B3
C3
D3
D2
C2
B2
A2A1
B1
C1
D1
E1 E2 E3 E4
F1 F2 F3 F4
G1 G2 G3 G4
H1 H2 H3 H4
J1 J2 J3 J4
K1 K2 K3 K4
A6
B10
E5 E6 E7 E8 E9 E10
F5 F6 F8 F9 F10
G5 G6 G7 G8 G9 G10
H5 H6 H7 H8 H9 H10
J5 J6 J7 J8 J9 J10
K5 K6 K7 K8 K9 K10
F7
5675 drw 02b
,
09/04/03
A
5R
A
8R
A
11R
UB
R
Vss VssSEM
R
I/O
15R
I/O
12R
I/O
10R
Vss
VssA
6R
I/O
7R
I/O
11R
I/O
14R
A
2R
A
1R
A
0R
LB
R
Vss Vss
SFEN Vss
Vss
V
DD
A
3R
A
7R
A
9R
CE
R
R/W
R
OE
R
I/O
9R
I/O
6R
A
4R
V
DD
V
DD
A
12R
(1)
A
10R
INT
R
I/O
13R
I/O
5R
BUSY
R
I/O
2R
ODR
2
ODR
4
I/O
8R
M/SODR
3
INT
L
IRR
1
I/O
4R
I/O
1R
ODR
1
BUSY
L
A
1L
NC NC
OE
L
I/O
0R
I/O
3R
I/O
15L
V
DDQL
ODR
0
A
2L
A
5L
A
12L
(1)
V
DD
I/O
3L
I/O
11L
I/O
12L
I/O
14L
I/O
13L
A
0L
A
4L
A
9L
LB
L
CE
L
I/O
1L
V
DDQL
I/O
10L
A
3L
A
7L
A
10L
IRR
0
I/O
4L
I/O
6L
I/O
8L
I/O
9L
A
6L
A
8L
A
11L
UB
L
SEM
L
R/W
L
I/O
0L
I/O
2L
I/O
5L
I/O
7L
Vss
70P258/248BY
BY-100
100-Ball 0.5mm Pitch BGA
Top View(5)
NOTES:
1. A12X is a NC for IDT70P248.
2. All VDD pins must be connected to power supply.
3. All VSS pins must be connected to ground supply.
4. BY100-1 package body is approximately 6mm x 6mm x 1mm, ball pitch 0.5mm.
5. This package code is used to reference the package diagram.
6. This text does not indicate orientation of the actual part-marking.
6.42
IDT70P258/248L
Low Power 1.8V 8K/4K x 16 Dual-Port Static RAM Industrial Temperature Range
3
Pin Names
Left Port Right Port Names
CE
L
CE
R
Chip E nab le (Input)
R/W
L
R/W
R
Re ad /Wri te E nable (Inp ut)
OE
L
OE
R
Outp ut Enab le (Input)
A
0L
- A
12L
(1)
A
0R
- A
12R
(1)
Address (Input)
I/O
0L
- I/ O
15L
I/O
0R
- I/O
15R
Data Inp ut/O utp ut
SEM
L
SEM
R
S e map ho re Enab le (Input)
UB
L
UB
R
Upper Byte Select (Input)
LB
L
LB
R
Lo we r By te Se le c t (Inp ut)
INT
L
INT
R
Inte rrup t Flag (Outp ut)
BUSY
L
BUSY
R
Busy Flag
IRR
0
, IRR
1
Input Read Register (Input)
ODR
0
- ODR
4
Output Drive Register (Output)
SFEN
(2)
Special Func tio n Enab le (Input)
M/SMaster or Slave Select (Input)
V
DD
P o wer (1. 8V ) (Inp ut)
V
DDQL
Left Port I/O Supply Voltage
(3.0V ) (Inp ut)
V
SS
Ground (0V) (Inp ut)
5675 tb l 01
NOTE:
1. A12X is a NC for IDT70P248.
2. SFEN is active when either CEL = VIL or CER = VIL.
SFEN is inactive when CEL = CER = VIH.
NOTE:
1. A0L — A12L ≠ A0R — A12R
Truth Table I: Non-Contention Read/Write Control
Inputs
(1)
Outputs
Mode
CE R/WOE UB LB SEM I/O
8-15
I/O
0-7
H X X X X H Hig h-Z Hig h-Z De s e le c ted : P o wer Do wn
X X X H H H High-Z High-Z Both Bytes De sele cted
LLXLHHDATA
IN
High-Z Write to Upper Byte Only
LLXHLHHigh-ZDATA
IN
Write to Lowe r Byte Only
LLXLLHDATA
IN
DATA
IN
Write to Bo th By tes
LHLLHHDATA
OUT
Hig h-Z Re ad Up p e r B yte Onl y
LHLHLHHigh-ZDATA
OUT
Read Lower By te Only
LHLLLHDATA
OUT
DATA
OUT
Read Both Bytes
X X H X X X High-Z High-Z Outputs Disabled
5675 tb l 02
6.42
IDT70P258/248L
Low Power 1.8V 8K/4K x 16 Dual-Port Static RAM Industrial Temperature Range
4
Truth Table II: Semaphore Read/Write Control(1)
NOTE:
1. There are eight semaphore flags written to via I/O0 and read from all of the I/O's (I/O0-I/O15). These eight semaphores are addressed by A0-A2.
Inputs Outputs
Mode
CE R/WOE UB LB SEM I/O
8-15
I/O
0-7
HHLXXLDATA
OUT
DATA
OUT
Re ad Data in S e map ho re F lag
XHLHHLDATA
OUT
DATA
OUT
Re ad Data in S e map ho re F lag
H↑XXXLDATA
IN
DATA
IN
Wri te D
IN0
into Semaphore Flag
X↑XHHLDATA
IN
DATA
IN
Wri te D
IN0
into Semaphore Flag
LXXLXL
____ ____
No t All o we d
LXXXLL
____ ____
No t All o we d
5675 tb l 03
Absolute Maximum Ratings(1)
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
2. VTERM must not exceed VDD + 0.3V for more than 25% of the cycle time or 10ns
maximum, and is limited to < 20mA for the period over VTERM = VDD + 0.3V.
3. Ambient Temperature under DC Bias. No AC Conditions. Chip Deselected.
4. VDDQLMAX + 0.3V for left port.
Symbol Rating Commercial
& Industri al Unit
V
TERM
(2) Te rminal Vo ltag e with
Re s p e c t to GND -0.5 to V
DDMAX
+0.3V(4) V
T
BIAS
(3) Te mperature Und e r Bi as -55 to + 125
o
C
T
STG
Sto rag e Te mp erature -65 to +150
o
C
T
JN
Junctio n Te mpe rature +150
o
C
I
OUT
(for
V
DDQL
=
3.0V) DC Output Curre nt 20 mA
I
OUT
(for
V
DDQL
=
1.8V) DC Output Curre nt 20 mA
5675 tbl 04
6.42
IDT70P258/248L
Low Power 1.8V 8K/4K x 16 Dual-Port Static RAM Industrial Temperature Range
5
Capacitance
(TA = +25°C, f = 1.0MHz)
NOTES:
1. This parameter is determined by device characterization but is not production
tested.
2. 3dV references the interpolated capacitance when the input and output signals
switch from 0V to 3V or from 3V to 0V.
Symbol Parameter Conditions
(2)
Max. Unit
C
IN
Inp ut Ca p acitan ce V
IN
= 3dV 9 pF
C
OUT
Output Capac i tance V
OUT
= 3d V 11 pF
5675 tbl 07
Maximum Operating Temperature
and Supply Voltage(1)
NOTES:
1. This is the parameter TA. This is the "instant on" case temperature.
Grade Ambient
Temperature GND V
DD
Industrial -40
O
C to +85
O
C0V1.8V
+
100mV
5675 tb l 05
Recommended DC Operating Conditions (VDDQL = 3.0V±300mV)
NOTES:
1. VIL > -1.5V for pulse width less than 10ns.
2. VTERM must not exceed VDD + 0.3V.
3. SFEN operates at the 1.8V VIH and VIL voltage levels.
4. M/S operates at the VDD and VSS voltage levels.
Symbol Parameter Min. Typ. Max. Unit
V
DD
Supply Voltage
(4)
1.7 1.8 1.9 V
V
DDQL
Left Port Supply Voltage 2.7 3.0 3.3 V
V
SS
Ground 0 0 0 V
V
IHL
Input High Voltage (V
DDQL
= 3.0V) 2.0
___
V
DDQL
+ 0.2 V
V
ILL
Input Low Voltage (V
DDQL
= 3.0V) -0.2
___
0.6 V
V
IHR
Input High Voltage
(3)
1.2
___
V
DD
+ 0.2 V
V
ILR
Input Low Voltage
(3)
-0.2
___
0.4 V
5675 tbl 06
Symbol Parameter Min. Typ. Max. Unit
V
DD
Supply Voltage
(4)
1.7 1.8 1.9 V
V
DDQL
Left Port Supply Voltage 2.4 2.5 2.6 V
V
SS
Ground 0 0 0 V
V
IHL
Input High Voltage (V
DDQL
= 2.5V) 1.7
___
V
DDQL
+ 0.3 V
V
ILL
Input Low Voltage (V
DDQL
= 2.5V) -0.3
___
0.7 V
V
IHR
Input High Voltage
(3)
1.2
___
V
DD
+ 0.2 V
V
ILR
Input Low Voltage
(3)
-0.2
___
0.4 V
5675 tbl 06_5
Recommended DC Operating Conditions (VDDQL = 2.5V±100mV)
6.42
IDT70P258/248L
Low Power 1.8V 8K/4K x 16 Dual-Port Static RAM Industrial Temperature Range
6
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range (VDD = 1.8V ± 100mV)
Symbol Parameter Test Co nditi ons Min. Max. Unit
I
LI
Input Leakage Current V
DD
= 1.8V, V
IN
= 0V
to
V
DD
___
1µA
I
LO
Output Leakage Current CE = V
IH
, V
OUT
= 0V
to
V
DD
___
1µA
V
OLL
Output Low Voltage (V
DDQL
= 3.0V) I
OLL
= +2mA
___
0.4 V
V
OHL
Output High Voltage (V
DDQL
= 3.0V) I
OHL
= -2mA 2.1
___
V
V
OLL
Output Low Voltage (V
DDQL
= 2.5V) I
OLL
= +2mA
___
0.4 V
V
OHL
Output High Voltage (V
DDQL
= 2.5V) I
OHL
= -2mA 2.0
___
V
V
OLR
Output Low Voltage I
OLR
= +0.1mA
___
0.2 V
V
OHR
Output High Voltage I
OHR
= -0.1mA V
DD
- 0.2V
___
V
5675 tbl 08
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range (VDD = 1.8V ±100mV)
NOTES:
1. VDD = 1.8V, TA = +25°C, and are not production tested. IDD DC = 15mA (typ.)
2. At f = fMAX, address and control lines are cycling at the maximum frequency read cycle of 1/tRC, and using “AC Test Conditions”.
3. Port "A" may be either left or right port. Port "B" is the opposite from port "A".
4 . If M/ S = V SS, then f BUSYL = fBUSYR = 0 for full standby mode.
70P258/248
Ind'l Only
Sym b ol P aram eter Test Cond i ti on Ver si on Typ .
(1)
Max. Unit
I
DD
Dy nami c Op erating Curre nt
(B o th Po rts Active ) CE = V
IL
, Outputs Op e n
f = f
MAX
(2)
IND'L L 15 25 mA
I
SB1
Standb y Curre nt ( Bo th P o rts
Inactive) CE
R
and CE
L
= V
IH,
SEM
R =
SEM
L =
V
IH
f = f
MAX
(2)
IND'L L 28µA
I
SB2
Stand b y Current (One Po rt
In acti ve, On e Po r t A c ti ve) CE"
A
" = V
IL
and CE"
B
" = V
IH
(3)
, Active Po rt Outputs Op en
f = f
MAX
(2)
IND'L L 8.5 14 mA
I
SB3
Full Standby Current (Both
Ports Inactive - CMOS Level
Inputs)
Both Ports CE
L
and CE
R
> V
DD
- 0. 2V,
SEM
L
and SEM
R
> V
DD
- 0. 2V, V
IN
> V
DD
- 0.2V or V
IN
< 0.2V
M/S = V
DD
or
V
SS
(4)
,
f = 0 IND'L L 2 8 µA
I
SB4
Stand b y Current (One Po rt
In acti ve, On e Po r t A c ti ve -
CMO S Lev e l Inp uts )
CE
"A"
< 0. 2V an d CE
"B"
> V
DD
- 0. 2V
(4)
V
IN
> V
DD
- 0.2V or V
IN
< 0.2V, A ctive Port Outp uts Op en
f = f
MAX
(2)
IND'L L 8.5 14 mA
5675 tb l 09
6.42
IDT70P258/248L
Low Power 1.8V 8K/4K x 16 Dual-Port Static RAM Industrial Temperature Range
7
R1
R2
30pF
(1)
3.0V
/
1.8V
5675 drw 03
Figure 1. AC Output Test Load
(5pF for tLZ, tHZ, tWZ, tOW)
3.0V 1.8V
R1 1022Ω13500Ω
R2 729Ω10800Ω
5675 tbl 10_5
Timing of Power-Up Power-Down
5675 drw 04
t
PU
I
CC
I
SB
t
PD
CE
50% 50
%,
AC Test Conditions
In p u t Pul s e L e vel s
In p u t Ri s e /F al l Tim e s
In p u t Ti m i ng Refer e n c e L e ve l s
Outp ut Re fe re nc e Le v els
Outp ut Load
GND to 3.0V /GND to 1. 8V
3ns Max.
1.5V/0.9V
1.5V/0.9V
Figure 1
5675 tbl 10
6.42
IDT70P258/248L
Low Power 1.8V 8K/4K x 16 Dual-Port Static RAM Industrial Temperature Range
8
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage Range(4)
NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage with Output Test Load.
2. This parameter is guaranteed by device characterization, but is not production tested.
3. To access RAM, CE = VIL, UB or LB = VIL, and SEM = VIH. To access semaphore, CE = VIH or UB and LB = VIH, and SEM = VIL.
4. The specification for tDH must be met by the device supplying write data to the SRAM under all operating conditions. Although tDH and tOW values will vary over
voltage and temperature, the actual tDH will always be smaller than the actual tOW.
5. At any given temperature and voltage condition, tHZ is less than tLZ for any given device.
70P258/248
Ind'l Only
UnitSymbol Parameter Min. Max.
READ CYCLE
t
RC
Re ad Cy c le Ti me 55
____
ns
t
AA
Ad dress Access Time
____
55 ns
t
ACE
Chip Enable Access Time
(3) ____
55 ns
t
ABE
Byte Enable Access Time
(3) ____
55 ns
t
AOE
Output Enable Access Time
(3) ____
30 ns
t
OH
Output Hold from Address Change 5
____
ns
t
LZ
Output Low-Z Time
(1,2,5)
5
____
ns
t
HZ
Output High-Z Time
(1,2,5) ____
25 ns
t
PU
Chip Enable to Po we r Up Time
(1,2)
0
____
ns
t
PD
Chi p Di sab l e to P o we r Do wn Ti me
(1,2) ____
55 ns
t
SOP
Semaphore Flag Update Pulse (OE or SEM)15
____
ns
t
SAA
Semaphore Address Access
(3) ____
55 ns
5675 tbl 1
1
6.42
IDT70P258/248L
Low Power 1.8V 8K/4K x 16 Dual-Port Static RAM Industrial Temperature Range
9
t
RC
R/W
CE
ADDR
t
AA
OE
UB,LB
5675 drw 05
(4)
t
ACE
(4)
t
AOE
(4)
t
ABE
(4)
(1)
t
LZ
t
OH
(2)
t
HZ
(3,4)
t
BDD
DATA
OUT
BUSY
OUT
VALID DATA
(4)
,
Waveform of Read Cycles(5)
NOTES:
1. Timing depends on which signal is asserted last, OE, CE, LB, or UB.
2. Timing depends on which signal is de-asserted first CE, OE, LB, or UB.
3. tBDD delay is required only in cases where opposite port is completing a write operation to the same address location. For simultaneous read operations BUSY has no relation
to valid output data.
4. Start of valid data depends on which timing becomes effective last tABE, tAOE, tACE, tAA or tBDD.
5. SEM = VIH.
6.42
IDT70P258/248L
Low Power 1.8V 8K/4K x 16 Dual-Port Static RAM Industrial Temperature Range
10
NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage with Output Test Load.
2. This parameter is guaranteed by device characterization, but is not production tested.
3. To access SRAM, CE = VIL, UB or LB = VIL, SEM = VIH. To access semaphore, CE = VIH or UB and LB = VIH and SEM = VIL. Either condition must be valid for
the entire tEW time.
4. The specification for tDH must be met by the device supplying write data to the SRAM under all operating conditions. Although tDH and tOW values will vary over
voltage and temperature, the actual tDH will always be smaller than the actual tOW.
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage(4)
Symbol Parameter
70P258/248
Ind'l Only
UnitMin. Max.
WRI TE CYCLE
t
WC
Write Cycle Time 55
____
ns
t
EW
Chip Enable to End-of-Write
(3)
45
____
ns
t
AW
Ad dress Valid to End-of-Write 45
____
ns
t
AS
Ad dress Set-up Time
(3)
0
____
ns
t
WP
Write Pulse Wid th 40
____
ns
t
WR
Wri te R e c o v e ry Tim e 0
____
ns
t
DW
Data Valid to End-of-Write 30
____
ns
t
HZ
Output High-Z Time
(1,2)
____
25 ns
t
DH
Data Hol d Ti me
(4)
0
____
ns
t
WZ
Write E nabl e to Ou tput i n High-Z
(1,2)
____
25 ns
t
OW
Outp ut Ac tiv e from End -o f-Write
(1,2,4)
0
____
ns
t
SWRD
SEM Flag Write to Read Time 10
____
ns
t
SPS
SEM Flag Contention Window 10
____
ns
5675 tbl 1 2
6.42
IDT70P258/248L
Low Power 1.8V 8K/4K x 16 Dual-Port Static RAM Industrial Temperature Range
11
Timing Waveform of Write Cycle No. 1, R/W Controlled Timing(1,5,8)
NOTES:
1. R/W or CE or UB & LB must be high during all address transitions.
2. A write occurs during the overlap (tEW or tWP) of a low UB or LB and a LOW CE and a LOW R/W for memory array writing cycle.
3. tWR is measured from the earlier of CE or R/W going HIGH (or SEM going LOW) to the end of write cycle.
4. During this period, the I/O pins are in the output state and input signals must not be applied.
5. If the CE or SEM LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the high-impedance state.
6. Timing depends on which enable signal is asserted last, CE, R/W or byte control.
7. This parameter is guaranteed by device characterization, but is not production tested.Transition is measured 0mV from low or high-impedance voltage with Output
Test Load.
8. If OE is LOW during R/W controlled write cycle, the write pulse width must be the larger of tWP or (tWZ + tDW) to allow the I/O drivers to turn off and data to be placed on the
bus for the required tDW. If OE is HIGH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified tWP.
9. To access SRAM, CE = VIL, UB or LB = VIL, SEM = VIH. To access semaphore, CE = VIH or UB and LB = VIH and SEM = VIL. Either condition must be valid for
the entire tEW time.
R/W
t
WC
t
HZ
t
AW
t
WR
t
AS
t
WP
DATA
OUT
(2)
t
WZ
t
DW
t
DH
t
OW
OE
ADDRESS
DATA
IN
(6)
(4) (4)
(7)
5675 drw 06
CE or SEM
(7)
(3)
,
CE or SEM
(9)
(9)
(9)
ADDRESS
t
AW
CE or SEM
t
WC
5675 drw 07
t
AS
t
WR
t
DW
t
DH
DATA
IN
R/W
t
EW
UB or LB
(9) (3)
(2)
(6)
,,
Timing Waveform of Write Cycle No. 2, CE, UB, LB Controlled Timing(1,5)
6.42
IDT70P258/248L
Low Power 1.8V 8K/4K x 16 Dual-Port Static RAM Industrial Temperature Range
12
Timing Waveform of Semaphore Read after Write Timing, Either Side(1)
Timing Waveform of Semaphore Write Contention(1,3,4)
NOTES:
1. D0R = D0L = VIL, CER = CEL = VIH, or Both UB & LB = VIH.
2. All timing is the same for left or right port. “A” may be either left or right port. “B” is the opposite port from “A”.
3. This parameter is measured from R/W"A" or SEM"A" going HIGH to R/W"B" or SEM"B" going HIGH.
4. If tSPS is not satisfied there is no guarantee which side will be granted the semaphore flag.
NOTES:
1. CE = VIH or UB & LB = VIH for the duration of the above timing (both write and read cycle).
2. “DATAOUT VALID” represents all I/O's (I/O0-I/O15)equal to the semaphore value.
SEM
"A"
5675 drw 09
t
SPS
MATCH
R/W
"A"
MATCH
A
0"A"
-A
2"A"
SIDE "A"
(2)
SEM
"B"
R/W
"B"
A
0"B"
-A
2"B"
SIDE
(2)
"B"
SEM tEW
5675 drw 08
tAW
I/O0
VALID ADDRESS
tSAA
R/W
tWR
tO
H
tACE
VALID ADDRESS
DATAIN
VALID
tDW
tWP tDH
tAS
tSWRD tAOE
Read CycleWrite Cycle
A0-A2
OE
DATAOUT
VALID
(2)
,
tSOP
6.42
IDT70P258/248L
Low Power 1.8V 8K/4K x 16 Dual-Port Static RAM Industrial Temperature Range
13
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage Range
NOTES:
1. Port-to-port delay through SRAM cells from writing port to reading port, refer to "Timing Waveform of Read With BUSY (M/S = VDD)" or "Timing Waveform of Write
With Port-To-Port Delay (M/S = VSS)".
2. To ensure that the earlier of the two ports wins.
3. tBDD is a calculated parameter and is the greater of 0ns, tWDD – t WP (actual) or tDDD – tDW (actual).
4. To ensure that the write cycle is inhibited during contention.
5. To ensure that a write cycle is completed after contention.
70P258/248
Ind'l Only
Symbol Parameter Min. Max. Unit
BUSY TIMING (M/S = V
DD
)
t
BAA
BUSY Access Time from Address Match
____
45 ns
t
BDA
BUSY Disable Time from Address Not Matched
____
45 ns
t
BAC
BUSY Access Time from Chip Enable LOW
____
45 ns
t
BDC
BUSY Dis ab le Ti me fro m Chip Enab le HIGH
____
45 ns
t
APS
Ar b itration P ri o ri ty S e t-up Tim e
(2)
5
____
ns
t
BDD
BUSY Disable to Valid Data
(3)
____
40 ns
t
WH
Write Hold Afte r BUSY
(5)
35
____
ns
BUSY TIMING (M/S = V
SS
)
t
WB
BUSY Inp ut to W rite
(4)
0
____
ns
t
WH
Write Hold Afte r BUSY
(5)
35
____
ns
PORT-TO-PORT DELAY TIMING
t
WDD
Write P ulse to Data Delay
(1)
____
80 ns
t
DDD
Wri te Data Val id to Re ad Data Del ay
(1)
____
65 ns
5675 tbl 1 3
6.42
IDT70P258/248L
Low Power 1.8V 8K/4K x 16 Dual-Port Static RAM Industrial Temperature Range
14
Timing Waveform of Slave Write (M/S = VIL)
5675 drw 11
R/W
"A"
BUSY
"B"
t
WP
t
WB
(3)
R/W
"B"
t
WH
(1)
(2) ,
NOTES:
1. tWH must be met for both BUSY input (slave) and output (master).
2. Busy is asserted on port "B" blocking R/W"B", until BUSY"B" goes HIGH.
3. tWB is only for the “slave” version.
5675 drw 10
t
DW
t
APS
ADDR
"A"
t
WC
DATA
OUT "B"
MATCH
t
WP
R/W
"A"
DATA
IN "A"
ADDR
"B"
t
DH
VALID
(1)
MATCH
BUSY
"B"
t
BDA
VALID
t
BDD
t
DDD
(3)
t
WDD
t
BAA
,
Timing Waveform of Read with BUSY(2,4,5) (M/S = VIH)
NOTES:
1. To ensure that the earlier of the two ports wins. tAPS is ignored for M/S = VIL (slave).
2. CEL = CER = VIL.
3. OE = VIL for the reading port.
4. If M/S = VSS (slave), BUSY is an input. Then for this example BUSY"A" = VIH and BUSY"B" input is shown above.
5. All timing is the same for both left and right ports. Port "A" may be either the left or right Port. Port "B" is the port opposite from port "A".
6.42
IDT70P258/248L
Low Power 1.8V 8K/4K x 16 Dual-Port Static RAM Industrial Temperature Range
15
Waveform of BUSY Arbitration Controlled by CE Timing(1) (M/S = VIH)
Waveform of BUSY Arbitration Cycle Controlled by Address Match
Timing(1) (M/S = VIH)
NOTES:
1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from “A”.
2. If tAPS is not satisfied, the BUSY signal will be asserted on one side or another but there is no guarantee on which side BUSY will be asserted.
5675 drw 12
ADDR
"A"
and
"B"
ADDRESSES MATCH
CE
"A"
CE
"B"
BUSY
"B"
t
APS
t
BAC
t
BDC
(2)
,
5675 drw 13
ADDR
"A"
ADDRESS "N"
ADDR
"B"
BUSY
"B"
t
APS
t
BAA
t
BDA
(2)
MATCHING ADDRESS "N"
,
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage Range
70P258/248
Ind'l Only
Symbol Parameter Min. Max. Unit
INTERRUPT TIMING
t
AS
Ad dress Set-up Time 0
____
ns
t
WR
Write R ec o v e ry Ti m e 0
____
ns
t
INS
Inte rrup t S e t Tim e
____
45 ns
t
INR
Inte rrup t R e set Time
____
45 ns
5675 tbl 1 4
6.42
IDT70P258/248L
Low Power 1.8V 8K/4K x 16 Dual-Port Static RAM Industrial Temperature Range
16
Waveform of Interrupt Timing(1)
NOTES:
1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from “A”.
2. See Interrupt Truth Table III.
3. Timing depends on which enable signal (CE or R/W) is asserted last.
4. Timing depends on which enable signal ( CE or R/W) is de-asserted first.
5675 drw 14
ADDR
"A"
INTERRUPT SET ADDRESS
CE
"A"
R/W
"A"
t
AS
t
WC
t
WR
(3) (4)
t
INS
(3)
INT
"B"
(2)
,
5675 drw 15
ADDR
"B"
INTERRUPT CLEAR ADDRESS
CE
"B"
OE
"B"
t
AS
t
RC
(3)
t
INR
(3)
INT
"B"
(2)
,
6.42
IDT70P258/248L
Low Power 1.8V 8K/4K x 16 Dual-Port Static RAM Industrial Temperature Range
17
Truth Table III — Interrupt Flag(1)
NOTES:
1. Assumes BUSYL = BUSYR = VIH.
2. If BUSYL = VIL, then no change.
3. If BUSYR = VIL, then no change.
4. A12X is a NC for IDT70P248, therefore Interrrupt Addresses are FFF and FFE.
Left Port Right P ort
FunctionR/W
L
CE
L
OE
L
A
12L
-A
0L
(4)
INT
L
R/W
R
CE
R
OE
R
A
12R
-A
0R
(4)
INT
R
L LX1FFFXXXX X L
(2)
S et R i g h t INT
R
Flag
XXXXXXLL1FFF H
(3)
Re s e t Rig ht INT
R
Flag
XXX X L
(3)
L L X 1 F F E X Set L e ft INT
L
Flag
X L L 1FFE H
(2)
X X X X X Re s e t Left INT
L
Flag
5675 tbl 15
Truth Table IV — Address BUSY
Arbitration
NOTES:
1. Pins BUSYL and BUSYR are both outputs when the part is configured as a master. Both are inputs when configured as a slave. BUSY outputs on the
IDT70P258/248 are push pull, not open drain outputs. On slaves the BUSY input internally inhibits writes.
2 . L if the inputs to the opposite port were stable prior to the address and enable inputs of this port. VIH if the inputs to the opposite port became stable after the address
and enable inputs of this port. If tAPS is not met, either BUSYL or BUSYR = LOW will result. BUSYL and BUSYR outputs cannot be LOW simultaneously.
3. Writes to the left port are internally ignored when BUSYL outputs are driving LO W regardless of actual logic level on the pin. Writes to the right port are internally ignored when
BUSYR outputs are driving LOW regardless of actual logic level on the pin.
Inputs Outputs
Function
CE
L
CE
R
A
0L
-A
12L
A
0R
-A
12R
BUSY
L
(1)
BUSY
R
(1)
X X NO MATCH H H No rmal
HX MATCH H H Normal
XH MATCH H H Normal
L L MATCH (2) (2) Write Inhib it
(3)
5675 tbl 16
6.42
IDT70P258/248L
Low Power 1.8V 8K/4K x 16 Dual-Port Static RAM Industrial Temperature Range
18
Truth Table V — Example of Semaphore Procurement Sequence(1,2,3)
NOTES:
1. This table denotes a sequence of events for only one of the eight semaphores on the IDT70P258/248.
2. There are eight semaphore flags written to via I/O0 and read from all I/O's (I/O0-I/O15). These eight semaphores are addressed by A0-A2.
3. CE = VIH, SEM = VIL to access the semaphores. Refer to the Semaphore Read/Write Control Truth Table.
Functions D
0
- D
15
Left D
0
- D
15
Right S tatu s
No Action 1 1 Semaphore free
Left Port Writes "0" to Semaphore 0 1 Le ft port has semaphore toke n
Right Port Writes "0" to Semaphore 0 1 No change. Right side has no write access to semaphore
Left Port Writes "1" to Semaphore 1 0 Right port obtains semaphore token
Left Port Writes "0" to Semaphore 1 0 No change. Left port has no write access to semaphore
Right Port Writes "1" to Semaphore 0 1 Left port obtains semaphore to ken
Left Port Writes "1" to Semaphore 1 1 Semapho re free
Right Port Writes "0" to Semaphore 1 0 Right port has semaphore token
Right Port Writes "1" to Semaphore 1 1 Semaphore fre e
Left Port Writes "0" to Semaphore 0 1 Le ft port has semaphore toke n
Left Port Writes "1" to Semaphore 1 1 Semapho re free
5675 tbl 17
SFEN CE R/WOE UB LB ADDR I/O
0
-I/O
1
I/O
2
-I/O
15
Mode
HLHL L
(1)
L
(1)
x 0000 - Max VALID
(1)
VALID
(1)
S tandar d Me mo ry A cc e ss
LLHL X Lx0000VALID
(2)
X IRR Re ad
(3)
5675 tbl 18
Truth Table VI — Input Read Register Operation(3)
NOTES:
1. UB or LB = VIL. If LB = VIL, then I/O0 - I/O7 are VALID. If UB = VIL, then I/O8 - I/O15 are VALID.
2. LB must be active (LB = VIL) for these bits to be valid.
3. SFEN = VIL to activate IRR reads.
SFEN CE R/WOE UB LB ADDR I/O
0
-I/O
4
I/O
5
-I/O
15
Mode
HLHX
(1)
L
(2)
L
(2)
x 0000 - Max VALID
(2)
VALID
(2)
S tandar d Me mo ry A cc e ss
L L L X X L x0001 VALID
(3)
X ODR W ri te
(4,5)
L L H L X L x0001 VALID
(3)
X ODR Re ad
(5)
5675 tbl 19
Truth Table VII — Output Drive Register Operation(5)
NOTES:
1. Output enable must be low (OE = Vil) during reads for valid data to be output.
2. UB or LB = VIL. If LB = VIL, then I/O0 - I/O7 are VALID. If UB = VIL, then I/O8 - I/O15 are VALID.
3. LB must be active (LB = VIL) for these bits to be valid.
4. During ODR writes data will also be written to the memory.
5. SFEN = VIL to activate ODR reads and writes.
6.42
IDT70P258/248L
Low Power 1.8V 8K/4K x 16 Dual-Port Static RAM Industrial Temperature Range
19
Device 1 Device 2
IRR
0
IRR
1
Input Read Register
(ADDRESS x0000)
Address & I/O
Control
A
0L -
A
12L
A
0R -
A
12R
I/O
0L -
I/O
15L
I/O
0R -
I/O
15R
Memory
Array
5675 drw 16
Figure 3. Input Read Register
Device 2 Device 4
Output Drive Register
(ADDRESS x0001)
Address & I/O
Control
A
0L -
A
12L
A
0R -
A
12R
I/O
0L -
I/O
15L
I/O
0R -
I/O
15R
Memory
Array
5675 drw 17
ODR
0
ODR
1
ODR
2
ODR
3
ODR
4
Device 1 Device 3 Device 5
Figure 4. Output Drive Register
6.42
IDT70P258/248L
Low Power 1.8V 8K/4K x 16 Dual-Port Static RAM Industrial Temperature Range
20
Figure 3. Busy and chip enable routing for both width and depth expansion with IDT70P258/248 SRAMs.
The busy outputs on the IDT 70P258/248 SRAM in master mode, are
push-pull type outputs and do not require pull up resistors to operate. If
these SRAMs are being expanded in depth, then the BUSY indication for
the resulting array requires the use of an external AND gate.
Width Expansion with BUSY Logic
Master/Slave Arrays
When expanding an IDT70P258/248 SRAM array in width while
using busy logic, one master part is used to decide which side of the SRAM
array will receive a BUSY indication, and to output that indication. Any
number of slaves to be addressed in the same address range as the
master, use the BUSY signal as a write inhibit signal. Thus on the
IDT70P258/248 SRAM the BUSY pin is an output if the part is used as a
master (M/S pin = VDD), and the BUSY pin is an input if the part used as
a slave (M/S pin = VSS) as shown in Figure 3.
If two or more master parts were used when expanding in width, a
split decision could result with one master indicating BUSY on one side
of the array and another master indicating BUSY on one other side of
the array. This would inhibit the write operations from one port for part
of a word and inhibit the write operations from the other port for the
other part of the word.
The BUSY arbitration, on a master, is based on the chip enable and
address signals only. It ignores whether an access is a read or write.
In a master/slave array, both address and chip enable must be valid
long enough for a BUSY flag to be output from the master before the
actual write pulse can be initiated with either the R/W signal or the byte
enables. Failure to observe this timing can result in a glitched internal
write inhibit signal and corrupted data in the slave.
The Input Read Register (IRR) of the IDT70P258/248 captures the
status of two external binary input devices connected to the Input Read pins
(e.g. DIP switches). The contents of the IRR are read as a standard
memory access to address x0000 from either port and the data is output
via the standard I/Os (Truth Table VI). During Input Register reads I/O0
- I/O1 are valid bits and I/O2 - I/O15 are "Dont' Care". Writes to address
x0000 are not allowed from either port. When SFEN = VIL, the IRR is active
and address x0000 is not available for standard memory operations.
When SFEN = VIH, the IRR is inactive and address x0000 can be used
as part of the main memory. The IRR supports inputs up to 3.5V (VIL < 0.4V,
VIH > 1.4V). Refer to Figure 3 and Truth Table VI for Input Read Register
operation.
Functional Description
The IDT70P258/248 provides two ports with separate control, ad-
dress and I/O pins that permit independent access to any location in
memory. The IDT70P258/248 has an automatic power down feature
controlled by CE. The CE controls on-chip power down circuitry that
permits the respective port to go into a standby mode when not selected
(CE HIGH). When a port is enabled, access to the entire memory array
is permitted.
Interrupts
If the user chooses the interrupt function, a memory location (mail
box or message center) is assigned to each port. The left port interrupt
flag (INTL) is asserted when the right port writes to memory location 1FFE
(HEX) (FFE for IDT70P248), where a write is defined as the CE=R/W=VIL
per Truth Table III. The left port clears the interrupt by accessing address
location 1FFE when CER = OER = VIL, R/W is a "don't care". Likewise,
the right port interrupt flag (INTR) is asserted when the left port writes
to memory location 1FFF (HEX) (FFF for IDT70P248) and to clear the
interrupt flag (INTR), the right port must read the memory location 1FFF.
The message (16 bits) at 1FFE or 1FFF is user-defined, since it is an
addressable SRAM location. If the interrupt function is not used, address
locations 1FFE and 1FFF are not used as mail boxes, but as part of the
random access memory. Refer to Truth Table IIII for the interrupt
operation.
Busy Logic
Busy Logic provides a hardware indication that both ports of the
SRAM have accessed the same location at the same time. It also
allows one of the two accesses to proceed and signals the other side
that the SRAM is “busy”. The BUSY pin can then be used to stall the access
until the operation on the other side is completed. If a write operation has
been attemp-ted from the side that receives a BUSY indication, the write
signal is gated internally to prevent the write from proceeding.
The use of BUSY logic is not required or desirable for all applications.
In some cases it may be useful to logically OR the BUSY outputs together
and use any BUSY indication as an interrupt source to flag the event of
an illegal or illogical operation. If the write inhibit function of BUSY logic is
not desirable, the BUSY logic can be disabled by placing the part in slave
mode with the M/S pin. Once in slave mode the BUSY pin operates solely
as a write inhibit input pin. Normal operation can be programmed by tying
the BUSY pins HIGH. If desired, unintended write operations can be
prevented to a port by tying the BUSY pin for that port LOW.
5675 drw 18
MASTER
Dual Port
SRAM
BUSY
L
BUSY
R
CE
MASTER
Dual Port
SRAM
BUSY
L
BUSY
R
CE
SLAVE
Dual Port
SRAM
BUSY
L
BUSY
R
CE
SLAVE
Dual Port
SRAM
BUSY
L
BUSY
R
CE
BUSY
L
BUSY
R
DECODER
,
Input Read Register
6.42
IDT70P258/248L
Low Power 1.8V 8K/4K x 16 Dual-Port Static RAM Industrial Temperature Range
21
The Output Drive Register (ODR) of the IDT70P258/248 determines
the state of up to five external binary-state devices by providing a path to
VSS for the external circuit. The five external devices supported by the ODR
can operate at different voltages (1.5V < VSUPPLY < 3.5V), but the combined
current of the devices must not exceed 40 mA (8mA IMAX for each external
device). The status of the ODR bits is set using standard write accesses
from either port to address x0001with a “1” corresponding to “on“ and a
“0” corresponding to “off”. The status of the ODR bits can also be read
(without changing the status of the bits) via a standard read to address
x0001. When SFEN = VIL, the ODR is active and address x0001 is not
available for standard memory operations. When SFEN = VIH, the ODR
is inactive and address x0001 can be used as part of the main memory.
During reads and writes to the ODR I/O0 - I/O4 are valid bits and I/O5 -
I/O15 are "Don't Care". Refer to Figure 4 and Truth Table VII for Output
Drive Register operation.
Semaphores
The IDT70P258/248 is an extremely fast Dual-Port 8K/4K x 16 CMOS
Static RAM with an additional 8 address locations dedicated to binary
semaphore flags. These flags allow either processor on the left or right side
of the Dual-Port SRAM to claim a privilege over the other processor for
functions defined by the system designer’s software. As an example, the
semaphore can be used by one processor to inhibit the other from
accessing a portion of the Dual-Port SRAM or any other shared resource.
The Dual-Port SRAM features a fast access time, and both ports are
completely independent of each other. This means that the activity on the
left port in no way slows the access time of the right port. Both ports are
identical in function to standard CMOS Static RAM and can be accessed
to, at the same time with the only possible conflict arising from the
simultaneous writing of, or a simultaneous READ/WRITE of, a non-
semaphore location. Semaphores are protected against such ambiguous
situations and may be used by the system program to avoid any conflicts
in the non-semaphore portion of the Dual-Port SRAM. These devices
have an automatic power-down feature controlled by CE, the Dual-Port
SRAM enable, and SEM, the semaphore enable. The CE and SEM pins
control on-chip power down circuitry that permits the respective port to go
into standby mode when not selected. This is the condition which is shown
in Truth Table I where CE and SEM are LOW.
Systems which can best use the IDT70P258/248 contain multiple
processors or controllers and are typically very high-speed systems
which are software controlled or software intensive. These systems can
benefit from a performance increase offered by the IDT70P258/248's
hardware semaphores, which provide a lockout mechanism without
requiring complex programming.
Software handshaking between processors offers the maximum in
system flexibility by permitting shared resources to be allocated in
varying configurations. The IDT70P258/248 does not use its semaphore
flags to control any resources through hardware, thus allowing the
system designer total flexibility in system architecture.
An advantage of using semaphores rather than the more common
methods of hardware arbitration is that wait states are never incurred
in either processor. This can prove to be a major advantage in very
high-speed systems.
How the Semaphore Flags Work
The semaphore logic is a set of eight latches which are independent
of the Dual-Port SRAM. These latches can be used to pass a flag, or token,
from one port to the other to indicate that a shared resource is in use. The
semaphores provide a hardware assist for a use assignment method
called “Token Passing Allocation.” In this method, the state of a semaphore
latch is used as a token indicating that shared resource is in use. If the left
processor wants to use this resource, it requests the token by setting the
latch. This processor then verifies its success in setting the latch by reading
it. If it was successful, it proceeds to assume control over the shared
resource. If it was not successful in setting the latch, it determines that the
right side processor has set the latch first, has the token and is using the
shared resource. The left processor can then either repeatedly request
that semaphore’s status or remove its request for that semaphore to perform
another task and occasionally attempt again to gain control of the token via
the set and test sequence. Once the right side has relinquished the token,
the left side should succeed in gaining control.
The semaphore flags are active HIGH. A token is requested by writing
a zero into a semaphore latch and is released when the same side writes
a one to that latch.
The eight semaphore flags reside within the IDT70P258/248 in a
separate memory space from the Dual-Port SRAM. This address
space is accessed by placing a LOW input on the SEM pin (which acts as
a chip select for the semaphore flags) and using the other control pins
(Address, OE, and R/W) as they would be used in accessing a standard
Static RAM. Each of the flags has a unique address which can be accessed
by either side through address pins A0 – A2. When accessing the
semaphores, none of the other address pins has any effect.
When writing to a semaphore, only data pin D0 is used. If a LOW level
is written into an unused semaphore location, that flag will be set to a zero
on that side and a one on the other side (see Truth Table V). That
semaphore can now only be modified by the side showing the zero. When
a one is written into the same location from the same side, the flag will be
set to a one for both sides (unless a semaphore request from the other side
is pending) and then can be written to by both sides. The fact that the side
which is able to write a zero into a semaphore subsequently locks out writes
from the other side is what makes semaphore flags useful in interprocessor
communications. (A thorough discussion on the use of this feature follows
shortly.) A zero written into the same location from the other side will be
stored in the semaphore request latch for that side until the semaphore is
freed by the first side.
When a semaphore flag is read, its value is spread into all data bits so
that a flag that is a one reads as a one in all data bits and a flag containing
a zero reads as all zeros. The read value is latched into one side’s output
register when that side's semaphore select (SEM) and output enable (OE)
signals go active. This serves to disallow the semaphore from changing
state in the middle of a read cycle due to a write cycle from the other side.
Because of this latch, a repeated read of a semaphore in a test loop must
cause either signal (SEM or OE) to go inactive or the output will never
change.
A sequence WRITE/READ must be used by the semaphore in
order to guarantee that no system level contention will occur. A
processor requests access to shared resources by attempting to write
a zero into a semaphore location. If the semaphore is already in use,
the semaphore request latch will contain a zero, yet the semaphore
flag will appear as one, a fact which the processor will verify by the
Output Drive Register
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IDT70P258/248L
Low Power 1.8V 8K/4K x 16 Dual-Port Static RAM Industrial Temperature Range
22
subsequent read (see Truth Table V). As an example, assume a
processor writes a zero to the left port at a free semaphore location. On
a subsequent read, the processor will verify that it has written success-
fully to that location and will assume control over the resource in question.
Meanwhile, if a processor on the right side attempts to write a zero to the
same semaphore flag it will fail, as will be verified by the fact that a one will
be read from that semaphore on the right side during subsequent read.
Had a sequence of READ/WRITE been used instead, system contention
problems could have occurred during the gap between the read and write
cycles.
It is important to note that a failed semaphore request must be followed
by either repeated reads or by writing a one into the same location. The
reason for this is easily understood by looking at the simple logic diagram
of the semaphore flag in Figure 4. Two semaphore request latches feed
into a semaphore flag. Whichever latch is first to present a zero to the
semaphore flag will force its side of the semaphore flag LOW and the other
side HIGH. This condition will continue until a one is written to the same
semaphore request latch. Should the other side’s semaphore request latch
have been written to a zero in the meantime, the semaphore flag will flip
over to the other side as soon as a one is written into the first side’s request
latch. The second side’s flag will now stay LOW until its semaphore request
latch is written to a one. From this it is easy to understand that, if a semaphore
is requested and the processor which requested it no longer needs the
resource, the entire system can hang up until a one is written into that
semaphore request latch.
The critical case of semaphore timing is when both sides request a
single token by attempting to write a zero into it at the same time. The
semaphore logic is specially designed to resolve this problem. If
simultaneous requests are made, the logic guarantees that only one
side receives the token. If one side is earlier than the other in making
the request, the first side to make the request will receive the token. If
both requests arrive at the same time, the assignment will be arbitrarily
made to one port or the other.
One caution that should be noted when using semaphores is that
semaphores alone do not guarantee that access to a resource is
secure. As with any powerful programming technique, if semaphores
are misused or misinterpreted, a software error can easily happen.
Initialization of the semaphores is not automatic and must be
handled via the initialization program at power-up. Since any sema-
phore request flag which contains a zero must be reset to a one, all
semaphores on both sides should have a one written into them at
initialization from both sides to assure that they will be free when
needed.
Using Semaphores—Some Examples
Perhaps the simplest application of semaphores is their application as
resource markers for the IDT70P258/248’s Dual-Port SRAM. Say the 8K/
4K x 16 SRAM was to be divided into two 4K/2K x 16 blocks which were
to be dedicated at any one time to servicing either the left or right port.
Semaphore 0 could be used to indicate the side which would control the
lower section of memory, and Semaphore 1 could be defined as the
indicator for the upper section of memory.
To take a resource, in this example the lower 4K/2K of Dual-Port
SRAM, the processor on the left port could write and then read a
zero in to Semaphore 0. If this task were successfully completed
(a zero was read back rather than a one), the left processor would
assume control of the lower 4K/2K. Meanwhile the right processor was
attempting to gain control of the resource after the left processor, it would
read back a one in response to the zero it had attempted to write into
Semaphore 0. At this point, the software could choose to try and gain control
of the second 4K/2K section by writing, then reading a zero into Semaphore
1. If it succeeded in gaining control, it would lock out the left side.
Once the left side was finished with its task, it would write a one to
Semaphore 0 and may then try to gain access to Semaphore 1. If
Semaphore 1 was still occupied by the right side, the left side could undo
its semaphore request and perform other tasks until it was able to write, then
read a zero into Semaphore 1. If the right processor performs a similar task
with Semaphore 0, this protocol would allow the two processors to swap
4K/2K blocks of Dual-Port SRAM with each other.
The blocks do not have to be any particular size and can even be
variable, depending upon the complexity of the software using the
semaphore flags. All eight semaphores could be used to divide the
Dual-Port SRAM or other shared resources into eight parts. Sema-
phores can even be assigned different meanings on different sides
rather than being given a common meaning as was shown in the
example above.
Semaphores are a useful form of arbitration in systems like disk
interfaces where the CPU must be locked out of a section of memory
during a transfer and the I/O device cannot tolerate any wait states.
With the use of semaphores, once the two devices has determined
which memory area was “off-limits” to the CPU, both the CPU and the
I/O devices could access their assigned portions of memory continu-
ously without any wait states.
Semaphores are also useful in applications where no memory
“WAIT” state is available on one or both sides. Once a semaphore
handshake has been performed, both processors can access their
assigned SRAM segments at full speed.
Another application is in the area of complex data structures. In this
case, block arbitration is very important. For this application one
processor may be responsible for building and updating a data
structure. The other processor then reads and interprets that data
structure. If the interpreting processor reads an incomplete data
structure, a major error condition may exist. Therefore, some sort of
arbitration must be used between the two different processors. The
building processor arbitrates for the block, locks it and then is able to
go in and update the data structure. When the update is completed, the
data structure block is released. This allows the interpreting processor
to come back and read the complete data structure, thereby guaran-
teeing a consistent data structure.
D
5675 drw 19
0DQ
WRITE D
0
D
Q
WRITE
SEMAPHORE
REQUEST FLIP FLOP SEMAPHORE
REQUEST FLIP FLOP
LPORT RPORT
SEMAPHORE
READ SEMAPHORE
READ ,
Figure 4. IDT70P258/248 Semaphore Logic
6.42
IDT70P258/248L
Low Power 1.8V 8K/4K x 16 Dual-Port Static RAM Industrial Temperature Range
23
Ordering Information
5675 drw 20
A
Power
999
Speed
A
Package
A
Process/
Temperature
Range
IIndustrial (-40°Cto+85°C)
BY 100 Ball 0.5mm-pitch BGA(BY100)
55
LLowPower
XXXXX
Device
Type
128K (8K x 16) 1.8V Dual-Port SRAM
64K (4K x 16) 1.8V Dual-Port SRAM
70P258
70P248
IDT
Speed in nanoseconds
Industrial Only
CORPORATE HEADQUARTERS for SALES: for Tech Support:
2975 Stender Way 800-345-7015 or 408-727-6116 831-754-4613
Santa Clara, CA 95054 fax: 408-492-8674 DualPortHelp@idt.com
www.idt.com
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
Datasheet Document History
09/11/03: Initial Datasheet
01/22/04: Page 6 Amended Parameter and Test Conditions in DC Electrical Characteristics table
03/22/04: Page 1 Added 2.5V to the feature supporting the I/O's
Page 5 Added Recommended DC Operating Conditions (VDDQL = 2.5V + 100mV) Table 06_5
Page 6 Added VOHL & VOLL for 2.5V to the DC Electrical Characteristics Over the Operating Temperature and
Supply Voltage Range (VDDQL = 1.8V + 100mV) Table 08
04/21/04: Removed Preliminary status from entire datasheet
