IDT70P9268L50BYGI8 - Integrated Device Technology

1 of 22 March 8, 2007

DSC 5695/1

Features

◆True Dual-Ported Memory Cells

–Allows simultaneous access of the same memory location

◆High per-port throughput performa nce

–Industrial: 800 Mbps

◆Low-Powe r Operation

–Active: 15 mA (typ.)

–Standby: 2 uA (typ.)

◆Multiplexed address and data I/Os

◆Counter enable and repeat features

◆Full synchronous operation on both ports

◆Separate upper-byte and lower-byte controls for multiplexed bus

and bus matching compatibility

◆LVTTL-compatible, single 1.8V (+/- 100mV) power supply

◆Industrial temperature range (-40C to +85C)

◆Available in a 100-ball fpBGA (fine pitch BGA)

◆Green parts available, see ordering information

Block Diagram

NOTES:

1. This block dia gram depicts oper ation with the addres s and data sig nals mux’d on the right port but not on the left port. If each port is set to o perate w ith the a ddress an d dat a signals

mux’d, then both sides of the block diagram will be the same as the right port pictured above.

16K x 16

MEMORY

ARRAY

CONTROL

LOGIC

SPECIAL FUNCTION

LOGIC

ZZ CONTROL

LOGIC

Address/Data

I/O Control

I/O

– I/O

15R

ADS

CNTEN

CNTRPT

R/W

INT

CLK

– SF

SFEN

CLK

Address/Data

I/O Control

I/O

– I/O

15L

ADS

CNTEN

CNTRPT

CLK

– A

13L

R/W

INT

CLK

DATA

0L – DATA15L

Addr0L – Addr13L

DATA0R – DATA15R

Addr0R – Addr13R

Advanced

Datasheet

IDT70P9268L

MOBILE MULTIMEDIA INTERFA CE (M2I)

VERY LOW POWER 1.8V

16K X 16

SYNCHRONOUS

DUAL-PORT STATIC RAM

2 of 22 March 8, 2007

IDT70P9268L Advanced Datasheet

Very Low Power 16K x 16 Synchronous Mobile Multimedia Interface (M2I) Dual Port Static RAM Industrial Temperature Range

Device Description

The 70P9268L is a very low power 16K x 16 synchronous Dual-Port RAM. The memory array utilizes Dual-Port memory cells to allow simultaneous

access of any address from both ports. Registers on control, data and address inputs provide minimal setup and hold times. The timing latitude

provided by this approach allows systems to be designed with very short cycle times. The 70P9268 supports two modes of operation. The first

features one port with multiplexed address and data s ignals. The sec ond features both ports w ith multiplexed address and data signals. Please refer

to the pinout below for more information on how to select the operation mode.

Pin Configur ation IDT70P9268

BY100

100-BALL fpBGA

NOTES:

1. The device setup shown above features multiplexed address and data signals on the right port and non-multiplexed address and data signals on the left port.

2. For multiplexed address and data signal operation on the left port, this pin should be set to VDD. For non-multiplexed address and data signal operation on the left port, this pin should be

set to VSS.

3. For multiplexed address and data signal operation on the left port, these pins should be set to VSS.

VSS

I/O0R

VDD

I/O4R

I/O7R

VDD

I/O10R

VDD

I/O15R

A10

SFEN

R/WR

CLKR

I/O1R

VSS

I/O5R

VSS

I/O11R

VSS

I/O14R

B10

OER

ADSR

CNTENR

CNTRPTR

I/O2R

I/O6R

I/O8R

I/O12R

ZZR

SF7

C10

VSS

CER

INTR

UBR

LBR

I/O3R

I/O9R

I/O13R

SF6

SF5

D10

SF4

INTL

VSS

VDD

UBL

CNTRPTL

SF0

MSEL(2)

VDD

VSS

E10

VDD

CEL

LBL

CNTENL

CLKL

VSS

A13L(3)

SF2

VSS

F10

SF1

ADSL

A0L(3)

A3L(3)

VDD

I/O8L

I/O12L

A7L(3)

ZZL

OEL

G10

SF3

R/WL

A2L(3)

I/O0L

VSS

I/O4L

I/O11L

I/O13L

A9L(3)

A12L(3)

H10

A1L(3)

A5L(3)

I/O1L

I/O6L

I/O7L

I/O9L

VDD

I/O15L

A10L(3)

J10

A11L(3)

A4L(3)

A6L(3)

I/O2L

I/O3L

I/O5L

VDD

I/O10L

VSS

I/O14L

K10

A8L(3)

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IDT70P9268L Advanced Datasheet

Very Low Power 16K x 16 Synchronous Mobile Multimedia Interface (M2I) Dual Port Static RAM Industrial Temperature Range

Pin Names (70P9268)

NOTES:

1. The device setup shown above features multiplexed address and data signals on both ports.

2. For non-multiplexed address and data signal operation on the left port, set p in E7 = VSS.

Left Port Right Port Names

CEL CER Chip Enable (Input)

R/WL R/WR Read/Write Enable (Input)

OEL OER Output Enable (Input)

A0L – A15L N/A Address (Input)

I/O0L – I/O15L N/A Data (Input/Output)

N/A I/O+A0R – I/O+A15R Multiplexed Address and Data (Input/Output)

CLKL CLKR Clock (Input)

UBL UBR Upper Byte Enable (Input)

LBL LBR Lower Byte Enable (Input)

ADSL ADSR Address Strobe Enable (Input)

CNTENL CNTENR Counter Enable (Input)

CNTRPTL CNTRPTR Counter Repeat (Input)

INTL INTR Interrupt Flag (Output)

ZZL ZZR Sleep Mode Enable (Input)

SFEN Special Function Enable (Input)

SF0-7 Special Function I/O (Input/Output)

MSEL Left Port Mode Select

VDD Power (1.8V)

VSS Ground (0V)

4 of 22 March 8, 2007

IDT70P9268L Advanced Datasheet

Very Low Power 16K x 16 Synchronous Mobile Multimedia Interface (M2I) Dual Port Static RAM Industrial Temperature Range

Truth Table I - Read/Write and Enable Control (Multiplexed Port)

Truth Table II - Read/Write and Enable Control (Non-Multiplexed Port)

Truth Table III - Address Counter Control

Recommended Operating Temperature and Supply Voltage

OE CLK CE UB LB R/W ADS ZZ Upper

Byte

Lower

Byte

Cycle Address Mode

X ↑ H X X X X L High Z High Z X X Deslected

X ↑ L H H X X L High Z High Z X X Both bytes deselected

X ↑ L L H L L L -- -- N AN

X ↑ X X X L H L DIN High Z N+1 --

Write to Upper Byte

X ↑ L H L L L L -- -- N AN

X ↑ X X X L H L High Z DIN N+1 --

Write to Lower Byte

X ↑ L L L L L L -- -- N AN

X ↑ X X X L H L DIN D

IN N+1 --

Write to Both Bytes

H ↑ L L H H L L -- -- N AN

L ↑ X X X H H L DOUT High Z N+2 --

Read Upper Byte Only

H ↑ L H L H L L -- -- N AN

L ↑ X X X H H L High Z DOUT N+2 --

Read Lower Byte Only

H ↑ L L L H L L -- -- N AN

L ↑ X X X H H L DOUT D

OUT N+2 --

Read Both Bytes

H ↑ L L L X H L High Z High Z X X Outputs Disabled

X X X X X X X H High Z High Z X X Sleep Mode – Power down

OE CLK CE UB LB R/W ZZ Upper Byte I/O Lower Byte I/O Mode

X ↑ H X X X L High Z High Z Deselected

X ↑ L H H X L High Z High Z Both Bytes Deselected

X ↑ L L H L L DIN High Z Write To Upper Byte Only

X ↑ L H L L L High Z DIN Write to Lower Byte Only

X ↑ L L L L L DIN D

IN Write to Both Bytes

L ↑ L L H H L DOUT High Z Read Upper Byte Only

L ↑ L H L H L High Z DOUT Read Lower Byte Only

L ↑ L L L H L DOUT D

OUT Read Both Bytes

H ↑ L L L X L High Z High Z Outputs Disabled

X X X X X X H High Z High Z Sleep Mode – Power Down

External

Address

Internal

Address

Internal

Address

Used

CLK ADS CNTEN CNTRPT Mode

An X An ↑ L X H External Address Used

X An A

n + 1 ↑ H L H Counter Enabled – Internal Address

Generation

X An + 1 A

n + 1 ↑ H H H External Address Blocked – Counter

Disabled (An + 1 reused)

X X An ↑ X X L Counter Reset to Last External Address

Loaded

Grade Am bient Temperature GND VDD

Indu strial -40°C to +85°C 0V 1.8V +/- 100m V

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IDT70P9268L Advanced Datasheet

Very Low Power 16K x 16 Synchronous Mobile Multimedia Interface (M2I) Dual Port Static RAM Industrial Temperature Range

Recommended DC Operating Conditions

Absolute Maximum Ratings

Capacitance

DC Electrical Characteristics Over the Operating Temperature and Supply

Voltage Range (VDD = 1.8V +/- 100mV)

Symbol Parameter Min. Typ. Max. Unit

VDD Supply Voltage 1.7 1.8 1.9 V

VSS Ground 0 0 0 V

VIH Input High Voltage 1.2 -- VDD + 0.2 V

VIL Input Low Voltage -0.2 -- 0.4 V

Symbol Rating Industrial Unit

VDD Voltage on Input, Output and

I/O Terminals with Respect to

VSS

-0.5V to VDD +0.3V V

VTERM Terminal Voltage with

Respect to GND

-0.5V to +2.9V V

TBIAS Temperature Under Bias -55 to +125 °C

TSTG Storage Temperature -65 to +150 °C

TJN Junction Temperature +150 °C

IOUT DC Output Current 20 mA

Symbol Parameter Conditions Max. Unit

CIN Input Capacitance VIN = 0V 9 PF

COUT Output Capacitance VOUT = 0V 11 PF

Symbol Parameter Test Conditions Min. Max. Unit

|ILI| Input Leakage Current VIN = VSS to VDD -- 1 Ua

|ILO| Output Leakage Current

CEx = VIH or OEx = VIH or

VOUT = VSS to VDD

-- 1 UA

VOL Output Low Voltage IOL = 0.1mA, VDD = Min -- 0.2 V

VOH Output High Voltage IOH = -0.1m A, VDD = Min VDD – 0.2V -- V

VOLSF Output Low Voltage IOL = 4mA, VDD = Min -- 0.4 V

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IDT70P9268L Advanced Datasheet

Very Low Power 16K x 16 Synchronous Mobile Multimedia Interface (M2I) Dual Port Static RAM Industrial Temperature Range

DC Electrical Characteristics Over the Operating Temperature and Supply

Voltage Range (VDD = 1.8V +/- 100mV)

NOTES:

1. At f = fMAX, address and control lines (except Output Enable) are cycling at the maximum frequency clock cycle of 1/tCYC, using “AC TEST CONDITIONS” at input levels of GND to 1.8V.

2. f = 0 means no address, clock, or control lines change. Applies only to input at CMOS level standby.

3. Port “A” may be either left or right port. Port “B” is the opposite from port “A”.

AC Test Conditions

Input Pulse Levels VSS to VDD

Input Rise/Fall Times 3ns Max.

Input Timing Reference Levels VDD/2

Output Reference Levels VDD/2

Output Load Figure 1

1.8V

R1 13500Ω

R2 13500Ω

70P9268 Symbol Parameter Test Conditions

Typ. Max.

IDD Dynamic Operating

Current (Both Ports

Active)

CEL and CER = VIL,

Outputs Disabled,

f = fMAX(1)

15 mA

25 mA

ISB1 Standby Current

(Both Ports – TTL

Inputs)

CEL = CER = VIH,

Outputs Disabled,

f = fMAX(1)

2 mA

4 mA

ISB2 Standby Current

(One Port – TTL

Inputs)

CE”A” = VIL and CE”B” = VIH,

Active Port Outputs Disabled,

f = fMAX(1)

3 mA

5 mA

ISB3 Full Standby Current

(Both Ports CMOS

Inputs)

Both Ports Outputs Disabled

CEL and CER > VDD – 0.2V,

VIN > VDD – 0.2V,

or VIN < 0.2V, f = 0(2)

2 uA

8 uA

ISB4 Full Standby Current

(One Port – CMOS

Inputs)

CE”A” < 0.2V and CE”B” > VDD – 0.2V,

VIN > VDD – 0.2V or VIN < 0.2V,

Active Port Outputs Disabled, f = fMAX(1)

3 mA

5 mA

IZZ Sleep Mode Current ZZL and ZZR > VDD – 0.2V 2 uA 8 uA

30pF(1)

1.8V

Figure 1. AC Output Test Level

(5pF for tLZ, tHZ, tWZ, tOW)

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IDT70P9268L Advanced Datasheet

Very Low Power 16K x 16 Synchronous Mobile Multimedia Interface (M2I) Dual Port Static RAM Industrial Temperature Range

AC Electrical Characteristics Over the Operating Temperature Range

(Read and Write Cycle Timing for Multiplexed Port) (VDD = 1.8V +/- 100mV)

70P9268L

Ind. Only

Symbol Parameter Min. Max.

tCYC Clock Cycle Time 20 --

tCH Clock High Time 8 --

tCL Clock Low Time 8 --

tR Clock Rise Time -- 3

tF Clock Fall Time -- 3

tSA Address Setup Time 5 --

tHA Address Hold Time 1 --

tSC Chip Enable Setup Time 5 --

tHC Chip Enable Hold Time 1 --

tSW R/W Setup Time 5 --

tHW R/W Hold Time 1 --

tSD Input Data Setup Time 5 --

tHD Input Data Hold Time 1 --

tSAD ADS Setup Time 5 --

tHAD ADS Hold Time 1 --

tSCN CNTEN Setup Time 5 --

tHCN CNTEN Hold Time 1 --

tSRST CNTRST Setup Time 5 --

tHRST CNTRST Hold Time 1 --

tOE Output Enable to Data Valid -- 10

tOLZ Output Enable to High Z 2 --

tOHZ Output Enable to Low Z -- 10

tCD Clock to Data Valid -- 12

tDC Data Output Hold After Clock High 2 --

tCKHZ Clock High to Output High Z 2 9

tCKLZ Clock High to Output Low Z 2 --

tINS Interrupt Flag Set Time 12 --

tINR Interrupt Flag Reset Time 12 --

tCO Clock to Clock Offset 5 --

8 of 22 March 8, 2007

IDT70P9268L Advanced Datasheet

Very Low Power 16K x 16 Synchronous Mobile Multimedia Interface (M2I) Dual Port Static RAM Industrial Temperature Range

AC Electrical Characteristics Over the Operating Temperature Range

(Read and Write Cycle Timing for Non-Multiplexed Port) (VDD = 1.8V +/- 100mV)

70P9268L

Ind. Only

Symbol Parameter Min. Max.

tCYC Clock Cycle Time 20 --

tCH Clock High Time 8 --

tCL Clock Low Time 8 --

tR Clock Rise Time -- 3

tF Clock Fall Time -- 3

tSA Address Setup Time 5 --

tHA Address Hold Time 1 --

tSC Chip Enable Setup Time 5 --

tHC Chip Enable Hold Time 1 --

tSW R/W Setup Time 5 --

tHW R/W Hold Time 1 --

tSD Input Data Setup Time 5 --

tHD Input Data Hold Time 1 --

tSAD ADS Setup Time 5 --

tHAD ADS Hold Time 1 --

tSCN CNTEN Setup Time 5 --

tHCN CNTEN Hold Time 1 --

tSRST CNTRST Setup Time 5 --

tHRST CNTRST Hold Time 1 --

tOLZ Output Enable to Low Z 2 --

tOHZ Output Enable to High Z -- 10

tCD Clock to Data Valid -- 12

tDC Data Output Hold After Clock High 2 --

tCKHZ Clock High to Output High Z 2 10

tCKLZ Clock High to Output Low Z 2 --

tINS Interrupt Flag Set Time 12 --

tINR Interrupt Flag Reset Time 12 --

tCO Clock to Clock Offset 5 --

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IDT70P9268L Advanced Datasheet

Very Low Power 16K x 16 Synchronous Mobile Multimedia Interface (M2I) Dual Port Static RAM Industrial Temperature Range

Timing Waveform for Mux’d Port Single Read Cycle

Timing Waveform for Mux’d Port Burst Read Cycle

ADDR / DATA

ADS

UB / LB

CLK

tCH tCL

tCYC

tSC

tSB

tSAD tHAD

tSA tHA

An Dn

tOHZ

tHC

tHB

tSW

R/W

tOLZ

tOE

tCLZ

tCD tCKHZ

ADDR / DATA

ADS

CLK

tCH tCL

tCYC

tSAD tHAD

tSA tHA

An Dn

CNTEN

tSCN tHCN

Dn+1

tCKLZ

tCD tCKHZ

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IDT70P9268L Advanced Datasheet

Very Low Power 16K x 16 Synchronous Mobile Multimedia Interface (M2I) Dual Port Static RAM Industrial Temperature Range

Timing Waveform for Mux’d Port Single Write Cycle

Timing Waveform for Mux’d Port Burst Write Cycle

ADDR / DATA

ADS

R/W

CLK

tCH tCL

tCYC

tSC

tSW

tSAD tHAD

tSA tHA tSD tHD

An Dn An+1 Dn+1

ADDR / DATA

ADS

R/W

CLK

tCH tCL

tCYC

tSC

tSW

tSAD tHAD

tSA tHA tSD tHD

An Dn Dn+1 Dn+2

CNTEN

tSCN

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IDT70P9268L Advanced Datasheet

Very Low Power 16K x 16 Synchronous Mobile Multimedia Interface (M2I) Dual Port Static RAM Industrial Temperature Range

Timing Waveform of Mux’d Port Write to Non-Mux’d Port Read

NOTES:

1. CE, UB/LBn = VIL; CNTEN an d REPEAT = VIH.

2. OE = VIL for Port, which is being read from. OE = VIH for Mux’d Port, which is being written to.

3. If tCO < minimu m spec ified, then d ata from N on-Mu x’d Po rt read is no t valid unt il follow ing N on-Mux ’d Por t clock cycle (ie, tim e from write to valid read on op posite port w ill be t CO + 2

tCYC2 + tCD2). If tCO > minimu m, th en da ta fro m No n-M ux’ d Por t read is ava ilab l e on first No n-M ux ’d Po rt cloc k cyc le (ie, time from w rite to valid read on opposite port will be tCO + tCYC2

+ tCD2).

ADDR / DATA

R/W

CLK

tCH tCL

tCYC

ADS

tHW

tSA tHA

MATCH VALID

tSA tHA tSD tHD

tCO

tSW tHW

tCD

tSA tHA

MATCH NO

MATCH

VALID

tCH tCL

tCYC

R/W

CLK

ADDRESS

DATA

tDC

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IDT70P9268L Advanced Datasheet

Very Low Power 16K x 16 Synchronous Mobile Multimedia Interface (M2I) Dual Port Static RAM Industrial Temperature Range

Timing Waveform of Non-Mux’d Port Write to Mux’d Port Read

DATA

IN”A”

R/W

CLK

tCH tCL

tCYC

ADDRESS

tHW

tSA tHA

MATCH

tSA tHA

tSW tHW

tCDtSA tHA

MATCH

R/W

CLK

ADDR/DATA

VALID

tSD tHD

VAL ID

tDC

NO MATCH

tCO

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IDT70P9268L Advanced Datasheet

Very Low Power 16K x 16 Synchronous Mobile Multimedia Interface (M2I) Dual Port Static RAM Industrial Temperature Range

Timing Waveform of Non-Mux’d Port Read-to-Write-to-Read

NOTES:

1. Output UB/LB state (High, Low, or High-impedance) is determined by the previous cycle control signals.

2. CE and ADS = VIL; CE1, CNTEN, and REPEAT = VIH. "NOP" is "No Operation".

3. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers

are for reference use only.

4. "NOP" is "No Operation." Data in memory at the selected address may be corrupted and should be re-written to guarantee data integrity.

CLK

Dn+2

tSA tHA

READ

An+1 An+2 An+2 An+3 An+4

Qn+3

NOP

(4)

WRITE READ

tSC tHC

tSD tHD

tCH tCL

tCYC

tSB tHB

tSW tHW tSW tHW

tCD tCKHZ tCKHZ

UB/LB

R/W

ADDRESS

DATA

OUT

(1)

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IDT70P9268L Advanced Datasheet

Very Low Power 16K x 16 Synchronous Mobile Multimedia Interface (M2I) Dual Port Static RAM Industrial Temperature Range

Timing Waveform of Non-Mux’d Port Read-to-Write-to-Read (OE Controlled)

NOTES:

1. Output UB/LB state (High, Low, or High-impedance) is determined by the previous cycle control signals.

2. CE and ADS = VIL; CE1, CNTEN, and REPEAT = VIH. "NOP" is "No Operation".

3. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers

are for reference use only.

ADDRESS

DATA

OUT

CLK

Dn+2

tSA tHA

READ

An+1 An+2 An+3 An+4 An+5

Qn+4

WRITE READ

tSC tHC

tSD tHD

tCH tCL

tCYC

tSB tHB

tSW tHW tSW tHW

tCD tCKHZ

UB/LB

R/W

DATA

Dn+3

tOHZ

(1)

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IDT70P9268L Advanced Datasheet

Very Low Power 16K x 16 Synchronous Mobile Multimedia Interface (M2I) Dual Port Static RAM Industrial Temperature Range

Timing Waveform of Non-Mux’d Port Write with Counter Advance

NOTES:

1. CE, UB/LB, and R/W = VIL; CE 1 and REPEAT = VIH.

2. CE, UB/LB = VIL.

3. The "Internal Address" is equal to the "External Address" when ADS = VIL and equals the counter output when ADS = VIH.

4. CNTEN = VIL advances Inter nal Addr ess fro m ‘An ’ to ‘An +1’ . The trans ition s how n ind icates the t ime re quired for the co unter to ad vance . The ‘A n +1’Addre ss is written to duri ng this

cycle.

CLK

Dn+1Dn Dn+2

Dn+1

ADS

tSAD tHAD

tSA tHA

An An+1 An+2 An+3 An+4

tSCN tHCN

Dn+3

WRITE EXTERNAL ADDRESS WRITE WITH COUNTER WRITE COUNTER HOLD

ADDRESS

INTERNAL

ADDRESS

CNTEN

DATA

Dn+4

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IDT70P9268L Advanced Datasheet

Very Low Power 16K x 16 Synchronous Mobile Multimedia Interface (M2I) Dual Port Static RAM Industrial Temperature Range

Timing Waveform of Non-Mux’d Port Operation with Counter Repeat

NOTES:

1. CE, UB/LB = VIL.

2. The "Internal Address" is equal to the "External Address" when ADS = VIL and equals the counter output when ADS = VIH.

3. No dead cycle exists during CNTRPT operation. A READ or WRITE cycle may be coincidental with the counter CNTRPT cycle: Address loaded by last valid ADS load will be accessed.

cycle.

CLK

Data 1Data 0 Data 3

Data 2

ADS

tSAD tHAD

tSA tHA

tSCN tHCN

WRITE TO ADS ADDRESS An ADVANCE COUNTER

WRITE TO An+1

ADDRESS

INTERNAL

ADDRESS

CNTEN

DATA

R/W

An+1 An+2 An+2 An An+1 An+2

tSW tHW

tSRPT tHRPT

Data 1

Data 0

ADVANCE COUNTER

WRITE TO An+2

HOLD COUNTER

WRITE TO An+2

REPEAT

READ LAST ADS ADDRESS An

ADVANCE COUNTER

READ An+1

ADVANCE

COUNTER

READ An+1

CNTRPT

DATA

OUT

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IDT70P9268L Advanced Datasheet

Very Low Power 16K x 16 Synchronous Mobile Multimedia Interface (M2I) Dual Port Static RAM Industrial Temperature Range

Timing Waveform for x8 to x16 Bus Matching

CLK

ADDR

/ DATA

DnAn

R/W

Dn+1An

R/W

ADDR

/ DATA

Dn, Dn+1An

ADS

tSAD tHAD

tSA tHA tSAD tHAD

tSB tHB

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IDT70P9268L Advanced Datasheet

Very Low Power 16K x 16 Synchronous Mobile Multimedia Interface (M2I) Dual Port Static RAM Industrial Temperature Range

Timing Waveform - Interrupt Timing

CLK

ADDR / DATA

tSAD tHAD

3FFE

tSA tHA

Data

tSD tHD

tINS

CLK

tINR

R/W

ADS

INT

tSOE tHOE

ADDR / DATA

3FFE Data

ADS

tSAD tHAD

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IDT70P9268L Advanced Datasheet

Very Low Power 16K x 16 Synchronous Mobile Multimedia Interface (M2I) Dual Port Static RAM Industrial Temperature Range

Timing Waveform - Entering Sleep Mode

Timing Waveform - Exiting Sleep Mode

ADDR / DATA

CLK

R/W

Sleep Mode Set Cycles

No New Reads or Writes AllowedNormal Operation Sleep Mode

DataData

ADDR / DATA

CLK

R/W

No New Reads Or Writes Allowed

Sleep Mode Recovery Cycles

Normal Operation

Sleep Mode

tSAD tHAD

tSA tHA tCD

tSC

tSW

ADS

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IDT70P9268L Advanced Datasheet

Very Low Power 16K x 16 Synchronous Mobile Multimedia Interface (M2I) Dual Port Static RAM Industrial Temperature Range

Functional Description

The 70P9268L provides a true synchronous multiplexed and non-multiplexed Dual-Port Static RAM interface. Registered inputs provide minimal set-

up and hold times on address, data, and all critical control inputs. All internal registers are clocked on the rising edge of the clock signal. Counter

enable and counter repeat inputs are provided to facilitate burst reads and writes to the memory.

Synchronous Interrupts

If the user chooses the interrupt function, a memory location (mail box or message center) is assigned to each por t. The left port interrupt flag (INTL) i s

asserted when the right port writes to memory location 3FFE (HEX), where a write is defined as CER = R/WR = VIL. The left port clears the interrupt

through access of address location 3FFE when CEL = V IL, R/WL = VIH. Likewise, the ri ght port interrupt flag (INT R) is asserted when the left port writes

to memory location 3FFF (HEX) and to clear the interrupt flag (INTR), the right port must read the memory location 3FFF. The message (16 bits) at

3FFE or 3FFF is user-defined since it is an addressable SRAM location. If the interrupt function is not used, address, locations 3FFE and 3FFF are not

used as mail boxes, but as part of the random access memory.

Truth Table IV - Interrupt Flag

Advanced Input Read and Output Drive Registers

The IDT70P9268L is equipped with 8 Special Function (SFX) pins that can be programmed to function as either Input Read Regis ter (IRR) or Output

Drive Register (ODR) pins . IRR pins allow the user to capture the status of external binary state devices and report that status to a processor, ASIC,

FPGA, etc. via a standard read access from either port. ODR pins allow the user to monitor and control the state of external binary state devices via

standard reads and writes from either port. The functionality of the SF pins are determined by the status of the Pin Direction Register (PDR). Refer to

Truth Table V for information on programming the PDR and operating the special function pins.

Truth Table V - Input Read and Output Drive Registers

NOTES:

1. If I/On = H, SFn is programmed as an output and I/On will be used to read and write to this ODR location during subsequent transactions when I/O8 = L. If I/On= L, SFn is programmed

as an input and I/On will be used to read this IRR location during subsequent reads where I/O8 = L.

2. For n = 0-7. If PDRn = 0, I/On = IRRn (the registered value of SFn). If PDRn = 1, I/On = ODRn (the value last written to ODRn).

3. For n = 8-15, I/On = PDRn-8.

4. For I/O0 - I/O7, the value written to I/On will be input to each ODRn location (where PDRn = 1) with a “1” corresponding to “on” and a “0” corresponding to “off”.

Left Port Right Port

CLKL R/WL CEL ADDL INTL CLKR R/WR CER ADDR INTR

Function

Ç L L 3FFF X Ç X X X L Set Right INTR Flag

Ç X X X X Ç H L 3FFF H Reset Right INTR Flag

Ç X X X L Ç L L 3FFE X Set Left INTL Flag

Ç H L 3FFE H Ç X X X X Reset Left INTL Flag

SFEN ADDR R/W I/O0 – I/O7 I/O8 I/O9 – I/O15 Function

L 0 L Note 1 H X Program Pin Direction Register

L 0 H Note 2 Note 3 Note 3 Reading the status of SFn and PDRn

L 0 L Note 4 L X Write to Output Drive Register

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Very Low Power 16K x 16 Synchronous Mobile Multimedia Interface (M2I) Dual Port Static RAM Industrial Temperature Range

Special Function I/O Oper ation

The PDR determines whether the SFX pins will operate as IRR or ODR. The PDR is programmed by writing to address x0000 with SFEN = VIL and

I/O8 = H. Writing a “0” to I/OX will set SFX to be an IRR pin. Writing a “1” to I/OX will set SFX to be an ODR pin.

The status of the Special Function pins and the PD R can be read as a standard memory access to address x0000 from either port and the data is

output via the standard I/Os (Truth Table V). D uring Special Function reads I/O0 - I/O7 output the status of the Special Function pins with I/On corre-

sponding to SFn. I/O8 - I/O15 outputs the status of the Pin Direction Register with I/On = PDRn-8.

For SF pins set to ODR operation, the status of these pins is determined by using standard write accesses from either port to address x0000 with

SFEN = VIL and I/O8 = L. A written “1” will correspond to “on” for the connected binary state device and a written “0” will correspond to “off”.

Sleep Mode

The IDT70P9268 is equipped with an optional sleep or low-power mode on both ports. The sleep mode pin on both ports is asynchronous and active

high. During normal operation, the ZZ- pin is pulled low. When ZZ is pulled high, the port will enter sleep mode where it will meet lowest possible power

conditions. The sleep mode timing diagram shows the modes of operation: Normal Operation, No Read/Write Allowed and Sleep Mode.

For normal operation all inputs must meet setup and hold times prior to s leep and after recovering from sleep. Clocks must also meet cycle high and

low times during these periods. Three cycles prior to asserting ZZ (ZZX = VIH) and three cycles after de-asserting ZZ (ZZX = VIL), the device must be

disabled via the chip enable pins. If a write or a read operation occurs during these periods, the memory array may be corrupted. Val idity of data out

from the RAM cannot be guaranteed immediately after ZZ is asserted (prior to being in sleep). When exiting sleep mode, the device must be in Read

mode (R/WX = VIH) when chip enable is asserted, and the chip enable must be valid for one full cycle before a read will result in the output of valid

data.

During sleep mode the RAM automatically deselects itself. The RAM disconnects its internal clock buffer. The external clock may continue to run

without impacting the RAMs sleep current (IZZ). All outputs wi ll remain in high-Z state w h ile in sleep mode. All inputs are allowed to toggle. The RAM

will not be selected and will not perform any reads or writes.

I/O Function

0 – 7 W ith SFEN = L, I/O8 = H, the value written to address 0 on I/On will determine the

status of PDRn (1 = output, 0 = input). With SFEN = L, I/O8 = L, the value written to

address 0 on I/On will be input to the corresponding ODRn location (1 = on, 0 = off).

8 With SFEN = L, writing a “0” to address 0 on this I/O causes the values of I/O0 – I/O7 to

be input to their corresponding ODR locations. With SFEN = L, writing a “1” to address

0 on this I/O causes the values of I/O0 – I/O7 to be input to their corresponding PDR

locations, which in turn determine whether SF0 – SF7 are individually programmed to

be inputs (IRR) or outputs (ODR).

9 – 15 With SFEN = L, reads to address 0 will output the status of the PDR, where I/On =

PDRn-8

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IDT70P9268L Advanced Datasheet

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San Jose, CA 95138

for SALES:

800-345-7015 or 408-284-8200

fax: 408-284-2775

www.idt.com

for Tech Support:

408-284-2794

DualPortHelp@idt.com

The IDT logo is a registered trademark of Integrated Device Technology, Inc.

Very Low Power 16K x 16 Dual Port Synchronous Static RAM Industrial Temperature Range

Ordering Information

Advanced Datasheet: Definition

"ADVANCED" datasheets contain descriptions for products that are in early release. “Advanced” datasheets are informational only. Advanced speci-

fications are subject to change without notice.

Revision History

02/06/07: Initial Release

XXXXX AA

Device

Type Package Process/

Temperature

Range

Blank

ICommercial (0°C to+70°C)

Industrial (-40°C to+85°C)

70P9268

100-pin FPBGA (BY-100)

16Kx16 Low-Power Dual-Port RAM

GGreen

999

Speed

50 Speed in Megahertz