8523BG www.icst.com/products/hiperclocks.html REV. D SEPTEMBER 13, 2004
1
Integrated
Circuit
Systems, Inc.
ICS8523
LOW SKEW, 1-TO-4
DIFFERENTIAL-TO-HSTL FANOUT BUFFER
BLOCK DIAGRAM PIN ASSIGNMENT
ICS8523
20-Lead TSSOP
6.5mm x 4.4mm x 0.92mm body package
G Package
Top View
GND
CLK_EN
CLK_SEL
CLK
nCLK
PCLK
nPCLK
nc
nc
VDD
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
Q0
nQ0
VDDO
Q1
nQ1
Q2
nQ2
VDDO
Q3
nQ3
GENERAL DESCRIPTION
The ICS8523 is a low skew, high perfor-
mance 1-to-4 Differential-to-HSTL fanout buffer
and a member of the HiPerClockS™ family of High
Performance Clock Solutions from ICS. The
ICS8523 has two selectable clock inputs. The
CLK, nCLK pair can accept most standard differential input
levels. The PCLK, nPCLK pair can accept LVPECL, CML, or
SSTL input levels. The clock enable is internally synchronized
to eliminate runt pulses on the outputs during asynchronous
assertion/deassertion of the clock enable pin.
Guaranteed output and part-to-part skew characteristics
make the ICS8523 ideal for those applications demanding
well defined performance and repeatability.
FEATURES
•4 differential HSTL compatible outputs
•Selectable diffferential CLK, nCLK or LVPECL clock inputs
•CLK, nCLK pair can accept the following differential
input levels: LVDS, LVPECL, HSTL, SSTL, HCSL
•PCLK, nPCLK supports the following input types:
LVPECL, CML, SSTL
•Maximum output frequency: 650MHz
•Translates any single-ended input signal to HSTL
levels with resistor bias on nCLK input
•Output skew: 30ps (maximum)
•Part-to-part skew: 200ps (maximum)
•Propagation delay: 1.6ns (maximum)
•3.3V core, 1.8V output operating supply
•0°C to 70°C ambient operating temperature
•Lead-Free package available
•Industrial temperature information available upon request
HiPerClockS™
ICS
CLK
nCLK
PCLK
nPCLK
Q0
nQ0
Q1
nQ1
Q2
nQ2
Q3
nQ3
0
1
CLK_EN
CLK_SEL
D
Q
LE
8523BG www.icst.com/products/hiperclocks.html REV. D SEPTEMBER 13, 2004
2
Integrated
Circuit
Systems, Inc.
ICS8523
LOW SKEW, 1-TO-4
DIFFERENTIAL-TO-HSTL FANOUT BUFFER
TABLE 1. PIN DESCRIPTIONS
TABLE 2. PIN CHARACTERISTICS
lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU
C
NI
ecnaticapaCtupnI 4Fp
R
PULLUP
rotsiseRpulluPtupnI 15KΩ
R
NWODLLUP
rotsiseRnwodlluPtupnI 15KΩ
rebmuNemaNepyTnoitpircseD
1DNGrewoP.dnuorgylppusrewoP
2NE_KLCtupnIpulluP
kcolcwollofstuptuokcolc,HGIHnehW.elbanek
colcgnizinorhcnyS
decroferastuptuoQn,woldecroferastuptuoQ,WOLnehW.tupni
.slevelecafretniLTTVL/SOMCVL.hg
ih
3LES_KLCtupnInwodlluP
KLCPn,KLCPlaitnereffidstceles,HGIHnehW.tupnitceleskcolC
.stupniKLCn,KLCstceles,WOL
nehW.stupni
.slevelecafretniLTTVL/SOMCVL
4KLCtupnInwodlluP.tupnikcolclaitnereffidgnitrevni-noN
5KLCntupnIpulluP.
tupnikcolclaitnereffidgnitrevnI
6KLCPtupnInwodlluP.tupnikcolcLCEPVLlaitnereffidgnitrevni-noN
7KLCPntupnIpulluP.
tupnikcolcLCEPVLlaitnereffidgnitrevnI
9,8cndesunU.tcennocoN
01V
DD
rewoP.nipylppuseroC
21,113Q,3QntuptuO.slevelecafretniLTSH.riaptuptuolaitnereffiD
81,31V
ODD
rewoP.snipylppustuptuO
51,412Q,2QntuptuO.slevelecafretniLTSH.riaptuptuolaitnereffiD
71,611Q,1QntuptuO.slevelec
afretniLTSH.riaptuptuolaitnereffiD
02,910Q,0QntuptuO.slevelecafretniLTSH.riaptuptuolaitnereffiD
:ETON
pulluP
dna
nwodlluP
.seulavlacipytrof,scitsiretcarahCniP,2elbaTeeS.srotsisertupnilanretniotrefer
8523BG www.icst.com/products/hiperclocks.html REV. D SEPTEMBER 13, 2004
3
Integrated
Circuit
Systems, Inc.
ICS8523
LOW SKEW, 1-TO-4
DIFFERENTIAL-TO-HSTL FANOUT BUFFER
TABLE 3A. CONTROL INPUT FUNCTION TABLE
TABLE 3B. CLOCK INPUT FUNCTION TABLE
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KLCProKLCKLCPnroKLCn3Q:0Q3Qn:0Qn
00WOLHGIHlaitnereffiDotlaitnereffiDgnitre
vnInoN
11 HGIHWOLlaitnereffiDotlaitnereffiDgnitrevnInoN
01ETON;desaiBWOLHGIHlaitnereffiDotdednEelgniSgnitrevnInoN
11
ETON;desaiBHGIHWOLlaitnereffiDotdednEelgniSgnitrevnInoN
1ETON;desaiB0HGIHWOLlaitnereffiDotdednEelgniSgnitrevnI
1
ETON;desaiB1WOLHGIHlaitnereffiDotdednEelgniSgnitrevnI
."sleveLdednEelgniStpeccAottupnIlaitnereffiDehtgniriW
",noitcesnoitamrofnInoitacilppAehtotreferesaelP:1ETON
FIGURE 1. CLK_EN TIMING DIAGRAM
Enabled
Disabled
nCLK, nPCLK
CLK, PCLK
CLK_EN
nQ0:nQ3
Q0:Q3
stupnIstuptuO
NE_KLCLES_KLCecruoSdetceleS3Q:0Q3Qn:0Qn
00 KLCn,KLCWOL;delbasiDHGIH;delbasiD
01 KLCPn,KLCPWOL;delbasiDHGI
H;delbasiD
10 KLCn,KLCdelbanEdelbanE
11 KLCPn,KLCPdelbanEdelbanE
egdekcolctupnignillafdnagnisiragniwollofdelbanero
delbasiderastuptuokcolceht,sehctiwsNE_KLCretfA
.1erugiFninwohssa
debircsedsastupniKLCPn,KLCPdnaKLCn,KLC
ehtfonoitcnufaerastuptuoehtfoetatseht,edomevitcaehtnI
.B3elbaTni
8523BG www.icst.com/products/hiperclocks.html REV. D SEPTEMBER 13, 2004
4
Integrated
Circuit
Systems, Inc.
ICS8523
LOW SKEW, 1-TO-4
DIFFERENTIAL-TO-HSTL FANOUT BUFFER
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = 3.3V±5%, VDDO = 1.8V±0.2V, TA = 0°C TO 70°C
TABLE 4B. LVCMOS / LVTTL DC CHARACTERISTICS, VDD = 3.3V±5%, VDDO = 1.8V±0.2V, TA = 0°C TO 70°C
TABLE 4C. DIFFERENTIAL DC CHARACTERISTICS, VDD = 3.3V±5%, VDDO = 1.8V±0.2V, TA = 0°C TO 70°C
lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU
V
DD
egatloVylppuSrewoPeroC 531.33.3564.3V
V
ODD
egatloVylppuSrewoPtuptuO6.18.10.2V
I
DD
tnerruCylppuSrewoP 05Am
lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU
V
HI
egatloVhgiHtupnILES_KLC,NE_KLC2V
DD
3.0+V
V
LI
egatloVwoLtupnILES_KLC,NE_KLC3.0-8.0V
I
HI
tnerruChgiHtupnI NE_KLCV
DD
V=
NI
V564.3=5Aµ
LES_KLCV
DD
V=
NI
V564.3=051Aµ
I
LI
tnerruCwoLtupnI NE_KLCV
DD
V,V564.3=
NI
V0=051-Aµ
LES_KLCV
DD
V,V564.3=
NI
V0=5-Aµ
lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU
I
HI
tnerruChgiHtupnI KLCnV
DD
V=
NI
V564.3=5Aµ
KLCV
DD
V=
NI
V564.3=051Aµ
I
LI
tnerruCwoLtupnI KLCnV
DD
V,V564.3=
NI
V0=051-Aµ
KLCV
DD
V,V564.3=
NI
V0=5-Aµ
V
PP
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V
RMC
;egatloVtupnIedoMnommoC
2,1ETON 5.0V
DD
58.0-V
VsiKLCndnaKLCrofegatlovtupnimumixamehtsnoitacilppadedneelgnisroF:1ETON
DD
.V3.0+
VsadenifedsiegatlovedomnommoC:2ETON
HI
.
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions be-
yond those listed in the
DC Characteristics
or
AC Character-
istics
is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, V
DD 4.6V
Inputs, VI-0.5V to VDD + 0.5V
Outputs, IO
Continuous Current 50mA
Surge Current 100mA
Package Thermal Impedance, θ
JA 73.2°C/W (0 lfpm)
Storage Temperature, T
STG -65°C to 150°C
8523BG www.icst.com/products/hiperclocks.html REV. D SEPTEMBER 13, 2004
5
Integrated
Circuit
Systems, Inc.
ICS8523
LOW SKEW, 1-TO-4
DIFFERENTIAL-TO-HSTL FANOUT BUFFER
TABLE 4D. LVPECL DC CHARACTERISTICS, VDD = 3.3V±5%, VDDO = 1.8V±0.2V, TA = 0°C TO 70°C
TABLE 5. AC CHARACTERISTICS, VDD = 3.3V±5%, VDDO = 1.8V±0.2V, TA = 0°C TO 70°C
lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU
I
HI
tnerruChgiHtupnI KLCPV
DD
V=
NI
V564.3=051Aµ
KLCPnV
DD
V=
NI
V564.3=5Aµ
I
LI
tnerruCwoLtupnI KLCPV
DD
V,V564.3=
NI
V0=5-Aµ
KLCPnV
DD
V,V564.3=
NI
V0=051-Aµ
V
PP
egatloVtupnIkaeP-ot-kaeP 3.01V
V
RMC
2,1ETON;egatloVtupnIedoMnommoC 5.1V
DD
V
VsadenifedsiegatlovedomnommoC:1ETON
HI
.
VsiKLCPndnaKLCProfegatlovtupnimumixamehtsnoitacilppadedneelgnisroF:2ETON
DD
.V3.0+
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f
XAM
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t
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t
)o(ks4,2ETON;wekStuptuO 03sp
t
)pp(ks4,3ETON;wekStraP-ot-traP 002sp
t
R
emiTesiRtuptuOzHM05@%08ot%02003007sp
t
F
emiTllaFtuptuOzHM05@%08ot%02003007sp
cdoelcyCytuDtuptuO5455%
.esiwrehtodetonsselnuzHM005taderusaemsretemarapllA
.rettijddatonseodtrapehT.tuptuoehtnorettijehtlauqelliwtupniehtnorettijelcycotelcycehT
.tniopgnissorctu
ptuolaitnereffidehtottniopgnissorctupnilaitnereffidehtmorfderusaeM:1ETON
.snoitidnocdaollauqehtiwdnaeg
atlovylppusemasehttastuptuoneewtebwekssadenifeD:2ETON
.stniopssorclaitnereffidtuptuotaderusaeM
segatlov
ylppusemasehttagnitareposecivedtnereffidnostuptuoneewtebwekssadenifeD:3ETON
derusaemerastuptuoeht,eciv
edhcaenostupnifoepytemasehtgnisU.snoitidnocdaollauqehtiwdna
.stniopssorclaitnereffidehtta
.56dradnatSCE
DEJhtiwecnadroccanidenifedsiretemarapsihT:4ETON
TABLE 4D. HSTL DC CHARACTERISTICS, VDD = 3.3V±5%, VDDO = 1.8V±0.2V, TA = 0°C TO 70°C
lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU
V
HO
;egatloVhgiHtuptuO
1ETON 9.04.1V
V
LO
;egatloVwoLtuptuO
1ETON 04.0V
V
XO
egatloVrevossorCtuptuO(x%04V
HO
-V
LO
+)V
LO
V(x%06
HO
V-
LO
V+)
LO
V
V
GNIWS
kaeP-ot-kaeP
gniwSegatloVtuptuO 57.052.1V
05htiwdetanimretstuptuO:1ETON Ω.dnuorgot
8523BG www.icst.com/products/hiperclocks.html REV. D SEPTEMBER 13, 2004
6
Integrated
Circuit
Systems, Inc.
ICS8523
LOW SKEW, 1-TO-4
DIFFERENTIAL-TO-HSTL FANOUT BUFFER
Clock
Outputs 20%
80% 80%
20%
t
R
t
F
V
SWING
Pulse Width
tPERIOD
tPW
tPERIOD
odc =
nQ0:nQ3
Q0:Q3
t
PD
nCLK,
nPCLK
CLK,
PCLK
nQ0:nQ3
Q0:Q3
Qx
nQx
Qy
nQy
PA RT 1
PA RT 2
t
sk(pp)
3.3V/1.8V OUTPUT LOAD AC TEST CIRCUIT DIFFERENTIAL INPUT LEVEL
PART-TO-PART SKEWOUTPUT SKEW
odc & tPERIOD
OUTPUT RISE/FALL TIME PROPAGATION DELAY
PARAMETER MEASUREMENT INFORMATION
t
sk(o)
nQx
Qx
nQy
Qy
V
CMR
Cross Points
V
PP
nCLK, nPCLK
CLK, PCLK
GND
VDD
SCOPE
HSTL
Qx
nQx
3.3V±5%
VDDO
VDD
GND = 0V
1.8V±0.2V
8523BG www.icst.com/products/hiperclocks.html REV. D SEPTEMBER 13, 2004
7
Integrated
Circuit
Systems, Inc.
ICS8523
LOW SKEW, 1-TO-4
DIFFERENTIAL-TO-HSTL FANOUT BUFFER
APPLICATION INFORMATION
Figure 2
shows how the differential input can be wired to accept
single ended levels. The reference voltage V_REF = VDD/2 is
generated by the bias resistors R1, R2 and C1. This bias circuit
should be located as close as possible to the input pin. The ratio
FIGURE 2. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
R2
1K
VDD
CLK_IN
+
-
R1
1K
C1
0.1uF
V_REF
of R1 and R2 might need to be adjusted to position the V_REF in
the center of the input voltage swing. For example, if the input
clock swing is only 2.5V and VDD = 3.3V, V_REF should be 1.25V
and R2/R1 = 0.609.
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
8523BG www.icst.com/products/hiperclocks.html REV. D SEPTEMBER 13, 2004
8
Integrated
Circuit
Systems, Inc.
ICS8523
LOW SKEW, 1-TO-4
DIFFERENTIAL-TO-HSTL FANOUT BUFFER
FIGURE 3C. HIPERCLOCKS CLK/NCLK INPUT DRIVEN BY
3.3V LVPECL DRIVER
FIGURE 3B. HIPERCLOCKS CLK/NCLK INPUT DRIVEN BY
3.3V LVPECL DRIVER
FIGURE 3D. HIPERCLOCKS CLK/NCLK INPUT DRIVEN BY
3.3V LVDS DRIVER
3.3V
R1
50
R3
50
Zo = 50 Ohm
LVPECL
Zo = 50 Ohm
HiPerClockS
CLK
nCLK
3.3V
Input
R2
50
Zo = 50 Ohm
Input
HiPerClockS
CLK
nCLK
3.3V
R3
125
R2
84
Zo = 50 Ohm
3.3V
R4
125
LVPECL
R1
84
3.3V
DIFFERENTIAL CLOCK INPUT INTERFACE
The CLK /nCLK accepts LVDS, LVPECL, HSTL, SSTL, HCSL
and other differential signals. Both VSWING and VOH must meet the
VPP and VCMR input requirements. Figures 3A to 3E show inter-
face examples for the HiPerClockS CLK/nCLK input driven by
the most common driver types. The input interfaces suggested
FIGURE 3A. HIPERCLOCKS CLK/NCLK INPUT DRIVEN BY
ICS HIPERCLOCKS HSTL DRIVER
here are examples only. Please consult with the vendor of the
driver component to confirm the driver termination requirements.
For example in
Figure 3A,
the input termination applies for ICS
HiPerClockS HSTL drivers. If you are using an HSTL driver from
another vendor, use their termination recommendation.
1.8V
R2
50
Input
LVHSTL Driver
ICS
HiPerClockS
R1
50
LVHSTL
3.3V
Zo = 50 Ohm
Zo = 50 Ohm
HiPerClockS
CLK
nCLK
FIGURE 3E. HIPERCLOCKS CLK/NCLK INPUT DRIVEN BY
3.3V LVPECL DRIVER WITH AC COUPLE
Zo = 50 Ohm
R3
125
HiPerClockS
CLK
nCLK
3.3V
R5
100 - 200
3.3V
R2
84
3.3V
R6
100 - 200
Input
R5,R6 locate near the driver pin.
Zo = 50 Ohm
R1
84
R4
125
C2
LVPECL C1
Zo = 50 Ohm
R1
100
3.3V
LVDS_Driv er
Zo = 50 Ohm
Receiv er
CLK
nCLK
3.3V
8523BG www.icst.com/products/hiperclocks.html REV. D SEPTEMBER 13, 2004
9
Integrated
Circuit
Systems, Inc.
ICS8523
LOW SKEW, 1-TO-4
DIFFERENTIAL-TO-HSTL FANOUT BUFFER
LVPECL CLOCK INPUT INTERFACE
The PCLK /nPCLK accepts LVPECL, CML, SSTL and other
differential signals. Both VSWING and VOH must meet the VPP
and VCMR input requirements.
Figures 4A to 4F
show interface
examples for the HiPerClockS PCLK/nPCLK input driven by
the most common driver types. The input interfaces suggested
here are examples only. If the driver is from another vendor,
use their termination recommendation. Please consult with
the vendor of the driver component to confirm the driver ter-
mination requirements.
FIGURE 4A. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN
BY AN OPEN COLLECTOR CML DRIVER
FIGURE 4B. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN
BY A BUILT-IN PULLUP CML DRIVER
FIGURE 4C. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN
BY A 3.3V LVPECL DRIVER
FIGURE 4F. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN
BY A 3.3V LVDS DRIVER
PCLK/nPCLK
2.5V
Zo = 60 Ohm
SSTL
HiPerClockS
PCLK
nPCLK
R2
120
3.3V
R3
120
Zo = 60 Ohm
R1
120
R4
120
2.5V
FIGURE 4E. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN
BY AN SSTL DRIVER
HiPerClockS
PCLK
nPCLK
PCLK/nPCLK
3.3V
R2
50
R1
50
3.3V
Zo = 50 Ohm
CML
3.3V
Zo = 50 Ohm
3.3V
HiPerClockS
PCLK
nPCLK
R2
84
R3
125
Input
Zo = 50 Ohm
R4
125
R1
84
LVPECL
3.3V
3.3V
Zo = 50 Ohm
C2
R2
1K
R5
100
Zo = 50 Ohm
3.3V
3.3V
C1
R3
1K
LVDS
R4
1K
HiPerClockS
PCLK
nPCLK
R1
1K
Zo = 50 Ohm
3.3V
PCLK/nPCLK
3.3V
R5
100 - 200
3.3V
3.3V
HiPerClockS
PCLK
nPCLK
R1
125
PCLK/nPCLK
R2
125
R3
84
C1
C2
Zo = 50 Ohm
R4
84
Zo = 50 Ohm
R6
100 - 200
3.3V LVPECL
FIGURE 4D. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN
BY A 3.3V LVPECL DRIVER WITH AC COUPLE
3.3V
3.3V
CML Built-In Pullup
R1
100
PCLK
nPCLK
HiPerClockS
PCLK/nPCLK
Zo = 50 Ohm
Zo = 50 Ohm
8523BG www.icst.com/products/hiperclocks.html REV. D SEPTEMBER 13, 2004
10
Integrated
Circuit
Systems, Inc.
ICS8523
LOW SKEW, 1-TO-4
DIFFERENTIAL-TO-HSTL FANOUT BUFFER
SCHEMATIC EXAMPLE
Figure 5
shows a schematic example of the ICS8523. In this
example, the input is driven by an ICS HiPerClockS HSTL driver.
The decoupling capacitors should be physically located near the
1.8V
LVHSTL Driver
Zo = 50
Zo = 50
C2
0.1u
R5
50
R6
50
R10
50
1.8V
R11
1K
R3
50
Zo = 50 Ohm
U3
8523
1
2
3
4
5
6
7
8
9
10 11
12
13
14
15
16
20
19
18
17
GND
CLK_EN
CLK_SEL
CLK
nCLK
PCLK
nPCLK
NC
NC
VDD nQ3
Q3
VDDO
nQ2
Q2
nQ1
Q0
nQ0
VDDO
Q1
Zo = 50
+
-
Zo = 50 Ohm
Zo = 50
R4
50
R12
1K
R1
50
1.8V
1.8V
+
-
R7
50
R2
50
3.3V
C3
0.1u
R9
50
+
-
Zo = 50
R8
50
+
-
Zo = 50
3.3V
Zo = 50
Zo = 50
C1
0.1u
FIGURE 5. ICS8523 HSTL BUFFER SCHEMATIC EXAMPLE
power pin. For ICS8523, the unused clock outputs can be left
floating.
8523BG www.icst.com/products/hiperclocks.html REV. D SEPTEMBER 13, 2004
11
Integrated
Circuit
Systems, Inc.
ICS8523
LOW SKEW, 1-TO-4
DIFFERENTIAL-TO-HSTL FANOUT BUFFER
POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS8523.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS8523 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
•Power (core)MAX = VDD_MAX * IDD_MAX = 3.465V * 50mA = 173.3mW
•Power (outputs)MAX = 32.6mW/Loaded Output pair
If all outputs are loaded, the total power is 4 * 32.6mW = 130.4mW
Total Power_MAX (3.465V, with all outputs switching) = 173.3mW + 130.4mW = 303.7mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
device. The maximum recommended junction temperature for HiPerClockSTM devices is 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = Junction Temperature
θJA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA
must be used. Assuming a
moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 66.6°C/W per Table 6 below.
Therefore, Tj for an ambient temperature of 70°C with all outputs switching is:
70°C + 0.304W * 66.6°C/W = 90.2°C. This is well below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,
and the type of board (single layer or multi-layer).
θθ
θθ
θJA by Velocity (Linear Feet per Minute)
0 200 500
Single-Layer PCB, JEDEC Standard Test Boards 114.5°C/W 98.0°C/W 88.0°C/W
Multi-Layer PCB, JEDEC Standard Test Boards 73.2°C/W 66.6°C/W 63.5°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TABLE 6. THERMAL RESISTANCE θθ
θθ
θJA FOR 20-PIN TSSOP, FORCED CONVECTION
8523BG www.icst.com/products/hiperclocks.html REV. D SEPTEMBER 13, 2004
12
Integrated
Circuit
Systems, Inc.
ICS8523
LOW SKEW, 1-TO-4
DIFFERENTIAL-TO-HSTL FANOUT BUFFER
3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load.
HSTL output driver circuit and termination are shown in
Figure 6.
To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load.
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
Pd_H = (V
OH_MIN
/R
L
) * (V
DDO_MAX
- V
OH_MIN
)
Pd_L = (V
OL_MAX
/R
L
) * (V
DDO_MAX
- V
OL_MAX
)
Pd_H = (0.9V/50Ω) * (2V - 0.9V) = 19.8mW
Pd_L = (0.4V/50Ω) * (2V - 0.4V) = 12.8mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 32.6mW
FIGURE 6. HSTL DRIVER CIRCUIT AND TERMINATION
VDDO
VOUT
RL
50Ω
Q1
8523BG www.icst.com/products/hiperclocks.html REV. D SEPTEMBER 13, 2004
13
Integrated
Circuit
Systems, Inc.
ICS8523
LOW SKEW, 1-TO-4
DIFFERENTIAL-TO-HSTL FANOUT BUFFER
RELIABILITY INFORMATION
TRANSISTOR COUNT
The transistor count for ICS8523 is: 472
TABLE 7. θJAVS. AIR FLOW TABLE FOR 20 LEAD TSSOP
θθ
θθ
θJA by Velocity (Linear Feet per Minute)
0 200 500
Single-Layer PCB, JEDEC Standard Test Boards 114.5°C/W 98.0°C/W 88.0°C/W
Multi-Layer PCB, JEDEC Standard Test Boards 73.2°C/W 66.6°C/W 63.5°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
8523BG www.icst.com/products/hiperclocks.html REV. D SEPTEMBER 13, 2004
14
Integrated
Circuit
Systems, Inc.
ICS8523
LOW SKEW, 1-TO-4
DIFFERENTIAL-TO-HSTL FANOUT BUFFER
PACKAGE OUTLINE - G SUFFIX FOR 20 LEAD TSSOP
TABLE 8. PACKAGE DIMENSIONS
Reference Document: JEDEC Publication 95, MS-153
LOBMYS sretemilliM
muminiMmumixaM
N02
A--02.1
1A50.051.0
2A08.050.1
b91.003.0
c90.002.0
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ECISAB04.6
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aaa--01.0
8523BG www.icst.com/products/hiperclocks.html REV. D SEPTEMBER 13, 2004
15
Integrated
Circuit
Systems, Inc.
ICS8523
LOW SKEW, 1-TO-4
DIFFERENTIAL-TO-HSTL FANOUT BUFFER
TABLE 9. ORDERING INFORMATION
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement
of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications.
Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by
ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments.
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The aforementioned trademark, HiPerClockS™ is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries.
8523BG www.icst.com/products/hiperclocks.html REV. D SEPTEMBER 13, 2004
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Integrated
Circuit
Systems, Inc.
ICS8523
LOW SKEW, 1-TO-4
DIFFERENTIAL-TO-HSTL FANOUT BUFFER
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