© Semiconductor Components Industries, LLC, 2011
June, 2011 − Rev. 12
1Publication Order Number:
MC14051B/D
MC14051B, MC14052B,
MC14053B
Analog
Multiplexers/Demultiplexers
The MC14051B, MC14052B, and MC14053B analog multiplexers
are digitally−controlled analog switches. The MC14051B effectively
implements an SP8T solid state switch, the MC14052B a DP4T, and
the MC14053B a Triple SPDT. All three devices feature low ON
impedance and very low OFF leakage current. Control of analog
signals up to the complete supply voltage range can be achieved.
Features
•Triple Diode Protection on Control Inputs
•Switch Function is Break Before Make
•Supply Voltage Range = 3.0 Vdc to 18 Vdc
•Analog Voltage Range (VDD − VEE) = 3.0 to 18 V
Note: VEE must be v VSS
•Linearized Transfer Characteristics
•Low−noise − 12 nV/√Cycle, f ≥ 1.0 kHz Typical
•Pin−for−Pin Replacement for CD4051, CD4052, and CD4053
•For 4PDT Switch, See MC14551B
•For Lower RON, Use the HC4051, HC4052, or HC4053
High−Speed CMOS Devices
•These Devices are Pb−Free and are RoHS Compliant
MAXIMUM RATINGS (Voltages Referenced to VSS)
Symbol Parameter Value Unit
VDD DC Supply Voltage Range
(Referenced to VEE, VSS ≥ VEE)
−0.5 to +18.0 V
Vin,
Vout
Input or Output Voltage Range
(DC or Transient) (Referenced to VSS for
Control Inputs and VEE for Switch I/O)
−0.5 to VDD + 0.5 V
Iin Input Current (DC or Transient)
per Control Pin
+10 mA
ISW Switch Through Current ±25 mA
PDPower Dissipation per Package (Note 1) 500 mW
TAAmbient Temperature Range −55 to +125 °C
Tstg Storage Temperature Range −65 to +150 °C
TLLead Temperature (8−Second Soldering) 260 °C
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
1. Temperature Derating: Plastic “P and D/DW” Packages: – 7.0 mW/_C From
65_C To 125_C
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
high−impedance circuit. For proper operation, Vin and Vout should be constrained to
the range VSS v (Vin or Vout) v VDD.
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either
VSS, VEE or VDD). Unused outputs must be left open.
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MARKING
DIAGRAMS
PDIP−16
P SUFFIX
CASE 648
MC1405xBCP
AWLYYWWG
SOIC−16
D SUFFIX
CASE 751B
TSSOP−16
DT SUFFIX
CASE 948F
SOEIAJ−16
F SUFFIX
CASE 966
See detailed ordering and shipping information in the package
dimensions section on page 9 of this data sheet.
ORDERING INFORMATION
16
1
1405xBG
AWLYWW
14
05xB
ALYWG
G
1
1
16
1
1
16
1
MC1405xB
ALYWG
1
16
x = 1, 2, or 3
A = Assembly Location
WL, L = Wafer Lot
Y = Year
WW, W = Work Week
G or G= Pb−Free Package
(Note: Microdot may be in either location)
1
MC14051B, MC14052B, MC14053B
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2
MC14051B
8−Channel Analog
Multiplexer/Demultiplexer
MC14052B
Dual 4−Channel Analog
Multiplexer/Demultiplexer
MC14053B
Triple 2−Channel Analog
Multiplexer/Demultiplexer
VDD = PIN 16
VSS = PIN 8
VEE = PIN 7
Note: Control Inputs referenced to VSS, Analog Inputs and Outputs reference to VEE. VEE must be ≤ VSS.
INHIBIT
A
B
C
X0
X1
X2
X3
X4
X5
X6
X7
X
4
2
5
1
12
15
14
13
9
10
11
6
CONTROLS
SWITCHES
IN/OUT
COMMON
OUT/IN
3
4
2
5
1
11
15
14
12
9
10
6
CONTROLS
SWITCHES
IN/OUT
13
3
COMMONS
OUT/IN
X
Y
VDD = PIN 16
VSS = PIN 8
VEE = PIN 7
3
5
1
2
13
12
9
10
11
6
CONTROLS
SWITCHES
IN/OUT
14
15
4
X
Y
Z
COMMONS
OUT/IN
VDD = PIN 16
VSS = PIN 8
VEE = PIN 7
INHIBIT
A
B
X0
X1
X2
X3
Y0
Y1
Y2
Y3
INHIBIT
A
B
C
X0
Y0
Y1
Z0
Z1
X1
PIN ASSIGNMENT
MC14051B MC14052B MC14053B
13
14
15
16
9
10
11
125
4
3
2
1
8
7
6
X3
X0
X1
X2
VDD
C
B
A
X7
X
X6
X4
VSS
VEE
INH
X5
13
14
15
16
9
10
11
125
4
3
2
1
8
7
6
X0
X
X1
X2
VDD
B
A
X3
Y3
Y
Y2
Y0
VSS
VEE
INH
Y1
13
14
15
16
9
10
11
125
4
3
2
1
8
7
6
X0
X1
X
Y
VDD
C
B
A
Z
Z1
Y0
Y1
VSS
VEE
INH
Z0
MC14051B, MC14052B, MC14053B
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3
ELECTRICAL CHARACTERISTICS
Characteristic Symbol VDD Test Conditions
− 55_C 25_C 125_C
Unit
Min Max Min Typ
(Note 2)
Max Min Max
SUPPLY REQUIREMENTS (Voltages Referenced to VEE)
Power Supply Voltage
Range
VDD −VDD – 3.0 ≥ VSS ≥ VEE 3.0 18 3.0 −18 3.0 18 V
Quiescent Current Per
Package
IDD 5.0
10
15
Control Inputs:
Vin = VSS or VDD,
Switch I/O: VEE v VI/O v
VDD, and DVswitch v
500 mV (Note 3)
−
−
−
5.0
10
20
−
−
−
0.005
0.010
0.015
5.0
10
20
−
−
−
150
300
600
mA
Total Supply Current
(Dynamic Plus
Quiescent, Per Package
ID(AV) 5.0
10
15
TA = 25_C only (The
channel component,
(Vin – Vout)/Ron, is
not included.)
(0.07 mA/kHz) f + IDD
Typical (0.20 mA/kHz) f + IDD
(0.36 mA/kHz) f + IDD
mA
CONTROL INPUTS — INHIBIT, A, B, C (Voltages Referenced to VSS)
Low−Level Input Voltage VIL 5.0
10
15
Ron = per spec,
Ioff = per spec
−
−
−
1.5
3.0
4.0
−
−
−
2.25
4.50
6.75
1.5
3.0
4.0
−
−
−
1.5
3.0
4.0
V
High−Level Input Voltage VIH 5.0
10
15
Ron = per spec,
Ioff = per spec
3.5
7.0
11
−
−
−
3.5
7.0
11
2.75
5.50
8.25
−
−
−
3.5
7.0
11
−
−
−
V
Input Leakage Current Iin 15 Vin = 0 or VDD −± 0.1 −±0.00001 ± 0.1 −1.0 mA
Input Capacitance Cin − − − − 5.0 7.5 − − pF
SWITCHES IN/OUT AND COMMONS OUT/IN — X, Y, Z (Voltages Referenced to VEE)
Recommended
Peak−to−Peak Voltage
Into or Out of the Switch
VI/O −Channel On or Off 0 VDD 0−VDD 0 VDD VPP
Recommended Static or
Dynamic Voltage Across
the Switch (Note 3)
(Figure 5)
DVswitch −Channel On 0 600 0 −600 0 300 mV
Output Offset Voltage VOO −Vin = 0 V, No Load − − − 10 − − − mV
ON Resistance Ron 5.0
10
15
DVswitch v 500 mV
(Note 3) Vin = VIL or VIH
(Control), and Vin =
0 to VDD (Switch)
−
−
−
800
400
220
−
−
−
250
120
80
1050
500
280
−
−
−
1200
520
300
W
DON Resistance Between
Any Two Channels in the
Same Package
DRon 5.0
10
15
−
−
−
70
50
45
−
−
−
25
10
10
70
50
45
−
−
−
135
95
65
W
Off−Channel Leakage
Current (Figure 10)
Ioff 15 Vin = VIL or VIH
(Control) Channel to
Channel or Any One
Channel
−± 100 −± 0.05 ± 100 −±1000 nA
Capacitance, Switch I/O CI/O −Inhibit = VDD − − − 10 − − − pF
Capacitance, Common O/I CO/I −Inhibit = VDD
(MC14051B)
(MC14052B)
(MC14053B)
−
−
−
−
−
−
−
−
−
60
32
17
−
−
−
−
−
−
−
−
−
pF
Capacitance, Feedthrough
(Channel Off)
CI/O −
−
Pins Not Adjacent
Pins Adjacent
−
−
−
−
−
−
0.15
0.47
−
−
−
−
−
−
pF
2. Data labeled “Typ” is not to be used for design purposes, but is intended as an indication of the IC’s potential performance.
3. For voltage drops across the switch (DVswitch) > 600 mV ( > 300 mV at high temperature), excessive VDD current may be drawn, i.e. the
current out of the switch may contain both VDD and switch input components. The reliability of the device will be unaffected unless the
Maximum Ratings are exceeded. (See first page of this data sheet.)
MC14051B, MC14052B, MC14053B
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4
ELECTRICAL CHARACTERISTICS (Note 4) (CL = 50 pF, TA = 25_C) (VEE v VSS unless otherwise indicated)
Characteristic Symbol VDD – VEE
Vdc
Typ (Note 5)
All Types
Max Unit
Propagation Delay Times (Figure 6)
Switch Input to Switch Output (RL = 1 kW)
MC14051
tPLH, tPHL = (0.17 ns/pF) CL + 26.5 ns
tPLH, tPHL = (0.08 ns/pF) CL + 11 ns
tPLH, tPHL = (0.06 ns/pF) CL + 9.0 ns
tPLH, tPHL
5.0
10
15
35
15
12
90
40
30
ns
MC14052
tPLH, tPHL = (0.17 ns/pF) CL + 21.5 ns
tPLH, tPHL = (0.08 ns/pF) CL + 8.0 ns
tPLH, tPHL = (0.06 ns/pF) CL + 7.0 ns
5.0
10
15
30
12
10
75
30
25
ns
MC14053
tPLH, tPHL = (0.17 ns/pF) CL + 16.5 ns
tPLH, tPHL = (0.08 ns/pF) CL + 4.0 ns
tPLH, tPHL = (0.06 ns/pF) CL + 3.0 ns
5.0
10
15
25
8.0
6.0
65
20
15
ns
Inhibit to Output (RL = 10 kW, VEE = VSS)
Output “1” or “0” to High Impedance, or
High Impedance to “1” or “0” Level
MC14051B
tPHZ, tPLZ,
tPZH, tPZL
5.0
10
15
350
170
140
700
340
280
ns
MC14052B 5.0
10
15
300
155
125
600
310
250
ns
MC14053B 5.0
10
15
275
140
110
550
280
220
ns
Control Input to Output (RL = 1 kW, VEE = VSS)
MC14051B
tPLH, tPHL
5.0
10
15
360
160
120
720
320
240
ns
MC14052B 5.0
10
15
325
130
90
650
260
180
ns
MC14053B 5.0
10
15
300
120
80
600
240
160
ns
Second Harmonic Distortion
(RL = 10KW, f = 1 kHz) Vin = 5 VPP
−10 0.07 −%
Bandwidth (Figure 7)
(RL = 50 W, Vin = 1/2 (VDD−VEE) p−p, CL = 50pF
20 Log (Vout/Vin) = − 3 dB)
BW 10 17 −MHz
Off Channel Feedthrough Attenuation (Figure 7)
RL = 1KW, Vin = 1/2 (VDD − VEE) p−p
fin = 4.5 MHz — MC14051B
fin = 30 MHz — MC14052B
fin = 55 MHz — MC14053B
−10 – 50 −dB
Channel Separation (Figure 8)
(RL = 1 kW, Vin = 1/2 (VDD−VEE) p−p,
fin = 3.0 MHz
−10 – 50 −dB
Crosstalk, Control Input to Common O/I (Figure 9)
(R1 = 1 kW, RL = 10 kW
Control tTLH = tTHL = 20 ns, Inhibit = VSS)
−10 75 −mV
4. The formulas given are for the typical characteristics only at 25_C.
5. Data labelled “Typ” is not lo be used for design purposes but In intended as an indication of the IC’s potential performance.
MC14051B, MC14052B, MC14053B
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5
Figure 1. Switch Circuit Schematic
IN/OUT
LEVEL
CONVERTED
CONTROL
VDD
VEE
VDD VDD
VDD
OUT/IN
VEE
IN/OUT OUT/IN
CONTROL
TRUTH TABLE
Control Inputs
ON Switches
Inhibit
Select
C* B A MC14051B MC14052B MC14053B
0 0 0 0 X0 Y0 X0 Z0 Y0 X0
0 0 01 X1 Y1 X1 Z0 Y0 X1
0 0 10 X2 Y2 X2 Z0 Y1 X0
0 0 11 X3 Y3 X3 Z0 Y1 X1
0 1 0 0 X4 Z1 Y0 X0
0 1 01 X5 Z1 Y0 X1
0 1 10 X6 Z1 Y1 X0
0 1 11 X7 Z1 Y1 X1
1 x x x None None None
*Not applicable for MC14052
x = Don’t Care
Figure 3. MC14052B Functional Diagram Figure 4. MC14053B Functional Diagram
16 VDD
8V
SS 7V
EE
13X
3Y
BINARY TO 1-OF-4
DECODER WITH
INHIBIT
LEVEL
CONVERTER
INH6
A10
B9
X012
X114
X215
X311
Y01
Y15
Y22
Y34
BINARY TO 1-OF-2
DECODER WITH
INHIBIT
LEVEL
CONVERTER
16 VDD
8V
SS 7V
EE
14X
15Y
4Z
INH6
A11
B10
C9
X012
X113
Y02
Y11
Z05
Z13
Figure 2. MC14051B Functional Diagram
INH6
A11
B10
C9
X013
X114
X215
X312
X41
X55
X62
X74
8V
SS 7V
EE
16 VDD
3X
BINARY TO 1-OF-8
DECODER WITH
INHIBIT
LEVEL
CONVERTER
MC14051B, MC14052B, MC14053B
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6
TEST CIRCUITS
Figure 5. DV Across Switch Figure 6. Propagation Delay Times,
Control and Inhibit to Output
Figure 7. Bandwidth and Off−Channel
Feedthrough Attenuation
Figure 8. Channel Separation
(Adjacent Channels Used For Setup)
Figure 9. Crosstalk, Control Input to
Common O/I
Figure 10. Off Channel Leakage
CONTROL
SECTION
OF IC
SOURCE
V
ON SWITCH
PULSE
GENERATOR
INH
A
B
C
RLCL
Vout
VDD VEE VEE VDD
INH
A
B
C
VSS
Vin
RLCL = 50 pF
Vout
VDD - VEE
2
INH
A
B
C
OFF
ON
RL
RLCL = 50 pF
Vout
Vin
VDD - VEE
2
INH
A
B
C
R1
RLCL = 50 pF
Vout
CONTROL
SECTION
OF IC
OFF CHANNEL UNDER TEST
OTHER
CHANNEL(S)
COMMON
VDD
VEE
VEE
VDD
VEE
VDD
NOTE: See also Figures 7 and 8 in the MC14016B data sheet.
A, B, and C inputs used to turn ON
or OFF the switch under test.
LOAD
MC14051B, MC14052B, MC14053B
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7
Figure 11. Channel Resistance (RON) Test Circuit
VDD
VEE = VSS
10 k
VDD
KEITHLEY 160
DIGITAL
MULTIMETER
1 kW
RANGE X-Y
PLOTTER
TYPICAL RESISTANCE CHARACTERISTICS
Figure 12. VDD = 7.5 V, VEE = − 7.5 V Figure 13. VDD = 5.0 V, VEE = − 5.0 V
RON, “ON” RESISTANCE (OHMS)
350
300
250
200
150
100
0
50
-8.0-10 -6.0 -4.0 -2.0 0 0.2 4.0 6.0 8.0 10
Vin, INPUT VOLTAGE (VOLTS)
TA = 125°C
25°C
-55°C
RON, “ON” RESISTANCE (OHMS)
350
300
250
200
150
100
0
50
-8.0-10 -6.0 -4.0 -2.0 0 0.2 4.0 6.0 8.0 10
Vin, INPUT VOLTAGE (VOLTS)
TA = 125°C
25°C
-55°C
Figure 14. VDD = 2.5 V, VEE = − 2.5 V
RON, “ON” RESISTANCE (OHMS)
700
600
500
400
300
200
0
100
-8.0-10 -6.0 -4.0 -2.0 0 0.2 4.0 6.0 8.0 10
Vin, INPUT VOLTAGE (VOLTS)
TA = 125°C
25°C
-55°C
Figure 15. Comparison at 25°C, VDD = −VEE
RON, “ON” RESISTANCE (OHMS)
350
300
250
200
150
100
0
50
-8.0-10 -6.0 -4.0 -2.0 0 0.2 4.0 6.0 8.0 10
Vin, INPUT VOLTAGE (VOLTS)
TA = 25°C
VDD = 2.5 V
5.0 V
7.5 V
MC14051B, MC14052B, MC14053B
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8
APPLICATIONS INFORMATION
Figure A illustrates use of the on−chip level converter
detailed in Figures 2, 3, and 4. The 0−to−5 V Digital Control
signal is used to directly control a 9 Vp−p analog signal.
The digital control logic levels are determined by VDD
and VSS. The VDD voltage is the logic high voltage; the VSS
voltage is logic low. For the example, VDD = + 5 V = logic
high at the control inputs; VSS = GND = 0 V = logic low.
The maximum analog signal level is determined by VDD
and VEE. The VDD voltage determines the maximum
recommended peak above VSS. The VEE voltage
determines the maximum swing below VSS. For the
example, VDD − VSS = 5 V maximum swing above VSS;
VSS − VEE = 5 V maximum swing below VSS. The example
shows a ± 4.5 V signal which allows a 1/2 volt margin at each
peak. If voltage transients above VDD and/or below VEE are
anticipated on the analog channels, external diodes (Dx) are
recommended as shown in Figure B. These diodes should be
small signal types able to absorb the maximum anticipated
current surges during clipping.
The absolute maximum potential difference between
VDD and VEE is 18.0 V. Most parameters are specified up to
15 V which is the recommended maximum difference
between VDD and VEE.
Balanced supplies are not required. However, VSS must
be greater than or equal to VEE. For example, VDD = + 10
V, V SS = + 5 V, and VEE – 3 V is acceptable. See the Table
below.
Figure A. Application Example
+5 V -5 V
VDD VSS VEE
9 Vp-p
ANALOG SIGNAL
0-TO-5 V DIGITAL
CONTROL SIGNALS
SWITCH
I/O
INHIBIT,
A, B, C
COMMON
O/I
9 Vp-p
ANALOG SIGNAL
+4.5 V
−4.5 V
GND
+5 V
EXTERNAL
CMOS
DIGITAL
CIRCUITRY
MC14051B
MC14052B
MC14053B
Figure B. External Germanium or Schottky Clipping Diodes
VDD VDD
VEE VEE
DXDX
DXDX
ANALOG
I/O
COMMON
O/I
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
POSSIBLE SUPPLY CONNECTIONS
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
VDD
In Volts
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
VSS
In Volts
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
VEE
In Volts
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
Control Inputs
Logic High/Logic Low
In Volts
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
Maximum Analog Signal Range
In Volts
ÎÎÎÎ
ÎÎÎÎ
+ 8
ÎÎÎÎÎ
ÎÎÎÎÎ
0
ÎÎÎÎ
ÎÎÎÎ
– 8
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
+ 8/0
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
+ 8 to – 8 = 16 Vp–p
ÎÎÎÎ
ÎÎÎÎ
+ 5
ÎÎÎÎÎ
ÎÎÎÎÎ
0
ÎÎÎÎ
ÎÎÎÎ
– 12
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
+ 5/0
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
+ 5 to – 12 = 17 Vp–p
ÎÎÎÎ
ÎÎÎÎ
+ 5
ÎÎÎÎÎ
ÎÎÎÎÎ
0
ÎÎÎÎ
ÎÎÎÎ
0
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
+ 5/0
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
+ 5 to 0 = 5 Vp–p
ÎÎÎÎ
ÎÎÎÎ
+ 5
ÎÎÎÎÎ
ÎÎÎÎÎ
0
ÎÎÎÎ
ÎÎÎÎ
– 5
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
+ 5/0
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
+ 5 to – 5 = 10 Vp–p
ÎÎÎÎ
ÎÎÎÎ
+ 10
ÎÎÎÎÎ
ÎÎÎÎÎ
+ 5
ÎÎÎÎ
ÎÎÎÎ
– 5
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
+ 10/ + 5
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
+ 10 to – 5 = 15 Vp–p
MC14051B, MC14052B, MC14053B
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9
ORDERING INFORMATION
Device Package Shipping†
MC14051BCPG PDIP−16
(Pb−Free)
500 Units / Rail
MC14051BDG SOIC−16
(Pb−Free)
48 Units / Rail
MC14051BDR2G SOIC−16
(Pb−Free)
2500 / Tape & Reel
MC14051BDTR2G TSSOP−16* 2500 / Tape & Reel
MC14051BFG SOEIAJ−16
(Pb−Free)
50 Units / Rail
MC14051BFELG SOEIAJ−16
(Pb−Free)
2000 / Tape & Reel
MC14052BCPG PDIP−16
(Pb−Free)
500 Units / Rail
MC14052BDG SOIC−16
(Pb−Free)
48 Units / Rail
MC14052BDR2G SOIC−16
(Pb−Free)
2500 / Tape & Reel
MC14052BDTR2G TSSOP−16* 2500 / Tape & Reel
MC14052BFG SOEIAJ−16
(Pb−Free)
50 Units / Rail
MC14052BFELG SOEIAJ−16
(Pb−Free)
2000 / Tape & Reel
MC14053BCPG PDIP−16
(Pb−Free)
500 Units / Rail
MC14053BDG SOIC−16
(Pb−Free)
48 Units / Rail
MC14053BDR2G SOIC−16
(Pb−Free)
2500 / Tape & Reel
MC14053BDTR2G TSSOP−16* 2500 / Tape & Reel
MC14053BFG SOEIAJ−16
(Pb−Free)
50 Units / Rail
MC14053BFELG SOEIAJ−16
(Pb−Free)
2000 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*This package is inherently Pb−Free.
MC14051B, MC14052B, MC14053B
http://onsemi.com
10
PACKAGE DIMENSIONS
PDIP−16
P SUFFIX
PLASTIC DIP PACKAGE
CASE 648−08
ISSUE T
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS
WHEN FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE
MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
−A−
B
FC
S
H
GD
J
L
M
16 PL
SEATING
18
916
K
PLANE
−T−
M
A
M
0.25 (0.010) T
DIM MIN MAX MIN MAX
MILLIMETERSINCHES
A0.740 0.770 18.80 19.55
B0.250 0.270 6.35 6.85
C0.145 0.175 3.69 4.44
D0.015 0.021 0.39 0.53
F0.040 0.70 1.02 1.77
G0.100 BSC 2.54 BSC
H0.050 BSC 1.27 BSC
J0.008 0.015 0.21 0.38
K0.110 0.130 2.80 3.30
L0.295 0.305 7.50 7.74
M0 10 0 10
S0.020 0.040 0.51 1.01
____
SOIC−16
D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751B−05
ISSUE K
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR PROTRUSION
SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D
DIMENSION AT MAXIMUM MATERIAL CONDITION.
18
16 9
SEATING
PLANE
F
J
M
RX 45_
G
8 PLP
−B−
−A−
M
0.25 (0.010) B S
−T−
D
K
C
16 PL
S
B
M
0.25 (0.010) A S
T
DIM MIN MAX MIN MAX
INCHESMILLIMETERS
A9.80 10.00 0.386 0.393
B3.80 4.00 0.150 0.157
C1.35 1.75 0.054 0.068
D0.35 0.49 0.014 0.019
F0.40 1.25 0.016 0.049
G1.27 BSC 0.050 BSC
J0.19 0.25 0.008 0.009
K0.10 0.25 0.004 0.009
M0 7 0 7
P5.80 6.20 0.229 0.244
R0.25 0.50 0.010 0.019
____
MC14051B, MC14052B, MC14053B
http://onsemi.com
11
PACKAGE DIMENSIONS
TSSOP−16
DT SUFFIX
PLASTIC TSSOP PACKAGE
CASE 948F−01
ISSUE B
ÇÇÇ
ÇÇÇ
DIM MIN MAX MIN MAX
INCHESMILLIMETERS
A4.90 5.10 0.193 0.200
B4.30 4.50 0.169 0.177
C−−− 1.20 −−− 0.047
D0.05 0.15 0.002 0.006
F0.50 0.75 0.020 0.030
G0.65 BSC 0.026 BSC
H0.18 0.28 0.007 0.011
J0.09 0.20 0.004 0.008
J1 0.09 0.16 0.004 0.006
K0.19 0.30 0.007 0.012
K1 0.19 0.25 0.007 0.010
L6.40 BSC 0.252 BSC
M0 8 0 8
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD FLASH.
PROTRUSIONS OR GATE BURRS. MOLD FLASH OR
GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER
SIDE.
4. DIMENSION B DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION. INTERLEAD FLASH OR
PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER
SIDE.
5. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR PROTRUSION
SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K
DIMENSION AT MAXIMUM MATERIAL CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE DETERMINED AT
DATUM PLANE -W-.
____
SECTION N−N
SEATING
PLANE
IDENT.
PIN 1
18
16 9
DETAIL E
J
J1
B
C
D
A
K
K1
H
G
ÉÉ
ÉÉ
DETAIL E
F
M
L
2X L/2
−U−
S
U0.15 (0.006) T
S
U0.15 (0.006) T
S
U
M
0.10 (0.004) V S
T
0.10 (0.004)
−T−
−V−
−W−
0.25 (0.010)
16X REFK
N
N
7.06
16X
0.36 16X
1.26
0.65
DIMENSIONS: MILLIMETERS
1
PITCH
SOLDERING FOOTPRINT
MC14051B, MC14052B, MC14053B
http://onsemi.com
12
PACKAGE DIMENSIONS
SOEIAJ−16
F SUFFIX
PLASTIC EIAJ SOIC PACKAGE
CASE 966−01
ISSUE A
HE
A1
DIM MIN MAX MIN MAX
INCHES
--- 2.05 --- 0.081
MILLIMETERS
0.05 0.20 0.002 0.008
0.35 0.50 0.014 0.020
0.10 0.20 0.007 0.011
9.90 10.50 0.390 0.413
5.10 5.45 0.201 0.215
1.27 BSC 0.050 BSC
7.40 8.20 0.291 0.323
0.50 0.85 0.020 0.033
1.10 1.50 0.043 0.059
0
0.70 0.90 0.028 0.035
--- 0.78 --- 0.031
A1
HE
Q1
LE
_10 _0
_10 _
LE
Q1
_
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS D AND E DO NOT INCLUDE
MOLD FLASH OR PROTRUSIONS AND ARE
MEASURED AT THE PARTING LINE. MOLD FLASH
OR PROTRUSIONS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
4. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
5. THE LEAD WIDTH DIMENSION (b) DOES NOT
INCLUDE DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08 (0.003)
TOTAL IN EXCESS OF THE LEAD WIDTH
DIMENSION AT MAXIMUM MATERIAL CONDITION.
DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OR THE FOOT. MINIMUM SPACE
BETWEEN PROTRUSIONS AND ADJACENT LEAD
TO BE 0.46 ( 0.018).
M
L
DETAIL P
VIEW P
c
A
b
e
M
0.13 (0.005) 0.10 (0.004)
1
16 9
8
D
Z
E
A
b
c
D
E
e
L
M
Z
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to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
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MC14051B/D
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