6.1
The encoder has an enable function for use in
multiplexer applications. Encoder and Decoder
forced idle facilities are provided forcing a
10101010..... pattern in encode and a VDD/2
bias in decode. The companding circuits may
be operated with a 3 or 4-bit algorithm which is
externally selected. The device may be put in
the standby mode by selection of the
powersave facility. A reference 1.024MHz
oscillator uses an external clock or Xtal.
The FX619 is a low-power, 5 volt CMOS
device and is available in 22-pin cerdip DIL,
24-lead/pin plastic and 28-lead ceramic
leadless SMT packages.
FX619 'Eurocom' Delta Codec
CML Semiconductor Products
PRODUCT INFORMATION
The FX619 is an LSI circuit designed as a
*Continuously Variable Slope Delta Codec and
is intended for use in military communications
systems.
Designed to meet Eurocom D1-IA8 with
external components, the device is suitable for
applications in military Delta Multiplexers,
switches and phones.
Encoder input and decoder output filters are
incorporated on-chip. Sampling clock rates can
be programmed to 16, 32 or 64 k bits/second
from an internal clock generator or may be
externally applied in the range 8 to 64 k bits/
second. Sampling clock frequencies are output
for the synchronization of external circuits.
Brief Description
Fig.1 Internal Block Diagram
DECODER DATA CLOCK
MODE 2
MODE 1
ENCODER DATA CLOCK
XTAL
DATA ENABLE
ENCODER FORCE IDLE
DECODER INPUT
MOD
ENCODER INPUT
DEMOD
XTAL/CLOCK
ENCODER OUTPUT
DECODER OUTPUT
CLOCK RATE
GENERATORS
SAMPLING RATE
CONTROL
ALGORITHM
POWERSAVE
3 or 4-BIT
CLOCK MODE
LOGIC
DECODER FORCE IDLE
f3f1
VSS
VDD
VBIAS
f0
f1f2
FX619
Publication D/619/6 September 1997
Features/Applications
Designed to Meet Eurocom D1-IA8f
Meets Stanag 4209 and
Stanag 4380
Delta MUX, Switch and Phone
Applications
Single Chip Full Duplex Codec
Military Communications Powersave Facility
Single 5V CMOS Process
Full Duplex CVSD* Codec
Programmable Sampling Clocks
3 or 4-bit Compand Algorithm
Forced Idle Facility
On-Chip Input and Output Filters
2
Pin Number Function
Xtal/Clock : Input to the clock oscillator inverter. A 1.024MHz Xtal input or externally
derived clock is injected here. See Clock Mode pins and Figure 3.
No connection
Xtal : Output of clock oscillator inverter. Xtal circuitry shown is in accordance with CML
application note D/XT/1 April 1986.
No connection
Encoder Data Clock : A logic I/O port. External encode clock input or internal data clock
output. Clock frequency is dependant upon clock mode 1, 2 inputs and Xtal frequency (see
Clock Mode pins).
Encoder Output : The encoder digital output, this is a three state output whose condition is
set by Data Enable and Powersave inputs as shown :
Data Enable Powersave Encoder Output
1 1 Enabled
0 1 High Z (o/c)
1 0 Vss
No connection
Encoder Force Idle : When this pin is a logical '0' the encoder is forced to an idle state and
the encoder digital output is 0101..., a perfect idle pattern. When this pin is a logical '1' the
encoder encodes as normal. Internal 1MΩ Pullup.
Data Enable : Data is made available at the encoder output pin by control of this input. See
Encoder Output pin. Internal 1MΩ Pullup.
No connection
Bias : Normally at VDD /2 bias, this pin requires to be externally decoupled by a capacitor,
C4. Internally pulled to VSS when "Powersave" is a logical '0'.
Encoder Input : The analogue signal input. Internally biased at VDD /2, external
components are required on this input. The source impedance should be less than 100Ω,
output idle channel noise levels will improve with an even lower source impedance. See
Fig. 3.
VSS : Negative Supply.
FX619
J
1
2
3
4
5
6
7
8
9
10
11
FX619
L1/L2
1
2
3
4
5
6
7
8
9
10
11
12
FX619
M1
1
2
3
4
5
6
7, 8
9
10
11
12
13
14
3
Pin Number Function
No connection
Decoder Output : The recovered analogue signal is output at this pin, it is the buffered
output of a bandpass filter and requires external components. During "Powersave" this
output is o/c.
No connection
Powersave : A logical '0' at this pin puts most parts of the codec into a quiescent non-
operational state. When at a logical '1' the codec operates normally. Internal 1MΩ Pullup.
No connection
Decoder Force Idle : A logical '0' at this pin gates a 0101...pattern internally to the
decoder so that the decoder output goes to VDD/2. When this pin is at a logical '1' the
decoder operates as normal. Internal 1MΩ Pullup.
Decoder Input : The received digital signal input. Internal 1MΩ Pullup.
Decoder Data Clock : A Logic I/O port. External decode clock input or internal data clock
output, dependant upon clock mode 1, 2 inputs, see Clock Mode pins.
Algorithm : A logical '1' at this pin sets this device for a 3-bit companding algorithm. A
logical '0' sets a 4-bit companding algorithm. Internal 1MΩ Pullup.
Clock Mode 2 : Clock Mode 1 Clock Mode 2 Facility
Clock Mode 1 : 0 0 External clocks
Internal 1MΩ0 1 Internal, 64kb/s = f ÷ 16
Pullups. 1 0 Internal, 32kb/s = f ÷ 32
1 1 Internal, 16kb/s = f ÷ 64
Clock rates refer to f = 1.024 MHz Xtal/clock input. During internal operation the data
clock frequencies are available at the ports for external circuit synchronization.
Independant or common data rate inputs to Encode and Decode data clock ports may be
employed in the External Clocks mode.
VDD : Positive Supply. A single + 5 volt power supply is required.
FX619
L1/L2
13
14
15
16
17
18
19
20
21
22
23
24
FX619
J
12
13
14
15
16
17
18
19
20
21
22
FX619
M1
15,16
17
18,19
20
21
22
23
24
25
26
27
28
4
Codec Integration
Fig.3 Recommended External Components
Fig.2 Eurocom System Configuration – showing the FX619, which with the indicated interfacing, will conform to
the Eurocom Basic Parameters Specification D1 – IA8.
EUROCOM
ANALOGUE
INPUT
INTERFACE
(BALUN
&
BUFFER)
EUROCOM
INPUT EUROCOM
OUTPUT
REGULATED POWER
SUPPLY
SYNCHRONOUS CLOCK
AND
DATA SYSTEM
FX619 PARAMETERS
MEASURED HERE FX619 PARAMETERS
MEASURED HERE
1.024 MHz 1.024 MHz
DATA
CLOCK MODE
16/32/64kb/s
EUROCOM
ANALOGUE
OUTPUT
INTERFACE
(BALUN
&
BUFFER)
FX619
ENCODER FX619
DECODER
DATA
CLOCKS
CLOCKS
Component Unit Value Note – with reference to Figure 3 (below)
R11M Oscillator Inverter bias resistor.
R2Selectable Xtal Drive limiting resistor.
C133p Xtal Circuit drain capacitor.
C233p Xtal Circuit gate capacitor.
C31.0µEncoder Input coupling capacitor – The drive source impedance to this
input should be less than 100Ω. Output Idle channel noise levels will
improve with an even lower source impedance.
C41.0µBias decoupling capacitor.
C51.0µVDD decoupling capacitor.
X1 1.024 MHz A 1.024 MHz Xtal/clock input will yield exactly 16/32/64 kb/s data clock
rates. Xtal circuitry shown is in accordance with CML application note
D/XT/1 April 1986.
Tolerance :– Resistors ± 10% Capacitors ± 20%
FX619J
1
2
3
4
5
6
7
8
9
10
11
22
21
20
19
18
17
16
15
14
13
12
R1
R2
C2C1
X1
XTAL/CLOCK
XTAL
N/C
ENCODER DATA CLOCK
ENCODER OUTPUT
DATA ENABLE
N/C
BIAS
ENCODER INPUT
VSS
VDD
C3
C4
CLOCK MODE 1
CLOCK MODE 2
ALGORITHM
DECODER DATA CLOCK
DECODER INPUT
DECODER FORCE IDLE
POWERSAVE
N/C
DECODER OUTPUT
N/C
C5
VDD
ENCODER FORCE IDLE
SS
V
5
Typical
Test Sample Rate Bit Sequence at Decoder Input MLA Output
Duty cycle Level
a. 16kbit/s 10110100100100101101 0 - 41.5dBm0
32kbit/s 1011011010101001001001001001010101101101 0 - 42.0dBm0
b. 16kbit/s 11011001001001001101 0.05 - 25.0dBm0
32kbits 1011011010101001001000100100101011011011 0.05 - 25.0dBm0
c. 16kbits 10110101000100101011 0.1 - 19.0dBm0
32kbit/s 1101101101010010001000100100101011011101 0.1 - 18.5dBm0
d. 16kbit/s 11011001000010011011 0.2 - 11.0dBm0
32kbit/s 1101110110010100010000100010011010111011 0.2 - 11.5dBm0
e. 16kbit/s 11011010000010010111 0.3 - 6.5dBm0
32kbit/s 1110111011001000100000010001001101110111 0.3 - 6.5dBm0
f. 16kbit/s 11011010000001001111 0.4 - 3.0dBm0
32kbit/s 1111011101010001000000001000101011101111 0.4 - 3.0dBm0
g. 16kbit/s 11101010000000101111 0.5 0dBm0
32kbit/s 1111101110100010000000000100010111011111 0.5 0dBm0
Table 1 Bit Sequence Test Table
Codec Performance ...... Using the Bit Sequence Tests (a to g) at the Decoder Input pin in accordance with
the Eurocom Specification D1 – IA8, the decoder output is as shown in Table 1.
Codec Timing Information
DECODER TIMING
ENCODER TIMING
MULTIPLEXING FUNCTION
HIGH Z HIGH Z
tDR tDF
DATA TRUE TIME
tSU tH
DATA CLOCKED
tCL
DATA CLOCKED
tCH tIF tIR
tPCO
tCH
ENCODER
CLOCK
ENCODER DATA
OUTPUT
DECODER
CLOCK
DECODER DATA
INPUT
ENCODER
OUTPUT
DATA ENABLE
Fig.4 Codec Timing Diagrams
TIMING
tCH Clock '1' Pulse
Width
1.0µs Min.
tCL Clock '0' Pulse
Width
1.0µs Min.
tIR Clock Rise Time
100ns Typ.
tIF Clock Fall Time
100ns Typ.
tSU Data Set-up Time
450ns Min.
tH Data Hold Time
600ns Min.
tSU + tH Data True
Time.
tPCO Clock to Output
Delay time
750ns Max.
tDR Data Rise Time
100ns Typ.
tDF Data Fall Time
100ns Typ.
Xtal Input Frequency
1.024MHz.
6
Fig.5 Gain vs Input Level (16kbit/s) Fig.6 Gain vs Input Level (32kbit/s)
Fig.8 S/N vs Input Level (32kbit/s)
Fig.7 S/N vs Input Level (16kbit/s)
Fig.9 Attenuation Distortion vs Frequency (16kbit/s)
Codec Performance ...... relative to the Eurocom Specification D1 - IA8
Input Level (dBm0)
- 40 - 30 - 20 - 10 0
8
10
15
20
S/N Ratio (dB)
Ref: 0dBm0 Input Level = 489mVrms
Input Frequency = 820Hz
Attenuation (dB)
0
1
- 1
2
3
- 2
- 3
100- 10- 20- 30- 40- 50
Input Level (dBm0)
Ref: 0dBm0 Input Level = 489mVrms
Input Frequency = 820Hz
ref.
Attenuation (dB)
0
1
- 1
2
3
- 2
- 3
100- 10- 20- 30- 40- 50 Input Level (dBm0)
ref.
Ref: 0dBm0 Input Level = 489mVrms
Input Frequency = 820Hz
Input Level (dBm0)
- 40 - 30 - 20 - 10 0
25
15
20
S/N Ratio (dB)
Ref: 0dBm0 Input Level = 489mVrms
Input Frequency = 820Hz
Frequency (kHz)
- 50
- 40
- 30
- 20
- 10
0
+ 10
Gain (dB)
- 60 0123456
0.3 2.6
1.5
1.5
Input Level = -20dBm0
7
Codec Performance ...... relative to the Eurocom Specification D1 - IA8
Fig.14 Attenuation Distortion vs Frequency (32kbit/s)
Fig.10 S/N vs Input Frequency (16kbit/s)
Fig.12 Principal Integrator Response Fig.13 Compand Envelope
Fig.11 S/N v
s
Input Frequency (32kbit/s)
Frequency (kHz)
- 50
- 40
- 30
- 20
- 10
0
+ 10
Gain (dB)
- 60 0123456
0.3 1.4 2.6 3.4
2
3
Input Level = -20dBm0
Input Frequency (kHz)
0 1 2 3
5
10
15
20
S/N Ratio (dB)
25
30 Input Level = -20dBm0
Frequency (Hz)
Amplitude (dB)
0
- 6
- 12
- 18
- 24
- 30
10 100 1k 10k
- 6dB/octave
Time (ms)
Amplitude
1.0
8.76 5.76
0.00794
0.1
0.397
0.9
Amplitude of test
signal (g) - Table 1.
Beginning of
discharge
Amplitude of
test signal (a)
Input Frequency (kHz)
0 1 2 3
5
10
15
20
S/N Ratio (dB)
Input Level = -20dBm0
8
Specifications
Absolute Maximum Ratings
Exceeding the maximum rating can result in device damage. Operation of the device outside the operating limits is
not implied.
Supply voltage -0.3 to 7.0V
Input voltage at any pin (ref VSS = 0V) -0.3 to (VDD + 0.3V)
Source/sink current (supply pins) ± 30mA
(other pins) ± 20mA
Total device dissipation @ 25°C 800mW Max.
Derating (J and M1 packages) 10mW/°C
Derating (L1 and L2 packages) 13mW/°C
Operating temperature range: FX619J -40°C to +85°C (cerdip)
FX619L1/L2 -40°C to +85°C (plastic)
FX619M1 -40°C to +85°C (cerquad)
Storage temperature range: FX619J -55°C to +125°C (cerdip)
FX619L1/L2 -40°C to +85°C (plastic)
FX619M1 -55°C to +125°C (cerquad)
Operating Limits
All characteristics are measured using the following parameters unless otherwise specified:
VDD = 5.0V, TAMB = 25°C, Xtal/Clock f0 = 1.024MHz, Audio Level 0dB ref (0dBm0) = 489 mV rms.
Audio Test Frequency = 820 Hz. Sample Clock Rate = 32kb/s. Compand Algorithm = 3-bit.
Characteristics See Note Min. Typ. Max. Unit
Static Values
Supply Voltage 1 4.5 5.0 5.5 V
Supply Current (Enabled) – 4.5 – mA
Supply Current (Powersave) – 1.0 – mA
Inputs Logic '1' 8 3.5 – – V
Inputs Logic '0' 8 – – 1.5 V
Outputs Logic '1' 8 4.0 – – V
Outputs Logic '0' 8 – – 1.0 V
Digital Input Impedance
(Logic I/O pins) 1.0 10 – MΩ
Digital Input Impedance
(Logic input pins, pullup resistor) 2 300 – – kΩ
Digital Output Impedance – – 4 kΩ
Analogue Input Impedance 4 1 – kΩ
Analogue Output Impedance 7 – – 800 Ω
Three State Output Leakage
Current (output disabled) -4 – +4 µA
Insertion Loss 3 -2 – +2 dB
Dynamic Values 1
Encoder:
Analogue Signal Input Levels 5,9 -35 – +6 dBm0
Principle Integrator Frequency – 275 – Hz
Encoder Passband 3400 Hz
Compand Time Constant – 4 – ms
Decoder:
Analogue Signal Output Levels 5,9 -35 – +6 dBm0
Decoder Passband 300 – 3400 Hz
Encoder Decoder (Full codec):
Compression Ratio (Cd = 0.5 to Cd = 0.0) – 50 –
Passband 300 – 3400 Hz
Stopband 6 – 10 kHz
Stopband Attenuation – 60 – dB
Passband Gain – 0 – dB
Passband Ripple (300Hz –1400Hz) -1 – +1 dB
(1400Hz – 2600Hz) -1 – +3 dB
(2600Hz – 3400Hz) -2 – +3 dB
Output Noise (Input short circuit) 9 – – -62 dBm0p
Perfect Idle Channel Noise (Encoder forced) 9 – -63 – dBm0p
Group Delay Distortion 6
(1000Hz to 2600Hz) – – 450 µs
(600Hz to 2800Hz) – – 750 µs
(500Hz to 3000Hz) – – 1.5 ms
Xtal/Clock Frequency 500 1024 1500 kHz
– Notes to be used with these specifications are detailed on page 9 (overleaf)
› › › ›
9
Specifications ......
Notes: 1. Dynamic characteristics are specified at 5V unless otherwise specified.
2. All logic inputs except, Encoder and Decoder Data Clocks.
3. For an Encoder/Decoder combination, Insertion Loss contributed by a single component is half this
figure.
4. Driven with a source impedance of <100Ω.
5. Recommended values – See Figures 5, 6, 7 and 8.
6 Group Delay Distortion for the full codec is relative to the delay with 820Hz, -20dB at the encoder input.
7. An Emitter Follower output stage.
8. 4V = 80% VDD, 3.5V = 70% VDD, 1.5V = 30% VDD, 1V = 20% VDD.
9. Analogue Voltage Levels used in this Data Sheet: 0dBm0 = 489mVrms = - 4dBm = 0dB.
- 20dBm0 = 49mVrms = - 24dBm.
(e) Inputs and outputs should be screened wherever
possible.
(f) A "ground plane" connected to VSS will assist in
eliminating external pick-up on the input and output
pins.
(g) It is recommended that the power supply rails
have less than 1mVrms of noise allowed.
(h) The source impedance to the Encoder Input pin
must be less than 100Ω, Output Idle channel noise
levels will improve with even lower source impedances.
(a) Care should be taken on the design and layout of
the printed circuit board.
(b) All external components (as recommended in
Figure 3) should be kept close to the package.
(c) Tracks should be kept short, particularly the
Encoder Input capacitor and the VBIAS capacitor.
(d) Xtal/clock tracks should be kept well away from
analogue inputs and outputs.
Application Recommendations
Due to the very low levels of signal and idle channel noise specified in the Eurocom Basic Parameters Specification
D1 – IA8 – a noisy or badly regulated power supply could cause instability putting the overall system performance
out of specification. Adherence to the points noted below will assist in minimizing this problem.
Process Information
The following Table gives details of the process and test controls employed in the manufacture of the FX619
Eurocom Delta Codec in J and M1 packages only. L1 and L2 products are supplied without the process and test
controls detailed below.
Function Reference Remarks
Hermeticity
Fine Leak Test – Mil Std 883C using Method 1014 – test condition A1.
Coarse Leak Test – Mil Std 883C using Method 1014 – test condition C.
Burnin Mil Std 883C using Method 1015 – test condition E.
168 Hours @ 85°C with 5v power, and clocks applied.
Temperature Cycling Mil Std 883C using Method 1010 – test condition B.
10 cycles -55°C to +125°C.
The following mechanical assembly tests are Qualified to BS9450
Vibration BS9450 Section 1.2.6.8.1
55Hz to 500Hz at 98 m/sec acceleration.
Shock BS9450 Section 1.2.6.6
981 m/sec for 6 msec.
Low Pressure BS9450 Section 1.2.6.12
Transport and Storage – 225mmHg (altitude 9000m).
Operation – 600mmHg (altitude 2400m).
Humidity BS9450 Section 1.2.6.4
96 Hours @ 45°C, 95% relative humidity plus condensed
water.
Package Outlines
The FX619 is available in the package styles outlined
below. Mechanical package diagrams and specifications
are detailed in Section 10 of this document.
Pin 1 identification marking is shown on the relevant
diagram and pins on all package styles number
anti-clockwise when viewed from the top.
Handling Precautions
The FX619 is a CMOS LSI circuit which includes input
protection. However precautions should be taken to
prevent static discharges which may cause damage.
CML does not assume any responsibility for the use of any circuitry described. No circuit patent licences are implied
and CML reserves the right at any time without notice to change the said circuitry.
10
Ordering Information
FX619J 22-pin cerdip DIL (J3)
FX619L1 24-pin quad plastic encapsulated
bent and cropped (LG)
NOT TO SCALE
Max. Body Length 27.38mm
Max. Body Width 9.75mm
FX619J 22-pin cerdip DIL (J3)
NOT TO SCALE
Max. Body Length 10.25mm
Max. Body Width 10.25mm
FX619L1 24-pin quad plastic encapsulated
bent and cropped (LG)
NOT TO SCALE
Max. Body Length 10.40mm
Max. Body Width 10.40mm
FX619L2 24-pin plastic leaded chip
carrier (LS)
NOT TO SCALE
Max. Body Length 11.60mm
Max. Body Width 11.60mm
FX619M1 28-lead ceramic leaded chip
carrier (M1)
FX619L2 24-pin plastic leaded chip carrier
(LS)
FX619M1 28-lead ceramic leaded chip
carrier (M1)
CML Product Data
In the process of creating a more global image, the three standard product semiconductor
companies of CML Microsystems Plc (Consumer Microcircuits Limited (UK), MX-COM, Inc
(USA) and CML Microcircuits (Singapore) Pte Ltd) have undergone name changes and, whilst
maintaining their separate new names (CML Microcircuits (UK) Ltd, CML Microcircuits (USA)
Inc and CML Microcircuits (Singapore) Pte Ltd), now operate under the single title CML Micro-
circuits.
These companies are all 100% owned operating companies of the CML Microsystems Plc
Group and these changes are purely changes of name and do not change any underlying legal
entities and hence will have no effect on any agreements or contacts currently in force.
CML Microcircuits Product Prefix Codes
Until the latter part of 1996, the differentiator between products manufactured and sold from
MXCOM, Inc. and Consumer Microcircuits Limited were denoted by the prefixes MX and FX
respectively. These products use the same silicon etc. and today still carry the same prefixes.
In the latter part of 1996, both companies adopted the common prefix: CMX.
This notification is relevant product information to which it is attached.
Company contact information is as below:
CML Microcircuits
(UK)Ltd
COMMUNICATION SEMICONDUCTORS
CML Microcircuits
COMMUNICATION SEMICONDUCTORS
CML Microcircuits
(Singapore)PteLtd
COMMUNICATION SEMICONDUCTORS
CML Microcircuits
(USA) Inc.
COMMUNICATION SEMICONDUCTORS
Oval Park, Langford, Maldon,
Essex, CM9 6WG, England
Tel: +44 (0)1621 875500
Fax: +44 (0)1621 875600
uk.sales@cmlmicro.com
www.cmlmicro.com
4800 Bethania Station Road,
Winston-Salem, NC 27105, USA
Tel: +1 336 744 5050,
0800 638 5577
Fax: +1 336 744 5054
us.sales@cmlmicro.com
www.cmlmicro.com
No 2 Kallang Pudding Road, 09-05/
06 Mactech Industrial Building,
Singapore 349307
Tel: +65 7450426
Fax: +65 7452917
sg.sales@cmlmicro.com
www.cmlmicro.com
D/CML (D)/1 February 2002
