I74F113D,623 - NXP - Datasheet.Directory

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74F113

Dual J-K negative edge-triggered

flip-flops without reset

Product specification

IC15 Data Handbook

1991 Feb 14

INTEGRATED CIRCUITS

Philips Semiconductors Product specification

74F113

Dual J-K negative edge-triggered flip-flops

without reset

1996 Mar 14 853–0339 16575

FEATURE

•Industrial temperature range available (–40°C to +85°C)

DESCRIPTION

The 74F113, dual negative edge-triggered JK-type flip-flop, features

individual J, K, clock (CP), set (SD) inputs, true and complementary

outputs. The asynchronous SD input, when low, forces the outputs

to the steady state levels as shown in the function table regardless

of the level at the other inputs.

A high level on the clock (CP) input enables the J and K inputs and

data will be accepted. The logic levels at the J and K inputs may be

allowed to change while the CP is high and flip-flop will perform

according to the function table as long as minimum setup and hold

times are observed. Output changes are initiated by the high-to-low

transition of the CP.

PIN CONFIGURATION

GND

VCC

SD1

CP1

CP0

SD0

SF00140

TYPE TYPICAL fmax TYPICAL SUPPLY CURRENT (TOTAL)

74F113 100MHz 15mA

ORDERING INFORMATION

ORDER CODE

DESCRIPTION COMMERCIAL RANGE

VCC = 5V ±10%,

Tamb = 0°C to +70°C

INDUSTRIAL RANGE

VCC = 5V ±10%,

Tamb = –40°C to +85°C

PKG. DWG. #

14-pin plastic DIP N74F113N I74F113N SOT27–1

14-pin plastic SO N74F113D I74F113D SOT108–1

INPUT AND OUTPUT LOADING AND FAN-OUT TABLE

PINS DESCRIPTION 74F (U.L.) HIGH/LOW LOAD VALUE HIGH/LOW

J0, J1 J inputs 1.0/1.0 20µA/0.6mA

K0, K1 K inputs 1.0/1.0 20µA/0.6mA

CP0, CP1Clock inputs (active falling edge) 1.0/4.0 20µA/2.4mA

SD0, SD1 Set inputs (active low) 1.0/5.0 20µA/3.0mA

Q0, Q1, Q0, Q1Data outputs 50/33 1.0mA/20mA

NOTE:

One (1.0) FAST unit load is defined as: 20µA in the High state and 0.6mA in the Low state.

LOGIC SYMBOL

Q0 Q0 Q1 Q1

56 98

VCC = Pin 14

GND = Pin 7

CP0

SD0

CP1

SD1

J1 K0

212

SF00141

K1J0

311

IEC/IEEE SYMBOL

SF00142

Philips Semiconductors Product specification

74F113

Dual J-K negative edge-triggered flip-flops

without reset

1996 Mar 14 3

LOGIC DIAGRAM

VCC = Pin 14

GND = Pin 7

CP1, 13

K2, 12

4, 10

5, 9

6, 8

3, 11

SF00143

FUNCTION TABLE

INPUTS OUTPUTS

OPERATING MODE

SD CP J K Q Q

OPERATING

MODE

L X X X H L Asynchronous set

H↓h h q q Toggle

H↓h l H L Load ”1” (set)

H↓l h L H Load ”0” (reset)

H↓l l q q Hold ’no change”

NOTES:

H = High-voltage level

h = High-voltage level one setup time prior to high-to-low

clock transition

L = Low-voltage level

l = Low-voltage level one setup time prior to high-to-low clock

transition

q = Lower case indicate the state of the referenced output

prior to the high-to-low clock transition

X = Don’t care

↓= high-to-low clock transition

ABSOLUTE MAXIMUM RATINGS

(Operation beyond the limits set forth in this table may impair the useful life of the device.

Unless otherwise noted these limits are over the operating free-air temperature range.)

SYMBOL PARAMETER RATING UNIT

VCC Supply voltage –0.5 to +7.0 V

VIN Input voltage –0.5 to +7.0 V

IIN Input current –30 to +5 mA

VOUT Voltage applied to output in High output state –0.5 to VCC V

IOUT Current applied to output in Low output state 40 mA

erating free air tem

erature range

Commercial range 0 to +70 °C

amb

Operating

free

air

temperat

range

Industrial range –40 to +85 °C

Tstg Storage temperature range –65 to +150 °C

RECOMMENDED OPERATING CONDITIONS

SYMBOL

PARAMETER

LIMITS

UNIT

SYMBOL

PARAMETER

MIN NOM MAX

UNIT

VCC Supply voltage 4.5 5.0 5.5 V

VIH High-level input voltage 2.0 V

VIL Low-level input voltage 0.8 V

IIK Input clamp current –18 mA

IOH High-level output current –1 mA

IOL Low-level output current 20 mA

erating free air tem

erature range

Commercial range 0 +70 °C

amb

Operating

free

air

temperat

range

Industrial range –40 +85 °C

Philips Semiconductors Product specification

74F113

Dual J-K negative edge-triggered flip-flops

without reset

1996 Mar 14 4

DC ELECTRICAL CHARACTERISTICS

(Over recommended operating free-air temperature range unless otherwise noted.)

SYMBOL

PARAMETER

TEST CONDITIONS1

LIMITS

UNIT

SYMBOL

PARAMETER

TEST

CONDITIONS1

MIN TYP2MAX

UNIT

High level out

ut voltage

= MIN

= MAX

IO= MAX

±10%VCC 2.5 V

High

oltage

VCC

MIN,

VIL

MAX,

VIH = MIN

OH =

MAX

±5%VCC 2.7 3.4 V

Low level out

ut voltage

= MIN

= MAX

IO= MAX

±10%VCC 0.30 0.50 V

oltage

VCC

MIN,

VIL

MAX,

VIH = MIN

OL =

MAX

±5%VCC 0.30 0.50 V

VIK Input clamp voltage VCC = MIN, II = IIK –0.73 –1.2 V

IIInput current at maximum input voltage VCC = MAX, VI = 7.0V 100 µA

IIH High-level input current VCC = MAX, VI = 2.7V 20 µA

Jn, Kn –0.6 mA

IIL Low-level input current CPnVCC = MAX, VI = 0.5V –2.4 mA

SDn –3.0 mA

IOS Short-circuit output current3VCC = MAX -60 –150 mA

ICC Supply current4 (total) VCC = MAX 15 21 mA

NOTES:

1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type.

2. All typical values are at VCC = 5V, Tamb = 25°C.

3. Not more than one output should be shorted at a time. For testing IOS, the use of high-speed test apparatus and/or sample-and-hold

techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting

of a high output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any

sequence of parameter tests, IOS tests should be performed last.

4. Measure ICC with the clock input grounded and all outputs open, then with Q and Q outputs high in turn.

AC ELECTRICAL CHARACTERISTICS

LIMITS

SYMBOL PARAMETER TEST

CONDITION

VCC = +5.0V

Tamb = +25°C

CL = 50pF

RL = 500Ω

VCC = +5.0V ± 10%

Tamb = 0°C to +70°C

CL = 50pF

RL = 500Ω

VCC = +5.0V ± 10%

Tamb = –40°C to +85°C

CL = 50pF

RL = 500Ω

UNIT

MIN TYP MAX MIN MAX MIN MAX

fmax Maximum clock frequency Waveform 1 85 100 80 80 ns

tPLH

tPHL Propagation delay

CPn to Qn or Qn Waveform 1 2.0

2.0 4.0

4.0 6.0

6.0 2.0

2.0 7.0

7.0 2.0

2.0 7.5

7.0 ns

tPLH

tPHL Propagation delay

SDn, to Qn or Qn Waveform 2 2.0

2.0 4.5

4.5 6.5

6.5 2.0

2.0 7.5

7.5 2.0

2.0 8.0

7.5 ns

AC SETUP REQUIREMENTS

LIMITS

SYMBOL PARAMETER TEST

CONDITION

VCC = +5.0V

Tamb = +25°C

CL = 50pF

RL = 500Ω

VCC = +5.0V ± 10%

Tamb = 0°C to +70°C

CL = 50pF

RL = 500Ω

VCC = +5.0V ± 10%

Tamb = –40°C to +85°C

CL = 50pF

RL = 500Ω

UNIT

MIN TYP MAX MIN MAX MIN MAX

tsu (H)

tsu(L) Setup time, high or low

Jn, Kn to CPnW aveform 1 4.0

3.5 5.0

4.0 5.0

4.5 ns

th (H)

th (L) Hold time, high or low

Jn, Kn to CPnW aveform 1 0.0

0.0 0.0

0.0 ns

tw (H)

tw (L) CP pulse width,

high or low W aveform 1 4.5

4.5 5.0

5.0 5.0

5.0 ns

tw (L) SDn pulse width, low Waveform 2 4.5 5.0 5.0 ns

trec Recovery time

SDn to CPn W aveform 2 4.5 5.0 5.0 ns

Philips Semiconductors Product specification

74F113

Dual J-K negative edge-triggered flip-flops

without reset

1996 Mar 14 5

AC WAVEFORMS

For all waveforms, VM = 1.5V.

The shaded areas indicate when the input is permitted to change for predictable output performance.

tPLH

CPn

VMVMVMVM

VMVM

Jn, Kn

tw(H)

1/fmax

tsu(L) th(L) = 0

tPLH

tw(L)

tPHL

tsu(H) th(H) = 0

SF00144

W aveform 1. Propagation Delay for Data to Output, Data Setup Time and Hold Times, and Clock Width,

and Maximum Clock Frequency

CPn

tPHL

tPLH

SDn VM

VMtw(L)

trec

Jn, Kn

SF00145

W aveform 2. Propagation Delay for Set to Output, Set Pulse Width, and Recovery Time for Set to Clock

Philips Semiconductors Product specification

74F113

Dual J-K negative edge-triggered flip-flops

without reset

1996 Mar 14 6

TEST CIRCUIT AND WAVEFORMS

tw90%

10%

90%

VM10%

90%

VM10%

90%

10%

NEGATIVE

PULSE

POSITIVE

PULSE

AMP (V)

tTHL (tf )

INPUT PULSE REQUIREMENTS

rep. rate twtTLH tTHL

1MHz 500ns 2.5ns 2.5ns

Input Pulse Definition

VCC

family

74F

D.U.T.

PULSE

GENERATOR

VIN VOUT

Test Circuit for Totem-Pole Outputs

DEFINITIONS:

RL= Load resistor;

see AC ELECTRICAL CHARACTERISTICS for value.

CL= Load capacitance includes jig and probe capacitance;

see AC ELECTRICAL CHARACTERISTICS for value.

RT= Termination resistance should be equal to ZOUT of

pulse generators.

tTHL (tf )

tTLH (tr )

tTLH (tr )AMP (V)

amplitude

3.0V 1.5V

SF00006

Philips Semiconductors Product specification

74F113

Dual J-K negative edge-triggered flip-flops without reset

1996 Mar 14 7

DIP14: plastic dual in-line package; 14 leads (300 mil) SOT27-1

Philips Semiconductors Product specification

74F113

Dual J-K negative edge-triggered flip-flops without reset

1996 Mar 14 8

SO14: plastic small outline package; 14 leads; body width 3.9 mm SOT108-1

Philips Semiconductors Product specification

74F113

Dual J-K negative edge-triggered flip-flops without reset

1996 Mar 14 9

NOTES

Philips Semiconductors Product specification

74F113

Dual J-K negative edge-triggered flip-flops without reset

yyyy mmm dd 10

Definitions

Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For

detailed information see the relevant data sheet or data handbook.

Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one

or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or

at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended

periods may af fect device reliability.

Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips

Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or

modification.

Disclaimers

Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can

reasonably be expected to result in personal injury . Philips Semiconductors customers using or selling these products for use in such applications

do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.

Right to make changes — Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard

cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no

responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these

products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless

otherwise specified.

Philips Semiconductors

811 East Arques Avenue

P.O. Box 3409

Sunnyvale, California 94088–3409

Telephone 800-234-7381

 Copyright Philips Electronics North America Corporation 1998

print code Date of release: 10-98

Document order number: 9397-750-05072

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Data sheet

status

Objective

specification

Preliminary

specification

Product

specification

Product

status

Development

Qualification

Production

Definition [1]

This data sheet contains the design target or goal specifications for product development.

Specification may change in any manner without notice.

This data sheet contains preliminary data, and supplementary data will be published at a later date.

Philips Semiconductors reserves the right to make chages at any time without notice in order to

improve design and supply the best possible product.

This data sheet contains final specifications. Philips Semiconductors reserves the right to make

changes at any time without notice in order to improve design and supply the best possible product.

Data sheet status

[1] Please consult the most recently issued datasheet before initiating or completing a design.