PHN203,518 - NXP Semiconductors - Datasheet.Directory

PHN203

Dual N-channel TrenchMOS logic level FET

Rev. 05 — 27 April 2010 Product data sheet

1. Product profile

1.1 General description

Dual logic level N-channel enhancem ent mode Field-Effect Transistor (FET) in a plastic

package using TrenchMOS technology. This product is designed and qualified for use in

computing, communications, consumer and industria l applications only.

1.2 Features and benefits

Suitable for high frequency

applications due to fast switching

characteristics

Suitable for logic level gate drive

sources

1.3 Applications

DC-to-DC converters Lithium-ion battery applications

1.4 Quick reference data

[1] Single device conducting.

Table 1. Quick reference data

Symbol Parameter Conditions Min Typ Max Unit

VDS drain-source

voltage Tj≥25 °C; Tj≤150°C --30V

IDdrain current Tamb = 25 °C; pulsed;

see Figure 1; see Figure 3 [1] --6.3A

Ptot total power

dissipation Tamb = 25 °C; pulsed;

see Figure 2 [1] --2W

Static characteristics

RDSon drain-source

on-state

resistance

VGS =10V; I

D=7A; T

j=25°C;

see Figure 9; see Figure 10 - 2430mΩ

Dynamic characteristics

QGD gate-drain charge VGS =10V; I

D=7A; V

DS =15V;

Tj=25°C; see Figure 11 -3-nC

Product data sheet Rev. 05 — 27 April 2010 2 of 13

NXP Semiconductors PHN203

Dual N-channel TrenchMOS logic level FET

2. Pinning information

3. Ordering information

4. Limiting values

[1] Single device conducting.

Table 2. Pinning info rmation

Pin Symbol Description Simplified outline Graphi c sy mbol

1S1source1

SOT96-1 (SO8)

2 G1 gate1

3S2source2

4 G2 gate2

5D2drain2

6D2drain2

7D1drain1

8D1drain1

8D1

mbk72

G1S1

D1 D2

G2S2

Table 3. Orderi ng information

Type number Package

Name Description Version

PHN203 SO8 plastic small outline package; 8 leads; body width 3.9 mm SOT96-1

Table 4. Limiting values

In accordance with the Absolute Maxi mum Rating System (IEC 60134).

Symbol Parameter Conditions Min Typ Max Unit

VDS drain-source voltage Tj≥25 °C; Tj≤150°C --30V

VDGR drain-gate voltage Tj≤150 °C; Tj≥25 °C; RGS =20kΩ--30V

VGS gate-source voltage -20 - 20 V

IDdrain current Tamb = 70 °C; pulsed; see Figure 1 [1] --5A

Tamb = 25 °C; pulsed; see Figure 1;

see Figure 3 [1] --6.3A

IDM peak drain current tp≤10 µs; pul sed; Tamb =25°C;

see Figure 3 [1] --18A

Ptot total power dissipation Tamb = 25 ° C; pulsed; see Figure 2 [1] --2W

Tstg storage temperature -55 - 150 °C

Tjjunction temperature -55 - 150 °C

Source-drain diode

ISsource current Tamb = 25 °C; pulsed [1] --2A

ISM peak source current tp≤10 µs; pulsed; Tamb =25°C [1] --4.1A

Avalanche rugg edness

EDS(AL)S non-repetitive

drain-source

avalanche energy

VGS =10V; T

j(init) =25°C; I

D=8.7A;

Vsup ≤30 V; unclamped; tp= 0.2 ms;

RGS =50Ω

- - 37.8 mJ

Product data sheet Rev. 05 — 27 April 2010 3 of 13

NXP Semiconductors PHN203

Dual N-channel TrenchMOS logic level FET

Fig 1. Normalized continuous drain current as a

function of ambient temperature Fig 2. Normalized total po we r dis sipa tion as a

function of ambient temperature

Fig 3. Safe operating area; continuous and peak drain currents as a fun ction of drain-source voltage

03aa19

120

0 50 100 150 200

Tamb (°C)

Ider

(%)

03aa11

120

0 50 100 150 200

Tamb (°C)

Pder

(%)

03an69

10−2

10−1

102

10−1 1 10 102

1 ms

1 s

100 ms

10 s

(A)

VDS (V)

Limit RDSon = VDS / ID

tp = 10 μs

Product data sheet Rev. 05 — 27 April 2010 4 of 13

NXP Semiconductors PHN203

Dual N-channel TrenchMOS logic level FET

5. Thermal characteristics

Table 5. Thermal characteristics

Symbol Parameter Conditions Min Typ Max Unit

Rth(j-sp) thermal resistance from

junction to solder point ---K/W

Rth(j-a) thermal resistance from

junction to ambient mounted on a printed-circuit board;

minimum footprint; see Figure 4 - - 62.5 K/W

Fig 4. Transient thermal impedance from junction to ambient as a function of pulse duration

10−1

102

103

10−510−410−310−210−1 1 10

single pulse

δ = 0.5

0.2

0.1

0.05

0.02

03an68

Zth(j-a)

(K/W)

tp (s)

Product data sheet Rev. 05 — 27 April 2010 5 of 13

NXP Semiconductors PHN203

Dual N-channel TrenchMOS logic level FET

6. Characteristics

Table 6. Characteristics

Symbol Parameter Conditions Min Typ Max Unit

Static characteristics

V(BR)DSS drain-source

breakdown voltage ID=250µA; V

GS =0V; T

j= -55 °C 27 - - V

ID=250µA; V

GS =0V; T

j=25°C 30--V

VGS(th) gate-source threshold

voltage ID=1mA; V

DS =V

GS; Tj=-55°C;

see Figure 8 --2.2V

ID=1mA; V

DS =V

GS; Tj= 150 °C;

see Figure 8 0.6--V

ID=1mA; V

DS =V

GS; Tj=25°C;

see Figure 8 11.52V

IDSS drain leakage current VDS =24V; V

GS =0V; T

j=25°C --1µA

VDS =24V; V

GS =0V; T

j=150°C --10µA

IGSS gate leakage current VGS =20V; V

DS =0V; T

j= 25 °C - 10 100 nA

VGS =-20V; V

DS =0V; T

j= 25 °C - 10 100 nA

RDSon drain-source on-state

resistance VGS =10V; I

D=7A; T

j=25°C;

see Figure 9; see Figure 10 - 2430mΩ

VGS =4.5V; I

D= 3.5 A; Tj=25°C;

see Figure 9; see Figure 10 - 3055mΩ

VGS =10V; I

D=7A; T

j= 150 °C;

see Figure 9; see Figure 10 - 40.8 51 mΩ

Dynamic characteristics

QG(tot) total gate charge ID=7A; V

DS =15V; V

GS =10V;

Tj=25°C; see Figure 11 - 14.6 - nC

QGS gate-source charge - 2 - nC

QGD gate-drain charge - 3 - nC

Ciss input capacitance VDS =20V; V

GS = 0 V; f = 1 MHz;

Tj=25°C; see Figure 12 - 560 - pF

Coss output capacitance - 125 - pF

Crss reverse transfer

capacitance VDS 20 V; VGS =0V; f=1MHz; T

j=25°C;

see Figure 12 -85-pF

td(on) turn-on delay time VDS =25V; R

L=25Ω; VGS =10V;

RG(ext) =6Ω; Tj=25°C -5-ns

trrise time - 6 - ns

td(off) turn-off delay time - 21 - ns

tffall time - 11 - ns

Source-drain diode

VSD source-drain voltage IS= 1.25 A; VGS =0V; T

j=25°C;

see Figure 13 -0.751V

trr reverse recovery time IS=2A; dI

S/dt = -100 A/µs; VGS =0V;

VDS =25V; T

j=25°C -30-ns

Product data sheet Rev. 05 — 27 April 2010 6 of 13

NXP Semiconductors PHN203

Dual N-channel TrenchMOS logic level FET

Fig 5. Output characteristics: drain current as a

function of drain-source voltage; typical value Fig 6. Transfer character istics: drain current as a

function of gate-s ourc e volt ag e ; typi ca l v al ue s

Fig 7. Sub-threshold drain current as a function of

gate-source voltage Fig 8. Gate-source threshold voltage as a func tion of

junction temperature

03ao26

0 0.5 1 1.5

2.6 V

10 V

2.8 V

3 V

3.4 V

3.2 V

4 V4.5 V6 V

3.6 V

(A)

VDS (V)

VGS = 2.4 V

Tj = 25 °C

03ae49

01234

VGS (V)

(A)

VDS > ID x RDSon

Tj = 25 °C

150 °C

03aa36

10-6

10-5

10-4

10-3

10-2

10-1

0123

VGS (V)

(A)

maxtypmin

03aa33

0.5

1.5

2.5

-60 0 60 120 180

Tj (°C)

VGS(th)

(V)

max

typ

min

Product data sheet Rev. 05 — 27 April 2010 7 of 13

NXP Semiconductors PHN203

Dual N-channel TrenchMOS logic level FET

Fig 9. Drain-source on-state resistance as a function

of drain current; typical values Fig 10. Normalized drain-source on-state resistance

factor as a function of junction temperature

Fig 11. Gate-source voltage as a function of gate

charge; typical values Fig 12. Input, output and reverse transfer capacitances

as a function of drain-source voltage; typical

values

0102030

ID (A)

RDSon

(mΩ)

VGS = 3.2 V

4 V

10 V

6 V

4.5 V

3.6 V

3.4 V

03ao27

Tj = 25 °C

03ad57

−60 0 60 120 180

Tj (°C)

0.5

1.5

03ae53

0 5 10 15

QG (nC)

VGS

(V)

ID = 7 A

Tj = 25 °C

VDD = 15 V

03ae52

102

103

10−1 1 10 102

VDS (V)

(pF)

Ciss

Coss

Crss

Product data sheet Rev. 05 — 27 April 2010 8 of 13

NXP Semiconductors PHN203

Dual N-channel TrenchMOS logic level FET

Fig 13. Source current as a function of sourc e-drain voltage; typical values

03ae51

0 0.3 0.6 0.9 1.2

(V)

(A)

= 25 °C

150 °C

= 0 V

Product data sheet Rev. 05 — 27 April 2010 9 of 13

NXP Semiconductors PHN203

Dual N-channel TrenchMOS logic level FET

7. Package outline

Fig 14. Package outline SOT96-1 (SO8)

UNIT A

max. A1A2A3bpcD

(1) E(2) (1)

ELL

pQZywv θ

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

inches

1.75 0.25

0.10

1.45

1.25 0.25 0.49

0.36

0.25

0.19

5.0

4.8

4.0

3.8 1.27 6.2

5.8 1.05 0.7

0.6

0.7

0.3 8

0.25 0.10.25

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

Notes

1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.

2. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included.

1.0

0.4

SOT96-1

detail X

vMA

(A )

pin 1 index

076E03 MS-012

0.069 0.010

0.004

0.057

0.049 0.01 0.019

0.014

0.0100

0.0075

0.20

0.19

0.16

0.15 0.05 0.244

0.228

0.028

0.024

0.028

0.012

0.010.010.041 0.004

0.039

0.016

0 2.5 5 mm

scale

O8: plastic small outline package; 8 leads; body width 3.9 mm SOT96

-1

99-12-27

03-02-18

Product data sheet Rev. 05 — 27 April 2010 10 of 13

NXP Semiconductors PHN203

Dual N-channel TrenchMOS logic level FET

8. Revision history

Table 7. Revision history

Document ID Release date Data sheet status Change notice Supersedes

PHN203 _5 20100427 Product data sheet - PHN203 _4

Modifications: •Various changes to content.

PHN203 _4 20091208 Product data sheet - PHN203-03

PHN203 -03 20040126 Product data - PHN203 _2

PHN203_2 19990101 Product specification - PHN203 _1

PHN203 _1 19980204 Objective specification - -

Product data sheet Rev. 05 — 27 April 2010 11 of 13

NXP Semiconductors PHN203

Dual N-channel TrenchMOS logic level FET

9. Legal information

9.1 Data sheet status

[1] Please consult the most recently issued document before initiating or completing a design.

[2] The term 'short data sheet' is explained in section "Definitions".

[3] The p r oduct status of device(s) des cribed in this document may hav e changed sinc e this document was publish ed and may differ in case of multiple devices. The latest product

status information is available on the Internet at URL http://www.nxp.com.

9.2 Definitions

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modifications or additions. NXP Semiconductors does not give any

representations or warranties as to the accuracy or completeness of

information included herein and shall have no liab ility for the consequences of

use of such information.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and tit le. A short data sh eet is intended

for quick reference only and shou ld not b e relied u pon to cont ain det ailed and

full information. For detailed and full information see the relevant full data

sheet, which is available on request via the local NXP Semicond uctors sales

office. In case of any inconsistency or conflict wit h the short data sheet, the

full data sheet shall pre va il.

Product specificat io n — The information and data provided in a Product

data sheet shall define the specification of the product as agreed between

NXP Semiconductors and its customer, unless NXP Semiconductors and

customer have explicitly agreed otherwise in writing. In no event however,

shall an agreement be valid in which the NXP Semiconductors product is

deemed to off er functions and qualities beyond those described in the

Product data sheet.

9.3 Disclaimers

Limited warranty and liability — Information in this d ocument is be lieved to

be accurate and reliable. However, NXP Semiconductors does not give any

representations or warrant ies, expressed or implied, as to the accuracy or

completeness of such information and shall have no liability for the

consequences of use of such information.

In no event shall NXP Semiconductors be liable for any indirect, incidental,

punitive, special or consequ ential damages (including - wit hout limitation - lost

profits, lost savings, business interruption, costs related to the removal or

replacement of any products or rework charges) whether or not such

damages are based on tort (including negligence), warranty, breach of

contract or any other legal theory.

Notwithstanding any damages that customer might incur for any reason

whatsoever, NXP Semiconductors’ aggreg ate and cumulative l iability towards

customer for the products described herein shall be limited in accordance

with the Terms and conditions of commercial sale of NXP Semiconductors.

Right to make changes — NXP Semiconductors reserves the right to make

changes to information published in this document, including without

limitation specifications and product descriptions, at any time and without

notice. This document supersedes and replaces all informa tion supplied prior

to the publication hereof .

Suitability for use — NXP Semiconductors products are not designed,

authorized or warranted to be suitable for use in medical, military, aircraft,

space or life support equipment, nor in applicati ons where failure or

malfunction of an NXP Semiconductors product can reasonably be expected

to result in perso nal injury, death or severe property or environmental

damage. NXP Semiconductors accepts no liab ility for inclusion and/or use of

NXP Semiconductors products in such equipment or applications and

therefore such inclusion and/or use is at the customer’s own risk.

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. NXP Semiconductors makes no

representation or warranty that such applications will be suitable for the

specified use without further testing or modification.

NXP Semiconductors does not accept any liability related to any default,

damage, costs or problem which is based on a weakness or default in the

customer application /use or t he application/use of customer’s third party

customer(s) (hereinafter both referred to as “Application”). It is customer’s

sole responsibility to check whether the NXP Semiconductors product is

suitable and fit for the Appl ica tion plann ed. Customer has to do all necessary

testing for the Application in order to avoid a default of the Application and t he

product. NXP Semiconductors does not accept any liability in this respect.

Quick reference data — The Quick reference data is an extract of the

product data given in the Limiting values and Characteristics sections of this

document, and as such is not complete, exhaustive or legally binding.

Limiting values — Stress above one or more limiting values (as defin ed in the

Absolute Maximum Ratings System of IEC 60134) will cause permanent

damage to the device. Limiting values are stress ratings only and (proper)

operation of the device at these or any other conditions above those given in

the Recommended operating conditions section (if present) or the

Characteristics sections of this document is not warranted. Constant or

repeated exposure to limiting values will permanently and irreversibly affect

the quality and reliability of the device.

Terms and conditions of commercial sale — NXP Semiconductors

products are sold subject to the general terms and conditions of commercial

sale, as published at http://www.nxp.com/profile/terms, unless otherwise

agreed in a valid written individua l agreement. In case an individual

agreement is concluded only the ter m s and conditions of the respective

agreement shall apply. NXP Semiconductors hereby expressly objects to

applying the customer’s general terms and conditions with regard to the

purchase of NXP Semiconductors products by customer.

No offer to sell or license — Nothing in this document may be interpreted or

construed as an of fer t o sell product s that is open for accept ance or the gr ant,

conveyance or implication of any license under any copyrights, patents or

other industrial or inte llectual property rights.

Export control — This document as well as the item(s) de scribed herein may

be subject to export control regulations. Export might require a prior

authorization from national authorities.

Document status[1][2] Product status[3] Definition

Objective [short] data sheet Development This document contains data from the objective specification for product deve lopment.

Preliminary [short] dat a sheet Qualification This document contains data from the preliminary specification.

Product [short] data sheet Production This document contains the product specification.

Product data sheet Rev. 05 — 27 April 2010 12 of 13

NXP Semiconductors PHN203

Dual N-channel TrenchMOS logic level FET

Non-automotive qualified products — Unless this data sheet expressly

states that this specific NXP Semiconductors product is automotive qualified,

the product is not suitable for aut omotive use. It i s neither qua lified nor tested

in accordance with automotive testing or application requirements. NXP

Semiconductors accepts no liability for inclusion and/or use of

non-automotive qualified products in au tomotive equipment or applications.

In the event that customer uses the product for design-in and use in

automotive applications to automot ive specifications and standards, custome r

(a) shall use the product without NXP Semiconductors’ warranty of the

product for such au tomotive applications, use and specificatio ns, and (b)

whenever customer uses the product for automotive applications beyond

NXP Semiconductors’ specifications such use shall be solely at customer’s

own risk, and (c) customer fully indemnifies NXP Semiconductors for any

liability, damages or failed product claims resulting from customer design and

use of the product for automotive appl ications beyond NXP Semiconductors’

standard warrant y and NXP Semiconductors’ product specifications.

9.4 Trademarks

Notice: All referenced b rands, produc t names, service names and trademarks

are the property of their respective ow ners.

Adelante, Bitport, Bitsound, CoolFlux, CoReUse, DESFire, EZ-HV,

FabKey, GreenChip, HiPerSmart, HITAG, I²C-bus logo, ICODE, I-CODE,

ITEC, Labelution, MIFARE, MIFARE Plus, MIFAR E Ultralight, MoReUse,

QLPAK, Silicon Tuner, SiliconMAX, SmartXA, STARplug, TOPFET,

TrenchMOS, TriMedia and UCODE — are trademarks of NXP B.V.

HD Radio and HD Radio logo — are trademarks of iBiquity Digital

Corporation.

10. Contact information

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

NXP Semiconductors PHN203

Dual N-channel TrenchMOS logic level FET

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 27 April 2010

Document identifier: PHN203

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section ‘Legal information’.

11. Contents

1 Product profile. . . . . . . . . . . . . . . . . . . . . . . . . . .1

1.1 General description . . . . . . . . . . . . . . . . . . . . . .1

1.2 Features and benefits. . . . . . . . . . . . . . . . . . . . .1

1.3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . .1

1.4 Quick reference data . . . . . . . . . . . . . . . . . . . . .1

2 Pinning information. . . . . . . . . . . . . . . . . . . . . . .2

3 Ordering information. . . . . . . . . . . . . . . . . . . . . .2

4 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . .2

5 Thermal characteristics . . . . . . . . . . . . . . . . . . .4

6 Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . .5

7 Package outline . . . . . . . . . . . . . . . . . . . . . . . . . .9

8 Revision history. . . . . . . . . . . . . . . . . . . . . . . . .10

9 Legal information. . . . . . . . . . . . . . . . . . . . . . . .11

9.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . .11

9.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

9.3 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . .11

9.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . .12

10 Contact information. . . . . . . . . . . . . . . . . . . . . .12