CY8CMBR2044
Four Button CapSense® Controller
Cypress Semiconductor Corporation • 198 Champion Court • San Jose,CA 95134-1709 • 408-943-2600
Document Number: 001-57451 Rev. *G Revised July 15, 2013
Four Button Ca pSense® Controller
Features
■Easy to use capacitive button controller
❐Four-button solution configurable through Hardware straps
❐No software tools or programming required
❐Four general-purpose outputs (GPOs)
❐GPOs linked to CapSense® buttons
❐GPOs support direct LED drive
■Robust noise performance
❐Specifically designed for superior noise immunity to external
radiated and conducted noise
❐Low radiated noise emission
■SmartSense™ Auto-Tuning
❐Saves time and effort in device tuning
❐CapSense parameters dynamically set in runtime
❐Maintains optimal button performance even in noisy
environment
❐Wide parasitic capacitance CP range (5 pF–40 pF)
■System Diagnostics of CapSense buttons - reports any faults
at device power up
❐Button shorted to Ground
❐Button shorted to VDD
❐Button to button short
❐Improper value of modulator capacitor (CMOD)
❐Parasitic capacitance (CP) out of range
■Advanced features
❐Toggle ON/OFF feature on GPOs
❐Flanking Sensor Suppression (FSS) provides robust sensing
even with closely spaced buttons
❐Configurable LED ON time after button release
❐Button output reset if touched for excessive time
❐User-controlled Button Scan Rate
❐Serial Debug Data output
• Simplifies production line testing and system debug
■Wide operating voltage range
❐1.71 V to 5.5 V – ideal for both regulated and unregulated
battery applications
■Low power consumption
❐Supply current in run mode as low as 15 µA[1] per button
❐Deep sleep current: 100 nA
■Industrial temperature range: –40 °C to + 85 °C
■16-pad quad flat no leads (QFN) package
(3 mm × 3 mm × 0.6 mm)
Overview
The CY8CMBR2044 incorporates several innovative features to
save time and money to quickly enable a capacitive touch
sensing user interface in your design. It is a hardware
configurable device and does not require any software tools or
coding. This device is enabled with Cypress's revolutionary
SmartSense™ Auto-Tuning algorithm. SmartSense™
Auto-Tuning ends the need to manually tune the user interface
during development and production ramp. This speeds the time
to volume and saves valuable engineering time, test time and
production yield loss.
The CY8CMBR2044 CapSense controller supports up to four
capacitive touch sensing buttons and four General Purpose
Outputs (GPOs). The GPO is an active low output controlled
directly by the CapSense input making it ideal for a wide variety
of consumer, industrial, and medical applications. The wide
operating range of 1.71 V to 5.5 V enables unregulated battery
operation, further saving component cost. Also, the same device
can be used in different applications with different power
supplies, including low power supplies.
This device supports ultra low-power consumption in both run
mode and deep sleep mode to stretch battery life. In addition,
this device also supports many advanced features which
enhance the robustness and user interface of the end solution.
Some of the key advanced features include Noise Immunity and
FSS. Noise Immunity improves the immunity of the device
against radiated and conducted noise, such as audio and radio
frequency (RF) noise. FSS provides robust sensing even with
closely spaced buttons. FSS is a critical requirement in small
form factor applications.
Serial Debug Data output gives the critical information about the
design, such as button Cp and Signal-to-Noise Ratio (SNR). This
further helps in production line testing.
Note
1. Power consumption calculated with 1.7% touch time, 500 ms scan rate, and CP of each sensor < 19 pF.
CY8CMBR2044
Document Number: 001-57451 Rev. *G Page 2 of 29
Contents
Pinout ................................................................................3
Typical Circuits .................................................................4
Schematic 1: 4-Buttons,
4-LEDs with Auto Reset Enabled .......................................4
Schematic 2: 3-Buttons, 3-LEDs,
2-Outputs to Master, and Advanced Features Enabled .....5
Configuring the CY8CMBR2044 ...................................... 6
Device Features ................................................................ 6
CapSense Buttons ......................................................6
SmartSense Auto Tuning ............................................6
General Purpose Outputs ............................................ 6
Toggle ON/OFF ...........................................................7
Flanking Sensor Suppression (FSS) ........................... 7
LED ON Time .............................................................. 7
Button Auto Reset ....................................................... 8
System Diagnostics ..................................................... 9
Serial Debug Data ..................................................... 10
Power Consumption and Device Operating Modes ..12
Additional Components
to Enable Advanced Features .......................................... 14
Response Time ......................................................... 14
Layout Guidelines and Best Practices ......................... 15
CapSense Button Shapes ......................................... 16
Button Layout Design ................................................16
Recommended Via Hole Placement ......................... 16
Example PCB Layout Design
with Four CapSense Buttons and Four LEDs ................... 17
Electrical Specifications ................................................ 18
Absolute Maximum Ratings ....................................... 18
Operating Temperature ............................................. 18
DC Electrical Characteristics ..................................... 19
AC Electrical Specifications ....................................... 21
CapSense Specifications .......................................... 21
Ordering Information ...................................................... 22
Ordering Code Definitions ......................................... 22
Package Diagram ............................................................ 23
Package Information ................................................. 23
Appendix ......................................................................... 24
Acronyms ........................................................................ 26
Document Conventions ................................................. 26
Units of Measure ....................................................... 26
Document History Page ................................................. 27
Sales, Solutions, and Legal Information ...................... 29
Worldwide Sales and Design Support ....................... 29
Products .................................................................... 29
PSoC® Solutions ...................................................... 29
Cypress Developer Community ................................. 29
Technical Support ..................................................... 29
CY8CMBR2044
Document Number: 001-57451 Rev. *G Page 3 of 29
Pinout
Table 1. Pin Diagram and Definitions – CY8CMBR2044
Pin Label Type [2] Description If Unused
1 GPO1 DO GPO activated by CS1 Leave
open
2 GPO0 DO GPO activated by CS0 Leave
open
3 Toggle/
FSS
AI Controls FSS and Toggle
ON/OFF features
Ground
4 Delay AI Controls LED ON Time. For
details refer to Table 2 on page 6
Ground
5 CS0 AIO CapSense input, controls GPO0
or serial debug data out
Ground
6 CS1 AIO CapSense input, controls GPO1
or serial debug data out
Ground
7V
SS PGround
8 CS2 AIO CapSense input, controls GPO2
or serial debug data out
Ground
9 ARST AIDO Controls Button Auto Reset Leave
open
10 CS3 AIO CapSense input, controls GPO3
or serial debug data out
Ground
11 XRES DI Device reset, active high, with
internal pull down
Leave
open
12 ScanRate
/
Sleep
AI Controls scan rate and deep
sleep
Ground
13 VDD P Power
14 GPO3 DO GPO activated by CS3 Leave
open
15 CMOD AI External modulator capacitor,
connect a 2.2 nF (±10%) to
ground
16 GPO2 DO GPO activated by CS2 Leave
open
QFN
(Top View)
GPO1
Toggle/FSS
Delay
CS0
1
2
3
4
11
10
9
16
15
14
13
CMOD
GPO3
VDD
ScanRate/Sleep
CS1
CS2
ARST
GPO0
CS3
XRES
GPO2
VSS
12
5
6
7
8
Note
2. AI – Analog Input, AIO – Analog Input / Output, AIDO – Analog Input / Digital Output, DI – Digital Input, DO – Digital Output, P – Power
CY8CMBR2044
Document Number: 001-57451 Rev. *G Page 4 of 29
Typical Circuits
Schematic 1: 4-Buttons, 4-LEDs with Auto Reset Enabled
In the above schematic, the device is configured to support:
■CS0–CS3 pins: 560- to CapSense button
❐Four CapSense buttons (CS0–CS3)
■GPO0–GPO3 pins: LED and 560- to VDD
❐CapSense buttons driving 4 LEDs (GPO0–GPO3)
■CMOD pin: 2.2 nF to ground
❐Modulator capacitor
■XRES pin: Floating
❐For external reset
■Toggle/FSS pin: Ground
❐Toggle ON/OFF disabled
❐FSS disabled
■ARST pin: 5 k to Ground
❐Button Auto Reset enabled, 20 second time
■Delay pin: Ground
❐LED ON Time disabled
■ScanRate/Sleep pin: Ground
❐User configured scan rate = 20 ms
To enable Serial Debug Data output, connect a 5.6 k resistor
on R9 or R12.
VDD
LED 2
D4
LED
R4560 E
LED3
D3
LED
R3560 E
VDD
C1
10uF
CS3
CS0
1R 7 560 E
CS1
R8 560E
CS1 1
VDD
VDD
R12 0E
TP2
CS2
XR E S
VDD
C3
0. 1uF
LED 1
D1 LED
LED 0
R 1 560 E
D2 LED R 2 560 E
VDD
U5
CY8CMBR2044
GPO1
1
GPO0
2
Tog gle /F SS
3
Delay
4
CS0
5
CS1
6
VSS
7
CS2
8
ARST 9
CS3 10
XR E S 11
Sc anrate/ Sleep 12
VDD 13
GPO3 14
CM OD 15
GPO2 16
C2 2.2n F
R9 0E
CS0
R 6 5 K(10% )
R 10 560E
CS2 1
R1 1 560E CS3
1
TP1
ARST
CY8CMBR2044
Document Number: 001-57451 Rev. *G Page 5 of 29
Schematic 2: 3-Buttons, 3-LEDs, 2-Outputs to Master, and Advanced Features Enabled
In the above schematic the device is configured to support:
■CS0–CS2 pins: 560- to CapSense buttons; CS3 pin: Ground
❐Three CapSense buttons (CS0–CS2)
❐CS3 not used in design
■GPO0–GPO2 pins: LED and 560- to VDD; GPO3 floating;
GPO0–GPO1 pins interfaced to Master
❐CapSense buttons driving 3 LEDs (GPO0–GPO2)
❐GPO0, GPO1 interfaced to master for direct status read
■CMOD pin: 2.2 nF to ground
❐Modulator capacitor
■XRES pin: Floating
❐For external reset
■Toggle/FSS pin: 5.1 k to Ground
❐Toggle ON/OFF disabled
❐FSS enabled
■ARST pin: 5 k to Ground
❐Button Auto Reset enabled, Auto Reset period = 20 seconds
■Delay pin: 4 k to Ground
❐LED ON Time of 1000 ms
■ScanRate/Sleep pin: 560 to Master
❐User configured scan rate = 30 ms
❐Master to control device operating mode
To enable Serial Debug Data output, connect a 5.6 k resistor
on R11.
R 9 560E
VDD
VDD
XR ES
LED0
LED1
C2 2.2nF
GPO3
ARST
R6 5K(10%)
R4 5.1K(5%)
D3
LED
R10
560E
LED2
R5 4K(1% )
VD D
R11 0E
R2 560E(1%)
SCAN
T O MA STERTO MAS TER
TO MAST ER
U5
C Y 8CMBR2044
GPO1
1
GPO0
2
Tog gle/ FSS
3
Delay
4
CS0
5
CS1
6
VS S
7
CS2
8
ARST 9
CS3 10
XRE S 11
Sc anrate/ Sleep 12
VDD 13
GP O 3 14
CM OD 15
GPO2 16
D1
LED
R1
560E
D2
LED
VDD
R3
560E
TP1
VDD
C3
0. 1uF
VD D
C1
10uF
CS0
CS0
1R7 560E
CS1
R8 560E
CS1 1
CS2 1CS2
CY8CMBR2044
Document Number: 001-57451 Rev. *G Page 6 of 29
Configuring the CY8CMBR2044
The CY8CMBR2044 device features are configured using
external resistors.
The resistors on the hardware configurable pins are determined
by the device upon power-on.
The Appendix gives the matrix of features enabled using
different external resistor configurations.
To know more about the required settings for your design, refer
to the CY8CMBR2044 Design Guide.
Device Features
CapSense Buttons
■Device supports up to four CapSense buttons
■Ground the CSx pin to disable CapSense input
■A 2.2-nF (+10%) capacitor must be connected on the CMOD pin
for proper CapSense operation
■The parasitic Capacitance (CP) of each button must be less
than 40 pF for proper CapSense operation
SmartSense Auto Tuning
■Device supports auto tuning of CapSense parameters
■No manual tuning required; all parameters are automatically
tuned by the device
■Compensates printed circuit board (PCB) variations, device
process variations, and PCB vendor changes
■Ensures portability of the user interface design
General Purpose Outputs
■The GPOx is controlled by the corresponding CSx
■GPOx pins output are in strong drive mode [3]
■Active low output – supports sinking configuration
■If CSx is disabled (grounded), then the corresponding GPOx
must be left floating
■A 5-ms active LOW pulse is sent after 175 ms after device
power-up, on a GPOx after that it is set to Logic HIGH, if the
CSx fails the System Diagnostics.
■GPOx pin outputs are in strong drive mode at logic level HIGH
in Deep sleep power mode.
■GPOx pins output are in strong drive mode and retain the logic
level same as before entering into low power sleep mode based
on feature like (Toggle ,etc).
■All GPO pins are placed in a High-impedance state during reset
i.e. XRES,POR.
Table 2. Advanced Features supported by CY8CMBR2044
Feature Benefits
Toggle ON/OFF Button retains state on touch
(ON/OFF)
Flanking Sensor Suppression
(FSS)
Helps in distinguishing closely
spaced buttons
LED ON Time Gives an LED effect on button
release
Button Auto Reset Disables false output trigger
due to conducting object
placed close to button
System Diagnostics Support for production testing
and debugging
Serial Debug Data Support for production testing
and validating design
Low Power Sleep Mode and
Deep Sleep Mode
Low power consumption
Note
3. When a pin in in strong drive mode, it is pulled up to VDD when the output is HIGH and pulled down to Ground when the output is LOW. The output cannot be floating.
CY8CMBR2044
Document Number: 001-57451 Rev. *G Page 7 of 29
Toggle ON/OFF
■Toggles the GPO state at each button touch.
■Used for mechanical button replacement. For example, wall
switch.
Flanking Sensor Suppression (FSS)
■Helps to distinguish closely spaced buttons.
■Also used in situations when a button can produce opposite
effects. For example, an interface with two buttons for
brightness control (UP or DOWN).
■FSS action can be explained for the following different
scenarios:
❐When only one button is touched, it is reported as ON.
❐When more than one button is detected as ON and previously
one of those buttons was touched, then the previously
touched button is reported as ON.
LED ON Time
■Provides better visual feedback when a button is released and
improves the design’s aesthetic value.
■The GPOx is driven low for a specified interval after the corre-
sponding CSx button is released.
■When a button gets reset, LED ON Time is not applied on the
corresponding GPO.
■In Figure 3 on page 7, GPO0 goes high prematurely (prior to
LED ON Time) because CS1 button is released. Therefore, the
LED ON Time counter is reset. Now, GPO1 remains LOW for
LED ON Time after releasing CS1.
■LED ON Time can range from 0–2000 ms.
■LED ON Time resolution is 20 ms.
Figure 1. Example of Toggle Feature on GP0
Figure 2. Button Status with Respect to Finger Touch when FSS is Enabled
Figure 3. Example LED ON timing diagram on GPO0
CS0
GPO0
LEDONTime
CY8CMBR2044
Document Number: 001-57451 Rev. *G Page 8 of 29
Figure 4. Example LED ON timing diagram on multiple GPO0 and GPO1
Button Auto Reset
■Prevents button stuck, due to metal object placed close to a
button.
■Useful when GPO output to be kept ON only for a specific time.
■If enabled, the GPOx is driven for a maximum of Button Auto
Reset period when CSx is continuously touched. See Figure 5
on page 8.
■Button Auto Reset period can be set to 5 or 20 seconds.
■After the Button Auto Reset has been triggered, the CSx hold
time of that button after the button has been released is given
in Table 3. The hardware configuration is shown in Ta bl e 15 in
Appendix.
Figure 5. Example of Button Auto Reset on GP0
CS0
GPO0
CS1
GPO1
StartLEDONTime
Counter
RestartLEDON
TimeCounter
ResetLEDON
TimeCounter
LEDONTime
Table 3. Button Hold Time After Auto Reset
Button Press Time after Button Auto Reset Button Hold Time (ms)
< 2 sec 220
> 2 sec ScanRate + 200
CS0
GPO0
AutoResetperiod
GPO0isnotdrivenafter
AutoResetperiod
Buttonistouchedformore
thantheAutoResetperiod
CY8CMBR2044
Document Number: 001-57451 Rev. *G Page 9 of 29
System Diagnostics
■A built-in Power-on Self Test (POST) mechanism performs
some tests at Power-on Reset (POR), which can be useful in
production testing.
■If any button fails these tests, a 5 ms pulse is sent out on the
corresponding GPO withing 175 ms after POR.
■Following tests are performed on all the buttons -
Button Shorted to Ground
If any button is found to be shorted to ground, it is disabled. See
Figure 6.
Figure 6. Button Shorted to Ground
Button Shorted to VDD
If any button is found to be shorted to VDD, it is disbled. See
Figure 7.
Figure 7. Button Shorted to VDD
Button to Button Short
If two or more buttons are found to be shorted to each other, all
of these buttons are disabled. See Figure 8.
Figure 8. Button to Button Short
Improper Value of CMOD
■Recommended value of CMOD is 2 nF to 2.4 nF.
■If the value of CMOD is found to be less than 1 nF or greater
than 4 nF, all the buttons are disabled.
Button CP > 40 pF
If the parasitic capacitance (CP) of any button is found to be more
than 40 pF, that button is disabled.
CY8CMBR2044
Document Number: 001-57451 Rev. *G Page 10 of 29
Figure 9. Example Showing CS0 and CS1 Passing the POST and CS2 and CS3 Failing
In Figure 9, CS0 and CS1 buttons are enabled; CS2 and CS3
buttons are disabled because they failed the Power-on Self Test.
A 5 ms pulse is observed on GPO2 and GPO3.
Serial Debug Data
■Used to see CapSense data for debug purposes
■If enabled, debug data is transmitted using UART
communication protocol.
■To enable this feature pull down any one of the CapSense pins
with a 5.6 k resistor to ground. Data is sent out on the same
CapSense pin
■If more than one CapSense pin is pulled down, debug data is
sent out only on one CapSense pin and the priority is CS0 >
CS1 > CS2 > CS3
■The Cypress MultiChart tool can be used to view the data as a
graph.
■Serial data is sent out with ~115,200 baud rate
■Firmware revision, CapSense status, GPO status, raw count,
baseline, difference count, and parasitic capacitance of all
sensors are sent out
■For designs having a maximum of three CapSense buttons,
Cypress recommends to take the debug data on a CapSense
button that is not used in design
■For designs with four CapSense buttons, Cypress
recommends taking debug data on two CapSense buttons. For
example, pull down CS0 with a 5.6 kresistor and read data
of CS1, CS2, and CS3. Next, pull down CS1 with a 5.6 k
resistor and read data of CS0, CS2, and CS3
For more information on Raw Count, Baseline, Difference Count
and Parasitic Capacitance, refer to Getting Started with
CapSense, section 2. For more information on MultiChart tool,
refer to AN2397 CapSense Data Viewing Tools, Method 2.
■MultiChart tool arranges the data in the format as shown in
Table 4.
■The Serial Debug Data is sent by the device in the order as per
Table 5.
Max time to get 5 ms pulse is 175 ms after power up
5 ms pulse
Table 4. Serial Debug Data arranged in MultiChart
S.No. Raw Count Array Baseline Array Signal Array
MSB LSB MSB LSB MSB LSB
0 0x00 FW_Revision CS_Status GPO_Status 0x00 CS2_CP
1 0x00 CS0_ CP0x00 CS1_CP0x00 CS3_ CP
2 CS0_RawCount CS0_Baseline CS0_DiffCount
3 CS1_RawCount CS1_Baseline CS1_DiffCount
4 CS2_RawCount CS2_Baseline CS2_DiffCount
5 CS3_RawCount CS3_Baseline CS3_DiffCount
CY8CMBR2044
Document Number: 001-57451 Rev. *G Page 11 of 29
Table 5. Serial Data Output sent by CY8CMBR2044
Byte Data Notes
0 0x0D Dummy data for multi chart
1 0x0A
20x00–
3 FW_Revision –
40x00–
5CS0_C
PCS0 parasitic capacitance in Hex
6 CS0_RawCount_MSB Unsigned 16-bit integer
7 CS0_RawCount_LSB –
8 CS1_RawCount_MSB Unsigned 16-bit integer
9 CS1_RawCount_LSB –
10 CS2_RawCount_MSB Unsigned 16-bit integer
11 CS2_RawCount_LSB –
12 CS3_RawCount_MSB Unsigned 16-bit integer
13 CS3_RawCount_LSB –
14 CS_Status Gives CapSense button status, least significant bit (LSB) contains CS0 status
15 GPO_Status Gives GPO status, LSB contains GPO0 status
16 0x00 –
17 CS1_CPCS1 parasitic capacitance in Hex
18 CS0_ Baseline _MSB Unsigned 16-bit integer
19 CS0_ Baseline _LSB –
20 CS1_ Baseline _MSB Unsigned 16-bit integer
21 CS1_ Baseline _LSB –
22 CS2_ Baseline _MSB Unsigned 16-bit integer
23 CS2_ Baseline _LSB –
24 CS3_ Baseline _MSB Unsigned 16-bit integer
25 CS3_ Baseline _LSB –
26 0x00 –
27 CS2_CPCS2 parasitic capacitance in Hex
28 0x00 –
29 CS3_CPCS3 parasitic capacitance in Hex
30 CS0_ DiffCount _MSB Unsigned 16-bit integer
31 CS0_ DiffCount _LSB –
32 CS1_ DiffCount _MSB Unsigned 16-bit integer
33 CS1_ DiffCount _LSB –
34 CS2_ DiffCount _MSB Unsigned 16-bit integer
35 CS2_ DiffCount _LSB –
36 CS3_ DiffCount _MSB Unsigned 16-bit integer
37 CS3_ DiffCount _LSB –
38 0x00
Dummy data for multi chart39 0xFF
40 0xFF
CY8CMBR2044
Document Number: 001-57451 Rev. *G Page 12 of 29
Power Consumption and Device Operating Modes
The CY8CMBR2044 is designed to meet the low power requirements of battery powered applications. To design for the lowest
operating current -
■Ground all unused CapSense inputs
■Minimize CP using the design guidelines in Getting Started with CapSense, section 3.7.1.
■Lower the supply voltage.
■Use a higher Button Scan Rate or Deep Sleep operating mode.
To know more about the steps to reduce power consumption, refer to CY8CMBR2044 Design Guide, section 5.
There are two device operating modes:
■Low power sleep mode
■Deep sleep mode
Low Power Sleep Mode
The following flow chart describes the low power sleep mode operation.
Figure 10. Low Power Sleep Mode Operation
Figure 11. Low Power Sleep Mode Implementation
Scan all buttons with 20 ms Scan
Rate (Scan time + Sleep time)
NO button touched for
2 secs?
Yes
Scan all buttons with user defined
scan rate.
Is any button active?
Yes
No
No
CY8CMBR2044
Document Number: 001-57451 Rev. *G Page 13 of 29
■To enable low power sleep mode, the hardware configurable pin ScanRate/Sleep should be pulled down to ground with resistor ‘R’
(1%). The scan rate values for different resistor values are given in Table 15 in Appendix.
■If the ScanRate/Sleep pin is pulled to ground without any resistor, the Button Scan Rate is set to 20 ms. The device operates in low
power sleep mode, unless a button is touched.
■The range of scan rate is 20 to 530 ms.
Figure 12. Average Current vs Scan Rate [4]
Note
4. Number of sensors = 3, Cp < 19 pF, 0% touch time, VDD = 3 V.
CY8CMBR2044
Document Number: 001-57451 Rev. *G Page 14 of 29
Deep Sleep Mode
Figure 13. ScanRate/Sleep Pin Connection to Enable Deep Sleep Mode
■To enable the deep sleep mode, the hardware configuration
pin ScanRate/Sleep should be connected to the master device
as shown in Figure 13.
■Host controller should pull the pin to VDD for the device to go
into deep sleep.
■The Host controller output pin should be in Strong drive mode,
so that the ScanRate/Sleep pin is not left floating.
■In deep sleep mode, all blocks are turned off and the device
current consumption is approximately 0.1 µA.
■There is no CapSense scanning in deep sleep mode.
■ScanRate/Sleep pin should be pulled low for the device to wake
up from deep sleep.
■When device comes out of deep sleep mode, the CapSense
system is reinitialized. Typical time for reinitialization is 8 ms.
Any button touch within this time is not reported.
■After the device comes out of deep sleep, the device operates
in low power sleep mode.
■If the ScanRate/Sleep pin is pulled high at power on, then the
device does not go to deep sleep immediately. The device goes
to deep sleep after initializing all internal blocks and scanning
all buttons once.
■If the ScanRate/Sleep pin is pulled high at power on, then the
button scan rate is calculated when the device is taken out of
Deep Sleep by the master.
Additional Components to Enable Advanced Features
Response Time
Response time is the minimum amount of time the button should be touched for the device to detect as valid button press.
CY8CMBR
2044 HOST
External Resistor R
(Controls Scan Rate)
ScanRate
/Sleep Digital Output pin
(Controls Deep Sleep)
S.No. Feature Resistors
required Notes
1 Low power sleep and
deep sleep
1 Deep sleep is controlled by a master device. When the device comes out of deep
sleep, it enters into low power sleep mode based on settings. Resistor is not required
if both features are not used.
2 Toggle/FSS 1 To enable both the features only one resistor is required. Resistor is not required if
both features are not used.
3 Delay Off 1 Resistor is not required if the feature is not used.
4 Sensor auto reset 1 Resistor is not required if the feature is not used.
Condition Response time (in ms)
First button press Button Scan rate value + 20. For button scan rate value, see
Tab l e 15 in Appendix.
Consecutive button press after first button press 80
CY8CMBR2044
Document Number: 001-57451 Rev. *G Page 15 of 29
Layout Guidelines and Best Practices
S.No. Category Min Max Recommendations / Remarks
1Button shape – – Solid round pattern, round with LED hole, rectangle with
round corners
2Button size 5 mm 15 mm Refer Design Toolbox
3Button-button spacing Equal to Button
Ground
Clearance
–8 mm
(Y dimension in Button Layout Design on page 16)
4Button ground clearance 0.5 mm 2 mm Refer Design Toolbox
(X dimension in Button Layout Design on page 16)
5Ground flood – top layer – – Hatched ground 7 mil trace and 45 mil grid (15% filling)
6Ground flood – bottom layer – – Hatched ground 7 mil trace and 70 mil grid (10% filling)
7Trace length from button pad to
CapSense controller pins
–450 mm Refer Design Toolbox
8Trace width 0.17 mm 0.20 mm 0.17 mm (7 mil)
9Trace routing – – Traces should be routed on the non button side. If any
non CapSense trace crosses CapSense trace, ensure
that intersection is orthogonal
10 Via position for the buttons – – Via should be placed near the edge of the button to
reduce trace length thereby increasing sensitivity
11 Via hole size for button traces – – 10 mil
12 No. of via on button trace 1 2 1
13 Distance of CapSense series
resistor from button pin
–10 mm Place CapSense series resistors close to the device for
noise suppression. CapSense resistors have highest
priority; place them first
14 Distance between any CapSense
trace to ground flood
10 mil 20 mil 20 mil
15 Device placement – – Mount the device on the layer opposite to button. The
CapSense trace length between the device and buttons
should be minimum (see trace length above)
16 Placement of components in two
layer PCB
– – Top layer – buttons and
bottom layer – device, other components and traces
17 Placement of components in four
layer PCB
– – Top layer – buttons,
second layer – CapSense traces and VDD (avoid VDD
traces below the buttons),
third layer – hatched ground,
bottom layer – CapSense IC or device, other
components, and non CapSense traces
18 Overlay thickness 0 mm 5 mm Refer Design Toolbox
19 Overlay material – – Should be non-conductive material. Glass, ABS plastic,
formica, wood, and so on. There should be no air gap
between PCB and overlay. Use adhesive to stick the
PCB and overlay
20 Overlay adhesives – – Adhesive should be non conductive and dielectrically
homogenous. 467MP and 468MP adhesives made by
3M are recommended
21 LED back lighting – – Cut a hole in the button pad and use rear mountable
LEDs. Refer to Example PCB Layout Design with Four
CapSense Buttons and Four LEDs on page 17
22 Board thickness – – Standard board thickness for CapSense FR4 based
designs is 1.6 mm.
CY8CMBR2044
Document Number: 001-57451 Rev. *G Page 16 of 29
CapSense Button Shapes
Figure 14. CapSense Button Shapes
Button Layout Design
Figure 15. Button Layout Design
X: Button to ground clearance (Refer to Layout Guidelines and Best Practices on page 15)
Y: Button to button clearance (Refer to Layout Guidelines and Best Practices on page 15)
Recommended Via Hole Placement
Figure 16. Recommended Via Hole Placement
CY8CMBR2044
Document Number: 001-57451 Rev. *G Page 17 of 29
Example PCB Layout Design with Four CapSense Buttons and Four LEDs
Figure 17. Top Layer
Figure 18. Bottom Layer
CY8CMBR2044
Document Number: 001-57451 Rev. *G Page 18 of 29
Electrical Specifications
This section presents the DC and AC electrical specifications of the CY8CMBR2044 device.
Absolute Maximum Ratings
Operating Temperature
Table 6. Absolute Maximum Ratings
Parameter Description Min Typ Max Unit Notes
TSTG Storage temperature –55 25 +125 °C Higher storage temperatures reduce data
retention time. Recommended storage
temperature is +25 °C ± 25 °C. Extended
duration storage temperatures above 85 °C
degrades reliability.
VDD Supply voltage relative to VSS –0.5 – +6.0 V
VIO DC voltage on CapSense inputs and
digital output pins
VSS – 0.5 – VDD + 0.5 V
IMIG Maximum current into any GPO
output pin
–25 – +50 mA
ESD Electro static discharge voltage 2000 – – V Human body model ESD
LU Latch up current – – 200 mA In accordance with JESD78 standard
Table 7. Operating Temperature
Parameter Description Min Typ Max Unit Notes
TAAmbient temperature –40 – +85 °C
TJOperational die temperature –40 – +100 °C
CY8CMBR2044
Document Number: 001-57451 Rev. *G Page 19 of 29
DC Electrical Characteristics
DC Chip Level Specifications
The following table lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges.
Table 8. DC Chip Level Specifications
Parameter Description Min Typ Max Unit Notes
VDD[5, 6, 7] Supply voltage 1.71 – 5.5 V
IDD Supply current – 2.88 4.0 mA Conditions are VDD = 3.0 V, TA = 25 °C
IDA Active current – 2.88 4.0 mA Conditions are VDD = 3.0 V, TA = 25 °C,
continuous sensor scan
IDS Deep sleep current – 0.1 0.5 µA Conditions are VDD = 3.0 V, TA = 25 °C
IAV1 Average current – 40 – µA Conditions are VDD = 3.0 V, TA = 25 °C,
4 – buttons used, 0% touch time, CP of all
sensors < 19 pF and scan rate = 530 ms
IAV2 Average current – 63 – µA Conditions are VDD = 3.0 V, TA = 25 °C,
4 – buttons used, 0% touch time, CP of all
sensors > 19 pF and scan rate = 530 ms
IAV3 Average current – 1 – mA Conditions are VDD = 3.0 V, TA = 25 °C,
4 – buttons used, 100% touch time, CP of all
sensors < 19 pF and scan rate = 20 ms
IAV4 Average current – 1.6 – mA Conditions are VDD = 3.0 V, TA = 25 °C,
4 – buttons used, 100% touch time, CP of all
sensors > 19 pF and < 40 pF,
scan rate = 20 ms
Notes
5. When VDD remains in the range from 1.75 V to 1.9 V for more than 50 µs, the slew rate when moving from the 1.75 V to 1.9 V range to greater than 2 V must be
slower than 1 V/500 µs. This helps to avoid triggering POR. The only other restriction on slew rates for any other voltage range or transition is the SRPOWER_UP
parameter.
6. After power down, ensure that VDD falls below 100 mV before powering backup.
7. For proper CapSense block functionality, if the drop in VDD exceeds 5% of the base VDD, the rate at which VDD drops should not exceed 200 mV/s. Base VDD can
be between 1.8 V and 5.5 V
CY8CMBR2044
Document Number: 001-57451 Rev. *G Page 20 of 29
DC General Purpose I/O Specifications
These tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 3.0 V to 5.5 V and
–40 °C < TA < 85°C, 2.4 V to 3.0 V and –40 °C < TA < 85 °C, or 1.71 V to 2.4 V and –40 °C < TA < 85 °C, respectively. Typical parameters
apply to 5 V and 3.3 V at 25 °C and are for design guidance only.
Table 9. 3.0 V to 5 V DC General Purpose I/O Specifications
Parameter [8] Description Min Typ Max Unit Notes
VOH1 High output voltage on GP0,
GP1, GP2, GP3
VDD – 0.2 – – V IOH < 10 µA, maximum of 40 µA
source current in all I/Os
VOH2 High output voltage on GP0, GP1 VDD – 0.9 – – V IOH = 1 mA, maximum of 2 mA
source current in all I/Os
VOH3 High output voltage on GP2, GP3 VDD – 0.9 – – V IOH = 5 mA, maximum of 10 mA
source current in all I/Os
VOL Low output voltage – – 0.75 V IOL = 25 mA/pin, VDD > 3.30,
maximum of 60 mA sink current on
GPO0, GPO1, GPO2, GPO3
Table 10. 2.4 V to 3.0 V DC General Purpose I/O Specifications
Parameter [8] Description Min Typ Max Unit Notes
VOH1 High output voltage on GP0,
GP1, GP2, GP3
VDD – 0.2 – – V IOH < 10 µA, maximum of 40 µA
source current in all I/Os
VOH2 High output voltage on GP0, GP1 VDD – 0.4 – – V IOH = 0.2 mA, maximum of 0.4 mA
source current in all I/Os
VOH3 High output voltage on GP2, GP3 VDD – 0.5 – – V IOH = 2 mA, maximum of 4 mA
source current in all I/Os
VOL Low output voltage – – 0.72 V IOL = 10 mA/pin, maximum of 30
mA sink current on GPO0, GPO1,
GPO2, GPO3
Table 11. 1.71 V to 2.4 V DC General Purpose I/O Specifications
Parameter [8] Description Min Typ Max Unit Notes
VOH1 High output voltage on GP0,GP1 VDD – 0.2 – – V IOH =10 µA, maximum of 20 µA
source current in all I/Os
VOH2 High output voltage on GP0,GP1 VDD – 0.5 – – V IOH = 0.5 mA, maximum of 1 mA
source current in all I/Os
VOH3 High output voltage on GP2,GP3 VDD – 0.2 – – V IOH = 100 µA, maximum of 200 µA
source current in all I/Os
VOH4 High output voltage on GP2,GP3 VDD – 0.5 – – V IOH = 2 mA, maximum of 4 mA
source current in all I/Os
VOL Low output voltage – – 0.4 V IOL = 5 mA/pin, maximum of 20 mA
sink current on GPO0, GPO1,
GPO2, GPO3
Note
8. XRES pin input voltage ranges at various DC Specifications (VDD) listed below:
Minimum Input voltage for reset is 2V at 3.0 V to 5.5 V.
Minimum Input voltage for reset is 1.4V at 2.4 V to 3.0 V.
Minimum Input voltage for reset is 0.65 × VDD at 1.71 V to 2.4 V.
CY8CMBR2044
Document Number: 001-57451 Rev. *G Page 21 of 29
AC Electrical Specifications
AC Chip-Level Specifications
The following table lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges.
AC General Purpose I/O Specifications
CapSense Specifications
Parameter Description Min Max Unit Notes
SRPOWER_UP Power supply slew rate – 250 V/ms VDD slew rate during power up
TXRST External reset pulse width at power up 1 – ms After supply voltage is valid
TXRST2 External reset pulse width after
power-up
10 – µs Applies after part has booted
Parameter Description Min Typ Max Unit Notes
TRise1 Rise time on GPO0 and GPO1,
Cload = 50 pF
15 – 80 ns VDD = 3.0 to 3.6 V, 10% – 90%
TRise2 Rise time on GPO2 and GPO3,
Cload = 50 pF
10 – 50 ns VDD = 3.0 to 3.6 V, 10% – 90%
TRise3 Rise time on GPO0 and GPO1,
Cload = 50 pF
15 – 80 ns VDD = 1.71 to 3.0V, 10% – 90%
TRise2 Rise time on GPO2 and GPO3,
Cload = 50 pF
10 – 80 ns VDD = 1.71 to 3.0 V, 10% – 90%
TRise4 Fall time, Cload=50 pF all GPO outputs 10 – 50 ns VDD = 3.0 to 3.6 V, 90% – 10%
TFall2 Fall time, Cload=50 pF all GPO outputs 10 – 70 ns VDD = 1.71 to 3.0 V, 90% – 10%
Parameter Description Min Typ Max Unit Notes
CPParasitic capacitance 5.0 – (CP+CF)<40 pF CP is the total capacitance seen
by the pin when no finger is
present. CP is sum of CBUTTON,
CTRACE, and Capacitance of
the vias and CPIN
CFFinger capacitance 0.25 – (CP+CF)<40 pF CF is the capacitance added by
the finger touch
CPIN Capacitive load on pins as input 0.5 1.7 7 pF
CMOD External modulator capacitor 2 2.2 2.4 nF Mandatory for CapSense to
work
Rs Series resistor between pin and the
sensor
–560 616 Reduces the RF noise
CY8CMBR2044
Document Number: 001-57451 Rev. *G Page 22 of 29
Ordering Information
Ordering Code Definitions
Ordering Code Package Type Operating
Temperature
CapSense
Inputs GPOs XRES Pin
CY8CMBR2044-24LKXI 16-pin QFN (3 × 3 × 0.6 mm) Industrial 4 4 Yes
CY8CMBR2044-24LKXIT 16-pin QFN (3 × 3 × 0.6 mm) (Tape and Reel) Industrial 4 4 Yes
X = blank or T
blank = Tube; T = Tape and Reel
Temperature Range:
I = Industrial
Pb-free
Package Type:
LK = 16-pin QFN
Speed Grade: 24 MHz
Part Number
Mechanical Button Replacement
Technology Code: C = CMOS
Marketing Code: 8 = PSoC
Company ID: CY = Cypress
IC MBR 2044 - 24 LKCY 8 X X
CY8CMBR2044
Document Number: 001-57451 Rev. *G Page 23 of 29
Package Diagram
Figure 19. 16-pin Chip On Lead (3 × 3 × 0.6 mm) LG16A/LD16A (Sawn) Package Outline, 001-09116
Package Information
001-09116 *H
Table 12. Thermal Impedances by Package
Package Typical JA[9]
16-pin QFN 32.7 °C/W
Table 13. Solder Reflow Peak Temperature
Package Minimum Peak Temperature [10] Maximum Peak Temperature
16-pin QFN 240 °C 260 °C
Notes
9. TJ = TA + Power x JA
10. Higher temperatures may be required based on the solder melting point. Typical temperatures for solder are 220 ± 5 °C with Sn-Pb or 245 ± 5 °C with Sn-Ag-Cu
paste. Refer to the solder manufacturer specifications.
CY8CMBR2044
Document Number: 001-57451 Rev. *G Page 24 of 29
Appendix
Table 14. Device Features vs. Resistor Configuration Matrix
Features Comments Pin Configuration Device Pin Name
Button Auto Reset Enabled, Auto Reset Period = 5 ms Ground / Floating ARST
Enabled, Auto Reset Period = 20 ms 5.1 k (±5%) to ground
Disabled VDD
LED ON Time 0 ms Ground Delay
20 ms 120 (±1%) to ground
40 ms 200 (±1%) to ground
60 ms 280 (±1%) to ground
………… …………
1980 ms 7060 (±1%) to ground
2000 ms 8040 (±1%) to ground
2000 ms > 8040 (±1%) to
ground
2000 ms VDD / Floating
Toggle ON/OFF /
Flanking Sensor
Suppression (FSS)
Toggle ON/OFF FSS Toggle/FSS
Disabled Disabled Ground / Floating
Enabled Disabled 1.5 k (±5%) to ground
Disabled Enabled 5.1 k (±5%) to ground
Enabled Enabled VDD
CY8CMBR2044
Document Number: 001-57451 Rev. *G Page 25 of 29
Table 15. ScanRate/Sleep Pin Hardware Configuration
Resistor R (1%) in ohms Approximate ScanRate (in ms) Resistor R (1%) in ohms Approximate ScanRate (in ms)
60 20 4060 209
185 22 4185 217
310 24 4310 226
435 27 4435 235
560 30 4560 244
685 34 4685 253
810 38 4810 263
935 42 4935 272
1060 46 5060 282
1185 51 5185 291
1310 55 5310 301
1435 61 5435 311
1560 66 5560 321
1685 71 5685 331
1810 77 5810 341
1935 83 5935 352
2060 89 6060 362
2185 96 6185 373
2310 102 6310 383
2435 107 6435 394
2560 115 6560 405
2685 122 6685 416
2810 129 6810 427
2935 137 6935 438
3060 144 7060 449
3185 152 7185 461
3310 159 7310 472
3435 167 7435 484
3560 175 7560 495
3685 183 7685 507
3810 192 7810 519
3935 200 7935 531
CY8CMBR2044
Document Number: 001-57451 Rev. *G Page 26 of 29
Acronyms Document Conventions
Units of Measure
Numeric Naming
Hexadecimal numbers are represented with all letters in
uppercase with an appended lowercase 'h' (for example, '14h' or
'3Ah'). Hexadecimal numbers may also be represented by a '0x'
prefix, the C coding convention. Binary numbers have an
appended lowercase 'b' (for example, 01010100b' or
'01000011b'). Numbers not indicated by an 'h', 'b', or 0x are
decimal.
Acronym Description
AC Alternating Current
AI Analog Input
AIO Analog Input/Output
AIDO Analog Input/Digital Output
DO Digital Output
P Power pins
CFFinger Capacitance
CPParasitic Capacitance
CS CapSense
FSS Flanking Sensor Suppression
GPO General Purpose Output
LSB Least Significant Bit
MSB Most Significant Bit
PCB Printed Circuit Board
POR Power On Reset
POST Power On Self Test
RF Radio Frequency
Symbol Unit of Measure
°C degree Celsius
kkilohm
µA microampere
µs microsecond
mA milliampere
ms millisecond
mV millivolt
nA nanoampere
ohm
pF picofarad
Vvolt
CY8CMBR2044
Document Number: 001-57451 Rev. *G Page 27 of 29
Document History Page
Document Title: CY8CMBR2044, Four Button CapSense® Controller
Document Number: 001-57451
Rev. ECN No. Orig. of
Change
Submission
Date Description of Change
** 2807997 SLAN 12/03/2009 New data sheet.
*A 2949368 SLAN 06/10/2010 Updated Features.
Updated Overview.
Updated Pinout.
Updated Typical Circuits (Updated Schematic 1: 4-Buttons, 4-LEDs with Auto
Reset Enabled and Schematic 2: 3-Buttons, 3-LEDs, 2-Outputs to Master, and
Advanced Features Enabled).
Updated Device Features (Added Tabl e 2 , updated Hardware Configuration
(description), updated Flanking Sensor Suppression (FSS) (Added Figure 2),
updated System Diagnostics (Added Figure 6, and Figure 8), added Serial
Debug Data).
Updated Power Consumption and Device Operating Modes (Updated Deep
Sleep Mode (description)).
Updated Layout Guidelines and Best Practices (Updated CapSense Button
Shapes, updated Example PCB Layout Design with Four CapSense Buttons
and Four LEDs).
Updated Electrical Specifications.
Added Ordering Code Definitions.
Added Units of Measure.
*B 2975370 SLAN 07/09/2010 Updated Features.
Updated Pinout.
Updated Typical Circuits.
Updated Device Features (Updated LED ON Time (Updated Figure 4),
updated System Diagnostics (Updated Figure 6, and Figure 8), updated Serial
Debug Data (description)).
Updated Power Consumption and Device Operating Modes (Updated Deep
Sleep Mode (description)).
*C 2996393 SLAN 07/29/2010 Updated Features.
*D 3036873 ARVM 09/23/2010 Updated Typical Circuits (Updated Schematic 1: 4-Buttons, 4-LEDs with Auto
Reset Enabled and Schematic 2: 3-Buttons, 3-LEDs, 2-Outputs to Master, and
Advanced Features Enabled).
Updated Layout Guidelines and Best Practices (Updated Example PCB Layout
Design with Four CapSense Buttons and Four LEDs (Updated Figure 17)).
CY8CMBR2044
Document Number: 001-57451 Rev. *G Page 28 of 29
*E 3624224 UDYG /
SLAN
05/22/2012 Updated Title to read as “Four Button CapSense® Controller”.
Updated Features.
Updated Overview.
Updated Pinout (Updated Table 1).
Updated Typical Circuits (Updated Schematic 1: 4-Buttons, 4-LEDs with Auto
Reset Enabled and Schematic 2: 3-Buttons, 3-LEDs, 2-Outputs to Master, and
Advanced Features Enabled).
Updated Device Features (Updated Ta b l e 2 , updated CapSense Buttons,
updated SmartSense Auto Tuning, updated General Purpose Outputs,
removed Hardware Configuration, updated Toggle ON/OFF, updated Flanking
Sensor Suppression (FSS), removed Delay Off, added LED ON Time, updated
Button Auto Reset, renamed Failure Mode Analysis as System Diagnostics
and updated the same section, renamed Debug Data as Serial Debug Data
and updated the same section, renamed Device Operating Modes as Power
Consumption and Device Operating Modes).
Updated Layout Guidelines and Best Practices.
Updated Electrical Specifications (Updated DC Electrical Characteristics
(Updated DC Chip Level Specifications (Updated Note 6)), updated DC
General Purpose I/O Specifications).
Updated CapSense Specifications.
Updated Ordering Information (Removed CapSense Block column).
Updated Package Diagram.
Added Appendix.
Replaced all instances of sensor with button across the document.
Updated in new template.
*F 3907113 SEEE 02/19/2013 Updated Device Features (Updated General Purpose Outputs)).
Updated Electrical Specifications (Updated DC Electrical Characteristics
(Updated DC General Purpose I/O Specifications (Added Note 8 and referred
the same note in parameter column in Table 9, Table 10, Tab l e 11 )))).
Updated Package Diagram:
spec 001-09116 – Changed revision from *F to *G.
*G 4062936 VAIR 07/15/2013 Replaced “CS _Status” with “CS_Status” in all instances across the document.
Updated Package Diagram:
spec 001-09116 – Changed revision from *G to *H.
Updated in new template.
Document History Page (continued)
Document Title: CY8CMBR2044, Four Button CapSense® Controller
Document Number: 001-57451
Rev. ECN No. Orig. of
Change
Submission
Date Description of Change
Document Number: 001-57451 Rev. *G Revised July 15, 2013 Page 29 of 29
PSoC Designer™ is a trademark and PSoC® and CapSense® are registered trademarks of Cypress Semiconductor Corporation.
Purchase of I2C components from Cypress or one of its sublicensed Associated Companies conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided
that the system conforms to the I2C Standard Specification as defined by Philips. As from October 1st, 2006 Philips Semiconductors has a new trade name - NXP Semiconductors.
All products and company names mentioned in this document may be the trademarks of their respective holders.
CY8CMBR2044
© Cypress Semiconductor Corporation, 2009-2013. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
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