Description
The AT43USB380 is a straightforward upgrade of the AT43USB370 Host/Function
Processor to suppor t the USB 2.0 On-The-Go (OTG) s pecification. It ca n operate
either as a single-chip Host/Function Processor or if used in conjunction with an exter-
nal Atmel Charge Pump, as a full OTG solution.
The AT43USB3 80 is functionall y equivalent to the AT4 3USB370 as a Host/F unction
Process or and can be used in pl ace of the AT43US B370 i n the existing AT43USB 370
design with minor hardware modifications. The pinout differences between the
AT43USB370 and the AT43USB380 are due to the inclusion of the on-chip OTG inter-
face in the AT43USB380.
To support OTG functionality, an exter nal Charge Pump has to be conn ected to th e
OTG interface of the AT43USB380, as shown in Figure 1 on page 7. The exter nal
Charge Pump serves i n the following two capacities:
1. As a power source to the downstream USB devices.
2. As a signaling interface during the OTG session negotiation upon connection.
From the hardware standpoint, the AT43USB380 is equivalent to the AT43USB370
with the following exceptions:
•On-chip OTG Interface. This hardware block is added to the AT43USB380 to
support the OTG functionality. Signals in the OTG interface include ID,
DISCHARGE, PUMP, CONTROL, EN, SESS_VLD, SESS_END, SESS_HIGH
and SESS _LOW. This interfa ce is used duri ng an OTG sess ion to deter mine the
roles o f the AT 43USB380 an d the con nected OTG-enabled USB devic e either as
a host or a function.
•8/16/32 Bit Generic Host Processor Interface. The AT43USB380 has a variable
width, generic host processor interface whereas the AT43USB370 supports only
32-bit host interface. The width of the host interface on the AT43USB380 is
determined by firmware configuration.
•Simplified System Interface. The GPIOs required in AT43USB370 for
hand shaking are no longer r equired in AT 43USB38 0. The system processo r can
write directly to the AT43USB380 registers thus eliminates the need for PROG,
SEL, READY, DONE, MORE, INTR_IN signals. The W A IT_N signal is not needed
either. It is only there for precaution for SYS_CLK synchronization.
•Up to 16 GPIO Pins. GPIO pins are multiplexed with the host processor interface.
When the interface to the host processor is 8 or 16 bits, up to 16 of the unused
pins i n the host proc essor interface can be used as GPIO pi ns. Hig h level APIs
are provided to access these GPIO pins.
From the standpoint of the firmware development environment, the AT43USB380
shares the same high level APIs and low level firmware libraries with the
AT43USB370. Additions to the AT43USB380 firmware suite include:
• High level APIs specific to the OTG support. The number of additional APIs is
less than 10.
• Low level OTG firmware embedded in the AT43USB380 hardware that support
Host Negotiation Protocol (HNP) and Session Request Protocol (SRP).
The AT43USB380 shar e the same debugging tools with the AT43USB370 as well.
During development, the AT43USB380 should be treated as a blac k box in terms of
On-The-Go
Upgrade of the
AT43USB370
USB 2.0
Full-Speed
Host/Function
Processor
AT43USB380
Upgrade Map
Summary
Note: This is a sum mary document. A complete document
is not available at this time. For more information, please
contact your local Atmel sales office.
3420AS–USB–03/04
2AT43USB380 Upgrade Map Summary 3420AS–USB–03/04
USB functionality. Communication with the AT43USB380 is achieved through a small
set (less than 25) of high level, ANSI C-compliant APIs. The actual USB protocol includ-
ing HNP and SRP is transparent to the host processor.
AT43USB380 OTG Processor Pin Description
Table 1 gives the description of the pins.
Table 1. Pin Description of the AT43USB380
Signal Name Dir. Polarity Width Description
System Interface
SYS_CLK I 1
Host system clock input for synchronization
of WAIT_N and D REQ_ N. (Synch roni zatio n
requirement can be enable/disable through
internal register settings)
A[7:0] I 8 System Address Bus
CS_N I LO 1 CHIP_SELECT signal from System (ARM®)
D[15:0] B 16 System Data Bus [15:0]
D[31:16]/
GPIO[15:0] B16
BWIDTH[1:0]=1x : Sys tem Data Bu s [3 1:16 ]
BWIDTH[1:0]=0x : GPIO[15:0]
DACK_N I LO 1 DMA Acknowledge from System (ARM)
DREQ_N O LO 1 DMA Request to System (ARM)
INTR_OUT O HI 1 Interrupt to System (ARM)
OE_N I LO 1 OUTPUT_ENABLE from System (ARM)
WAIT_N O LO 1 WAIT to System (ARM)
WE_N I LO 1 WRITE_ENABLE from System (ARM)
BWIDTH[1:0] I 2
System Data Bus Size:
00 : 8 Bit Interface D[7:0]
01 : 16 Bit Interfa ce D[15:0]
1x : 32 Bit Interface D[31:0]
WAKEUP_N I LO 1 Wakeup Request from System
USB Interface
DM B 1 USB Line (D-)
DP B 1 USB Line (D+)
ID I 1 OTG device type identification; used to
differentiate a Mini-A and Mini-B plug
RPU_EN O 1 Enable resistive pull-up to the D+ line
RPD_EN O 1 Enable resistive pull-down to the D+/D- lines
Char ge Pump Interface
CPClk O 1 Charge Pump clock output
EN O 1 Charge Pump; Enable for Charge Pump
PUMP_EN O 1 Charge Pump; Enable for C harge Pump
3
AT43USB380 Upgrade Map Summary
3420AS–USB–03/04
SESS_VLD I 1 Charge Pump; Active high when VBUS >
VSESS_VLD otherwise "0"
SESS_END I 1 Charge Pump; Active high when VBUS >
VSESS_END otherwise "0"
SESS_LOW I 1 Charge Pump; Active high when VBUS >
VSESS_LOW otherwise "0"
SESS_HIGH I 1 Charge Pump; Active high when VBUS >
VSESS_HIGH otherwise "0"
LOW_CUR O 1 Limits the current output of the Charge
Pump. Used during VBUS pulsing when
configur ed as B-device
DISCHARGE O 1 Charge Pump; Connect VBUS to ground
Oscillator, Clocks
XTAL1 I 1 Oscillator input
XTAL2 O 1 Oscillator output
LFT I 1 PLL loop filter
CLK_SEL I 1 Clock Source selection between crystal and
external oscillator
RESET_N I LO 1 RESET for USB Processor
Jtag Interface
TCK/SI I 1 TP3=0: JTAG Clock - from JTAG controller;
TP3=1: SI-EEPROM
TDI/SCK I 1 TP3=0: JTAG Serial Data IN - from JTAG
controller;
TP3=1: SCK-EEPROM
TDO/SO O 1 TP3=0: JTAG Serial Data OUT - from JTAG
controller;
TP3=1: SO-EEPROM
TMS/CS I 1 TP3=0: JTAG Mode Select - from JTAG
controller;
TP3=1: CS-EEPROM
TRST_N I LO 1 JTAG Reset - from JTAG controller
Test Pins
TP0 I 1 Test pin 0
TP1 I 1 Test Pin 1
TP2 I 1 Test pin 2
TP3 I 1 Test pin 3
TP4/SCAN_EN I 1 Test pin 4/SCAN_EN
TP_CLK
/D_CLK O 1 Clock test output/SIE DPLL extracted clock
TP_RCV_DATA
/RCV_DATA O 1 Extracted ser i al data test output
Table 1. Pin Description of the AT43USB380 (Continued)
Signal Name Dir. Polarity Width Description
4AT43USB380 Upgrade Map Summary 3420AS–USB–03/04
AT43USB380 OTG Processor Pin Assignment
Power/Ground Pins
VEXT18 O 3 1.8V regulated output
VDD I 5 3.3V input
VSS 10 Ground
Table 1. Pin Description of the AT43USB380 (Continued)
Signal Name Dir. Polarity Width Description
Pin # Signal Type
1 A7 Input
2 A6 Input
3 A5 Input
4 A4 Input
5 A3 Input
6 A2 Input
7 A1 Input
8 A0 Input
9 CS_N Input
10 OE_N Input
11 WE_N Input
12 INTR_OUT Output
13 VSS Power Supply/Ground
14 VDD18 Power Supply/Ground
15 VDD Power Supply/Ground
16 SYS_CLK Input
17 WAIT_N Output
18 DREQ_N Output
19 DACK_N Input
20 CPClk Output
21 DISCHARGE Output
22 EN Output
23 LOW_CUR Output
24 PUMP_EN Output
25 SESS_LOW Input
26 VSS Power Supply/Ground
27 SESS_VLD Input
28 SESS_HIGH Input
29 SESS_END Input
5
AT43USB380 Upgrade Map Summary
3420AS–USB–03/04
30 ID Input
31 TP0 Input
32 TP1 Input
33 CLK_SEL Input
34 VSS Power Supply/Ground
35 XTAL1 Input
36 XTAL2 Output
37 LFT Input
38 VDD18 Power Supply/Ground
39 VDD Power Supply/Ground
40 VSS Power Supply/Ground
41 DM Bi-directional
42 DP Bi-directional
43 TP2 Input
44 TP3 Input
45 RPD_EN Output
46 RPU_EN Output
47 RESET_N Input
48 TCK/SI Input
49 TMS/CS Input
50 VDD Power Supply/Ground
51 VSS Power Supply/Ground
52 TDI/SCK Input
53 TDO/SO Output
54 TRST_N Input
55 TP_CLK/D_CLK Output
56 TP_RCV_DATA/RCV_DATA Output
57 TP4/scan_en Input
58 BWIDTH[0] Input
59 WAKEUP_N Input
60 D31/GPIO[15] Bi-directional
61 D30/GPIO[14] Bi-directional
62 D29/GPIO[13] Bi-directional
63 D28/GPIO[12] Bi-directional
64 VSS Power Supply/Ground
65 VDD18 Power Supply/Ground
66 VDD Power Supply/Ground
Pin # Signal Type
6AT43USB380 Upgrade Map Summary 3420AS–USB–03/04
67 D27/GPIO[11] Bi-directional
68 D26/GPIO]10] Bi-directional
69 D25/GPIO[9] Bi-directional
70 D24/GPIO[8] Bi-directional
71 D23/GPIO[7] Bi-directional
72 D22/GPIO[6] Bi-directional
73 D21/GPIO[5] Bi-directional
74 D20/GPIO[4] Bi-directional
75 VDD Power Supply/Ground
76 VSS Power Supply/Ground
77 D19/GPIO[3] Bi-directional
78 D18/GPIO[2] Bi-directional
79 D17/GPIO[1] Bi-directional
80 D16/GPIO[0] Bi-directional
81 BWIDTH[1] Input
82 D15 Bi-directional
83 D14 Bi-directional
84 D13 Bi-directional
85 D12 Bi-directional
86 D11 Bi-directional
87 VDD Power Supply/Ground
88 VSS Power Supply/Ground
89 D10 Bi-directional
90 D9 Bi-directional
91 D8 Bi-directional
92 D7 Bi-directional
93 D6 Bi-directional
94 D5 Bi-directional
95 VSS Power Supply/Ground
96 D4 Bi-directional
97 D3 Bi-directional
98 D2 Bi-directional
99 D1 Bi-directional
100 D0 Bi-directional
Pin # Signal Type
7
AT43USB380 Upgrade Map Summary
3420AS–USB–03/04
USB-OTG Interface Connections for Host Mode
Figure 1. AT43USB380 USB and Charge Pump Connection for Host Mode
Mini-AB
Receptacle
DM
ID
DP
GND
B Receptacle
DM
VBUS
DP
GND
Charge Pump
AT43CD001
AT43USB380
(OTG Interface)
VBUS
DISCHARGE
PUMP_EN
LOW_CUR
EN
SESS_VLD
SESS_END
SESS_HIGH
SESS_LOW
CPCLK
SELECT
CEXT1
CEXT2
VSSAC
DM
DP
ID
VDDAC
C3
3.3V
10 kOhm
3.3V
100 kOhm
RPD_EN
VBUS
C1
3.3V
C2
15 kOhm 15 kOhm
DISCHARGE
PUMP_EN
LOW_CUR
EN
SESS_VLD
SESS_END
SESS_HIGH
SESS_LOW
CLK
Printed on recycled paper.
Disclaimer: Atme l Corporation makes no warranty for the use of its produc ts, other than those expressly contained in the Company’s standard
warranty which is detailed in Atmel’s Term s and Conditions located on the Com pany’s web site. The Company assumes no responsibility for any
errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and
does not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are
granted by the Com pany in connection with the sale of Atmel product s, expressly or by implication. Atmel’s products are not authorized for use
as critical components in life suppor t devices or systems.
Atmel Corporation Atmel Operations
2325 Orchard Parkway
San Jose, CA 95131, USA
Tel: 1(408) 441-0311
Fax: 1(408) 487-2600
Regional Headquar ters
Europe
Atmel Sarl
Route des Arsenaux 41
Case Postale 80
CH-1705 Fribourg
Switzerland
Tel: (41) 26-426-5555
Fax: (41) 26-426-5500
Asia
Room 1219
Chin ache m G old en Pla za
77 Mody Road Tsimshatsui
East Kowloon
Hong Kong
Tel: (852) 2721-9778
Fax: (852) 2722-1369
Japan
9F, Tonetsu Shinkawa Bldg.
1-24 -8 Shin kawa
Chuo-ku, Tokyo 104-0033
Japan
Tel: (81) 3-3523-3551
Fax: (81) 3-3523-7581
Memory
2325 Orchard Parkway
San Jose, CA 95131, USA
Tel: 1(408) 441-0311
Fax: 1(408) 436-4314
Microcontrollers
2325 Orchard Parkway
San Jose, CA 95131, USA
Tel: 1(408) 441-0311
Fax: 1(408) 436-4314
La Chantrerie
BP 70602
44306 Nantes Cedex 3, France
Tel : (33) 2 -40-1 8-18 -18
Fax: ( 33) 2- 40-1 8-19-6 0
ASIC/ASSP/Smart Cards
Zone Industrielle
13106 Rousset Cedex, France
Tel : (33) 4 -42-5 3-60 -00
Fax: ( 33) 4- 42-5 3-60-0 1
1150 East Cheyenne Mtn. Blvd.
Colorado Springs, CO 80906, USA
Tel: 1(719) 576-3300
Fax: 1(719) 540-1759
Scottish Enterprise Technology Park
Maxwell Building
East Kilbride G75 0QR, Scotland
Tel: (44) 1355-803-000
Fax: (44) 1355-242-743
RF/Automotive
Theresienstrasse 2
Postfach 3535
74025 Heilbr onn, Ge rmany
Tel: (49) 71-31-67-0
Fax: (49) 71-31-67-2340
1150 East Cheyenne Mtn. Blvd.
Colorado Springs, CO 80906, USA
Tel: 1(719) 576-3300
Fax: 1(719) 540-1759
Biometrics/Imaging/Hi-Rel MPU/
High Speed Converters/RF Datacom
Avenue de Rochepleine
BP 123
38521 Saint-Egreve Cedex, France
Tel: (33) 4-76-58-30-00
Fax: ( 33) 4- 76-5 8-34-8 0
Literature Requests
www.atmel.com/literature
3420AS–USB–03/04
© Atmel Corporation 2003. All rights reserved. Atmel® and combinations thereof, are the registered trademarks of Atmel Corporation or its
subsidiaries. ARM® is the registered t rademark of ARM Limited. Other ter ms an d product names may be the trademar ks of others.
