Document :1G5-0183 Rev.1 Page 1
VIS
VG36128401BT / VG36128801BT / VG36128161BT
CMOS Synchronous Dynamic RAM
Description
The VG36128401B, VG36128801B and VG3664128161B are high-speed 134,217,728-bit synchro-
nous dynamic random-access memories, organized as 8,388,608 x 4 x 4, 4,194,304 x 8 x 4 and 2,097,152 x
16 x 4 (word x bit x bank), respectively.
The synchronous DRAMs achieved high-speed data transfer using the pipeline architecture. All input
and outputs are synchronized with the positive edge of the clock.The synchronous DRAMs are compatible
with Low Voltage TTL (LVTTL).These products are packaged in 54-pin TSOPII.
Features
• Single 3.3V () power supply
• High speed clock cycle time -7H: 133MHz<2-2-2>, -7L: 133MHz<3-3-3>, -8H: 100MHz<2-2-2>
• Fully synchronous operation referenced to clock rising edge
• Possible to assert random column access in every cycle
• Quad internal banks controlled by BA0 & BA1 (Bank Select)
• Byte control by LDQM and UDQM for VG36128161DT
• Programmable Wrap sequence (Sequential / Interleave)
• Programmable burst length (1, 2, 4, 8 and full page)
• Programmable /CAS latency (2 and 3)
• Automatic precharge and controlled precharge
• CBR (Auto) refresh and self refresh
• X4, X8, X16 organization
• LVTTL compatible inputs and outputs
• 4,096 refresh cycles / 64ms
.
0.3V
±
Document :1G5-0183 Rev.1 Page 2
VIS
VG36128401BT / VG36128801BT / VG36128161BT
CMOS Synchronous Dynamic RAM
Pin Configurations
VDD
DQ0
VDDQ
V
SSQ
V
DDQ
/CAS
/RAS
WE
A10
BA0(A13)
A1
A2
A3
VDD
VSS
VSSQ
VDDQ
DQ11
VSS
DQ9
VDDQ
NC
CLK
UDQM
CKE
NC
VSS
A9
A8
A7
A6
A5
A11
DQ3
V
SSQ
V
DD
LDQM
/CS
BA1(A12)
A0
A4
VSSQ
DQ13
DQ15
VG36128161 (x16)
VDD
DQ0
VDDQ
V
SSQ
DQ2
V
DDQ
NC
/CAS
/RAS
WE
A10
A1
A2
A3
VDD
NC
DQ1
NC
DQ3
V
SSQ
NC
V
DD
NC
/CS
BA1(A12)
A0
VSS
VSSQ
VDDQ
DQ5
VSS
DQ4
VDDQ
CLK
DQM
CKE
NC
VSS
A9
A8
A7
A6
A5
A11
NC
A4
NC
NC
NC
VSSQ
DQ6
DQ7
NC
DQ14
DQ12
DQ10
DQ8
DQ4
DQ5
DQ6
DQ7
BA0(A13)
VG36128801 (x8)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
16
17
18
19
20
21
22
44
43
42
23
24
25
26
27 29
28
31
30
36
35
34
33
32
38
37
39
40
41
46
45
47
48
49
50
51
52
53
54
15
VG36128401 (x4)
VDD
NC
VDDQ
V
SSQ
NC
V
DDQ
NC
/CAS
/RAS
/WE
A10
A1
A2
A3
VDD
NC
DQ0
NC
DQ1
V
SSQ
NC
V
DD
NC
/CS
BA1(A12)
A0
BA0(A13)
VSS
VSSQ
VDDQ
NC
VSS
DQ2
VDDQ
CLK
DQM
CKE
NC
VSS
A9
A8
A7
A6
A5
A11
NC
A4
NC
NC
NC
VSSQ
DQ3
NC
NC
DQ2
DQ1
Pin Descriptions
Pin Name Function Pin Name Function
CLK Master Clock DQM DQ Mask Enable
CKE Clock Enable A0-11 Address Input
/CS Chip Select BA0,1 Bank Address
/RAS Row Address Strobe VDD Power Supply
/CAS Column Address Strobe VDDQ Power Supply for DQ
/WE Write Enable VSS Ground
DQ0 ~ DQ15 Data I/O VSSQ Ground for DQ
Document :1G5-0183 Rev.1 Page 3
VIS
VG36128401BT / VG36128801BT / VG36128161BT
CMOS Synchronous Dynamic RAM
Block Diagram
CLK
CKE Clock
Generator
CS
RAS
Mode
Register
Column
Address
Buffer
&
Burst
Counter
CAS
WE
Command Decoder
Control Logic
Address Row
Address
Buffer
&
Refresh
Counter
Bank B
Bank A
Sense Amplifier
Column Decoder &
Latch Circuit
Row Decoder
Data Control Circuit DQ
DQM
Latch Circuit
Input & Output
Buffer
Bank C
Bank D
Document :1G5-0183 Rev.1 Page 4
VIS
VG36128401BT / VG36128801BT / VG36128161BT
CMOS Synchronous Dynamic RAM
Pin Function
Symbol Input Function
CLK Input Maste Clock: Other inputs signals are referenecd to the CLK rising edge.
CKE Input Clock Enable: CKE HIGH activates, and CKE LOW deactivates internal clock signals,
device input buffers and output drivers. Deactivating the clock provides PRECHARGE
POWER-DOWN and SELF REFRESH operation (all banks idle), or ACTIVE POWER-
DOWN (row ACTIVE in any bank).
/CS Input Chip Select: /CS enables (registered LOW) and disables (registered HIGH) the com-
mand decoder. All commands are masked when /CS is registered HIGH. /CS provides
for external bank selection on systems with multiple banks. /CS is considered part of
the command code.
/RAS, /CAS,
/WE Input Command Inputs: /RAS, /CAS and /WE (along with /CS) define the command being
entered.
A0 - A13 Input Address Inputs: Provide the row address for ACTIVE commands, and the column
address and AUTO PRECHARGE bit for READ/WRITE commands, to select one loca-
tion out of the memory array in the respective bank.
The row address is specified by A0-A11.
The column address is specified by A0-A9, A11 (X4) / A0-A9 (X8) / A0-A8 (X16)
BA0,BA1 Input Bank Address Inputs: BA0 and BA1 define to which bank an ACTIVE, READ, WRITE or
PRECHARGE command is being applied.
DQM, UDQM ,
LDQM Input Din Mask / Output Disable: When DQM is high in burst write, Din for the current cycle is
masked. When DQM is is high in burst read, Dout is disable at the next but one cycle.
DQ0 - DQ15 I/O Data Input / Output: Data bus.
VDD, VSS Supply Power Supply for the memory array and peripheral circuitry.
VDDQ, VSSQ Supply Power Supply are supplied to the output buffers only.
Document :1G5-0183 Rev.1 Page 5
VIS
VG36128401BT / VG36128801BT / VG36128161BT
CMOS Synchronous Dynamic RAM
Absolute Maximum Ratings
Caution Exposing the device to stress above those listed in Absolute Maximum Ratings could cause permanent damage. The
device is not meant to be operated under conditions outside the limits described in the operational section of this
specification. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability.
Parameter Symbol Conditions Value Unit
Supply Voltage VDD with respect to VSS -0.5 to 4.6 V
Supply Voltage for Output VDDQ with respect to VSSQ -0.5 to 4.6 V
Input Voltage VI with respect to VSS -0.5 to 4.6 V
Output Voltage VO with respect to VSSQ -0.5 to 4.6 V
Short circuit output current IO50 mA
Power dissipation PD Ta = 25 °C 1W
Operating temperature TOPT 0 to 70 °C
Storage temperature TSTG -65 to 150 °C
Recommended Operating Conditions (Ta = 0 ~ 70 °C, unless otherwise noted)
Parameter Symbol Limits Unit
Min. Typ. Max.
Supply Voltage VDD 3.0 3.3 3.6 V
Supply Voltage for DQ VDDQ 3.0 3.3 3.6 V
Ground VSS 000V
Ground for DQ VSSQ 000V
High Level Input Voltage (all inputs) VIH 2.0 VDDQ + 0.3 V
Low Level Input Voltage (all inputs) VIL -0.3 0.8 V
Pin Capacitance (Ta = 0 ~ 70°C, VDD = VDDQ = 3.30.3V , VSS = VSSQ = 0V, unless otherwise noted)
Parameter Symbol Limits (Min) Limits (Max) Unit
-7H -7L/-8H
Input Capacitance, address & control pin CIN 2.5 3.8 5.0 pF
Input Capacitance, CLK pin CCLK 2.5 3.5 4.0 pF
Data input / output capacitance CI/O 4.0 6.5 6.5 pF
±
Document :1G5-0183 Rev.1 Page 6
VIS
VG36128401BT / VG36128801BT / VG36128161BT
CMOS Synchronous Dynamic RAM
DC Characteristics 1
(Ta = 0 ~ 70°C, VDD = VDDQ = 3.30.3V, VSS = VSSQ = 0V, Ouput Open, unless otherwise noted)
NOTES
1. ICC(max) is specified at the output open condition.
2. Input signals are changed one time during 30ns.
3. Normal version: VG36128401BT-7H / VG36128801BT-7L / VG36128161BT-8H
4. Low power version: VG36128401BTL-7H / VG3636128401BTL-7L / VG3636128401BTL-8H
Parameter Symbol Test Conditions Organization Limits (max.) Unit Notes
-7H -7L -8H
Operating current ICC1 One bank active
tRC = tRC(MIN), tCLK = tCLK(MIN),
BL = 1, CL=3
x4 100 95 95 mA 1x8 110 100 100
x16 130 120 120
Precharge standby current
in power down mode ICC2P CKE VIL(MAX), tCK = 15ns x4/x8/x16 2 2 2 mA
ICC2PS CKE VIL(MAX), CLK VIL(MAX) x4/x8/x16 1 1 1
Precharge standby current
in non power down mode ICC2N CS VCC - 0.2V
tCK = 15ns, CKE VIH(MIN)
x4/x8/x16 25 25 25 mA 2
ICC2NS CS VCC - 0.2V
CLK VIL(MAX), CKEVIH(MIN)
All input signals are stable. x4/x8/x16 15 15 15 mA
Active standby current in
Nonpower down mode ICC3N CS VCC - 0.2V
tCK = 15ns, CKE VIH(MIN) x4/x8/x16 30 30 30 mA 2
ICC3NS CS VCC - 0.2V
CLK VIL(MAX), CKEVIH(MIN)
All input signals are stable. x4/x8/x16 20 20 20 mA
Operating current
(Burst mode) ICC4 All banks active
tCK = tCK(MIN), BL=4, CL=3
All banks active
x4 140 110 110 mAx8 150 120 120
x16 160 130 130
Refresh current ICC5 tRC = tRC(MIN), tCLK = tCLK(MIN)x4/x8/x16 160 160 160 mA
Self refresh current ICC6 CKE 0.2V x4/x8/x16 2 2 2 mA 3
0.8 0.8 0.8 mA 4
±
≤
≤
≤
CKEV
≥
CKEV
≥
CKEV
≥
≤
CKEV
≥
CKEV
≥
CKEV
≥
CKEV
≥
≤
CKEV
≥
≤
DC Characteristics 2
(Ta = 0 ~ 70°C, VDD = VDDQ = 3.30.3V , VSS = VSSQ = 0V, unless otherwise noted)
Parameter Symbol Test Condition Min Max Unit
Input leakage current (Inputs) II (L) 0 VIN VDD(MAX)
Pins not under test = 0V -10 10 uA
Output leakage current (I/O pins) IO (L) 0 VOUT VDD(MAX)
DQ# in H - Z., DOUT is disabled -10 10 uA
High level output voltage VOH (DC) IOH = -2mA 2.4 V
Low level output voltage VOL (DC) IOL = 2mA 0.4 V
±
≤
≤
≤
≤
Document :1G5-0183 Rev.1 Page 7
VIS
VG36128401BT / VG36128801BT / VG36128161BT
CMOS Synchronous Dynamic RAM
AC Characteristics (Ta = 0 ~ 70°C, VDD = VDDQ = 3.30.3V , VSS = VSSQ = 0V, unless otherwise noted)
Test Conditions
Output Load Conditions
AC input Levels (VIH/VIL)2.0 / 0.8V Input timing reference level /
Output timing reference level 1.4V
Input rise and fall time 1ns Output load condition 50pF
±
Ω
V
DDQ
V
DDQ
V
OUT
Device
Under
Test
50PF
Z = 50
Document :1G5-0183 Rev.1 Page 8
VIS
VG36128401BT / VG36128801BT / VG36128161BT
CMOS Synchronous Dynamic RAM
A.C. Characteristics (Ta = 0 ~ 70°C, VDD = VDDQ = 3.30.3V , VSS = VSSQ = 0V, unless otherwise noted)
Parameter Symbol
Limits
Unit-7H -7L -8H
Min Max Min Max Min Max
CLK cycle time CL = 3 tCK3 7.5 7.5 10 ns
CL = 2 tCK2 7.5 10 8 ns
CLK to valid output delay CL = 3 tAC3 5.4 5.4 6ns
CL = 2 tAC2 5.4 66ns
CLK high pulse width tCH 2.5 2.5 3ns
CLK low pulse width tCL 2.5 2.5 3ns
Input setup time (all input) tIS 1.5 1.5 2ns
Input hold time (all input) tIH 0.8 0.8 1ns
Output data hold time CL = 3 tOH3 2.7 2.7 3ns
CL = 2 tOH2 2.7 3 3 ns
CLK to output in low - Z tLZ 0 0 0 ns
CLK to output in H - Z tHZ 2.7 5.4 2.7 5.4 3 6 ns
ROW cycle time tRC 67.5 67.5 70 ns
ROW active time tRAS 45 100K 45 100K 50 100K ns
RAS to CAS delay tRCD 15 20 20 ns
Row precharge time tRP 15 20 20 ns
Row active to active delay tRRD 14 15 20 ns
Write recovery time tWR 14 15 20 ns
Transition time tT110 110 1 10 ns
Mode reg. set cycle tRSC 14 15 20 ns
Power down exit setup time tPDE 77.5 10 ns
Self refresh exit time tSRX 77.5 10 ns
Refresh time tREF 64 64 64 ms
±
Document :1G5-0183 Rev.1 Page 9
VIS
VG36128401BT / VG36128801BT / VG36128161BT
CMOS Synchronous Dynamic RAM
Basic Features and Function Description
1. Simplified State Diagram
Self
Refresh
MRS
Mode
Register
Set IDLE
AUTO
Refresh
REF
ACT
CKE
CKE
BST
Power
Down
Active
Power
Down
ROW
ACTIVE
Read
CKE
CKE
READ READ
SUSPEND
CKE
CKE
READ A READA
SUSPEND
Read with
Auto Precharge
CKE
CKE
Write (Write recovery)
WRITE
WRITE
SUSPEND
WRITE A
WRITE A
SUSPEND CKE
CKE
Write with
Auto Precharge
POWER
ON Precharge Precharge
PRE (Precharge termination)
PRE (Precharge termination)
Read with
Write with
Auto predharge
Auto Precharge
Read
BST
Write
Read with
Auto Precharge (write recovery)
Write with
Auto Precharge
Write
Read (write recovery)
PRE
CKE
CKE
Automatic sequence
Manual input
Note: After the AUTO refresh operation, precharge operation is
performed automatically and enter the IDLE state
SELF entry
SELF exit
Write recovery
Document :1G5-0183 Rev.1 Page 10
VIS
VG36128401BT / VG36128801BT / VG36128161BT
CMOS Synchronous Dynamic RAM
2. Truth Table
2.1 Command Truth Table
2.2 DQM Truth Table
2.3 CKE Truth Table
H : High level, L : Low level
X : High or Low level (Don’t care), V : Valid Data input
FUNCTION Symbol CKE CS RAS CAS WE BA A10 A11
A9 - A0n - 1 n
Device deselect DESL HXHX X X X X X
No operation NOP HXLH H H X X X
Mode register set MRS HXL L L L L L V
Bank activate ACT HXLLH H V V V
Read READ HXLHLHVLV
Read with auto precharge READA HXLHLHVHV
Write WRIT HXLHL L VLV
Write with auto precharge WRITA HXLHL L VHV
Precharge select bank PRE HXLLHLVLX
Precharge all banks PALL HXLLHLXHX
Burst stop BST HXLH H LX X X
CBR (Auto) refresh REF H H L L L HX X X
Self refresh SELF HL L L L HX X X
FUNCTION Symbol CKE DQM
n - 1 n - 1
Data write/output enable ENB HXL
Data mask/output disable MASK HXH
Current State Function Symbol CKE CS RAS CAS WE Add -
ressn - 1 n
Activating Clock suspend mode entry HLX X X X X
Any Clock suspend L L X X X X X
Clock suspend Clock suspend mode exit LHX X X X X
Idle CBR refresh command REF H H L L L HX
Idle Self refresh entry SELF HL L L L HX
Self refresh Self refresh exit LHLH H H X
LH H X X X X
Idle Power down entry HLX X X X X
Power down Power down exit LHX X X X X
Document :1G5-0183 Rev.1 Page 11
VIS
VG36128401BT / VG36128801BT / VG36128161BT
CMOS Synchronous Dynamic RAM
2.4 Operative Command Table (note 1)
HCurrent state CS RAS CAS WE Address Command Action Notes
Idle HX X X X DESL Nop or Power down 2
LH H X X NOP or BST Nop or Power down 2
LHLHBA, CA, A10 READ/READA ILLEGAL 3
LHL L BA, CA, A10 WRIT/WRITA ILLEGAL 3
L L H H BR, RA ACT Row active
L L HLBA, A10 PRE/PALL Nop
L L L HXREF/SELF Refresh or Self refresh 4
L L L L Op-Code MPS Mode register access
Row active HX X X X DESL Nop
LH H X X NOP or BST Nop
LHLHBA, CA, A10 READ/READA Begin read : Determine AP 5
LHL L BA, CA, A10 WRIT/WRITA Begin write : Determine AP 5
L L H H BA, RA ACT ILLEGAL 3
L L HLBA, A10 PRE/PALL Precharge 6
L L L HXREF/SELF ILLEGAL
L L L L Op-Code MRS ILLEGAL
Read HX X X X DESL Continue burst to end Row active
LH H H XNOP Continue burst to end Row active
LH H LXBST Burst stop Row active
LHLHBA, CA, A10 READ/READA Term burst, new read : Determine AP 7
LHL L BA, CA, A10 WRIT/WRITA Term burst, start write : Determine AP 7,8
L L H H BA, RA ACT ILLEGAL 3
L L HLBA, A10 PRE/PALL Term burst, precharging
L L L HXREF/SELF ILLEGAL
L L L L Op-Code MRS ILLEGAL
Write HX X X X DESL Continue burst to end write recovering
LH H H XNOP Continue burst to end write recovering
LH H LXBST Burst stop Row active
LHLHBA, CA, A10 READ/READA Term burst, start read : Determine AP 7,8
LHL L BA, CA, A10 WRIT/WRITA Term burst, new write : Determine AP 7
L L H H BA, RA ACT ILLEGAL 3
L L HLBA, A10 PRE/PALL Term burst, precharging 9
L L L HXREF/SELF ILLEGAL
L L L L Op-Code MRS ILLEGAL
→
→
→
→
→
→
(1/3)
Document :1G5-0183 Rev.1 Page 12
VIS
VG36128401BT / VG36128801BT / VG36128161BT
CMOS Synchronous Dynamic RAM
(2/3)
Current state CS RAS CA WE Address Command Action Notes
Read with auto
precharge HX X X X DESL Continue burst to end Precharging
LH H H XNOP Continue burst to end Precharging
LH H LXBST ILLEGAL
LHLHBA, CA, A10 READ/READA ILLEGAL 11
LHL L BA, CA, A10 WRIT/WRITA ILLEGAL 11
L L H H BA, RA ACT ILLEGAL 3,11
L L HLBA, A10 PRE/PALL ILLEGAL 3,11
L L L HXPEF/SELF ILLEGAL
L L L L Op - Code MRS ILLEGAL
Write with auto
precharge HX X X X DESL Continue burst to end write
recovering with auto precharte
LH H H XNOP Continue burst to end write
recovering with auto precharge
LH H LXBST ILLEGAL
LHLHBA, CA, A10 READ/READA ILLEGAL 11
LHL L BA, CA, A10 WRIT/WRITA ILLEGAL 11
L L H H BA, RA ACT ILLEGAL 3,11
L L HLBA, A10 PRE/PALL ILLEGAL 3,11
L L L HXREF/SELF ILLEGAL
L L L L Op - code MRS ILLEGAL
Precharging HX X X X DESL Nop Enter idle after tRP
LH H H XNOP Nop Enter idle after tRP
LH H LXBST Nop Enter idle after tRP
LHLHBA, CA, A10 READ/READA ILLEGAL 3
LHL L BA, CA, A10 WRIT/WRITA ILLEGAL 3
L L H H BA, RA ACT ILLEGAL 3
L L HLBA, A10 PRE/PALL Nop Enter idle after tRP
L L L HXREF/SELF ILLEGAL
L L L L Op - Code MRS ILLEGAL
Row activating HX X X X DESL Nop Enter row active after tRCD
LH H H XNOP Nop Enter row active after tRCD
LH H LXBST Nop Enter row active after tRCD
LHLHBA, CA, A10 READ/READA ILLEGAL 3
LHL L BA, CA, A10 WRIT/WRITA ILLEGAL 3
L L H H BA, RA ACT ILLEGAL 3, 9
L L HLBA, A10 PRE/PALL ILLEGAL 3
L L L HXREF/SELF ILLEGAL
L L L L Op - Code MRS ILLEGAL
→
→
→
→
→
→
→
→
→
→
→
Document :1G5-0183 Rev.1 Page 13
VIS
VG36128401BT / VG36128801BT / VG36128161BT
CMOS Synchronous Dynamic RAM
(3/3)
Current CS RAS CAS WE Address Command Action Notes
Write
recovering HX X X X DESL Nop Enter row active after tDPL
LH H H XNOP Nop Enter row active after tDPL
LH H LXBST Nop Enter row active after tDPL
LHLHBA, CA, A10 READ/READA Start read, Determine AP 8
LHL L BA, CA, A10 WRIT/WRITA New write, Determine AP
L L H H BA, RA ACT ILLEGAL 3
L L HLBA, A10 PRE/PALL ILLEGAL 3
LLLHXPEF/SELF ILLEGAL
L L L L Op - Code MRS ILLEGAL
Write
recovering
with auto
precharge
HX X X X DESL Nop Enter precharge after tDPL
LH H H XNOP Nop Enter precharge after tDPL
LH H LXBST Nop Enter precharge after tDPL
LHLHBA, CA, A10 READ/READA ILLEGAL 3,8,11
LHL L BA, CA, A10 WRIT/WRITA ILLEGAL 3,11
L L H H BA, RA ACT ILLEGAL 3,11
L L HLBA, A10 PRE/PALL ILLEGAL 3
LLLHXREF/SELF ILLEGAL
L L L L Op - Code MRS ILLEGAL
Auto
Refreshing
HX X X X DESL Nop Enter idle after tRC
LH H X X NOP/BST Nop Enter idle after tRC
LHLX X READ/WRIT ILLEGAL
L L HX X ACT/PRE/PALL ILLEGAL
LLLX X REF/SELF/MRS ILLEGAL
Mode regis-
ter
setting
HX X X X DESL Nop Enter idle after 2 Clocks
LH H H XNOP Nop Enter idle after 2 Clocks
LH H LXBST ILLEGAL
LHLX X READ/WRITE ILLEGAL
L L X X X ACT/PRE/PALL/
REF/SELF/MRS ILLEGAL
→
→
→
→
→
→
→
→
Note
1. All entries assume that CKE was active (High level) during the preceding clock cycle.
2. If both banks are idle, and CKE is inactive (Low level), the device will enter Power downmode.
All input buffers except CKE will be disabled.
3. Illegal to bank in specified states; Function may be legal in the bank indicated by BankAddress(BA), depending on the
state of that bank.
4. If both banks are idle, and CKE is inactive (Low level), the device will enter Self refresh mode.
All input buffers except CKE will be disabled.
5. Illegal if tRCD is not satisfied.
6. Illegal if tRAS is not satisfied.
7. Must satisfy burst interrupt condition.
8. Must satisfy bus contention, bus turn around, and/or write recovery requirements.
9. Must mask preceding data which don’t satisfy tDPL.
10. Illegal if tRRD is not satisfied.
11. Illegal for single bank, but legal for other banks in multi-bank devices.
Document :1G5-0183 Rev.1 Page 14
VIS
VG36128401BT / VG36128801BT / VG36128161BT
CMOS Synchronous Dynamic RAM
2.5 Command Truth Table for CKE (Note 1)
Note:
Current state CKE
n - 1 CKE
nCS RAS CAS WE Address Action Notes
Self refresh
(S.R.) HX X X X X X INVALID, CLK (n - 1)would exit S.R.
LH H X X X X S.R. Recovery 2
LHLH H X X S.R. Recovery 2
LHLHLX X ILLEGAL
LHL L XX XILLEGAL
L L X X X X X Maintain S.R.
Self refresh
recovery H H H X X X X Idle after tRC
H H LH H X X Idle after tRC
H H LHLX X ILLEGAL
H H L L XX XILLEGAL
HLHX X X X Begin clock suspend next cycle 5
HL L H H X X Begin clock suspend next cycle 5
HL L HLX X ILLEGAL
HLLL XX XILLEGAL
LHX X X X X Exit clock suspend next cycle 2
L L X X X X X Maintain clock suspend
Power down
(P.D.) HX X X X X INVALID, CLK (n - 1) would exit P.D.
LHX X X X X EXIT P.D. Idle 2
L L X X X X X Maintain power down mode
Both banks
idle H H H X X X Refer to operations in Operative
Command Table
H H LHX X Refer to operations in Operative
Command Table
H H L L HXRefer to operation in Operative
Command Table
H H L L L HXAuto Refresh
H H L L L L Op - Code Refer to operations in Operative
Command Table
HLHX X X Refer to operations in Operative
Command Table
HL L HX X Refer to operations in Operative
Command Table
HLLL HXRefer to operations in Operative
Command Table
HL L L L HXSelf refresh 3
HL L L L L Op - Code Refer to operations in Operative
Command Table
LX X X X X X Power down 3
Any state
other than
listed above
H H X X X X X Refer to operations in Operative
Command Table
HLX X X X X Begin clock suspend next cycle 4
LHX X X X X Exit clock suspend next cycle
L L X X X X X Maintain clock suspend
→
1. H : Hight level, L : low level, X : High or low level (Don't care).
2. CKE Low to High transition will re-enable CLK and other inputs asynchronously. A minimum setup
time must be satisfied before any command other than EXIT.
3. Power down and Self refresh can be entered only from the both banks idle state.
4. Must be legal command as defined in Operative Command Table.
5. Illegal if tSREX is not satisfied.
Document :1G5-0183 Rev.1 Page 15
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VG36128401BT / VG36128801BT / VG36128161BT
CMOS Synchronous Dynamic RAM
3. Initiallization
Before starting normal operation, the following power on sequence is necessary to prevent SDRAM from damged or
malfunctioning.
1. Apply power and start clock. Attempt to maintain CKE high , DQN high and NOP condition at the inputs.
2. Maintain stable power, table clock , and NOP input conditions for a minimum of 200us.
3. Issue precharge commands for all bank. (PRE or PREA)
4. After all banks become idle state (after tRP), issue 8 or more auto-refresh commands.
5. Issue a mode register set command to initialize the mode regiser.
After these sequence, the SDRAM is in idle state and ready for normal operation.
4. Programming the Mode Register
The mode register is programmed by the mode register set command using address bits A13 through A0 as data
inputs. The register retains data until it is reprogrammed or the device loses power.
The mode register has four fields;
Options : A13 through A7
CAS latency : A6 through A4
Wrap type : A3
Burst length : A2 through A0
Following mode register programming, no command can be asserted befor at least two clock cycles have elapsed.
CAS Latency
CAS latency is the most critical parameter being set. It tells the device how many clocks must elapse before the data
will be available.
The value is determined by the frequency of the clock and the speed grade of the device. The value can be pro-
grammed as 2 or 3.
Burst Length
Burst Length is the number of words that will be output or input in read or write cycle. After a read burst is completed,
the output bus will become high impedance.
The burst length is programmable as 1, 2, 4, 8 or full page.
Wrap Type (Burst Sequence)
The wrap type specifies the order in which the burst data will be addressed. The order is programmable as either
“Sequential” or “Interleave”. The method chosen will depend on the type of CPU in the system.
Document :1G5-0183 Rev.1 Page 16
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VG36128401BT / VG36128801BT / VG36128161BT
CMOS Synchronous Dynamic RAM
5. Mode Register
0 0 000
11 10 987 6 543210
LTMODE WT BL
Burst length
Bits2 - 0 WT = 1
WT = 0
000
001
010
011
100
101
110
111
1
2
4
8
R
R
R
Fullpage
1
2
4
8
R
R
R
R
Wrap type 0
1Sequential
Interleave
Latency
Bits 6-4 CAS Iatency
000
001
010
011
100
101
110
111
R
R
2
3
R
R
R
R
mode
Remark R : Reserved
13 12
0
0
Document :1G5-0183 Rev.1 Page 17
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CMOS Synchronous Dynamic RAM
6. Burst Length and Sequence
(Burst of Two)
(Burst of Four)
(Burst of Eight)
Full page burst is an extension of the above tables of sequential addressing, with the length being 2,048
(for 32Mx4), 1,024 (for 16M x 8) and 512 (for 8Mx16).
Starting Address
(column address A0, binary) Sequential Addressing
Sequence (decimal) Interleave Addressing Sequence
(decimal)
00, 1 0, 1
11, 0 1, 0
Starting Address
(column address A1 - A0, binary) Sequential Addressing
Sequence (decimal) Interleave Addressing Sequence (decimal)
00 0, 1, 2, 3 0, 1, 2, 3
01 1, 2, 3, 0 1, 0, 3, 2
10 2, 3, 0, 1 2, 3, 0, 1
11 3, 0, 1, 2 3, 2, 1, 0
Starting Address
(column address A2 - A0, binary) Sequential Addressing
Sequence (decimal) Interleave Addressing Sequence
(decimal)
000 0, 1, 2, 3, 4, 5, 6, 7 0, 1, 2, 3, 4, 5, 6, 7
001 1, 2, 3, 4, 5, 6, 7, 0 1, 0, 3, 2, 5, 4, 7, 6
010 2, 3, 4, 5, 6, 7, 0, 1 2, 3, 0, 1, 6, 7, 4, 5
011 3, 4, 5, 6, 7, 0, 1 ,2 3, 2, 1, 0, 7, 6, 5, 4
100 4, 5, 6, 7, 0, 1, 2, 3 4, 5, 6, 7, 0, 1, 2, 3
101 5, 6 ,7, 0, 1, 2, 3, 4 5, 4, 7, 6, 1, 0, 3, 2
110 6, 7 ,0 ,1 ,2 ,3 ,4 ,5 6, 7, 4, 5, 2, 3, 0, 1
111 7, 0, 1, 2, 3, 4, 5, 6 7, 6, 5, 4, 3, 2, 1, 0
Document :1G5-0183 Rev.1 Page 18
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VG36128401BT / VG36128801BT / VG36128161BT
CMOS Synchronous Dynamic RAM
7. Precharge
The precharge command can be asserted anytime after tRAS(min.) is satisfied.
Soon after the precharge command is asserted, the precharge operation is performed and the synchronous DRAM enters the
idle state after tRP(min.) is satisfied. The parameter tRP is the time required to perform the precharge.
The earliest timing in a read cycle that a precharge command can be asserted without losing any data in the burst is as follows.
PrechargeE
In order to write all data to the memory cell correctly, the asynchronous parameter ”tDPL” must be satisfied. The
tDPL(min.) specification defines the earliest time that a precharge command can be asserted. The minimum number of
clocks can be calculated by dividing tDPL(min.) with the clock cycle time.
In summary, the precharge command can be asserted relative to the reference clock that indicates the last data word is
valid. In the following table, minus means clocks before the reference; plus means time after the reference.
CAS latency Read Write
2-1 + tDPL(min.)
3-2 + tDPL(min.)
Burst lengh=4
CLK
Command
CAS latency = 2
DQ
Command
CAS latency = 3
DQ
(tRAS is satisfied)
Hi - Z
Q0 Q3
Q2
Q1
PRE
Q0 Q3Q2
Q1
Read
Read
T0 T1 T2 T3 T4 T5 T6 T7
PRE
Hi - Z
Document :1G5-0183 Rev.1 Page 19
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CMOS Synchronous Dynamic RAM
8. Auto Precharge
During a read or write command cycle, A10 controls whether auto precharge is selected. If A10 is high in the read or write
command (Read with Auto precharge command or Write with Auto precharge command), auto precharge is selected and
begins automatically.
In the write cycle, tDAL(min.) must be satisfied before asserting the next activate command to the bank being precharged.
When using auto precharge in the read cycle, knowing when the precharge starts is important because the next activate
command to the bank being precharged cannot be executed until the precharge cycle ends. Once auto precharge has
started, an activate command to the bank can be asserted after tRP has been satisfied.
A Read or Write command without auto - precharge can be terminated in the midst of a burst operation. However, a Read
or Write command with auto - precharge can not be interrupted by the same bank commands before the entire burst opera-
tion is completed. Therefore use of the same bank Read, Write, Precharge or Burst Stop command is prohibited during a
read or write cycle with auto - precharge. It should be noted that the device will not respond to the Auto - Precharge com-
mand if the device is programmed for full page burst read or write cycles.
The timing when the auto precharge cycle begins depends both on both the CAS Iatency programmed into the mode reg-
ister and whether the cycle is read or write.
8.1 Read with Auto Precharge
During a READA cycle, the auto precharge begins one clock earlier (CL = 2) or two clocks earlier (CL = 3) than the last
word output.
READ with AUTO PRECHARGE
Burst lengh = 4
CLK
Command
CAS latency = 2
DQ
Command
CAS latency = 3
DQ
Remark READA means READ with AUTO PRECHARGE
Hi - Z
Auto precharge starts
QB0 QB3QB2
QB1
READA B
READA B
T0 T1 T2 T3
T4
T5 T6 T7
Auto precharge starts
Hi - Z
T8
QB0 QB3
QB2
QB1
No New Command to Bank B
No New Command to Bank B
Document :1G5-0183 Rev.1 Page 20
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CMOS Synchronous Dynamic RAM
8.2 Write with Auto Precharge
During a write cycle, the auto precharge starts at the timing that is equal to the value of tDPL(min.) after the last data
word input to the device.
WRITE with AUTO PRECHRGE
In summary, the auto precharge cycle begins relative to a reference clock that indicates the last data word is valid.
In the table below, minus means clocks before the reference; plus means clocks after the reference.
CAS latency Read Write
2-1 + tDPL(min.)
3-2 + tDPL(min.)
Burst lengh = 4
CLK
Command
CAS latency = 2
DQ
Command
CAS latency = 3
DQ
Remark WRITA means WRITE with AUTO Precharge
Hi - Z
DB0 DB3DB2
DB1
WRITA B
WRITA B
T0 T1 T2T3 T4 T5 T6 T7
Hi - Z_
T8
tDPL
tDPL
DB0 DB3
DB2
DB1
AUTO PRECHARGE starts
AUTO PRECHARGE starts
Document :1G5-0183 Rev.1 Page 21
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VG36128401BT / VG36128801BT / VG36128161BT
CMOS Synchronous Dynamic RAM
9. Read / Writw Command Interval
9.1 Read to Read Command Interval
During a read cycle when a new read command is asserted, it will be effective after the CAS latency, even if the previ-
ous read operation has not completed. READ will be interrupted by another READ.
Each read command can be asserted in every clock without any restriction.
Burst lengh=4, CAS latency=2
CLK
Command
DQ
QA0 QB2QB1
QB0
Read A
T0 T1 T2 T3 T4 T5 T6 T7
Hi-Z_
T8
1 cycle
QB3
Read B
Burst lengh=4, CAS latency=2
CLK
Command
DQ QA0 QB2QB1
QB0
Write A
T0 T1 T2 T3 T4 T5 T6 T7
Hi-Z_
T8
1 cycle
QB3
Write B
WRITE to WRITE Command Interval
9.2 Write to Write Command Interval
During a write cycle, when a new Write command is asserted, the previous burst will terminated and the new burst will
begin with a new write command. WRITE will be interrupted by another WRITE.
Each write command can be asserted in every clock without any restriction.
READ to READ Command Interval
Document :1G5-0183 Rev.1 Page 22
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VG36128401BT / VG36128801BT / VG36128161BT
CMOS Synchronous Dynamic RAM
9.3 Write to Read Command Interval
The write command to read command interval is also a minimum of 1 cycle. Only the write data before the read command
will be written. The data bus must be Hi-Z at least one cycle prior to the first DOUT.
WRITE to READ Command Interval
9.4 Read to Write Command Interval
During a read cycle, READ can be interrupted by WRITE.
DQM must be in High at least 3 clocks prior to the write command. There is a restriction to avoid a data conflict. The data
bus must be Hi-Z using DQM before Write.
Burst lengh=4
CLK
Command
CAS latency=2
DQ
Command
CAS latency=3
DQ
QB0 QB3QB2
QB1
WRITE A
Write A
T0 T1 T2 T3 T4 T5 T6 T7 T8
QB0 QB3
QB2
QB1
1 cycle
Read B
DA0
Read B
DA0 Hi-Z
Hi-Z
Document :1G5-0183 Rev.1 Page 23
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CMOS Synchronous Dynamic RAM
READ to WRITE Command Interval
CAS latency=2
CLK
Command
DQM
DQ Hi-Z D0 D3D2
D1
Read
T0 T1 T2 T3 T4 T5 T6 T7 T8
1 cycle
Write
Burst length=8, CAS latency=2
CLK
Command
DQM
DQ Q0
Read
T0 T1 T2 T3 T4 T5 T6 T7 T8
Write
T9
necessary
Q2
Q1 D0 D2
D1
Hi-Z is
example: Burst length=4, CAS latency=3
CLK
Command
DQM
DQ
Read
T0 T1 T2 T3 T4 T5 T6 T7 T8
Write
necessary
D0 D2
D1
Hi-Z is
Q2
Document :1G5-0183 Rev.1 Page 24
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VG36128401BT / VG36128801BT / VG36128161BT
CMOS Synchronous Dynamic RAM
10. BURST Termination
There are two methods to terminate a burst operation other than using a read or a write command. One is the burst
stop command and the other is the precharge command.
10.1 BURST Stop Command
During a read burst, when the burst stop command is issued, the burst read data are terminated and the data bus
goes to high-impedance after the CAS latency from the burst stop command.
During a write burst, when the burst stop command is issued, the burst write data are termained and data bus goes to
Hi-Z at the same clock with the burst stop command.
Burst Termination
Remark BST: Burst stop command
Remark BST: Burst command
Burst lengh=X, CAS Intency=2,3
CLK
Command
CAS latency=2
DQ
CAS latency=3
DQ
Q0 Q2
Q1
Read
T0 T1 T2 T3 T4 T5 T6 T7
BST
Hi-Z
Q0 Q2
Q1 Hi-Z
Burst lengh=X, CAS latency=2,3
CLK
Command
CAS latency=2,3
DQ Q0 Q2
Q1
Write
T0 T1 T2 T3 T4 T5 T6 T7
BST
Hi-Z_
Q0
Document :1G5-0183 Rev.1 Page 25
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CMOS Synchronous Dynamic RAM
10.2 PRECHARGE TERMINATION
10.2.1 PRECHARGE TERMINATION in READ Cycle
During READ cycle, the burst read operation is terminated by a precharge command.
When the precharge command is issued, the burst read operation is terminated and precharge starts.
The same bank can be activated again after tRP from the precharge command.
When CAS latency is 2, the read data will remain valid until one clock after the precharge command.
When CAS latency is 3, the read data will remain valid until two clocks after the precharge command.
Precharge Termination in READ Cycle
Burst lengh= X
CLK
Command
CAS latency=2
DQ Hi-Z
Read
T0 T1 T2 T3 T4 T5 T6 T7 T8
PRE ACT
DQ
Read PRE ACT
tRP
CAS latency=3
Q0 Q3
Q2
Q1 Hi-Z
Q0 Q3
Q2
Q1
command
tRP
Document :1G5-0183 Rev.1 Page 26
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VG36128401BT / VG36128801BT / VG36128161BT
CMOS Synchronous Dynamic RAM
10.2.2 Precharge Termination in WRITE Cycle
During WRITE cycle, the burst write operation is terminated by a precharge command.
When the precharge command is issued, the burst write operation is terminated and precharge starts.
The same bank can be activated again after tRP from the precharge command. The DQM must be high to mask
invalid data in.
During WRITE cycle, the write data written prior to the precharge command will be correctly stored. However,
invalid data may be written at the same clock as the precharge command. To prevent this from happening, DQM
must be high at the same clock as the precharge command. This will mask the invalid data.
PRECHARGE TERMINATION in WRITE Cycle
Burst lengh = X
CLK
Command
CAS latency = 2
DQM
Hi - Z
Write
T0 T1 T2 T3 T4 T5 T6 T7 T8
t
RP
PRE ACT
DQ
Write PRE ACT
t
RP
CAS latency = 3
Hi - Z
D0 D3
D2
D1
D0 D3
D2
D1
DQM
D4
D4
command
DQ
Document :1G5-0183 Rev.1 Page 27
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CMOS Synchronous Dynamic RAM
Timing Diagram
Document :1G5-0183 Rev.1 Page 28
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CMOS Synchronous Dynamic RAM
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10
Mode Register Set
CLK
CKE
CS
RAS
CAS
WE
BS0,1
A10
ADD
DQM
DQ
Command
Mode Register
Set
Command
All Banks
Precharge Command
tRP
tRSC
Hi-Z
Address Key
Document :1G5-0183 Rev.1 Page 29
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VG36128401BT / VG36128801BT / VG36128161BT
CMOS Synchronous Dynamic RAM
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
t
CH
t
CL
t
CKS
t
CMS
t
CMH
tAS tAH
Begin Auto Precharge
Bank A Begin Auto Precharge
Bank B t
CKH
t
CK2
AC Parameters for Write Timing (1 of 2)
CLK
CKE
CS
RAS
CAS
WE
*BS0
A10
ADD
DQM
DQ
tRCD
tRRD
tRC
tDAL
QAa0 QAa1 QAa2 QAa3 QBa0 QBa1 QBa2 QBa3 QAb0 QAb1 QAb2 QAb3
Activate
Command
Bank A
Write with
Auto Precharge
Command
Bank A
Activate
Command
Bank B
Write with
Auto Precharge
Command
Bank B
Activate
Command
Bank A
Write without
Auto Precharge
Command
Bank A
tDS
tDH tDPL RP
t
Precharge
Command
Bank A
Activate
Command
Bank A
Burst Length=4, CAS Latency=2
Activate
Command
Bank B
AC Parameters for Write Timing (1 of 2)
* BS1=”L”, Bank C,D = Idle
Document :1G5-0183 Rev.1 Page 30
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VG36128401BT / VG36128801BT / VG36128161BT
CMOS Synchronous Dynamic RAM
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23
t
CH
t
CL
t
CKS
t
CMS
t
CMH
tAS tAH
Begin Auto Precharge
Bank A Begin Auto Precharge
Bank B t
CKH
t
CK3
AC Parameters for Write Timing (2 of 2)
CLK
CKE
CS
RAS
CAS
WE
A10
ADD
DQM
DQ
tRCD
tRRD
RC
tDAL
QAa0 QAa1 QAa2 QAa3 QBa0 QBa1 QBa2 QBa3 QAb0 QAb1 QAb2 QAb3
Activate
Command
Bank A
Write with
Auto Precharge
Command
Bank A
Activate
Command
Bank B
Write with
Auto Precharge
Command
Bank B
Activate
Command
Bank A
Write without
Auto Precharge
Command
Bank A
tDS
tDH
tDPL RP
t
Precharge
Command
Bank A
Activate
Command
Bank A
Burst Length=4, CAS Latency=3
* BS1=”L”, Bank C,D = Idle
*BS0
Document :1G5-0183 Rev.1 Page 31
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VG36128401BT / VG36128801BT / VG36128161BT
CMOS Synchronous Dynamic RAM
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13
AC Parameters for Read Timing (1 of 2)
CLK
CKE
CS
RAS
CAS
WE
A10
ADD
DQM
DQ
Burst Length=2, CAS Latency=2
tCH tCL tCK2
Begin Auto
Precharge
Bank B
tCKH
tCKS
tCMS
tCMH
tAH
tAS
tRRD tRAS tRC
tRCD
tAC2
tLZ tOH
tAC2 tOH
tHZ tRP tHZ
Hi-Z
Activate
Command
Bank A
Read
Command
Bank A
Activate
Command
Bank B
Read with
Auto Precharge
Bank B
Precharge
Command
Bank A
Activate
Command
Bank A
QAa0 QAa1 QBa0 QBa1
Command
* BS1=”L”, Bank C,D = Idle
*BS0
Document :1G5-0183 Rev.1 Page 32
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CMOS Synchronous Dynamic RAM
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15
AC Parameters for Read Timing (2 of 2)
CLK
CKE
CS
RAS
CAS
WE
A10
ADD
DQM
DQ
Burst Length=2, CAS Latency=3
tLZ tHZ
Hi-Z
Activate
Command
Bank A
Read
Command
Bank A
Activate
Command
Bank B
Read with
Auto Precharge
Bank B
Precharge
Command
Bank A
Activate
Command
Bank A
tCHtCL
tCKS
tCK3
tCMS
tCMH
tAH
tAS
tRRD tRAS tRC
tRP
tRCD
tAC3 tOH
tAC3
QAa0 QAa1 QBa0 QBa1
tOH
tHZ
Command
tCKH
Begin Auto
Precharge
Bank B
* BS1=”L”, Bank C,D = Idle
*BS0
Document :1G5-0183 Rev.1 Page 33
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CMOS Synchronous Dynamic RAM
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
Power on Sequence and Auto Refresh (CBR)
CLK
CKE
CS
RAS
CAS
WE
A10
ADD
DQM
DQ
High level
is required Minimum of 8 Refresh Cycles are required tRSC
tRP
High Level is Necessary
tRC
Address Key
Inputs
be stable
for 200us
Precharge
All Banks
must Command 1st Auto
Command
Refresh 2nd Auto
Refresh
Command
Mode
Set Command Command
Register
Hi-Z
BS0, 1
Document :1G5-0183 Rev.1 Page 34
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VG36128401BT / VG36128801BT / VG36128161BT
CMOS Synchronous Dynamic RAM
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
Clock Suspension During Burst Read (Using CKE) (1 of 2)
CLK
CKE
CS
RAS
CAS
WE
A10
ADD
DQM
DQ
tHZ
Activate
Bank A
Command Read
Bank A
Command Clock
2 Cycles
Hi-Z
QAa0 QAa1 QAa2 QAa3
RAa CAa
RAa
tCK2
Clock
Suspended
1 Cycle Suspended Clock
3 Cycles
Suspended
Burst Length=4, CAS Latency=2
* BS1=”L”, Bank C,D = Idle
*BS0
Document :1G5-0183 Rev.1 Page 35
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CMOS Synchronous Dynamic RAM
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
Clock Suspension During Burst Read (Using CKE) (2 of 2)
CLK
CKE
CS
RAS
CAS
WE
A10
ADD
DQM
DQ
tHZ
Activate
Bank A
Command Read
Bank A
Command Clock
2 Cycles
Hi-Z
QAa0 QAa1 QAa2 QAa3
RAa
RAa
tCK3
Clock
Suspended
1 Cycles Suspended Clock
3 Cycles
Suspended
Burst Length=4, CAS Latency=3
CAa
* BS1=”L”, Bank C,D = Idle
*BS0
Document :1G5-0183 Rev.1 Page 36
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CMOS Synchronous Dynamic RAM
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
Clock Suspension During Burst Write (Using CKE) (1 of 2)
CLK
CKE
CS
RAS
CAS
WE
A10
ADD
DQM
DQ
Activate
Bank A
Command Write
Bank A
Command
Clock
2 Cycles
Hi-Z
RAa CAa
RAa
tCK2
Clock
Suspended
1 Cycle Suspended Clock
3 Cycles
Suspended
Burst Length=4, CAS Latency=2
DAa0 DAa1 DAa2 DAa3
* BS1=”L”, Bank C,D = Idle
*BS0
Document :1G5-0183 Rev.1 Page 37
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CMOS Synchronous Dynamic RAM
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
Clock Suspension During Burst Write (Using CKE) (2 of 2)
CLK
CKE
CS
RAS
CAS
WE
A10
ADD
DQM
DQ
RAa
RAa
tCK3
Burst Length=4, CAS Latency=3
CAa
Activate
Bank A
Command Write
Bank A
Command
Clock
2 Cycles
Hi-Z
Clock
Suspended
1 Cycle Suspended Clock
3 Cycles
Suspended
DAa0 DAa1 DAa2 DAa3
* BS1=”L”, Bank C,D = Idle
*BS0
Document :1G5-0183 Rev.1 Page 38
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CMOS Synchronous Dynamic RAM
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
Power Down Mode and Clock Mask
CLK
CKE
CS
RAS
CAS
WE
A10
ADD
DQM
DQ
RAa
RAa
tCK2
Burst Length=4, CAS Latency=2
Activate
Bank A
Command
Power Down
Mode Entry Power Down
Bank A
Hi-Z
ACTIVE
STANDBY Read
Clock Mask
CAa
tCKS
tCKH
VALID
tCKS
RAa
QAa0 QAa1 QAa2
Mode Exit
Command
Start Clock Mask
End
Precharge
Command
Power Down
Mode Entry
Precharge
Standby Power
Mode
Down
Exit Command
* BS1=”L”, Bank C,D = Idle
*BS0
QAa3
Document :1G5-0183 Rev.1 Page 39
VIS
VG36128401BT / VG36128801BT / VG36128161BT
CMOS Synchronous Dynamic RAM
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
Auto Refresh (CBR)
CLK
CKE
CS
RAS
CAS
WE
A10
ADD
DQM
DQ
tCK2
Burst Length=4, CAS Latency=2
Precharge
All Banks
Command CBR Refresh
Hi-Z
CBR Refresh
Command
Activate
Command Read
RAa
CAa
RAa
Q0 Q1 Q2 Q3
Command Command
tRP tRC tRC
* BS1=”L”, Bank C,D = Idle
*BS0, 1
Document :1G5-0183 Rev.1 Page 40
VIS
VG36128401BT / VG36128801BT / VG36128161BT
CMOS Synchronous Dynamic RAM
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
Self Refresh (Entry and Exit)
CLK
CKE
CS
RAS
CAS
WE
A10
ADD
DQM
DQ
tSRX
All Banks Self refresh
Hi-Z
Self Refresh
Exit Self Refresh
Entry Exit
tRC
tCKS
tSRX tCKS
tRC
must be idle Self Refresh
Entry Activate
Command
CLK can be Stopped
**
* BS1=”L”, Bank C,D = Idle
*BS0
* Clock can be stopped at CKE=Low. If clock is stopped, it must be restarted/stable for 4 clock cycles before CKE=High
Document :1G5-0183 Rev.1 Page 41
VIS
VG36128401BT / VG36128801BT / VG36128161BT
CMOS Synchronous Dynamic RAM
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
Random Column Read (Page With Same Bank) (1 of 2)
CLK
CKE
CS
RAS
CAS
WE
A10
ADD
DQM
DQ
tCK2
Burst Length=4, CAS Latency=2
Precharge
Bank A
Command Read
Hi-Z
Activate Read
RAa
QAd0
Command Command
RAa CAa
RAa
CAb CAc
RAd
RAd CAd
QAa0 QAa1 QAa2 QAa3 QAb0 QAb1 QAc0 QAc1 QAc2 QAc3 QAd1 QAd2 QAd3
Bank A
Read
Command
Bank A
Read
Command
Bank A
Precharge
Command
Bank A Bank A Command
Bank A
* BS1=”L”, Bank C,D = Idle
*BS0
Document :1G5-0183 Rev.1 Page 42
VIS
VG36128401BT / VG36128801BT / VG36128161BT
CMOS Synchronous Dynamic RAM
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
Random Column Read (Page With Same Bank) (2 of 2)
CLK
CKE
CS
RAS
CAS
WE
A10
ADD
DQM
DQ
tCK3
Burst Length=4, CAS Latency=3
Activate
Bank A
Command Read
Hi-Z
Activate Read
Command Command
RAa CAa CAb CAc RAd CAd
QAc2 QAc3
QAa0 QAa1 QAa2 QAa3 QAb0 QAb1 QAc0 QAc1
Bank A
Read
Command
Bank A
Precharge
Command
Bank A Bank A Command
Bank A
RAd
Read
Command
Bank A
RAa
* BS1=”L”, Bank C,D = Idle
*BS0
Document :1G5-0183 Rev.1 Page 43
VIS
VG36128401BT / VG36128801BT / VG36128161BT
CMOS Synchronous Dynamic RAM
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
Random Column Write (Page With Same Bank) (1 of 2)
CLK
CKE
CS
RAS
CAS
WE
A10
ADD
DQM
DQ
tCK2
Burst Length=4, CAS Latency=2
Activate
Bank B
Command Write
Hi-Z
Activate Write
Command Command
Ra Ca
Ra
Cb Cc Rd Cd
Dc2 Dc3
Da1 Da2 Da3 Db0 Db1 Dc0 Dc1
Bank B
Write
Command
Bank B
Precharge
Command
Bank B Bank B Command
Bank B
Write
Command
Bank B
Rd
Dd2 Dd3
Dd0 Dd1
Da0
* BS1=”L”, Bank C,D = Idle
*BS0
Document :1G5-0183 Rev.1 Page 44
VIS
VG36128401BT / VG36128801BT / VG36128161BT
CMOS Synchronous Dynamic RAM
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
Random Column Write (Page With Same Bank) (1 of 2)
CLK
CKE
CS
RAS
CAS
WE
A10
ADD
DQM
DQ
tCK
Burst Length=4, CAS Latency=3
Activate
Bank B
Command Write
Hi-Z
Activate
Command
Ra Ca
Ra
Cb Cc Cd
Rd
Bank B
Write
Command
Bank B
Precharge
Command
Bank B Command
Bank B
Write
Command
Bank B
Rd
Write
Command
Bank B
Dc2 Dc3
Da1 Da2 Da3 Db0 Db1 Dc0 Dc1
Da0 Dd0 Dd1
* BS1=”L”, Bank C,D = Idle
*BS0
Document :1G5-0183 Rev.1 Page 45
VIS
VG36128401BT / VG36128801BT / VG36128161BT
CMOS Synchronous Dynamic RAM
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
Random Row Read (Interleaving Banks) (1 of 2)
CLK
CKE
CS
RAS
CAS
WE
A10
ADD
DQM
DQ
tCK2
Burst Length=8, CAS Latency=2
Activate
Bank B
Command Read
Hi-Z
Command
QAa0 QAa1
QBa1 QBa2 QBa3 QBa4 QBa5 QBa6 QBa7
Bank B
Activate
Command
Bank A
Active
Command
Bank B
Read
Command
Bank A
QBb1
QBb0QBa0
Read
Command
Bank B
QAa3 QAa4 QAa5 QAa6 QAa7
QAa2
Precharge
Command
Bank B
tRCD tAC2 tRP
High
* BS1=”L”, Bank C,D = Idle
*BS0
Document :1G5-0183 Rev.1 Page 46
VIS
VG36128401BT / VG36128801BT / VG36128161BT
CMOS Synchronous Dynamic RAM
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
Random Row Read (Interleaving Banks) (2 of 2)
CLK
CKE
CS
RAS
CAS
WE
A10
ADD
DQM
DQ
tCK3
Burs tLength=8, CAS Latency=3
Activate
Bank B
Command Read
Hi-Z
Command
QAa0 QAa1
QBa1 QBa2 QBa3 QBa4 QBa5 QBa6 QBa7
Bank B
Activate
Command
Bank A
Precharge
Command
Bank B
QBb0QBa0
Read
Command
Bank B
QAa3 QAa4 QAa5 QAa6 QAa7
QAa2
Read
Command
Bank A
tRCD tAC3 tRP
High
Activate
Bank B
Command Precharge
Command
Bank A
* BS1=”L”, Bank C,D = Idle
*BS0
Document :1G5-0183 Rev.1 Page 47
VIS
VG36128401BT / VG36128801BT / VG36128161BT
CMOS Synchronous Dynamic RAM
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
Random Row Write (Interleaving Banks) (1 of 2)
CLK
CKE
CS
RAS
CAS
WE
A10
ADD
DQM
DQ
tCK2
Burst Length=8, CAS Latency=2
Activate
Bank A
Command Write
Hi-Z
Command
QBa0 QBa1
QAa1 QAa2 QAa3 QAa4 QAa5 QAa6 QAa7
Bank A
Activate
Command
Bank B
Active
Command
Bank A
Write
Command
Bank B
QAb3
QAb2QAa0
Write
Command
Bank A
QBa3 QBa4 QBa5 QBa6 QBa7
QBa2
Precharge
Command
Bank A
tRCD tRP
High
tDPL
QAb0 QAb1 QAb4
Precharge
Command
Bank B
* BS1=”L”, Bank C,D = Idle
*BS0
Document :1G5-0183 Rev.1 Page 48
VIS
VG36128401BT / VG36128801BT / VG36128161BT
CMOS Synchronous Dynamic RAM
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
Random Row Write (Interleaving Banks) (2 of 2)
CLK
CKE
CS
RAS
CAS
WE
A10
ADD
DQM
DQ
tCK
Burst Length=8, CAS Latency=3
Activate
Bank A
Command Write
Hi-Z
Command
QAa7 QBa0
QAa0 QAa1 QAa2 QAa3 QAa4 QAa5 QAa6
Bank A
Activate
Command
Bank B
QAb2
QAb1
Activate
Command
Bank A
QBa2 QBa3 QBa4 QBa5 QBa6
QBa1
Write
Command
Bank B
RBa
tRP
High
tDPL tDPL
QBb7 QAb0 QAb3
Write
Command
Bank A
Precharge
Command
Bank A
Precharge
Command
Bank B
* BS1=”L”, Bank C,D = Idle
*BS0
Document :1G5-0183 Rev.1 Page 49
VIS
VG36128401BT / VG36128801BT / VG36128161BT
CMOS Synchronous Dynamic RAM
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
Read and Write Cycle (1 of 2)
CLK
CKE
CS
RAS
CAS
WE
A10
ADD
DQM
DQ
tCK2
Burst Length=4, CAS Latency=2
Activate
Bank A
Command Write
Hi-Z
Command
DAb3 QAc0
QAa0 QAa1 QAa2 QAa3 DAb0 DAb1
Bank A
Write
Command
Bank A
Read
Command
Bank A
QAc3
QAc1
The Read Data
The Write Data
is Masked with a
Zero Clock
RAa
RAa CAb CAc CAa
latency
is Masked with
Two Clocks
Latency
* BS1=”L”, Bank C,D = Idle
*BS0
Document :1G5-0183 Rev.1 Page 50
VIS
VG36128401BT / VG36128801BT / VG36128161BT
CMOS Synchronous Dynamic RAM
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
Read and Write Cycle (2 of 2)
CLK
CKE
CS
RAS
CAS
WE
A10
ADD
DQM
DQ
tCK3
Burst Length=4, CAS Latency=3
Activate
Bank A
Command Read
Hi-Z
Command
DAb3 QAc0
QAa0 QAa1 QAa2 QAa3 DAb0 DAb1
Bank A
Write
Command
Bank A
QAc3
QAc1
The Read Data
The Write Data
is Masked with a
Zero Clock
RAa
Latency
is Masked with
Two Clock
Latency
RAa
CAb
CAa CAc
Read
Command
Bank A
* BS1=”L”, Bank C,D = Idle
*BS0
Document :1G5-0183 Rev.1 Page 51
VIS
VG36128401BT / VG36128801BT / VG36128161BT
CMOS Synchronous Dynamic RAM
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
Interleaved Column Read Cycle (1 of 2)
CLK
CKE
CS
RAS
CAS
WE
A10
ADD
DQM
DQ
tCK2
Burst Length=4, CAS Latency=2
Activate
Bank A
Command Read
Hi-Z
Command
QBb1 QBd0
QAa0 QAa1 QAa2 QAa3 QBa0 QBa1
Bank A
Read
Command
Bank B
QBd2
QBd1
Precharge
Ra Ra
Ra Ca Ra Ca Cb Cc Cb Cd
QAb1
QBc0 QBc1 QBd3
Activate
Command
Bank B
Read
Command
Bank B
QBb0 QAb0
Read
Command
Bank B
Read
Command
Bank A
Read
Command
Bank B
Precharge
Command
Bank A
Command
Bank B
tRCD tAC2
* BS1=”L”, Bank C,D = Idle
*BS0
Document :1G5-0183 Rev.1 Page 52
VIS
VG36128401BT / VG36128801BT / VG36128161BT
CMOS Synchronous Dynamic RAM
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
Interleaved Column Read Cycle (2 of 2)
CLK
CKE
CS
RAS
CAS
WE
A10
ADD
DQM
DQ
tCK3
Burst Length=4, CAS Latency=3
Activate
Bank A
Command
Hi-Z QBb1 QAb2
QAa0 QAa1 QAa2 QAa3 QBa0 QBa1 QAb3
Precharge
Ra Ra
Ra Ca Ra Ca Cb Cc Cb
QAb1
QBc0 QBc1
Read
Command
Bank A
Read
Command
Bank B
QBb0 QAb0
Read
Command
Bank B
Read
Command
Bank B
Read
Command
Bank A
Precharge
Command
Bank B Command
Bank A
tRRD
Activate
Command
Bank B
tRCD tAC3
* BS1=”L”, Bank C,D = Idle
*BS0
Document :1G5-0183 Rev.1 Page 53
VIS
VG36128401BT / VG36128801BT / VG36128161BT
CMOS Synchronous Dynamic RAM
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
Interleaved Column Write Cycle (1 of 2)
CLK
CKE
CS
RAS
CAS
WE
A10
ADD
DQM
DQ
tCK2
Burst Length=4, CAS Latency=2
Activate
Bank A
Command
Hi-Z DBb1 DBd0
DAa0 DAa1 DAa2 DAa3 DBa0 DBa1 DBd1
Precharge
Ra Ra
Ra Ca Ra Ca Cb Cc Cb
DAb1
DBc0 DBc1
Write
Command
Bank A
Write
Command
Bank B
DBb0 DAb0
Command Write
Command
Bank B
Write
Command
Bank A
Precharge
Command
Bank A Command
Bank B
tRRD
Activate
Command
Bank B
tRCD tRP
Cb
DBd2 DBd3
Write
Bank B
tDPL
Write
Command
Bank B
* BS1=”L”, Bank C,D = Idle
*BS0
Document :1G5-0183 Rev.1 Page 54
VIS
VG36128401BT / VG36128801BT / VG36128161BT
CMOS Synchronous Dynamic RAM
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
Interleaved Column Write Cycle (2 of 2)
CLK
CKE
CS
RAS
CAS
WE
A10
ADD
DQM
DQ
tCK3
Burst Length=4, CAS Latency=3
Activate
Bank A
Command
Hi-Z QBb1 QBd0
QAa0 QAa1 QAa2 QAa3 QBa0 QBa1 QBd1
Precharge
Ra Ra
Ra Ca Ra Ca Cb Cc Cb
QAb1
QBc0 QBc1
Write
Command
Bank A
Write
Command
Bank B
QBb0 QAb0
Write
Command
Bank B
Write
Command
Bank B
Write
Command
Bank A
Write
Command
Bank B
Command
Bank A
tRRD
Activate
Command
Bank B
tRCD
Cd
tDPL
tRP
QBd2 QBd3
tDPL
Precharge
Command
Bank B
* BS1=”L”, Bank C,D = Idle
*BS0
Document :1G5-0183 Rev.1 Page 55
VIS
VG36128401BT / VG36128801BT / VG36128161BT
CMOS Synchronous Dynamic RAM
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
Auto Precharge after Read Burst (1 of 2)
CLK
CKE
CS
RAS
CAS
WE
A10
ADD
DQM
DQ
tCK2
Burst Length=4, CAS Latency=2
Activate
Bank A
Command
Hi-Z QBa3 QBb0
QAa0 QAa1 QAa2 QAa3 QBa0 QBa1 QBb1
Read with
Ra Ra
Ca Ra Ca Cb Rb Cb
QAb3
QAb0 QAb1
Activate
Command
Bank B
QBa2 QAb2
Read with
Command
Bank A Activate
Command
Bank B
Read with
Command
Bank B
Activate
Command
Bank A
Command
Bank A
Read with
Auto Precharge
Bank B
Rc
QBb2 QBb3
Rb Rc
Ra Cc
QAc0 QAc2
Read
Bank A
Command Command
QAc1
Auto Precharge
Auto Precharge
Auto Precharge
Start Auto Precharge
Bank B Start Auto Precharge
Bank A Start Auto Precharge
Bank B
High
* BS1=”L”, Bank C,D = Idle
*BS0
Document :1G5-0183 Rev.1 Page 56
VIS
VG36128401BT / VG36128801BT / VG36128161BT
CMOS Synchronous Dynamic RAM
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
Auto Precharge after Read Burst (2 of 2)
CLK
CKE
CS
RAS
CAS
WE
A10
ADD
DQM
DQ
tCK3
Burst Length=4, CAS Latency=3
Activate
Bank A
Command
Hi-Z QBa3
QAa0 QAa1 QAa2 QAa3 QBa0 QBa1
Ra Ra
Ra
QAb3
QAb0 QAb1
Read
Command
Bank A
Read with
Command
Bank B
QBa2 QAb2
Command
Bank A
Activate
Command
Bank B
QBb0
Ra Ca
Ca RBb
Cb
Auto Precharge
Start Auto Precharge
Bank B Start Auto
Bank A
Start Auto Precharge
Bank B
High
Rb
Cb
QBb1 QBb2
Activate
Command
Bank B
Write with
Auto Precharge Auto precharge
Command
Bank B
Read with
Rb
Precharge
* BS1=”L”, Bank C,D = Idle
*BS0
Document :1G5-0183 Rev.1 Page 57
VIS
VG36128401BT / VG36128801BT / VG36128161BT
CMOS Synchronous Dynamic RAM
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
Auto Precharge after Write Burst (1 of 2)
CLK
CKE
CS
RAS
CAS
WE
A10
ADD
DQM
DQ
tCK2
Burst Length=4, CAS Latency=2
Activate
Bank A
Command
Hi-Z QBa3 QBb0
QAa0 QAa1 QAa2 QAa3 QBa0 QBa1 QBb1
Ra Ra
Ra
QAb3
QAb0 QAb1
Write
Command
Bank A
Write with
Command
Bank B
QBa2 QAb2
Write with
Command
Bank A
Activate
Command
Bank B
Write with
Command
Bank B
Activate
Command
Bank B
QBb2 QBb3
Rb
Ra Ca Cb Ca Rb
Cb
Auto Precharge Auto Precharge
Auto Precharge
Start Auto Precharge
Bank B Start Auto Precharge
Bank A Start Auto Precharge
Bank B
High
Rc
Rc Cc
QAc0 QAc1 QAc2 QAc3
Activate
Command
Bank A Write with
Auto Precharge
Bank A
Start Auto
Precharge
Bank A
* BS1=”L”, Bank C,D = Idle
*BS0
Document :1G5-0183 Rev.1 Page 58
VIS
VG36128401BT / VG36128801BT / VG36128161BT
CMOS Synchronous Dynamic RAM
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
Auto Precharge after Write Burst (2 of 2)
CLK
CKE
CS
RAS
CAS
WE
A10
ADD
DQM
DQ
tCK3
Burst Length=4, CAS Latency=3
Activate
Bank A
Command
Hi-Z QBa3
QAa0 QAa1 QAa2 QAa3 QBa0 QBa1
Ra Ra
Ra
QAb3
QAb0 QAb1
Read
Command
Bank A
Read with
Command
Bank B
QBa2 QAb2
Command
Bank A
Activate
Command
Bank B
QBb0
Ra Ca
Ca RBb
Cb
Auto Precharge
Start Auto Precharge
Bank B Start Auto
Bank A
Start Auto Precharge
Bank B
High
Rb
Cb
QBb1 QBb2
Activate
Command
Bank B
Write with
Auto Precharge Auto precharge
Command
Bank B
Read with
Rb
Precharge
QBb3
* BS1=”L”, Bank C,D = Idle
*BS0
Document :1G5-0183 Rev.1 Page 59
VIS
VG36128401BT / VG36128801BT / VG36128161BT
CMOS Synchronous Dynamic RAM
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
Full Page Read Cycle (1 of 2)
CLK
CKE
CS
RAS
CAS
WE
A10
ADD
DQM
DQ
tCK2
Burst Length=Full Page, CAS Latency=2
Activate
Bank A
Command Read
Hi-Z
Command
Ra
QAa+1
Bank A
The burst counter wraps Burst Stop
Read
Command
Bank B
QAa
Full page burst operation does not
Ra Ca Rb
tRP
High
Activate
Command
Bank B
Ra Rb
Ca
QAa+2 QAa-2 QAa-1 QAa QAa+1 QBa QBa+1 QBa+2 QBa+3 QBa+4 QBa+51QBa+6
Activate
Command
Bank B
from the highest order
page address back to zero
during this time interval
terminate when the burst length is
satisfied; the burst counter
increments and continues bursting
beginning with the starting address
Command
Precharge
Command
Bank B
Ra
* BS1=”L”, Bank C,D = Idle
*BS0
Document :1G5-0183 Rev.1 Page 60
VIS
VG36128401BT / VG36128801BT / VG36128161BT
CMOS Synchronous Dynamic RAM
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
Full Page Read Cycle (2 of 2)
CLK
CKE
CS
RAS
CAS
WE
A10
ADD
DQM
DQ
tCK3
Burst Length=Full Page, CAS Latency=3
Activate
Bank A
Command Read
Hi-Z
Command
Ra
QAa+1
Bank A
The burst counter wraps Burst Stop
Read
Command
Bank B
QAa
Full page burst operation
Ra Ca Rb
High
Activate
Command
Bank B
Ra Rb
Ca
QAa+2 QAa-2 QAa-1 QAa QAa+1 QBa0 QBa+1 QBa+2 QBa+3 QBa+4 QBa+5
Activate
Command
Bank B
from the highest order
page address back to zero
during this time interval
Command
Precharge
Command
Bank B
does not teminate when
the burst length is satisfied;
the burst counter increments
and continues bursting
beginning with the starting
address
Ra
* BS1=”L”, Bank C,D = Idle
*BS0
Document :1G5-0183 Rev.1 Page 61
VIS
VG36128401BT / VG36128801BT / VG36128161BT
CMOS Synchronous Dynamic RAM
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
Full Page Write Cycle (1 of 2)
CLK
CKE
CS
RAS
CAS
WE
A10
ADD
DQM
DQ
tCK2
Burst Length=Full Page, CAS Latency=2
Activate
Bank A
Command Write
Hi-Z
Command
Ra
QAa+1
Bank A
The burst counter wraps Burst Stop
Write
Command
Bank B
QAa
Full page burst operation
Ra Ca Rb
tBDL
High
Activate
Command
Bank B
Ra Rb
Ca
QAa+2 QAa+3 QAa-1 QAa QAa+1 QBa QBa+1 QBa+2 QBa+3 QBa+4 QBa+5
Activate
Command
Bank B
from the highest order
page address back to zero
during this time interval
Command
Precharge
Command
Bank B
does not terminate when
the burst length is satisfied;
the burst counter increments
and continues bursting
beginning with the starting
address
QBa+6
Data is ignored
Ra
* BS1=”L”, Bank C,D = Idle
*BS0
Document :1G5-0183 Rev.1 Page 62
VIS
VG36128401BT / VG36128801BT / VG36128161BT
CMOS Synchronous Dynamic RAM
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
Full Page Write Cycle (2 of 2)
CLK
CKE
CS
RAS
CAS
WE
A10
ADD
DQM
DQ
tCK3
Burst Length=Full Page, CAS Latency=3
Activate
Bank A
Command Write
Hi-Z
Command
Ra
DAa+1
Bank A The burst counter wraps Burst Stop
Write
Command
Bank B
DAa
Full page burst operation
Ra
tBDL
High
Activate
Command
Bank B
DAa+2 DAa+3 DAa-1 DAa DAa+1 DBa DBa+1 DBa+2 DBa+3 DBa+4 DBa+5
Activate
Command
Bank B
from the highest order
page address back to zero
during this time interval Command
Precharge
Command
Bank B
does not terminate when
the burst length is satisfied;
the burst counter increments
and continues bursting
beginning with the starting
address
Ra Rb
Ca Ra Ca Rb
Data is ignored.
* BS1=”L”, Bank C,D = Idle
*BS0
Document :1G5-0183 Rev.1 Page 63
VIS
VG36128401BT / VG36128801BT / VG36128161BT
CMOS Synchronous Dynamic RAM
Hi-Z
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
Burst Read and Single Write Operation
CLK
CKE
CS
RAS
CAS
WE
A10
ADD
DQM
tCK2
Burst Length=4, CAS Latency=2
RAa
RAa
High
Activate
CAa CAb CAd
DQ
Command
Bank A
Read
Command
Bank A
Single Write Single Write Read
Command
Bank A
DQs are
masked
CAc CAe
Command
Bank A Command
Bank A
Single Write
Command
Bank A
DQs are
masked
* BS1=”L”, Bank C,D = Idle
*BS0
Document :1G5-0183 Rev.1 Page 64
VIS
VG36128401BT / VG36128801BT / VG36128161BT
CMOS Synchronous Dynamic RAM
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
Full Page Random Column Read
CLK
CKE
CS
RAS
CAS
WE
BS
A10
ADD
DQM
DQ
tCK2
Burst Length=Full Page, CAS Latency=2
Activate
Bank A
Command Activate
Hi-Z
Command
Ra
QBa0
Bank B
Read
Command
Bank B
QAa0
Ra
Activate
Command
Bank B
QAb0 QAb1 QBb0 QBb1 QAc0 QAc1 QAc2 QBc0 QBc1 QBc2
Read
Command
Bank A
Precharge
Cc Cc Rb
Ra
Ra Ca Ca Cb Cb
Rb
tRP
Read
Command
Bank B
Read
Command
Bank A
Read
Command
Bank A
Read
Command
Bank B Command Bank B
(Precharge Termination)
(Bank D)
* BS1=”L”, Bank C,D = Idle
Document :1G5-0183 Rev.1 Page 65
VIS
VG36128401BT / VG36128801BT / VG36128161BT
CMOS Synchronous Dynamic RAM
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
Full Page Random Column Write
CLK
CKE
CS
RAS
CAS
WE
A10
ADD
DQM
DQ
tCK2
Burst Length=Full Page, CAS Latency=2
Activate
Bank A
Command Activate
Hi-Z
Command
Ra
QBa0
Bank B
Write
Command
Bank B
QAa0
Ra
Activate
Command
Bank B
QAb0 QAb1 QBb0 QBb1 QAc0 QAc1 QAc2 QBc0 QBc1 QBc2
Write
Command
Bank A
Precharge
Cc Cc Rb
Ra
Ra Ca Ca Cb Cb
Rb
tRP
Write
Command
Bank B
Write
Command
Bank A
Write
Command
Bank A
Write
Command
Bank B Command Bank B
(Precharge Termination)
Write Data
is masked
(Bank D)
* BS1=”L”, Bank C,D = Idle
*BS0
Document :1G5-0183 Rev.1 Page 66
VIS
VG36128401BT / VG36128801BT / VG36128161BT
CMOS Synchronous Dynamic RAM
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
Precharge Termination of a Burst (1 of 2)
CLK
CKE
CS
RAS
CAS
WE
A10
ADD
DQM
DQ
tCK2
Burst Length=8, CAS Latency=2
Activate
Bank A
Command Write
Hi-Z
Command
RAa
Bank A
Activate
Command
Bank A
Read
Command
Bank A
RAc CAb
RAb
RAb
RAc
Precharge Termination
of a Write Burst. Write
data is masked.
Precharge
Command Read
Command
Bank A
Precharge
Command
Bank A
Precharge Termination
High
RAa CAcCAa
QAa1
QAa0 QAa2 Da3 QAb0 QAb1 QAb2 QAc0 QAc1 QAc2
tDPL tRP tRP tRP
Bank A
of a Read Burst.
Activate
Command
Bank A
Precharge
Command
Bank A
* BS1=”L”, Bank C,D = Idle
*BS0
Document :1G5-0183 Rev.1 Page 67
VIS
VG36128401BT / VG36128801BT / VG36128161BT
CMOS Synchronous Dynamic RAM
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
Precharge Termination of a Burst (2 of 2)
CLK
CKE
CS
RAS
CAS
WE
A10
ADD
DQM
DQ
tCK3
Activate
Bank A
Command Write
Hi-Z
Command
RAa
Bank A
Activate
Command
Bank A
CAb
RAb
RAb
RAc
Precharge
Command Read
Command
Bank A
High
RAa RAcCAa
DAa1DAa0 QAb0 QAb1 QAb2 QAb3
tDPL tRP
Bank A
Activate
Command
Bank A
Activate
Command
Bank A
tRCD
tRP
Write Data
is masked Precharge Termination
of a Write Burst.
Precharge Termination
of a Read Burst.
t
RAS
* BS1=”L”, Bank C,D = Idle
*BS0
Burst Length=8, CAS Latency=3
Document :1G5-0183 Rev.1 Page 68
VIS
VG36128401BT / VG36128801BT / VG36128161BT
CMOS Synchronous Dynamic RAM
Ordering information
VG36128401BT(L)-7L
• VG : VIS Memory Product
• 36 : Technology/Design Rule
• 128 : 128Mb
• 80 : Device Configuration, 40:x4, 80: x8, 16: x16
• 1 : Interface Type, 1: LVTTL
• B : Mask/Design Version
• T : Package Type, T: TSOP
• L : None: normal version; L:low power version
• 7L : Cycle time, 7H: 133MHz 2/2/2, 7L: 133MHz 3/3/3, 8H: 100MHz 2/2/2
Packaging Information
• 400mil, 54-Pin Plastic TSOP
Part Number Cycle time Package
VG3612840(80/16)1BT(L)-7H 7.5 ns (133MHz 2/2/2) 400mil, 54-Pin
Plastic TSOP
VG3612840(80/16)1BT(L)-7L 7.5 ns (133MHz 3/3/3)
VG3612840(80/16)1BT(L)-8H 10 ns (100MHz 2/2/2)
1. CONTROLLING DIMENSION : MILLIMETERS
2. DIMENSION D DOES NOT INCLUDE MOLD PROTRUSION.
MOLD PROTRUSION SHALL NOT EXCEED 0.15mm(0.006") PER SIDE.
DIMENSION E1 DOES NOT INCLUDE INTERLEAD PROTRUSION.
INTERLEAD PROTRUSION SHALL NOT EXCEED 0.25mm(0.01") PER SIDE.
3. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSIONS/INTRUSION.
ALLOWABLE DAMBAR PROTRUSION SHALL NOT CAUSE THE LEAD TO
DAMBAR INTRUSION SHALL NOT CAUSE THE LEAD TO BE NARROWER
THAN THE MIN b DIMENSION BY MORE THAN 0.07mm.
BE WIDER THAN THE MAX b DIMENSION BY MORE THAN 0.13mm.
NOTE:
22.09
11.56
10.03
R1
ZD
E1
L
R
E
e
c
D
c1
b1
b
A
A1
A2
DIM
--- ------ ---0.12 0.005
0.012
0.012
0.005
0.005
0.870
0.455
0.016
0.005
0.395
0.71 REF.
0.80 BASIC
10.16
0.40
0.12
0.50
---
11.76
10.29
0.25
0.60
11.96
---0.12
0.12
22.22
---
0.30
0.30
---
---
0.21
22.35
0.16
0.45
0.40
0.028 REF.
0.400
0.020
---
0.463
0.0315 BASIC
0.405
0.024
0.010
0.471
---
0.875
---
---
---
0.008
0.880
0.006
0.016
0.018
MIN.
0.002
0.037
MILLIMETERS
------
0.05
0.95
---
1.00
MIN. NOM.
1.20
0.15
1.05
MAX.
------
0.039
---
INCHES
NOM.
0.047
0.006
0.041
MAX.
A
b
0.100(0.004")
eE
SEATING PLANE
28
27
D
ZD
1
54
c
B
RAD R
A2
A1
E1 DETAIL A
DETAIL A
B
L0¢X~8¢X
RAD R1
c1 c
BASE METAL
WITH PLATING
SECTION B-B
b1
b
