SAK-C167CR-16RM - Siemens Semiconductors

Data Sheet 12.96 (Advance Information)

Microcomputer Components

C167CR-16RM

16-Bit CMOS Single-Chip Microcontrollers

Controller Area Network (C AN): Lic ense of Robert Bosch G mbH

C167CR-16RM

Revision Histo ry: Original Version 12.96 (Advance Information)

Previous Releases: -

Page S ubj ects (compar ed to Data Sheet C167CR, 06.95)

21 Incremental Interface Mode added.

22 T3 capture tr igger for C APREL added.

Edition 12.96

Published by Siemens AG, B ereich Halbleit er, Marketing -Komm unikation

Balanstraße 73, D-81541 München.

As far as patents or other rights of third parties are concerned, liability is only assumed for

components per se, not for applications, processes and circuits implemented within components or

assemblies.

The information describes the type of component and shall not be considered as assured

characteristics.

Terms of delivery and rights to change design reserved.

For questions on technology, delivery and prices please contact the Offices of Siemens

Aktiengesellschaft in Ger many or the Siemens Companies and Representatives worldwide.

Due to technical requirements components may contain dangerous substances. For information on

the type in questio n please contact your nearest S iem ens Office, Com ponents Group.

Siemens AG is an approved CECC manufacturer .

●High Performance 16-bit C PU with 4- Stage Pipeline

●100 ns Instruction Cy cle Time at 20 MH z CPU Clock

●500 ns Multiplication (16 × 16 bit), 1 µs Div ision (32 / 16 bit)

●E nhanced B oolean Bit Manipulation F acilities

●A dditional Instructions to Support HLL and Operating Systems

●Register-Based Design with Multiple Variable Register Banks

●S ingle-Cycle Context Sw itching Support

●Clock Generation via on-chip PLL or via direct clock input

●Up to 16 MBytes Linear Address Space for Code and Data

●2 KBytes On-Chip Internal RAM (IRAM)

●2 KBytes On-Chip Extensi on RAM (XRAM)

●128 KBytes On-Chip ROM

●P rogrammable External Bus Characteri stics for D ifferent Address Ranges

●8-Bit or 16-Bi t External Data Bus

●Multiplexed or Demultiplexed External Address/Data Buses

●Five Programmable Chip-Select Signals

●Hold- and Hold-Acknowle dge Bus Arbitration Suppor t

●1024 Bytes On-Chip Special Function Register Area

●Idle and Power Down Modes

●8-Channel Interrupt-Driven Single-Cycle Data Transfer Facilities via Peripheral Event

Controller (PEC)

●16-Pri ority-Lev el Interrupt System with 56 Sourc es, Sample-R ate down to 50 ns

●16-Channel 10-bit A/D Converter wi th 9.7µs Conversion Time

●Tw o 16-Channel Capture/Com pare Units

●4-Channel PWM Unit

●Two Multi-Functional General Purpose Timer U nits with 5 T im ers

●Tw o S erial Channels (Synchronous/As ynchronous and Hi gh-Speed-Synchronous)

●On-Chip CAN Interface with 15 Message Objects (Full-CAN/Basic-CAN)

●P rogrammable Watchdog Tim e r

●Up to 111 General Purpose I/O Lines, partly with Selectable Input Thresholds and Hy steresis

●Supported by a Wealth of Development Tools like C-Compilers, Macro-Assembler Packages,

Emulators, Evaluation Boards, HLL-Debuggers, Simulators, Logic Analyzer Disassemblers,

P rogramming Boards

●On-Chip Bootstrap Loader

●144-Pin MQFP Package (EIAJ)

This d ocume nt describes the SAB-C167CR-16RM and the SAK-C167CR-16RM. For simplic ity all

versions are referred to by the term C167CR-16RM throughout this docume n t.

C16x -Family of

Hig h-Performan ce CMO S 16 -Bit M icroc ont ro lle rs

Advance Information

C167CR-16RM 16-Bit Microcontroller

C167CR-16RM

1 12.96

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Semiconductor Group 2

C167CR-16RM

Introduction

The C167CR-16RM is a new derivative of the Siemens C16x Family of full featured single-chip

CMOS microcontrollers. It combines high CPU performance (up to 10 million instructions per

second) with high peripheral functionality and enhanced IO-capabilities. It also provides on-chip

ROM, on-chip high-speed RAM and cloc k generation via PLL.

Figure 1

Logic Symbol

Ordering Information

Type Ordering Code Package Function

SAB-C167CR-16RM Q67121-D... P-MQFP-144-1 16-bit microcontroller with

2 * 2 KByte RAM

Temperature ra nge 0 to +70 °C

SAF-C167CR-16RM Q67121-D... P-MQFP-144-1 16-bit microcontroller with

2 * 2 KByte RAM

Temperature ra nge -40 to +85 °C

SAK-C167CR-16RM Q67121-D... P-MQFP-144-1 16-bit microcontroller with

2 * 2 KByte RAM

Temperature ra nge -40 to +125 °C

C167CR-

16RM

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C167CR-16RM

Note: The ordering codes (Q67121-D...) for the Mask-ROM versions are defined for each product

after verifiction of the respec tive ROM code.

Pin Configuration

(top view )

Figure 2

C167CR-16RM A22/CAN_TxD

/CAN_RxD

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C167CR-16RM

Pin Definitions and Functions

Symbol Pin

Number Input (I)

Output (O) Function

P6.0 –

P6.7 1 -

8

1

...

5

6

7

8

I/O

O

...

O

I

O

Port 6 is an 8-bit bidirectional I/O port. It is bit-wise

programmable for input or output via direction bits. For a pin

configured as input, the output driver is put into high-

impedance state. Port 6 outputs can be configured as push/

pull or open drain driv ers.

The following Port 6 pins also serve for alternate functions:

P6.0 CS0 Chip Select 0 Output

... ... ...

P6.4 CS4 Chip Select 4 Output

P6.5 HOLD External Master Hold Request Input

P6.6 HLDA Hold Acknowledge Output

P6.7 BREQ Bus Request Output

P8.0 –

P8.7 9 -

16

9

...

16

I/O

...

I/O

Port 8 is an 8-bit bidirectional I/O port. It is bit-wise

programmable for input or output via direction bits. For a pin

configured as input, the output driver is put into high-

impedance state. Port 8 outputs can be configured as push/

pull or open drain drivers. The input threshold of Port 8 is

selectable (TTL or special) .

The following Port 8 pins also serve for alternate functions:

P8.0 CC16IO CAPCOM2: CC16 Cap.-In/Comp.Out

... ... ...

P8.7 CC23IO CAPCOM2: CC23 Cap.-In/Comp.Out

P7.0 –

P7.7 19 -

26

19

...

22

23

...

26

I/O

O

...

O

I/O

...

I/O

Port 7 is an 8-bit bidirectional I/O port. It is bit-wise

programmable for input or output via direction bits. For a pin

configured as input, the output driver is put into high-

impedance state. Port 7 outputs can be configured as push/

pull or open drain drivers. The input threshold of Port 7 is

selectable (TTL or special) .

The following Port 7 pins also serve for alternate functions:

P7.0 POUT0 PWM Channel 0 Output

... ... ...

P7.3 POUT3 PWM Channel 3 Output

P7.4 CC28IO CAPCOM2: CC28 Cap.-In/Comp.Out

... ... ...

P7.7 CC31IO CAPCOM2: CC31 Cap.-In/Comp.Out

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C167CR-16RM

P5.0 –

P5.15 27 – 36

39 – 44

39

40

41

42

43

44

I

Port 5 is a 16-bit input-only port with Schmitt-Trigger

characteristics. The pins of P ort 5 also serve as the (u p t o 16)

analog input channels for the A/D converter, where P5.x

equals ANx (Analog input channel x), or they serve as timer

inputs:

P5.10 T6EUD GPT2 Timer T6 Ext.Up/Down Ctrl.Input

P5.11 T5EUD GPT2 Timer T5 Ext.Up/Down Ctrl.Input

P5.12 T6IN GPT2 Timer T6 Count Input

P5.13 T5IN GPT2 Timer T5 Count Input

P5.14 T4EUD GPT1 Timer T4 Ext.Up/Down Ctrl.Input

P5.15 T2EUD GPT1 Timer T2 Ext.Up/Down Ctrl.Input

P2.0 –

P2.15 47 – 54

57 - 64

47

...

54

57

...

64

I/O

...

I/O

I

...

I/O

I

Port 2 is a 16-bit bidirectional I/O port. It is bit-wise

programmable for input or output via direction bits. For a pin

configured as input, the output driver is put into high-

impedance state. Port 2 outputs can be configured as push/

pull or open drain drivers. The input threshold of Port 2 is

selectable (TTL or special) .

The following Port 2 pins also serve for alternate functions:

P2.0 CC0IO CAPCOM: CC0 C ap.-In/Comp.Out

... ... ...

P2.7 CC7IO CAPCOM: CC7 C ap.-In/Comp.Out

P2.8 CC8IO CAPCOM: CC8 C ap.-In/Comp.Out,

EX0IN Fast External Interrupt 0 Input

... ... ...

P2.15 CC15IO CAPCOM: CC15 Cap.-In/Comp.Out,

EX7IN Fast External Interrupt 7 Input

T7IN CAPCOM2 Timer T7 Count Input

Pin Definitions and Functions (cont’d)

Symbol Pin

Number Input (I)

Output (O) Function

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C167CR-16RM

P3.0 –

P3.13,

P3.15

65 – 70,

73 – 80,

81

65

66

67

68

69

70

73

74

75

76

77

78

79

80

81

I/O

I

O

I

O

I

I/O

O

I/O

O

I/O

O

Port 3 is a 15-bit (P3.14 is missing) bidi rectional I/O port. It is

bit-wise programmable for input or output via direction bits.

For a pin configured as input, the output dr iver is put into high -

impedance state. Port 3 outputs can be configured as push/

pull or open drain drivers. The input threshold of Port 3 is

selectable (TTL or special) .

The following Port 3 pins also serve for alternate functions:

P3.0 T0IN CAPCOM Timer T0 Count Input

P3.1 T6OUT GPT2 Timer T6 Toggle Latch Output

P3.2 CAPIN GPT2 Register CAPREL C apture Input

P3.3 T3OUT GPT1 Timer T3 Toggle Latch Output

P3.4 T3EUD GPT1 Timer T3 Ext.Up/Down Ctrl.Input

P3.5 T4IN GPT 1 Timer T4 Input for

Count/Gate/Reload/Capture

P3.6 T3IN GPT1 Timer T3 Count/Gate Input

P3.7 T2IN GPT 1 Timer T2 Input for

Count/Gate/Reload/Capture

P3.8 MRST SSC Master-Rec./Slave-Transmit I/O

P3.9 MTSR SSC Master-Transmit/Slave-Rec. O/I

P3.10 T×D0 ASC0 Clock/D ata Output (Asyn./Syn.)

P3.11 R×D0 ASC0 Data Input (Asyn.) or I/O (Syn.)

P3.12 BHE Ext. Memory High Byte Enable Signal ,

WRH Ext. Memory High Byte W ri te Strobe

P3.13 SCLK SSC Master Clock Outp./Slave Cl. Inp.

P3.15 CLKOUT System Cloc k Output (=CP U C lock)

P4.0 –

P4.7 85 - 92

85

...

89

90

91

92

I/O

O

...

O

I

O

Port 4 is an 8-bit bidirectional I/O port. It is bit-wise

programmable for input or output via direction bits. For a pin

configured as input, the output driver is put into high-

impedance s tate.

In case of an external bus configuration, Port 4 can be used to

output the segment address lines:

P4.0 A16 Least Significant Segment Addr. Line

... ... ...

P4.4 A20 Segment Address Line

P4.5 A21 Segment Address Line,

CAN_RxD CAN Receive Data Input

P4.6 A22 Segment Address Line,

CAN_TxD CAN Transmit Data Output

P4.7 A23 Most Significant Segment Addr. Line

RD 95 O External Memory Read Strobe. RD is activated for every

external i nstruction or data read access.

Pin Definitions and Functions (cont’d)

Symbol Pin

Number Input (I)

Output (O) Function

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C167CR-16RM

WR/

WRL 96 O External Memory Write Strobe. In WR-mode this pin is

activated for every external data write access. In WRL-mode

this pin is activated for low byte data wr ite accesses on a 16-

bit bus, and for every data write access on an 8-bit bus. See

WRCFG in register SYSC ON for mode selection.

READY 97 I Ready Input. When the Ready function is enabled, a high

level at this pin during an external memory access will force

the insertion of memory cycle time waitstates until the pin

returns to a low level.

ALE 98 O Address Latch Enable Output. Can be used for latching the

address into external memory or an address latch in the

multi plexed bus modes.

EA 99 I Ex ternal Access Enable pin. A low level at this pin during and

after Reset forces the C167CR-16RM to begin instruction

execution out of external m emory. A high level forces

execution out of the internal R OM. ROMless ver sions must

have this pin tied to ‘0’.

PORT0:

P0L.0 –

P0L.7,

P0H.0 -

P0H.7

100 –

107

108,

111-117

I/O PORT0 consists of the two 8-bit bidirectional I/O ports P0L

and P0H. It is bit-wise programmable for input or output via

direction bits. For a pin configured as input, the output driver

is put into high- impedance state.

In case of an external bus configuration, PORT0 serves as

the add ress (A) and address/data (AD) bus in multiplexed bus

modes and as the data (D ) bus in dem ultiplexed bus modes.

Demultiplexed bus modes:

Data Path Width: 8-bit 16-bit

P0L.0 – P0L.7: D0 – D7 D0 - D7

P0H.0 – P0H.7: I/O D8 - D 15

Multiplexed bu s modes:

Data Path Width: 8-bit 16-bit

P0L.0 – P0L.7: AD0 – AD7 AD0 - AD7

P0H.0 – P0H.7: A8 - A15 AD8 - AD15

Pin Definitions and Functions (cont’d)

Symbol Pin

Number Input (I)

Output (O) Function

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Semiconductor Group 8

C167CR-16RM

PORT1:

P1L.0 –

P1L.7,

P1H.0 -

P1H.7

118 –

125

128 –

135

132

133

134

135

I/O

I

PORT1 consists of the two 8-bit bidirectional I/O ports P1L

and P1H. It is bit-wise programmable for input or output via

direction bits. For a pin configured as input, the output driver

is put into hi gh-impedance s t ate. PORT1 is used as the 16-bit

address bus (A) in demultiplexed bus modes and also after

switching from a demultiplexed bus mode to a multiplexed bus

mode.

The following PORT1 pins als o serve for alternate functions:

P1H. 4 CC24IO CAPC OM2: CC24 Capture Input

P1H. 5 CC25IO CAPC OM2: CC25 Capture Input

P1H. 6 CC26IO CAPC OM2: CC26 Capture Input

P1H. 7 CC27IO CAPC OM2: CC27 Capture Input

XTAL1

XTAL2

138

137

I

O

XTAL1: Input to the oscillator amplifier and input to the

internal clock generator

XTAL2: Output of the oscillator amplifier circuit.

To clock the device from an external source, drive XTAL1,

while leaving XTAL2 unconnected. Minimum and maximum

high/low and ris e/fall times specified in the AC Char acteristics

must be obser ved.

RSTIN 14 0 I Reset Input with Schmitt-Trigger characteristics. A low level at

this pin for a specified duration while the oscillator is running

resets the C167CR-16RM. An internal pullup resistor permits

power-on reset using only a capac itor connected to VSS.

RSTOUT 141 O Inter nal Reset Indication O utput. T his pin is set to a l ow level

when the part is executing either a hardware-, a software- or a

watchdog timer reset. RSTOUT remains low until the EINIT

(end of initialization) instruction is executed.

NMI 142 I Non-Maskable Interrupt Input. A high to low transition at this

pin causes the CPU to vector to the NMI trap routine. When

the PWRDN (power down) instruction is executed, the NMI

pin must be low in order to fo rce the C167CR-16RM to g o into

power down mode. If NMI is high, when PWRD N is executed,

the part will continue to run in norm al mode.

If not used, pin NMI should be pulled high externall y.

VAREF 37 -Reference voltage for the A/D converter.

VAGND 38 -Reference ground for the A/D converter .

VPP 84 -Flash programming voltage. This pin accepts the

programming voltage for flash versions of the C167CR-16RM.

Note: This pin is not connected (NC) on non-flash v ersions.

Pin Definitions and Functions (cont’d)

Symbol Pin

Number Input (I)

Output (O) Function

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9 Semiconductor Gr oup

C167CR-16RM

VCC 17, 46,

56, 72,

82, 93,

109,

126,

136, 144

-Digit al Supply Voltage:

+ 5 V during normal operation and idle mode.

≥ 2.5 V during power down mode.

VSS 18, 45,

55, 71,

83, 94,

110,

127,

139, 143

-Digital Ground.

Pin Definitions and Functions (cont’d)

Symbol Pin

Number Input (I)

Output (O) Function

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C167CR-16RM

Functional Description

The architectur e of the C167CR-16RM com bines adv antages of both RISC and CISC processors

and of advanced per ipher al subsys tems in a very well-balanced way. The following block diagram

gives an overview of the different on-chip components and of the advanced, high bandwidth internal

bus structure of the C 167CR-16RM .

Note: A ll time s pecifications refer to a C PU clock of 20 MHz

(see definition in the AC Characteristics secti on).

Figure 3

Block Diagram

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11 Semiconductor Gr oup

C167CR-16RM

Memory Organization

The memory space of the C167CR-16RM is configured in a Von Neumann architecture which

means that code memory, data memory, registers and I/O ports are organized within the same

linear address space which includes 16 MBytes. The entire memory space can be accessed

bytewise or wordwise. Particular portions of the on-chip memory have additionally been made

directly bitaddres sable.

The C167CR-16RM contains 128 KBytes of on-chip mask-programmable ROM for code or

constant data. The lower 32 KBytes of the on-chip ROM can be mapped either to segment 0 or

segment 1.

2 KBytes of on-chip Internal RAM are provided as a storage for user defined variables, for the

system stack, general purpose register banks and even for code. A register bank can consist of up

to 16 wordwide (R0 to R15) and/or bytewide (RL0, RH0, …, RL7, RH7) so-called General Purpose

Registers (GPRs).

1024 bytes (2 * 512 bytes) of the address space are reserved for the Special Function Register

areas (S FR space and ESFR s pace). SF R s ar e wor dw ide regi sters w hich ar e used for contr olli ng

and monitoring functions of the different on-chip units. Unused SFR addresses are reserved for

future members of the C16x fam ily.

2 KBytes of on-chip Extensi on RAM (XR AM) are provi ded to store user data, user stack s or code.

The XRAM is accessed like external memory and therefore cannot be used for the system stack or

for register banks and is not bitadressable. The XRAM allows 16-bit accesses with maximum speed.

In order to meet the needs of designs where more memory is required than is provided on chip, up

to 16 MBytes of external RAM and/or ROM can be connected to the microcontroller.

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C167CR-16RM

External Bus C ontroller

All of the external m emory accesses are perfor med by a partic ular on-chip Ex ternal Bus Controller

(EBC) . It can be programmed either to Single Chip Mode when no ex t ernal memory is required, or

to one of four different external memory access m odes, which are as follows:

– 16-/18-/20-/24-bit Address es, 16-bit Data, D emultiplex e d

– 16-/18-/20-/24-bit Address es, 16-bit Data, M ultiplexed

– 16-/18-/20-/24-bit Address es, 8-bit Data, Multipl exed

– 16-/18-/20-/24-bit Address es, 8-bit Data, Demul tiplexed

In the demultiplexed bus modes, addresses are output on PORT1 and data is input/output on

PORT0 or P0L, respectively. In the multiplexed bus modes both addresses and data use PORT0 for

input/output.

Important timing characteristics of the external bus interface (Memory Cycle Time, Memory Tri-

State Ti me, Length of ALE and Read Wr ite Delay) have been made programmable to allow the user

the adaption of a wide range of different types of memories and external peripherals.

In addition, up to 4 independent address windows may be defined (via regis ter pairs ADDRS ELx /

BUSCONx) which allow to access different resources with different bus characteristics. These

address windows are arranged hierarchically where BUSCON4 overrides BUSCON3 and

BUSCON2 overrides BUSCON1. All accesses to locations not covered by these 4 address windows

are controlled by BU SCON0.

Up to 5 external CS signals (4 windows plus default) can be generated in order to save external glue

logic. Access to very slow memories is supported via a particular ‘Ready’ function.

A HOLD/HLDA protocol is available for bus arbitration and allows to share external resources wi th

other bus masters. The bus arbitrati on is enabled by setting bit HLDEN in register SYSC ON . After

setting HLDEN once, pins P6.7...P6.5 (BREQ, HLDA, HOLD) are automatically controlled by the

EBC. In Master Mode (def ault after reset) the HLDA pin is an output. By settin g bit DP6.7 to ’1’ the

Slave Mode is selected where pin HLDA is switched to input. This allows to directly connect the

slave contr oller to another master controller without glue logic.

For appli cations whic h require les s than 16 MBytes of ex ternal mem ory space, thi s address spac e

can be restricted to 1 MByte, 256 KByte or to 64 KBy te. In this case Port 4 outputs four, two or no

address lines at all. It outputs all 8 address lines, if an address space of 16 MBytes is used.

Note: When the on-chip CAN Module is to be used the segment address output on Port 4 must be

limi ted to 4 bits (ie. A19...A16) in order to enable the alternate function of the CAN interface

pins.

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C167CR-16RM

Central Processing Unit (CPU)

The main core of the CPU consists of a 4-stage instruction pipeline, a 16-bit arithmetic and logic unit

(ALU) and ded icated SFRs. Additional hardware has been spent for a separate multiply and divide

unit, a bit-m ask generator and a barrel shifter.

Based on these hardware provis ions, most of the C167CR-16RM’s instructions can be executed in

just one machine cy cle whic h requires 100 ns at 20- MHz CPU clock. For example, shift and r otate

instructi ons ar e always pr ocess e d duri ng one machine cy cle i ndependent of the number of bits t o

be shifted. All multiple-cycle instructions have been optimized so that they can be executed very fast

as well: branches in 2 cycles, a 16 × 16 bit multiplication in 5 cycles and a 32-/16 bit division in

10 cycles. Another pipeline optimization, the so-called ‘Jump Cache’, allows reducing the execution

time of repeatedly performed jumps in a loop from 2 cycles to 1 cycle.

Figure 4

CPU Block Diagram

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Semiconductor Group 14

C167CR-16RM

The CPU disposes of an actual register context consisting of up to 16 w ordwide GPRs w hich are

physical ly allocated within the on- chip RAM ar ea. A Context P ointer (CP) register determines the

base address of the active register bank to be accessed by the CPU at a time. The number of

re gister banks is only restricted by the available internal R AM space. For easy parameter passing,

a register bank may overlap others.

A system stack of up to 2048 bytes is provided as a storage for temporary data. T he system stack

is allocated in the on-chip RAM area, and it is accessed by the CPU via the stack pointer (SP)

register. Two separate SFRs, STKOV and STKUN, are implicitly compared against the stack

pointer value upon each stack access for the detection of a stack over flow or underflow.

The high performance offered by the hardware implementation of the CPU can efficiently be utili zed

by a programmer via the highly efficient C167CR-16RM instruction set which includes the following

instruction clas ses:

– A rithmetic Instructions

– Logical Instructions

– Boolean Bit Manipulation Instruction s

– Com pare and Loop Control Instr uctions

– Shift and Rotate Instructions

– Prioritize Instruc tion

– Data M ovement Instructions

– S ystem Stack Instructio ns

– Jump and Call Instructions

– Return Instructions

– System Control Instr uctions

– Mi scellaneous Instr uctions

The basic instructio n length is either 2 or 4 bytes. Possible operand types are bits, bytes and words.

A variety of direct, indirect or immediate addressing modes are provided to specify the required

operands.

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15 Semiconductor Gr oup

C167CR-16RM

Interrupt System

With an interrupt response time within a range from just 250 ns to 600 ns (in case of internal

program execution), the C167CR-16RM is capable of reacting very fast to the occurence of non-

deterministic events.

The architecture of the C167CR-16RM supports several mechanisms fo r fast and flexible response

to service requests that can be generated from various sources internal or external to the

microcontroller. Any of these interrupt requests can be programmed to being serviced by the

Interrupt Controller or by the Peripheral Event Controller (PEC ).

In contrast to a standard inter rupt servi ce w here the current progr am execution i s suspended a nd

a branch to the interrupt vector table is performed, just one cycle i s ‘stolen’ from t he current CPU

activity to perform a PEC service. A PEC service implies a single byte or word data transfer between

any two memory locations with an additional increment of either the PEC source or the destination

pointer. An individ ual PEC transfer counter is implic ity decremented for each PEC s ervice excep t

when performing in the continuous transfer mode. When this counter reaches zero, a standard

interrupt i s performe d to the corr esponding source related vector location. PEC services are v ery

well suited, for example, for supporting the transmission or reception of blocks of data. The

C167CR-16RM has 8 PEC channels each of which offers such fast interrupt-driven data transfer

capabilities.

A separate control register which conta ins an inte rrupt request flag, an interrupt enable flag and an

interrupt priority bitfield exists for each of the possible interrupt sources. Via its related register, each

source c an b e progr ammed to one of sixteen interrupt prior ity level s. Once having been accepted

by the CPU, an interrupt service can only be interrupted by a higher prioritized service request. For

the standard interrupt processing, each of the possible interrupt sources has a dedicated vector

location.

Fast external interrupt inputs are provided to service external interrupts with high precision

requirements. These fast interrupt inputs feature programmable edge dete ction (rising edge, falling

edge or both edges).

Software interrupts are supported by means of the ‘TRAP’ instruction in combination with an

individual trap (i nterrupt) number.

The following table shows all of the possible C167CR-16RM interrupt sources and the

corresponding hardware-related interrupt flags, vectors, vector locations and trap (interrupt)

numbers:

Note: Three nodes in the table (X-Peripheral nodes) are prepared to accept interrupt requests from

integrated X-Bus peri pherals . Nodes, wher e no X-Per ipheral s are c onnected, may be us ed

to generate software controlled interrupt r equests by setting the respective XPnIR bit.

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Semiconductor Group 16

C167CR-16RM

Source of Interrupt or

PEC Service Request Request

Flag Enable

Flag Interrupt

Vector Vector

Location Trap

Number

CAPCOM Register 0 CC0IR CC0IE CC0INT 00’0040H10H

CAPCOM Register 1 CC1IR CC1IE CC1INT 00’0044H11H

CAPCOM Register 2 CC2IR CC2IE CC2INT 00’0048H12H

CAPCOM Register 3 CC3IR CC3IE CC3INT 00’004CH13H

CAPCOM Register 4 CC4IR CC4IE CC4INT 00’0050H14H

CAPCOM Register 5 CC5IR CC5IE CC5INT 00’0054H15H

CAPCOM Register 6 CC6IR CC6IE CC6INT 00’0058H16H

CAPCOM Register 7 CC7IR CC7IE CC7INT 00’005CH17H

CAPCOM Register 8 CC8IR CC8IE CC8INT 00’0060H18H

CAPCOM Register 9 CC9IR CC9IE CC9INT 00’0064H19H

CAPCOM Register 10 CC10IR CC 10IE CC10INT 00’0068H1AH

CAPCOM Register 11 CC11IR CC 11IE CC11INT 00’006CH1BH

CAPCOM Register 12 CC12IR CC 12IE CC12INT 00’0070H1CH

CAPCOM Register 13 CC13IR CC 13IE CC13INT 00’0074H1DH

CAPCOM Register 14 CC14IR CC 14IE CC14INT 00’0078H1EH

CAPCOM Register 15 CC15IR CC 15IE CC15INT 00’007CH1FH

CAPCOM Register 16 CC16IR CC 16IE CC16INT 00’00C0H30H

CAPCOM Register 17 CC17IR CC 17IE CC17INT 00’00C4H31H

CAPCOM Register 18 CC18IR CC 18IE CC18INT 00’00C8H32H

CAPCOM Register 19 CC19IR CC 19IE CC19INT 00’00CCH33H

CAPCOM Register 20 CC20IR CC 20IE CC20INT 00’00D0H34H

CAPCOM Register 21 CC21IR CC 21IE CC21INT 00’00D4H35H

CAPCOM Register 22 CC22IR CC 22IE CC22INT 00’00D8H36H

CAPCOM Register 23 CC23IR CC 23IE CC23INT 00’00DCH37H

CAPCOM Register 24 CC24IR CC 24IE CC24INT 00’00E0H38H

CAPCOM Register 25 CC25IR CC 25IE CC25INT 00’00E4H39H

CAPCOM Register 26 CC26IR CC 26IE CC26INT 00’00E8H3AH

CAPCOM Register 27 CC27IR CC 27IE CC27INT 00’00ECH3BH

CAPCOM Register 28 CC28IR CC 28IE CC28INT 00’00E0H3CH

CAPCOM Register 29 CC29IR CC 29IE CC29INT 00’0110H44H

CAPCOM Register 30 CC30IR CC 30IE CC30INT 00’0114H45H

CAPCOM Register 31 CC31IR CC 31IE CC31INT 00’0118H46H

CAPCOM Timer 0 T0IR T0IE T0INT 00’0080H20H

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C167CR-16RM

CAPCOM Timer 1 T1IR T1IE T1INT 00’0084H21H

CAPCOM Timer 7 T7IR T7IE T7INT 00’00F4H3DH

CAPCOM Timer 8 T8IR T8IE T8INT 00’00F8H3EH

GPT1 Timer 2 T2IR T2 IE T2INT 00’0088H22H

GPT1 Timer 3 T3IR T3 IE T3INT 00’008CH23H

GPT1 Timer 4 T4IR T4 IE T4INT 00’0090H24H

GPT2 Timer 5 T5IR T5 IE T5INT 00’0094H25H

GPT2 Timer 6 T6IR T6 IE T6INT 00’0098H26H

GPT2 CAPREL Register CRIR CRIE CRINT 00’009CH27H

A/D Conversi on Complete ADCIR ADCIE ADCINT 00’00A0H28H

A/D Overrun Error ADEIR ADEIE AD EINT 00’00A4H29H

ASC0 Transmit S0TIR S0TIE S0T INT 00’00A8H2AH

ASC0 Transmit Buffer S0TBIR S0TBIE S0TBINT 00’011CH47H

ASC0 Receive S0RIR S0RIE S0RINT 00’00ACH2BH

ASC0 Error S0EIR S0EIE S0EIN T 00’00B0H2CH

SSC Transmit SCTIR SCTIE SCTINT 00’00B4H2DH

SSC Receive SCRIR SCRIE SCRINT 00’00B8H2EH

SSC Error SCEIR SCEIE SCEINT 00’00BCH2FH

PWM Channel 0...3 PWMIR PWMIE PWMINT 00’00FCH3FH

CAN Interface XP0I R XP0 IE XP0INT 00’010 0H40H

X-Peripheral Node XP1IR XP1IE XP1INT 00’0104H41H

X-Peripheral Node XP2IR XP2IE XP2INT 00’0108H42H

PLL Unlock XP3IR X P3IE XP3INT 00’010CH43H

Source of Interrupt or

PEC Service Request Request

Flag Enable

Flag Interrupt

Vector Vector

Location Trap

Number

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Semiconductor Group 18

C167CR-16RM

The C167CR-16RM also provides an excellent mechanism to identify and to p rocess exceptions or

error conditions that arise during run-time, so-called ‘Hardware Traps’. Hardware traps cause

immediate non-maskable system reaction which is similar to a standard interrupt service (branching

to a dedic ated vector t able locati on). Th e occur ence of a hardware tr ap is ad ditionall y signified by

an indivi dual bit in the trap flag r egister (TFR ). Exce pt when another higher priori tized trap ser vice

is in progr ess, a hardwar e trap will interr upt any actual program execution. In turn, hardw are trap

services can normally not be interrupted by standard or PEC inter rupts.

The following table shows all of the possible exceptions or error conditions that can arise during run-

tim e:

Exception Condition Trap

Flag Trap

Vector Vector

Location Trap

Number Trap

Priority

Reset Functions:

Har dware Reset

Software Reset

Watchdog Timer Overflow

RESET

00’0000H

00H

III

Class A Hardware Traps:

Non-Mas kable Interrupt

Stack Overflow

Stack Underflow

NMI

STKOF

STKUF

NMITRAP

STOTRAP

STUTRAP

00’0008H

00’0010H

00’0018H

02H

04H

06H

II

Class B Hardware Traps:

Undefined Opc ode

P rotected Instruction

Fault

Illegal Word Operand

Access

Illegal Instruction Ac cess

Illegal External Bus

Access

UNDOPC

PRTFLT

ILLOPA

ILLINA

ILLBUS

BTRAP

00’0028H

0AH

I

Reserved [2CH – 3CH][0B

H

– 0FH]

Software Traps

TRAP Instruction Any

[00’0000H –

00’01FCH]

in steps

of 4H

Any

[00H – 7FH]Current

CPU

Priority

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C167CR-16RM

Capture/Compare (C APCOM) Units

The CAPCOM units support generation and control of timing sequences on up to 32 chan nels with

a max imum resoluti on of 400 ns (at 20-M Hz sys tem clock) . The CAPC OM units are typic ally us ed

to handle high speed I/O tasks such as pulse and waveform generation, pulse width modulation

(PMW), Digital to Analog (D/A) conversion, software timing, or time recording relative to external

events.

Four 16-bit timers ( T0/T1, T7/T8) with reloa d registers provide tw o independent time bases for th e

capture/compare r egister array.

The input clock for the timers is pr ogrammable to several prescaled values of the internal sys tem

clock, or may b e derived from an overflow /underflow of timer T6 in modul e GPT2. This provi des a

wide range of variation for the timer period and resolution and allows precise adjustments to the

application specific requirements. In addition, exte rnal count inpu ts for CAPCOM timers T0 and T7

allow event scheduling for the capture/com pare registers r elative to ex ternal events.

Both of the two capture/compare register arrays contain 16 dual purpose capture/compare

re gister s, each of which may be individually allocated to either CAPCOM timer T0 or T1 (T7 or T8,

respectively), and programmed for capture or compare function. Each register has one port pin

associated with it which serves as an input pin for triggering the capture function, or as an output pin

(except for C C24...CC27) to indicate the occure nce of a compare event.

When a captur e /compare r egister has been selected for capture mode, the current contents of the

allocated timer will be latched (‘capture’d) into the capture/compare register in response to an

external event at the port pi n whi ch is associated wit h this register . In addition, a speci fic i nterru pt

request for this capture/compare register is generated. Either a positive, a negative, or both a

positive and a negative external signal transition at the pin can be selected as the triggering event.

The contents of all registers which have been selected for one of the five compare modes are

continuously compared with the contents of the allocated timers. When a match occurs between the

timer value and the value in a capture/compare register, specific actions will be taken based on the

selected compare m ode.

Compare Modes Function

Mode 0 Interrupt-only compare mode;

several compare interrupts per timer period are possible

Mode 1 Pin toggles on each compare matc h;

several compare events per timer period ar e possible

Mode 2 Interrupt-only compare mode;

only one compare interrupt per timer per iod is generated

Mode 3 Pin set ‘1’ on matc h; pin res et ‘0’ on compare time overflow;

only one compare event per timer period is generated

Double

Register Mode Two registers operate on one pin; pin toggles on each compare m atch;

several compare events per timer period ar e possible.

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Semiconductor Group 20

C167CR-16RM

Figure 5

CAPCOM Unit Block Diagram

*)

*) 12 outputs on CAPCOM2

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21 Semiconductor Gr oup

C167CR-16RM

P WM Module

The Pulse Width Modulation Module can generate up to four PWM output signals using edge-

aligned or center-aligned PWM. In addition th e PWM mod ule can generate PWM b urst signals and

single shot outputs. The frequency range of the PWM signals covers 4.8 H z to 1 MH z (referred t o

a CPU cl ock of 20 MHz), depending on the resoluti on of the PWM output signal. The l evel of the

output signals is selectable and the PWM module can generate inter rupt req uests.

General Purpose T imer (GPT ) U nit

The GPT unit repr esents a very flexible mul tifunctional timer/counter str ucture whi ch may be us ed

for many different time related tasks such as event timing and counting, pulse width and duty cycle

measur ements, pulse generation, or pulse multiplicatio n.

The GPT unit incorporates five 1 6- bit timers w hich are or ganized in two s epar ate modules, GPT 1

and GPT2. Each timer in each module may operate independently in a number of d ifferent modes,

or may be concatenated with another timer of the same module.

Each of the three timers T2, T3, T4 of module GPT1 can be configured individually for one of four

basic modes of operation, which are Timer, Gated Timer, Counter, and Incremental Interface Mode.

In Timer Mode, the input clock for a timer is derived from the CPU clock, divided by a programmable

prescaler, whi le Counter Mode allows a timer to be clocked in reference to external events.

Pulse width or duty cyc le measurement is supported in Gated T imer Mode, where the operation of

a timer is controlled by the ‘gate’ level on an external input pin. For these pu rposes, each ti mer has

one associated port pin (TxIN) which serves as gate or clock input. The maximum resolution of the

timers in module GPT1 is 400 ns (@ 20-MHz CPU clock).

The count direction (u p/dow n) for each timer is program mable by software or may additionall y be

altered dynamically by an external signal on a port pin (TxEUD) to facilitate eg. position tracking.

In Incremental Interface Mode the GPT1 timers (T2, T3, T4) can be directly connected to the

incremental posi tion sensor signals A and B via their respective inputs TxIN and TxEUD. Directi on

and count signals are internally derived from these two input signals, so the contents of the

respective timer Tx corresponds to the sensor position. The thir d position sensor signal TOP0 can

be connected to an interrupt input.

Timers T3 and T4 have output togg le latches (TxOTL) which change their state on each ti mer ove r-

flow/underflow. The state of these latches may be output on port pins (TxOUT) eg. for time out

monitor ing of external hardw are components, or m ay be used internall y to clock timers T2 and T 4

for measuring l ong time periods w ith high resoluti on.

In addition to t heir basic operating modes, timers T2 and T4 may be configured as reload or capture

registers for timer T3. When used as capture or reload registers, timers T2 and T4 are stoppe d. The

contents of tim er T3 is captured into T2 or T 4 in r esponse to a signal at t heir associ ated input pins

(TxIN ) . Tim er T3 is rel o aded with the contents of T2 or T4 tr iggered either by an external signal or

by a selec tabl e state transitio n of its toggle latc h T 3OTL. When both T2 and T4 are configured to

alternately reload T3 on opposite state transitions of T3OTL with the low and high tim es of a PWM

signal, this s ignal can be constantly generated without softw are intervention.

With its maximum resolution of 200 ns (@ 20 MHz), the GPT2 module provides precise event

control and time measurement. It includes two timers (T5, T6) and a capture/reload register

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Semiconductor Group 22

C167CR-16RM

(CAPREL). Both timers can be clocked with an input clock which is derived from the CPU clock via

a programmabl e prescaler or wi th external signals. T he count direction (up/dow n) for each timer is

programmable by software or may additionally be altered dynamically by an external signal on a

port pin ( TxEUD). Conc atenation of the timers is s up ported via the output toggle latch ( T6OTL) o f

timer T6, which changes its state on each timer overflow/underflow .

The sta te of this latch may be used to clock timer T5, and /or it may be output on a port pin (T6OUT).

The overflow s/underfl ows of timer T6 can ad ditionally be used to clock the CAPCOM timer s T0 or

T1, and to cause a reload from the CAPREL register. The CAPREL register may capture the

contents of timer T5 based on an external signal transi tion on the corr esponding port pin (C APIN),

and timer T5 may optionally be cleared after the capture procedure. This allows absolute time

differences to be measured or pulse multi plication to be performed without software overhead.

The capture tr igger (timer T5 to CAPR EL) may also be generated upon transitions of GPT1 timer

T3’s inputs T3IN a nd/or T3EUD. This is especially advantageo us when T3 operates in Incremental

Interface Mode.

Figure 6

Block Diagram of GPT1

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23 Semiconductor Gr oup

C167CR-16RM

Figure 7

Block Diagram of GPT2

Watchdog Timer

The Watchdog Timer represents one of the fail-safe mechanisms which have been i mplemented to

prevent the controller from malfunc tioning for longer periods of time.

The Watchdog Timer is always enabled after a reset of the chip, and can only be disabled in the time

interval until the EINIT (end of initializat ion) instruction has be en e xecuted. Thus, the chip’s start-up

procedure is always monitored. The software has to be designed to service the Watchdog Timer

before it overfl ows. If, due to hardware or software r elated failures, the softw are fails to do so, the

Watchdog Timer overflows and generates an internal hardware reset and pulls the RSTOUT pin low

in order to allow external hardware com ponents to be reset.

The Watchdog Timer is a 16-bit ti mer , clocked with the system clock divided either by 2 or by 128.

The high byte of the W atchdog Timer regis ter can be s et to a pres pecified reload value (store d in

WDTR EL) in order to allow further variation of the monitored tim e interval. Each time it is ser vice d

by the application s oftwar e, the high byte of the Watchdog T imer is r eloaded. Thus , time inter vals

between 25 µs and 420 m s can be monitored (@ 20 M Hz). T he default Watchdog Timer interval

after reset is 6.55 ms (@ 20 MHz).

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Semiconductor Group 24

C167CR-16RM

A/D Converter

For analog s ignal measurement, a 10- bit A/D converter with 1 6 multiplexed input channels and a

sample and hold circuit has been integrated on-chip. It uses the method of successive

approximation. The sample time (for loading the capacitors) and the conversion time is

program mable and can so be adjusted to the external circuitry.

Overrun error detection/protection is provided for the conversion result register (ADDAT): either an

interrupt request wil l be gene rated when the result of a previous conversion has not been read from

the result regist er at the time the next con version is complete, or the next conversion is suspended

in such a case until the previous res ult has been read.

For applications which require less than 16 analog input channels, the remaining channel inputs can

be used as digital input port pins.

The A/D converte r of the C167CR-16RM supports four different conversion modes. In the standard

Single Channel conversion mode, the analog level on a specified channel is sampled once and

converted to a digital result. In the Single Channel Continuous mode, the analog level on a specified

channel is repeatedly sampled and converted without software intervention. In the Auto Scan mode,

the analog levels on a prespecified number of channels are sequentially sampled and converted. In

the Auto Scan Contin uous mode, the number of prespecified channels is repeatedly sam pled an d

converted. In addition, the conversion of a specific channel can be inserted (injected) in to a running

sequence without disturbing this sequence. This is called Channel Injection Mode.

The Peripher al Event Controller (P EC) may be used t o autom atically store the conver sion results

into a table in memory for later evaluation, without requiring the overhead of entering and exiting

interrupt routines for eac h data transfer.

After each reset and also during normal operation the ADC automatically performs calibration

cycles. This automatic self-calibration constantly adjusts the converter to changing operating

conditions (eg. temperature) and compensates process vari ations.

These calibration cycles are part of the con version cycle, so they do not affect the normal operation

of the A/D converter.

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25 Semiconductor Gr oup

C167CR-16RM

Serial Channels

Serial communication with other microcontrollers, processors, terminals or external peripheral

components is provided by two serial interfaces with different functionality, an Asynchronous/

Synchronous Serial Channel (ASC0) and a High- Speed Synchronous Serial Channel (SSC).

The A SC0 is upw ard compatibl e with th e seri al ports of the S iem ens 8-bit mi crocontrol ler fami lies

and supports full-duplex asynchronous communication at up to 625 KBaud and half-duplex

synchronous communication at up to 2.5 M Baud @ 20 MHz CPU clock.

A dedicated b aud rate generator allow s to s et up all s ta ndard baud rates without oscillator tuning .

For transmission, reception and error handling 4 separate interrupt vectors are provided. In

asynchronous mode, 8- or 9-bit data frames are transmitted or received, preceded by a start bit and

terminated by one or two stop bits. For multiprocessor communication, a mechanism to distinguish

address from data bytes has been included (8- bit data plus wake up bit m ode).

In synchronous mode, the ASC0 transmits or receives bytes (8 bits) sync hronously to a s hift clock

which is generated by the ASC0. The ASC0 always shifts the LSB first. A loop back option is

available for testing purposes.

A number of optional hardware error detection capabilities has been included to increase the

reliability of data transfers. A parity bit can automatically be generated on transmission or be

checked on reception. Framing error detecti on allows to recogniz e data fram es with mis sing stop

bits. An overrun error will be generated, if the l ast character received has not been r ead out of the

receive buffer register at the time the reception of a new character is complete.

The SSC supports full-duplex synchronous communication at up to 5 Mbaud @ 20 MHz CPU clock.

It may be configured s o it interfaces with ser iall y linked per ipheral com ponents. A dedi cated baud

rate generator allows to set up all standard baud rates without oscill ator tuning. For transm ission,

reception and error handling 3 separate interrupt vector s are provi ded.

The SSC transmits or receives characters of 2...16 bits length synchronously to a shift clock which

can b e generated by th e SSC (maste r mode) or b y an external maste r (sla ve mode). The SSC can

start shifting with the LSB or with the MSB and allows the selection of shifting and latching clock

edges as well as the cloc k polarity.

A number of optional hardware error detection capabilities has been included to increase the

reliability of data transfers. Transmit and receive error supervise the correct handling of the data

buffer. Phase and baudrate error detect incorrect serial data.

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Semiconductor Group 26

C167CR-16RM

CAN-Module

The integrated CAN-Module handles the completely autonomous transmission and reception of

CAN frames in accordance with the CAN specification V2.0 part B (active), ie. the on-chip CAN-

Module can receive and transmit stan dard frames with 11-bit identifiers as well as extended frames

with 29-bit identifiers.

The module provides Full CAN functionality on up to 15 message objects. Message object 15 may

be configured for Basic CAN functionality. Both modes provide separate masks for acceptance

filtering which allows to accept a number of identifiers in Full CAN mode and also allows to disregard

a number of identifiers in Basic CAN mode. All me ssage objects can be updated independent f rom

the other objects and are equipped for the maximum m essage length of 8 bytes.

The bit tim ing is derived from the XCLK and is progr ammabl e up to a data rate of 1 MBaud. Th e

CAN -Module uses two pins of Port 4 to interface to a bus transcei ver.

Note: When the CAN interface is to be used the segment address output on Port 4 must be li mited

to 4 bits, ie. A19...A16. This is necessary to enable the alternate function of the CAN

interface pins.

Parallel Ports

The C167CR-16R M provides up to 111 I/O lines which are or ganized into eight input/output ports

and one i nput port. All port lines are bit-addressa ble, and all i nput/output lines are individually (bit-

wise) programmable as inpu ts or o utputs via direction registers. The I/O ports are true bidirectional

ports which are switched to high impedance state when configured as inputs. The output drivers of

five I/O por ts c an be configured (pin by pin) for push/pull operation or open- drain operation vi a

control register s. During the inter nal reset, all port pins are configured as inputs.

The input threshold of Port 2, Port 3, Port 7 and Port 8 is selectable (TTL or CMOS like), where the

special CMO S like input threshold reduces noise sensiti vity due to the input hysteresis. The input

threshold may be select e d indivi dually for each byte of the respective por ts.

All port lines have program mable alternate input or output functions ass ociated with them .

PORT0 and PORT1 may be used as address and data lines when accessing external memory,

while Port 4 outputs the additional segment address bits A23/19/17...A16 in systems where

segmentation is enabled to access more than 64 KBytes of m emory.

Port 2, Port 8 and Port 7 are associate d with t he capture inputs or compare outputs of the CAPCOM

units and/or with the outputs of the PWM module.

Port 6 provi des optional bus arbitrati on signals (BREQ, HLDA, HOLD) and chip select signals.

Port 3 includes alternate fu nctions of timer s, s erial inter faces, the optional bus contr ol signal BHE

and the syst em clock output (CLKOUT ).

Port 5 is used for the analog input channels to the A/D converter or timer control signals.

All port lines that are not used for these alternate functions may be used as general purpose IO

lines.

20D ec96 @09 :2 5h In ter med iate Version

27 Semiconductor Gr oup

C167CR-16RM

Instruction Set Summary

The table below l ists the instructions of the C167CR-16RM in a condensed w ay.

The various addressing modes that can be used with a specific instruction, the operation of the

instructions, parameters for conditional execution of instructions, and the opcodes for each

instruction can be found in the “C16x Family Instruction Set Manual”.

This docum ent also provides a detailled desc ription of each instr uction.

Instruction Set Summary

Mnemonic Description Bytes

ADD (B) Add word (byte) operands 2 / 4

ADDC(B) Add word (byte) operands with Carry 2 / 4

SUB(B) Subtract word (byte) operands 2 / 4

SUBC(B) Subtract word (byte) operands with C arr y 2 / 4

MU L(U) (Un)Signed multiply direct GPR by dir ect GPR (16-16-bit) 2

DIV(U) (Un)Signed divide register MDL by direct GPR (16-/16-bit) 2

DIVL(U) (Un)Signed long divide reg. M D by direct GPR (32- /16-bit) 2

CPL(B) Complement direct word (byte) GPR 2

NEG(B) Negate direct w ord (byte) GPR 2

AND(B) Bitwise AND, ( word/byte operands) 2 / 4

OR(B) Bitwis e OR, (word/byte operands) 2 / 4

XOR(B) Bitwise XOR, (word/byte operan ds) 2 / 4

BCL R Clear direct bit 2

BSET Set direct bit 2

BMOV(N) Move (negated) direct bit to direct bit 4

BAND, BOR, BXOR AND/OR/XOR direct bit with direct bit 4

BCMP Compare direct bit to direct bit 4

BFLDH/L Bitwise modify m asked high/low byte of bi t-addressable

direct word memory with immediate data 4

CMP(B) Compare word (byte) operands 2 / 4

CMPD1/2 Compare word data to GPR and decr ement GPR by 1/2 2 / 4

CMPI1/2 Compar e word data to GPR and increment GPR by 1/2 2 / 4

PRIOR Determine number of shift cycles to normalize direct

word GPR and store result in direct word GPR 2

SHL / SHR Shift left/right direct word GPR 2

ROL / ROR Rot ate left/right direct word GPR 2

ASHR Arithmetic ( sign bit) shift right direct word GPR 2

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Semiconductor Group 28

C167CR-16RM

MOV(B) Move word (byte) data 2 / 4

MOVBS Move byte operand to w ord operand with si gn extension 2 / 4

MOVBZ Move byte operand to word operand. with zer o extension 2 / 4

JMPA, JMPI, JMPR Jump absolute/indirect/relative if condi tion is met 4

JMPS Jump absolute to a code segment 4

J(N)B Jump relative if direc t bit is (not) set 4

JBC Jump relative and clear bit if direct bit is set 4

JNBS Jump rel ative and set bit if dir ect bit is n ot set 4

CALLA, CALLI, CALLR Call absolute/indirect/rel ative subroutine if condi tion is met 4

CALLS Call absolute subroutine i n an y code segm ent 4

PCALL Push dir ect word r egister onto system stack and call

absolute subroutine 4

TRAP Call interrupt service routine via im mediate trap number 2

PUSH, POP Push/pop direct word r egister onto/from system s tac k 2

SCXT Push direct word register onto system stack und update

register with word operand 4

RET Return from intra-segment subroutine 2

RETS Re turn from inter-segment subroutine 2

RETP Ret urn from intr a-segment s ubroutine and pop direct

word register fr om system stack 2

RETI Re turn from interrupt service subroutine 2

SRST Software Reset 4

IDLE Enter Idle Mode 4

PWR DN Enter Power Dow n Mode

(supposes NMI-pin bei ng l ow) 4

SR VWD T Se rvice Watch dog Tim er 4

DISWDT Disable Watchdog Timer 4

EINIT Signify End-of-Initial izatio n on RSTOUT- p in 4

ATOM IC Begin ATOM IC sequence 2

EXTR Begin EXTended Regis ter sequence 2

EXTP(R) Begin EXTended Page (and Register) sequence 2 / 4

EXTS(R) Begin EXTended Segment (an d Register) sequence 2 / 4

NOP Null operation 2

Instruction Set Summary (cont’d)

Mnemonic Description Bytes

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29 Semiconductor Gr oup

C167CR-16RM

Special Functio n Registers Overview

The following table lists all SFRs which are implemented in the C167CR-16RM in alphabetical

order.

Bit-addressable SFRs are marked with the letter “b” in column “Name”. SFRs within the Extended

SFR-Space ( ESFRs) are marked with the letter “E” i n column “P hy sical Address”.

An SFR can be specified via its individual mnemonic name. Depending on the selected addressing

mode, an SFR can be accessed via its physical address (using the Data Page Pointers), or via its

short 8-bit address (wi thout using the Data Page Poi nters) .

Special Functio n Registers Overview

Name Physical

Address 8-Bit

Address Description Reset

Value

ADCIC b FF98HCCHA/D Converter E nd of Conversion Interrupt

Control Register 0000H

ADCON b FFA0HD0HA/D Converter Control Regi ster 0 000H

ADDAT FEA0H50HA/D Converter Result Register 0000H

ADDAT2 F0A0HE50HA/D Converter 2 Result Register 0000H

ADDRSEL1 FE18H0CHAddress Select Register 1 0000H

ADDRSEL2 FE1AH0DHAddress Select Register 2 0000 H

ADDRSEL3 FE1CH0EHAddress Select Register 3 0000 H

ADDRSEL4 FE1EH0FHAddress Select Register 4 0000H

ADEIC b FF9AHCDHA/D Converter Overrun Error Interrupt Control

Register 0000H

BUSCON0 b FF0CH86HBus Configuration Register 0 0XX0 H

BUSCON1 b FF14H8AHBus Configuration Register 1 0000H

BUSCON2 b FF16H8BHBus Configuration Register 2 0000H

BUSCON3 b FF18H8CHBus Configuration Register 3 0000H

BUSCON4 b FF1AH8DHBus Configuration Register 4 0000H

CAPREL FE4AH25HGPT2 Capture/Reload Register 0000H

CC0 FE80H40HCAPCOM Register 0 0000H

CC0IC b FF78HBCHC APCOM Register 0 Interr upt Control Register 0000H

CC1 FE82H41HCAPCOM Register 1 0000H

CC1IC b FF7AHBDHCAPCOM Register 1 Interr upt Control Register 0000H

CC2 FE84H42HCAPCOM Register 2 0000H

CC2IC b FF7CHBEHCAPCOM Register 2 Interrupt Control Register 00 00H

20Dec96@09:25h Intermediate Version

Semiconductor Group 30

C167CR-16RM

CC3 FE86H43HCAPCOM Register 3 0000H

CC3IC b FF7EHBFHC APCOM Register 3 Interr upt Control Register 0000H

CC4 FE88H44HCAPCOM Register 4 0000H

CC4IC b FF80HC0HCAPCOM Register 4 Interrupt Control Register 0000H

CC5 FE8AH45HCAPCOM Register 5 0000H

CC5IC b FF82HC1HCAPCOM Register 5 Interrupt Control Register 0000H

CC6 FE8CH46HCAPCOM Register 6 0000H

CC6IC b FF84HC2HCAPCOM Register 6 Interrupt Control Register 0000H

CC7 FE8EH47HCAPCOM Register 7 0000H

CC7IC b FF86HC3HCAPCOM Register 7 Interrupt Control Register 0000H

CC8 FE90H48HCAPCOM Register 8 0000H

CC8IC b FF88HC4HCAPCOM Register 8 Interrupt Control Register 0000H

CC9 FE92H49HCAPCOM Register 9 0000H

CC9IC b FF8AHC5HCAPCOM Register 9 Interrupt Control R egister 0000H

CC10 FE94H4AHCAPC OM Regi ster 10 0000H

CC10IC b FF8CHC6HCAPCOM Register 10 Interrupt Control Register 0000H

CC11 FE96H4BHCAPC OM Regi ster 11 0000H

CC11IC b FF8EHC7HCAPCOM Register 11 Interr upt Control R egister 0 000H

CC12 FE98H4CHCAPCOM Register 12 0000 H

CC12IC b FF90HC8HCAPCOM Register 12 Interr upt Control R egister 0 000H

CC13 FE9AH4DHCAPCOM Register 13 0000H

CC13IC b FF92HC9HCAPCOM Register 13 Interr upt Control R egister 0 000H

CC14 FE9CH4EHCAPCOM Register 14 0000H

CC14IC b FF94HCAHCAPCOM Register 14 Interr upt Control R egister 0 000H

CC15 FE9EH4FHCAPCOM Register 15 0000 H

CC15IC b FF96HCBHCAPCOM Register 15 Interr upt Control R egister 0 000H

CC16 FE60H30HCAPCOM Register 16 0000H

CC16IC b F160HEB0HCAPCOM Register 16 Interr upt Control R egister 0 000H

CC17 FE62H31HCAPCOM Register 17 0000H

Special Functio n Registers Overview (cont’d)

Name Physical

Address 8-Bit

Address Description Reset

Value

20D ec96 @09 :2 5h In ter med iate Version

31 Semiconductor Gr oup

C167CR-16RM

CC17IC b F162HEB1HCAPCOM Register 17 Interr upt Control R egister 0 000H

CC18 FE64H32HCAPCOM Register 18 0000H

CC18IC b F164HEB2HCAPCOM Register 18 Interr upt Control R egister 0 000H

CC19 FE66H33HCAPCOM Register 19 0000H

CC19IC b F166HEB3HCAPCOM Register 19 Interr upt Control R egister 0 000H

CC20 FE68H34HCAPCOM Register 20 0000H

CC20IC b F168HEB4HCAPCOM Register 20 Interr upt Control R egister 0 000H

CC21 FE6AH35HCAPC OM Register 21 00 00H

CC21IC b F16AHEB5HCAPCOM Register 21 Interrupt Control Register 0000H

CC22 FE6CH36HC APCOM Register 22 0000H

CC22IC b F16CHEB6HCAPC OM Register 22 Interrupt Contr ol Register 0000H

CC23 FE6EH37HCAPC OM Register 23 00 00H

CC23IC b F16EHEB7HCAPCOM Register 23 Interrupt Control Register 0000H

CC24 FE70H38HCAPCOM Register 24 0000H

CC24IC b F170HEB8HCAPCOM Register 24 Interr upt Control R egister 0 000H

CC25 FE72H39HCAPCOM Register 25 0000H

CC25IC b F172HEB9HCAPCOM Register 25 Interr upt Control R egister 0 000H

CC26 FE74H3AHCAPC OM Regi ster 26 0000H

CC26IC b F174HEBAHCAPCOM Register 26 Interrupt Control Register 0000H

CC27 FE76H3BHCAPC OM Regi ster 27 0000H

CC27IC b F176HEBBHCAPCOM Register 27 Interrupt Control Register 0000H

CC28 FE78H3CHCAPCOM Register 28 0000 H

CC28IC b F178HEBCHCAPC OM Register 28 Interrupt Contr ol Register 0000H

CC29 FE7AH3DHCAPCOM Register 29 0000H

CC29IC b F184HEC2HCAPCOM Register 29 Interrupt Contr ol Register 0000H

CC30 FE7CH3EHCAPCOM Register 30 0000H

CC30IC b F18CHEC6HCAPCOM Register 30 Interr upt Control R egister 0 000H

CC31 FE7EH3FHCAPCOM Register 31 0000 H

CC31IC b F194HECAHCAPCOM Register 31 Interrupt Control Register 0000H

Special Functio n Registers Overview (cont’d)

Name Physical

Address 8-Bit

Address Description Reset

Value

20Dec96@09:25h Intermediate Version

Semiconductor Group 32

C167CR-16RM

CCM0 b FF52HA9HCAPCOM Mode Control Register 0 0000H

CCM1 b FF54HAAHCAPCOM Mode Control Register 1 0000H

CCM2 b FF56HABHCAPCOM Mode Control Register 2 0000H

CCM3 b FF58HACHCAPCOM Mode Control Register 3 0000H

CCM4 b FF22H91HCAPCOM Mode Control Register 4 0000H

CCM5 b FF24H92HCAPCOM Mode Control Register 5 0000H

CCM6 b FF26H93HCAPCOM Mode Control Register 6 0000H

CCM7 b FF28H94HCAPCOM Mode Control Register 7 0000H

CP FE10H08HCPU Context Pointer Register FC 00H

CRIC b FF6AHB5HGPT2 CAPREL Interrupt Control Register 0000 H

CSP FE08H04HCPU Code Segment Pointer Register (read only) 0000H

DP0L b F100HE80HP0L Direction Control Register 00H

DP0H b F102HE81HP0H Direction Control Register 00H

DP1L b F104HE82HP1L Direction Control Register 00H

DP1H b F106HE83HP1H Direction Control Register 00H

DP2 b FFC2HE1HPort 2 Direction C ontrol Regi ster 0000H

DP3 b FFC6HE3HPort 3 Direction C ontrol Regi ster 0000H

DP4 b FFCAHE5HPort 4 Direction C ontrol Regi ster 00H

DP6 b FFCEHE7HPort 6 Direction C ontrol Regi ster 00H

DP7 b FFD2HE9HPort 7 Direction C ontrol Regi ster 00H

DP8 b FFD6HEBHPort 8 Direction C ontrol Regi ster 00H

DPP0 FE00H00HCPU Data Page Pointer 0 Register (10 bits) 0 000H

DPP1 FE02H01HCPU Data Page Pointer 1 Register (10 bits) 0 001H

DPP2 FE04H02HCPU Data Page Pointer 2 Register (10 bits) 0 002H

DPP3 FE06H03HCPU Data Page Pointer 3 Register (10 bits) 0 003H

EXICON b F1C0HEE0HExternal Interrupt Control Register 0000H

MDC b FF0EH87HCPU Multiply D ivide Control Register 0000H

MDH FE0CH06HCPU M ultiply Divide Register – High Word 00 00H

MDL FE0EH07HCPU Multiply Divide Register – Low Word 0000H

Special Functio n Registers Overview (cont’d)

Name Physical

Address 8-Bit

Address Description Reset

Value

20D ec96 @09 :2 5h In ter med iate Version

33 Semiconductor Gr oup

C167CR-16RM

ODP2 b F1C2HEE1HPor t 2 Op en Dr ain Control Register 0000H

ODP3 b F1C6HEE3HPor t 3 Op en Dr ain Control Register 0000H

ODP6 b F1CEHEE7HPor t 6 Op e n Drain Control Register 00H

ODP7 b F1D2HEE9HPor t 7 Op en Dr ain Control Register 00H

ODP8 b F1D6HEEBHPor t 8 Op e n Drain Control Register 00H

ONES FF1EH8FHConstant Value 1’s Register (read only) FFFF H

P0L b FF00H80HPort 0 Low Register (Lower half of PORT0) 00H

P0H b FF02H81HPort 0 High Register (Upper half of PORT 0) 00H

P1L b FF04H82HPort 1 Low Register (Lower half of PORT1) 00H

P1H b FF06H83HPort 1 High Register (Upper half of PORT 1) 00H

P2 b FFC0HE0HPort 2 Register 0000H

P3 b FFC4HE2HPort 3 Register 0000H

P4 b FFC8HE4HPort 4 Register (8 bits) 0 0H

P5 b FFA2HD1HPor t 5 Register (read only) XXXXH

P6 b FFCCHE6HPort 6 Register (8 bits) 00H

P7 b FFD0HE8HPort 7 Register (8 bits) 0 0H

P8 b FFD4HEAHPort 8 Register (8 bits) 00H

PECC0 FEC0H60HPEC Channel 0 Control Register 0000H

PECC1 FEC2H61HPEC Channel 1 Control Register 0000H

PECC2 FEC4H62HPEC Channel 2 Control Register 0000H

PECC3 FEC6H63HPEC Channel 3 Control Register 0000H

PECC4 FEC8H64HPEC Channel 4 Control Register 0000H

PECC5 FECAH65HPEC Channel 5 Control Regi ster 0000H

PECC6 FECCH66HPEC Channel 6 Control Register 0000H

PECC7 FECEH67HPEC Channel 7 Control Regi ster 0000H

PICON F1C4HEE2HPor t Input Threshold Control Register 0000H

PP0 F038HE1CHPWM Module Period Register 0 0000H

PP1 F03AHE1DHPWM M odule Period Regis ter 1 0000H

PP2 F03CHE1EHPWM M odule Period Regis ter 2 0000H

Special Functio n Registers Overview (cont’d)

Name Physical

Address 8-Bit

Address Description Reset

Value

20Dec96@09:25h Intermediate Version

Semiconductor Group 34

C167CR-16RM

PP3 F03EHE1FHPWM Module Period Register 3 0000H

PSW b FF10H88HCPU Program Status Word 0000H

PT0 F030HE18HPWM Module Up/Down Counter 0 0000H

PT1 F032HE19HPWM Module Up/Down Counter 1 0000H

PT2 F034HE1AHPWM Module Up/Down Counter 2 0000H

PT3 F036HE1BHPWM Module Up/Down Counter 3 0000H

PW0 FE30H18HPWM Module Pulse Width Register 0 0000H

PW1 FE32H19HPWM Module Pulse Width Register 1 0000H

PW2 FE34H1AHPWM M odule Pulse Width Register 2 0000H

PW3 FE36H1BHPWM M odule Pulse Width Register 3 0000H

PWMCON0 b FF30H98HPWM Module Control Register 0 0000H

PWMCON1 b FF32H99HPWM Module Control Register 1 0000H

PWMIC b F17EHEBFHPWM Module Interrupt Control Register 0000H

RP0H b F108HE84HSystem S tartup Configuration R egister (Rd. only) XXH

S0BG FEB4H5AHSerial Channel 0 Baud Rate Generator Reload

Register 0000H

S0CON b FFB0HD8HSerial Channel 0 Control Register 0000H

S0EIC b FF70HB8HSerial Channel 0 Error Interrupt Control Register 0000H

S0RBUF FEB2H59HSerial Channel 0 Receive Buffer Register

(read only) XXH

S0RIC b FF6EHB7HSerial Channel 0 Receive Interrupt Control

Register 0000H

S0TBIC b F19CHECEHSerial Channel 0 Transmit Buffer Interrupt Control

Register 0000H

S0TBUF FEB0H58HSerial Channel 0 Transmit Buffer Register

(write only) 00H

S0TIC b FF6CHB6HSerial Channel 0 Transmit Interr upt Control

Register 0000H

SP FE12H09HCPU System Stack Pointer Register FC00H

SSCBR F0B4HE5AHSSC Baudrate Register 0000H

SSCCON b FFB2HD9HSSC Control Register 0000H

Special Functio n Registers Overview (cont’d)

Name Physical

Address 8-Bit

Address Description Reset

Value

20D ec96 @09 :2 5h In ter med iate Version

35 Semiconductor Gr oup

C167CR-16RM

SSCEIC b FF76HBBHSSC Error Interrupt Control R egister 0000H

SSCRB F0B2HE59HSSC Receive Buffer (read only) XXXXH

SSCRIC b FF74HBAHSSC Receive Interrupt Control Register 0 000H

SSCTB F0B0HE58HSSC Transmit Buffer (write only) 0000H

SSCTIC b FF72HB9HSSC Transmit Interrupt Control Register 0000H

STKOV FE14H0AHCPU Stack Overflow Pointer Register FA00H

STKUN FE16H0BHCPU Stack Underflow Pointer Register FC00H

SYSCON b FF12H89HCPU System Configuration Register 0xx0H1)

T0 FE50H28HCAPCOM Timer 0 Register 0000H

T01CON b FF50HA8HC APCOM Timer 0 and Timer 1 Control Register 0000H

T0IC b FF9CHCEHCAPC OM Timer 0 Interrupt Control Register 0000H

T0REL FE54H2AHCAPCOM Timer 0 Rel oad Register 0000H

T1 FE52H29HCAPCOM Timer 1 Register 0000H

T1IC b FF9EHCFHCAPC OM Timer 1 Interrupt Control Register 0000H

T1REL FE56H2BHCAPCOM Timer 1 Rel oad Register 0000H

T2 FE40H20HGPT1 Timer 2 Register 0000H

T2CON b FF40HA0HGPT1 Timer 2 Control Register 0000H

T2IC b FF60HB0HGPT 1 Timer 2 Interrupt Control Register 0000H

T3 FE42H21HGPT1 Timer 3 Register 0000H

T3CON b FF42HA1HGPT1 Timer 3 Control Register 0000H

T3IC b FF62HB1HGPT 1 Timer 3 Interrupt Control Register 0000H

T4 FE44H22HGPT1 Timer 4 Register 0000H

T4CON b FF44HA2HGPT1 Timer 4 Control Register 0000H

T4IC b FF64HB2HGPT 1 Timer 4 Interrupt Control Register 0000H

T5 FE46H23HGPT2 Timer 5 Register 0000H

T5CON b FF46HA3HGPT2 Timer 5 Control Register 0000H

T5IC b FF66HB3HGPT 2 Timer 5 Interrupt Control Register 0000H

T6 FE48H24HGPT2 Timer 6 Register 0000H

T6CON b FF48HA4HGPT2 Timer 6 Control Register 0000H

Special Functio n Registers Overview (cont’d)

Name Physical

Address 8-Bit

Address Description Reset

Value

20Dec96@09:25h Intermediate Version

Semiconductor Group 36

C167CR-16RM

1) The system configur ation is selected duri ng reset.

2) Bit WDTR indic ates a watchdog timer triggered reset.

Note: The Interrupt Control Registers XPnIC are prepared to control interrupt requests from

integrated X-Bus peri pherals . Nodes, wher e no X-Per ipheral s are c onnected, may be us ed

to generate software controlled interrupt r equests by setting the respective XPnIR bit.

T6IC b FF68HB4HGPT 2 Timer 6 Interrupt Control Register 0000H

T7 F050HE28HCAPCOM Timer 7 Register 0000H

T78CON b FF20H90HCAPCOM Timer 7 a nd 8 Control Register 0000H

T7IC b F17AHEBEHCAPCOM Timer 7 Interrupt Control Register 00 00H

T7REL F054HE2AHCAPCOM Timer 7 Rel oad Register 0000H

T8 F052HE29HCAPCOM Timer 8 Register 0000H

T8IC b F17CHEBFHCAPCOM Timer 8 Interrupt Control Register 0000H

T8REL F056HE2BHCAPCOM Timer 8 Rel oad Register 0000H

TFR b FFACHD6HTrap Fl ag Register 0000H

WDT FEAEH57HWatchdog Timer Register (read only) 0000H

WDTCON FFAEHD7HWatchdog Timer Control Regis ter 000XH2)

XP0IC b F186HEC3HCAN Module Interrupt Control Register 0000H

XP1IC b F18EHEC7HX-Peripheral 1 Interrupt Control Register 0000H

XP2IC b F196HECBHX-Peripheral 2 Interrupt Control Register 0000H

XP3IC b F19EHECFHPLL Interrupt Control R egister 0000H

ZEROS b FF1CH8EHConstant Value 0’s Regis ter (read only) 0000 H

Special Functio n Registers Overview (cont’d)

Name Physical

Address 8-Bit

Address Description Reset

Value

20D ec96 @09 :2 5h In ter med iate Version

37 Semiconductor Gr oup

C167CR-16RM

Absolute Maximum Ratings

Ambient temperature under bias (TA):

SAB-C 167CR-16RM........................................................................................................0 to +70 ° C

SAF-C167CR-16RM....................................................................................................–40 to +85 °C

SAK-C167CR-16RM..................................................................................................–40 to +125 °C

Storage temperature (TST).........................................................................................– 65 to +150 °C

Voltage on VCC pins with respect to ground (VSS) ....................................................... –0.5 to +6.5 V

Voltage on any pin with respect to ground (VSS)...................................................–0.5 to VCC +0.5 V

Input current on any pin during overload condition.................................................... –10 to +10 mA

Absolute sum of all input currents during overload condition .............................................. |100 mA|

Power dissipation..................................................................................................................... 1.5 W

Note: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent

damage to the device. This is a stress ratin g only and functional operatio n of the device a t

these or any other conditions above those indicated in the operational sections of this

specification is not implied. Exposure to absolute maximum rating conditions for extended

periods may affect device reliability. During overload conditions (VIN>VCC or VIN<VSS) the

voltage on pins with respect to ground (VSS) must not exceed the values defined by the

Absolute Maximum Ratings.

Parameter Interpretation

The parameters listed in the following partly represent the characteristics of the C167CR-16RM and

partly its demands on the system. To aid in interpreting the parameters right, when evaluating them

for a design, they are marked in column “Symbol” :

CC (Controller Characteristics):

The logic of the C167CR-16RM will pr ovide signals w ith the respective timing characteri stics.

SR (System Requirement):

The external system must provide signals with the respective timing characteristics to the C167CR-

16RM.

20Dec96@09:25h Intermediate Version

Semiconductor Group 38

C167CR-16RM

DC Characteristics

VCC = 5 V ± 10 %; VSS = 0 V; fCPU = 20 MHz

TA = 0 to +70 °C for SAB-C167CR-16RM

TA = -40 to +85 °C for SAF-C167CR-16RM

TA = -40 to +125 °C for SAK- C167CR-16RM

Parameter Symbol Limit Values Unit Test Condition

min. max.

Input low voltage

(TTL) VIL SR – 0.5 0.2 VCC

– 0.1 V–

Input low voltage

(Special Threshold) VILS SR – 0.5 2.0 V –

Input high voltage, all except

RSTIN and XTAL1 (TTL) VIH SR 0.2 VCC

+ 0. 9 VCC + 0.5 V –

Input high voltage RSTIN VIH1 SR 0.6 VCC VCC + 0.5 V –

Input high voltage XTA L1 VIH2 SR 0.7 VCC VCC + 0.5 V –

Input high voltage

(Special Threshold) VIHS SR 0.8 VCC

- 0.2 VCC + 0.5 V –

Input Hysteresis

(Special Threshold) HYS 400 - mV –

Output low voltage

(PORT0, PORT1, Port 4, ALE, RD,

WR, BHE , CLKOUT, RSTOU T)

VOL CC – 0.45 V IOL = 2.4 mA

Output low voltage

(all other outputs) VOL1 CC – 0.45 V IOL1 = 1.6 mA

Output high voltage

(PORT0, PORT1, Port 4, ALE, RD,

WR, BHE , CLKOUT, RSTOU T)

VOH CC 0.9 VCC

2.4 –V

I

OH = – 500 µA

IOH = – 2.4 mA

Output high voltage 1)

(all other outputs) VOH1 CC 0.9 VCC

2.4 –V

V

I

OH = – 250 µA

IOH = – 1.6 mA

Input leakage current (Port 5) IOZ1 CC – ±200 nA 0.45V < VIN < VCC

Input leakage current (all other) IOZ2 CC – ±500 nA 0.45V < VIN < VCC

Overload curre nt IOV SR – ±5mA

5) 8)

RSTIN pullup resistor RRST CC 50 250 kΩ–

Read/Write inactive current 4) IRWH 2) –-40µAV

OUT = 2.4 V

Read/Write active current 4) IRWL 3) -500 – µAVOUT = VOLmax

ALE inactive current 4) IALEL 2) –40µAV

OUT = VOLmax

ALE active current 4) IALEH 3) 500 – µAVOUT = 2.4 V

Port 6 inactive curr ent 4) IP6H 2) –-40µAV

OUT = 2.4 V

20D ec96 @09 :2 5h In ter med iate Version

39 Semiconductor Gr oup

C167CR-16RM

Notes

1) Th is spe cifica tion is not v alid fo r ou tputs wh ich are sw itche d to o pe n drain mo de. In th is cas e the re spe ctive

o u tp ut wi ll flo a t an d the volt a ge re sult s from the externa l ci rc uitry.

2) Th e maximu m cur rent ma y be dra w n wh ile th e resp e ctiv e sign al line re m ain s ina c tive .

3) The minimum current must be drawn in order to drive the respective signal line active.

4) Th is sp ecific at ion is only v alid during Res et, or durin g Ho ld- or Adap t- mode . Po rt 6 pins are o nly a ffecte d, if

they are used for CS output and the ope n dra i n fu nct io n i s no t e n ab led.

5) Not 100% tested, guaranteed by design characterization.

6) The supply current is a function of the operating frequency. This dependency is illustrated in the figure below.

These parameters are tested at VCCmax and 20 MH z CP U cloc k with all ou tpu ts dis conne cted and all inp uts

at VIL or VIH.

7) Th is para meter is te sted in cluding leakag e curren ts. All inpu ts (inclu ding pin s con figu re d as inpu ts) at 0 V to

0.1 V or at VCC – 0.1 V to VCC, VREF = 0 V, all outputs (including pins configured as outputs) disconnected.

8) Overload conditions occur if the standard operatings conditions are exceeded, ie. the voltage on any pin

exceeds the specified range (ie. VOV >V

CC+0.5V or VOV <V

SS-0.5V). The absolute sum of input overload

c urr en ts on all po rt pins ma y no t ex ce e d 50 m A. Th e sup p ly volt age mu st rem a in wit hin t he spe cif ied lim its.

Port 6 active current 4) IP6L 3) -500 – µAVOUT = VOL1max

PORT0 configuration current 4) IP0H 2) –-10µAV

IN = VIHmin

IP0L 3) -100 – µAVIN = VILmax

XTAL1 input current IIL CC – ±20 µA 0 V < VIN < VCC

Pin capacitance 5)

(digital inputs/outputs) CIO CC – 10 pF f = 1 MHz

TA = 25 °C

Power supply cur rent ICC – 20 +

5 * fCPU

mA RSTIN = VIL2

fCPU in [MHz] 6)

Idle mode supply curr ent IID – 20 +

2 * fCPU

mA RSTIN = VIH1

fCPU in [MHz] 6)

Power-down m ode supply curr ent IPD –100µAV

CC = 5.5 V 7)

Parameter Symbol Limit Values Unit Test Condition

min. max.

20Dec96@09:25h Intermediate Version

Semiconductor Group 40

C167CR-16RM

Figure 8

Supply/Idle C urrent as a F unction of Operating Frequ ency

AA

AAAA

AA

AAAA

AA

AAAA

AA

I [mA]

fCPU [MHz]

510 15 20

150

100

50

10

ICCtyp

IIDmax

ICCmax

IIDtyp

AA

AAAA

AA

20D ec96 @09 :2 5h In ter med iate Version

41 Semiconductor Gr oup

C167CR-16RM

A/D Converter Characteristics

VCC = 5 V ± 10 %; VSS = 0 V

TA = 0 to +70 °C for SAB-C167CR-16RM

TA = -40 to +85 °C for SAF-C167CR-16RM

TA = -40 to +125 °C for SAK-C167CR-16RM

4.0 V ≤ VAREF ≤ VCC+0.1 V ; VSS-0.1 V ≤ VAGND ≤ VSS+0.2 V

Sample time and conversion time of the C167CR-16RM’s ADC are programmable. The tab le below

should be used to calculate the above tim ings.

Parameter Symbol Limit Values Unit Test Condition

min. max.

Analog in put voltage range VAIN SR VAGND VAREF V1)

Sample time tSCC – 2 tSC 2) 4)

Conversion time tCCC – 14 tCC +

tS + 4TCL

3) 4)

Total unadjusted error T U E CC – ± 2LSB

5)

Internal resistance of reference

voltage source RAREF SR – tCC / 165

- 0.25 kΩtCC in [ns] 6) 7)

Internal resistance of analog

source RASRC SR – tS / 330

- 0.25 kΩtS in [ns] 2) 7)

ADC input capacitance CAIN CC – 33 pF 7)

ADCON.15|14

(ADCTC) Co n version cloc k tCC ADCON.13|12

(ADSTC) Sample clock tSC

00 TCL * 24 00 tCC

01 Reserv ed , do no t use 0 1 tCC * 2

10 TCL * 96 10 tCC * 4

11 TCL * 48 11 tCC * 8

20Dec96@09:25h Intermediate Version

Semiconductor Group 42

C167CR-16RM

Notes

1) VAIN may exceed VAGND or VAREF up to t he ab sol ute max imum rat ing s. How eve r, t he co nv ersi on resu l t i n the se

cases will be X000H or X3FFH, respectively.

2) During the sample time the input capacitance CI can be charged/discharged by the external source. The

internal resistance of the analog source must allow the capacita nce to reac h its final v oltage level within tS.

Aft er th e end of th e sampl e ti me tS, c han ges o f the an al og i np ut vo lta ge h ave n o e ffec t on th e con ve rsi on res ult .

Values for the samp le clock tSC depend on programming and can be taken from the table above.

3) This parameter includes the sample time tS, the time for determining the digital result and the time to load the

result register with the conversion result.

Values for the conversion clock tCC depend on programming and can be taken from the table above.

4) Th is pa ram e te r dep e nds on the AD C co nt rol log ic. It is no t a rea l ma xim u m valu e, but rat he r a fixum .

5) TU E is teste d at VAREF=5.0V, VAGND=0V, VCC=4.9V. It is guaranteed by design characterizatio n for all other

v ol ta ges with in the def in ed voltag e r ang e.

Th e sp ecifie d T UE is gua ran teed onl y if a n ov er load con ditio n (se e IOV sp ecific ation ) occu rs o n ma ximu m 2

not selected analog input pin s and the absolute sum of inpu t overload currents on all analog input pins does

not exceed 10 mA.

During the reset calibration sequence the maximum TUE may be ±4 LSB.

6) During the conversion the ADC’s capacitance must be repeatedly charged or discharged. The internal

resistance of the reference voltage source must allow the capacitance to reach its respective voltage level

within tCC. The maximum internal resistance results from the programmed conversion timing.

7) Not 100% tested, guaranteed by design characterization.

20D ec96 @09 :2 5h In ter med iate Version

43 Semiconductor Gr oup

C167CR-16RM

Testing Waveforms

Figure 9

Input Output Waveforms

Figure 10

Float Waveforms

AC inputs during testing are driven at 2.4 V for a logic ‘1’ an d 0.45 V for a logic ‘0’.

Timing measurements are m ade at VIH min for a logic ‘1’ and VIL max for a logic ‘0 ’.

For timing purposes a port pin i s no longer floating when a 100 m V change from load

voltage occurs, but begins to float when a 100 mV change from the loaded VOH/VOL level occurs

(IOH/IOL = 20 mA).

20Dec96@09:25h Intermediate Version

Semiconductor Group 44

C167CR-16RM

AC Characteristics

Definition of Internal Timing

The internal operation of the C167CR-16RM is controlled by the internal CPU clock fCPU. Both

edges of the CPU clock c an trigger internal (eg. pipeline) or external (eg. bus cy cles) operations.

The specification of the external timing (AC Characteristics) therefore depends on the t ime between

two consecutive edges of the CPU clock, called “TCL” (see figure below).

Figure 11

Generation Mechanisms for the CPU Clock

The CPU clock si gnal can be gener ated via different mec hanisms. The duration of TCLs and their

variation (and also the der iv e d external timing) depends on the used mechanism to generate fCPU.

This influence must be regar ded when calculating the timings for the C167CR-16RM.

Direct Drive

When pin P0.15 (P0H .7) is low (‘0’) during res et the on-chip phase loc ked loop is disabled and the

CPU clock is directly driven fr om the internal oscilla tor with the input clock sign al.

The frequency of fCPU directly follows the frequency of fXTAL so t he high and lo w t ime of fCPU (ie. the

duratio n of an individual TCL) is defined by the duty cycle of the input clock fXTAL.

The timings listed below that refer to TCLs therefore must be calculated using the minim um T CL

that is possible under the respective circumstances. This m inimum val ue can be calculated via the

following formula:

TCLmin = 1/fXTAL * DCmin (DC = duty cycle)

For two consecutive TCLs the deviation caused by the duty cycle of fXTAL is compensated so the

duration of 2TCL is always 1/fXTAL. The minimum value TCLmin therefore has to be used only once

for timings that require an odd number of TCLs (1,3,...). Timings that require an even number of

TCLs (2,4,...) may use the formula 2TCL = 1/fXTAL.

Note: The address float timings in Multiplexed bus mode (t11 and t45) use the maximu m duration of

TCL (TCLmax = 1/fXTAL * DCmax) instead of TCLmin.

A

TCLTCL

A

TCLTCL

fCPU

fXTAL

fCPU

fXTAL

Phase Locked Loop Operation

Direct Clock Drive

20D ec96 @09 :2 5h In ter med iate Version

45 Semiconductor Gr oup

C167CR-16RM

Phase Locked Loop

When pin P0.15 (P0H.7) is high (‘1’) during reset the on-chip phase locked loop is enabled and

provides the CPU clock. The PLL multiplies the input frequency by 4 (ie. fCPU = fXTAL * 4). With every

fourth transition of fXTAL the PLL circuit synchronizes the CPU clock to the input clock. This

synchronization is done smoothely, ie. the C PU clock frequency does not change abru ptly.

Due to this adaptation to the input clock the frequency of fCPU is constantly adjusted so it is locked

to fXTAL. The slight variation causes a jitter of fCPU which also effects the duration of individual TCLs.

The timings listed in the AC Characteristics that refer to TCLs therefore must be calculated using the

minimum TCL that is possible under the respective c ircumstances.

The actual minimum value for TCL depends on the jitter of the PLL. As the PLL is constantly

adjusting its output frequency so it corresponds to the applied input frequency (crystal or oscil lato r)

the relative deviation for periods of more than one TCL is lower than for one single TCL (see formula

and figure below).

For a period of

N

* TCL the minim um val ue is computed using the corresponding deviation D

N

:

TCLmin = TCLNOM * (1 - D

N

/ 100) D

N

= ±(4 -

N

/15) [%],

where

N

= number of consecutive TCLs

and 1 ≤

N

≤ 40.

So for a period of 3 TCLs (ie.

N

= 3): D

3

= 4 -

3

/15 = 3.8%,

and TCLmin = TCLNOM * (1 - 3.8 / 100) = TCLNOM * 0.962 (24.1 nsec @ fCPU = 20 MHz).

This is especially important for bus cycles using waitstates and eg. for the operation of t imers, serial

interfaces, etc. For all slower operations and longer periods (eg. pulse train generation or

measur ement, lower baudrates, etc.) the deviation caus ed by the PLL jitter is neglectible.

Figure 12

App roximated Maximum PLL Jitter

3216

8

42

±1

±2

±3

±4

Max.jitter [%]

N

This approxim ated formula is valid for

1 ≤

N

≤ 40 and 10MHz ≤ fCPU ≤ 20M Hz .

20Dec96@09:25h Intermediate Version

Semiconductor Group 46

C167CR-16RM

AC Characteristics

External Clock D rive XTAL1

VCC = 5 V ± 10 %; VSS = 0 V

TA = 0 to +70 °C for SAB-C167CR-16RM

TA = -40 to +85 °C for SAF-C167CR-16RM -

TA = -40 to +125 °C for SAK- C167CR-16RM

1) For temperatures above TA = +85 °C the minimum value for t1 and t2 is 25 ns.

2) The clock input signal mus t reach the defined levels VIL and VIH2.

Figure 13

External Clock D rive XTAL1

Parameter Symbol Direct Drive 1:1 PLL 1:4 Unit

min. max. min. max.

Oscillator period tOSC SR 50 1000 200 333 ns

High time t1SR 23 1) 2) –10–ns

Low time t2SR 23 1) 2) –10–ns

Rise time t3SR – 10 2) –10

2) ns

Fall time t4SR – 10 2) –10

2) ns

20D ec96 @09 :2 5h In ter med iate Version

47 Semiconductor Gr oup

C167CR-16RM

Memo ry Cycle Variables

The timing tables below use three variables which are derived from the BUSCONx registers and

represent the special characteristics of the programmed memory cycle. The following table

describes, how these variables are to be computed.

AC Characteristics

Multiplexed Bus

VCC = 5 V ± 10 %; VSS = 0 V

TA = 0 to +70 °C for SAB-C167CR-16RM

TA = -40 to +85 °C for SAF-C167CR-16RM

TA = -40 to +125 °C for SAK-C167CR-16RM

CL (for PORT0, PORT1, Port 4, ALE, RD, WR, BHE, CLKOUT) = 100 pF

CL (for Port 6, C S) = 100 pF

ALE cycle time = 6 TCL + 2tA + tC + tF (150 ns at 20-MHz CPU clock wi thout waits tates)

Description Symbol Values

ALE Extension tATCL * <ALECTL >

Memory Cycle Time Waitstates tC2TCL * (15 - <MCTC>)

Memory Tristate Time tF2TCL * (1 - <MTTC>)

Parameter Symbol Max. CPU Clock

= 20 MHz Variable CPU Clo ck

1/2TC L = 1 to 20 MHz Unit

min. max. min. max.

ALE high time t5CC 15 + tA– TC L - 10 + tA–ns

Address setup to ALE t6CC 10 + tA– TC L - 15 + tA–ns

Address hold after ALE t7CC 15 + tA– TC L - 10 + tA–ns

ALE falling edge to RD,

WR (with RW-delay) t8CC 15 + tA– TC L - 10 + tA–ns

ALE falling edge to RD,

WR (no R W-delay) t9CC -10 + tA– -10 + tA–ns

Address float after RD,

WR (with RW-delay) t10 CC –5– 5 ns

Address float after RD,

WR (no RW-delay ) t11 CC – 30 – TCL + 5 ns

RD, WR low time

(with RW-delay) t12 CC 40 + tC–2TCL - 10

+

tC

–ns

RD, WR low time

(no RW-delay) t13 CC 65 + tC–3TCL - 10

+

tC

–ns

20Dec96@09:25h Intermediate Version

Semiconductor Group 48

C167CR-16RM

RD to valid data in

(with RW-delay) t14 SR – 30 + tC– 2TC L - 20

+ tC

ns

RD to valid data in

(no RW-delay) t15 SR – 55 + tC– 3TC L - 20

+ tC

ns

ALE low to valid data in t16 SR – 55

+ tA + tC

– 3TCL - 20

+ tA + tC

ns

Address to valid data in t17 SR – 70

+ 2tA + tC

– 4TCL - 30

+ 2tA + tC

ns

Data hold after RD

risi ng edge t18 SR0–0 – ns

Data float after RD t19 SR – 35 + tF– 2TC L - 15

+ tF

ns

Data valid to WR t22 CC 25 + tC–2TCL - 25

+

tC

–ns

Data hold after WR t23 CC 35 + tF–2TCL - 15

+

tF

–ns

ALE rising edge after RD,

WR t25 CC 35 + tF–2TCL - 15

+

tF

–ns

Address hold after RD,

WR t27 CC 35 + tF–2TCL - 15

+

tF

–ns

ALE falling edge to CS t38 CC -5 - tA10 - tA-5 - tA10 - tAns

CS low to Valid D ata In t39 SR – 55

+ tC + 2tA

– 3TCL - 20

+ tC + 2tA

ns

CS hold after RD, WR t40 CC 60 + tF–3TCL - 15

+

tF

–ns

ALE fall. edge to RdCS,

WrCS (with RW delay) t42 CC 20 + tA– TC L - 5

+ tA

–ns

ALE fall. edge to RdCS,

WrCS (no RW delay) t43 CC -5 + tA–-5

+

tA

–ns

Address float after RdC S ,

WrCS (with RW delay) t44 CC–0– 0 ns

Address float after RdC S ,

WrCS (no RW delay) t45 CC – 25 – TCL ns

RdCS to Val id Data In

(with RW delay) t46 SR – 25 + tC– 2TCL - 25

+ tC

ns

Parameter Symbol Max. CPU Clock

= 20 MHz Variable CPU Clo ck

1/2TC L = 1 to 20 MHz Unit

min. max. min. max.

20D ec96 @09 :2 5h In ter med iate Version

49 Semiconductor Gr oup

C167CR-16RM

RdCS to Val id Data In

(no RW delay) t47 SR – 50 + tC– 3TCL - 25

+ tC

ns

RdCS, WrCS Low Time

(with RW delay) t48 CC 40 + tC–2TCL - 10

+

tC

–ns

RdCS, WrCS Low Time

(no RW delay) t49 CC 65 + tC–3TCL - 10

+

tC

–ns

Data valid to WrCS t50 CC 35 + tC–2TCL - 15

+

tC

–ns

Data hold after RdCS t51 SR0–0 – ns

Data float after RdCS t52 SR – 30 + tF– 2TC L - 20

+ tF

ns

Address hold after

RdCS, WrCS t54 CC 30 + tF–2TCL - 20

+

tF

–ns

Data hold after WrCS t56 CC 30 + tF–2TCL - 20

+

tF

–ns

Parameter Symbol Max. CPU Clock

= 20 MHz Variable CPU Clo ck

1/2TC L = 1 to 20 MHz Unit

min. max. min. max.

20Dec96@09:25h Intermediate Version

Semiconductor Group 50

C167CR-16RM

Figure 14-1

External Memo ry Cycle: M ultiplexed Bus, W ith Read/Write Delay, Normal ALE

Data In

Data Out

A

AA

A

AA

A

AA

A

AA

A

Address

t

38

t

44

t

10

A

AA

A

AA

A

AA

A

AA

A

AA

A

AA

A

AA

A

AA

Address

ALE

CSx

A23-A16

(A15-A8)

BHE

BUS

Read C ycle

RD

RdCSx

BUS

Write C ycle

WR,

WRL, WRH

WrCSx

t

5

t

16

t

17

t

6

t

7

t

39

t

40

t

25

t

27

t

18

t

19

t

14

t

46

t

12

t

48

t

10

t

22

t

23

t

44

t

12

t

48

t

8

t

42

t

42

t

8

t

50

t

51

t

54

t

52

t

56

20D ec96 @09 :2 5h In ter med iate Version

51 Semiconductor Gr oup

C167CR-16RM

Figure 14-2

External Memo ry Cycle: Multiplexed Bus, W ith Read/Write Delay, Extended ALE

A

AA

A

AA

A

Data OutAddress

Data InAddress

t

38

t

44

t

10

A

AA

A

AA

A

AA

A

AA

A

AA

A

AA

A

AA

Address

ALE

CSx

A23-A16

(A15-A8)

BHE

BUS

Read C ycle

RD

RdCSx

BUS

Write C ycle

WR,

WRL, WRH

WrCSx

t

5

t

16

t

17

t

6

t

7

t

39

t

40

t

25

t

27

t

18

t

19

t

14

t

46

t

12

t

48

t

10

t

22

t

23

t

44

t

12

t

48

t

8

t

42

t

42

t

8

t

50

t

51

t

54

t

52

t

56

20Dec96@09:25h Intermediate Version

Semiconductor Group 52

C167CR-16RM

Figure 14-3

External Memo ry Cycle: Mult iplexed Bu s, No Read/Write Delay, Normal ALE

AA

A

AA

A

AA

A

Data OutAddress

Address Data In

t

38

A

AA

A

AA

A

AA

A

AA

A

AA

A

AA

A

AA

A

AA

Address

ALE

CSx

A23-A16

(A15-A8)

BHE

BUS

Read C ycle

RD

RdCSx

BUS

Write C ycle

WR,

WRL, WRH

WrCSx

t

5

t

16

t

17

t

6

t

7

t

39

t

40

t

25

t

27

t

18

t

19

t

15

t

47

t

13

t

49

t

22

t

23

t

13

t

49

t

9

t

43

t

43

t

9

t

11

t

45

t

11

t

45

t

50

t

51

t

54

t

52

t

56

20D ec96 @09 :2 5h In ter med iate Version

53 Semiconductor Gr oup

C167CR-16RM

Figure 14-4

External Memo ry Cycle: Multiplexed Bus, No Read/Write Delay, Extended ALE

A

AA

A

AA

A

Data OutAddress

Data InAddress

t

38

A

AA

A

AA

A

AA

A

AA

A

AA

A

AA

A

AA

Address

ALE

CSx

A23-A16

(A15-A8)

BHE

BUS

Read C ycle

RD

RdCSx

BUS

Write C ycle

WR,

WRL, WRH

WrCSx

t

5

t

16

t

17

t

6

t

7

t

39

t

40

t

25

t

27

t

18

t

19

t

15

t

47

t

13

t

49

t

22

t

23

t

13

t

49

t

9

t

43

t

43

t

9

t

11

t

45

t

11

t

45

t

50

t

51

t

54

t

52

t

56

20Dec96@09:25h Intermediate Version

Semiconductor Group 54

C167CR-16RM

AC Characteristics

Demultiplexed Bus

VCC = 5 V ± 10 % ; VSS = 0 V

TA = 0 to +70 °C for SAB-C167CR-16RM

TA = -40 to +85 °C for SAF-C167CR-16RM

TA = -40 to +125 °C for SAK-C167CR-16RM

CL (for PORT0, PORT1, Port 4, ALE, RD, WR, BHE, CLKOUT) = 100 pF

CL (for Port 6, C S) = 100 pF

ALE cycle time = 4 TCL + 2tA + tC + tF (100 ns at 20-MHz CPU clock without waitstates)

Parameter Symbol Max. CPU Clock

= 20 MHz Variable CPU Clo ck

1/2TC L = 1 to 20 MHz Unit

min. max. min. max.

ALE high time t5CC 15 + tA– TC L - 10 + tA–ns

Address setup to ALE t6CC 10 + tA– TC L - 15 + tA–ns

ALE falling edge to RD,

WR (with RW-delay) t8CC 15 + tA– TC L - 10

+ tA

–ns

ALE falling edge to RD,

WR (no R W-delay) t9CC -10 + tA–-10

+

tA

–ns

RD, WR low time

(with RW-delay) t12 CC 40 + tC–2TCL - 10

+

tC

–ns

RD, WR low time

(no RW-delay) t13 CC 65 + tC–3TCL - 10

+

tC

–ns

RD to valid data in

(with RW-delay) t14 SR – 30 + tC– 2TC L - 20

+ tC

ns

RD to valid data in

(no RW-delay) t15 SR – 55 + tC– 3TC L - 20

+ tC

ns

ALE low to valid data in t16 SR – 55

+ tA + tC

– 3TCL - 20

+ tA + tC

ns

Address to valid data in t17 SR – 70

+ 2tA + tC

– 4TCL - 30

+ 2tA + tC

ns

Data hold after RD

risi ng edge t18 SR0–0 – ns

Data float after RD rising

edge (with RW-delay 1))t20 SR – 35 + tF– 2TCL - 15

+ 2tA + tF 1) ns

Data float after RD rising

edge (no RW -delay 1))t21 SR – 15 + tF– TCL - 10

+ 2tA + tF 1) ns

Data valid to WR t22 CC 25 + tC–2TCL - 25

+

tC

–ns

Data hold after WR t24 CC 15 + tF– TCL - 10 + tF–ns

20D ec96 @09 :2 5h In ter med iate Version

55 Semiconductor Gr oup

C167CR-16RM

1) RW-delay and tA refer to the next following bus cycle.

ALE rising edge after RD,

WR t26 CC -10 + tF–-10

+

tF

–ns

Address hold after RD,

WR t28 CC 0 + tF–0

+

tF

–ns

ALE falling edge to CS t38 CC -5 - tA10 - tA-5 - t A10 - tAns

CS low to Valid D ata In t39 SR – 55

+ tC + 2tA

– 3TCL - 20

+ tC + 2tA

ns

CS hold after RD, WR t41 CC 10 + tF– TC L - 15

+ tF

–ns

ALE falling edge to RdCS,

WrCS (with RW-delay) t42 CC 20 + tA– T CL - 5

+ tA

–ns

ALE falling edge to RdCS,

WrCS (no RW-delay) t43 CC -5 + tA–-5

+

tA

–ns

RdCS to Val id Data In

(with RW-delay) t46 SR – 25 + tC– 2TC L - 25

+ tC

ns

RdCS to Val id Data In

(no RW-delay) t47 SR – 50 + tC– 3TC L - 25

+ tC

ns

RdCS, WrCS Low Time

(with RW-delay) t48 CC 40 + tC–2TCL - 10

+

tC

–ns

RdCS, WrCS Low Time

(no RW-delay) t49 CC 65 + tC–3TCL - 10

+

tC

–ns

Data valid to WrCS t50 CC 35 + tC–2TCL - 15

+

tC

–ns

Data hold after RdCS t51 SR0–0 – ns

Data float after RdCS

(with RW-delay) t53 SR – 30 + tF– 2TC L - 20

+ tF

ns

Data float after RdCS

(no RW-delay) t68 SR – 5 + tF– TCL - 20

+ tF

ns

Address hold after

RdCS, WrCS t55 CC -10 + tF–-10

+

tF

–ns

Data hold after WrCS t57 CC 10 + tF– TC L - 15

+ tF

–ns

Parameter Symbol Max. CPU Clock

= 20 MHz Variable CPU Clo ck

1/2TC L = 1 to 20 MHz Unit

min. max. min. max.

20Dec96@09:25h Intermediate Version

Semiconductor Group 56

C167CR-16RM

Figure 15-1

External Memo ry Cycle: Demultiplexed Bus, With Read/Write Delay, Normal ALE

AA

A

AA

A

AA

A

Data Out

Data In

t

38

AA

A

AA

A

AA

A

AA

A

AA

A

AA

A

AA

A

AA

A

AA

Address

ALE

CSx

A23-A16

A15-A0

BHE

BUS

(D15-D8)

D7-D0

Read C ycle

RD

RdCSx

Write C ycle

WrCSx

t

5

t

16

t

17

t

6

t

39

t

41

t

26

t

28

t

18

t

20

t

14

t

46

t

12

t

48

t

22

t

24

t

12

t

48

t

8

t

42

t

42

t

8

t

50

t

51

t

55

t

53

t

57

BUS

(D15-D8)

D7-D0

WR,

WRL, WRH

20D ec96 @09 :2 5h In ter med iate Version

57 Semiconductor Gr oup

C167CR-16RM

Figure 15-2

External Memo ry Cycle: Demultiplexed Bus, With Read/Write Delay, Extended ALE

A

AA

A

AA

A

Data Out

Data In

t

38

AA

A

AA

A

AA

A

AA

A

AA

A

AA

Address

ALE

CSx

A23-A16

A15-A0

BHE

Read C ycle

RD

RdCSx

Write C ycle

WrCSx

t

5

t

16

t

17

t

6

t

39

t

41

t

26

t

28

t

18

t

20

t

14

t

46

t

12

t

48

t

22

t

24

t

12

t

48

t

8

t

42

t

42

t

8

t

50

t

51

t

55

t

53

t

57

BUS

(D15-D8)

D7-D0

BUS

(D15-D8)

D7-D0

WR,

WRL, WRH

20Dec96@09:25h Intermediate Version

Semiconductor Group 58

C167CR-16RM

Figure 15-3

External Memo ry Cycle: Demultiplexed Bus, No Read/Write Delay, Normal ALE

AA

A

AA

A

Data O ut

Data In

t

38

AA

A

AA

A

AA

A

AA

A

AA

A

AA

A

AA

A

AA

Address

ALE

CSx

A23-A16

A15-A0

BHE

Read C ycle

RD

RdCSx

Write C ycle

WrCSx

t

5

t

16

t

17

t

6

t

39

t

41

t

26

t

28

t

18

t

21

A

t

15

t

47

t

13

t

49

t

22

t

24

t

13

t

49

t

9

t

43

t

43

t

9

t

50

t

51

t

55

t

68

t

57

BUS

(D15-D8)

D7-D0

BUS

(D15-D8)

D7-D0

WR,

WRL, WRH

20D ec96 @09 :2 5h In ter med iate Version

59 Semiconductor Gr oup

C167CR-16RM

Figure 15-4

External Memo ry Cycle: Demultiplexed Bus, No Read/Write Delay, Extended ALE

A

AA

A

AA

A

Data Out

Data In

t

38

AA

A

AA

A

AA

A

AA

A

AA

A

AA

Address

ALE

CSx

A23-A16

A15-A0

BHE

Read C ycle

RD

RdCSx

Write C ycle

WR,

WRL, WRH

WrCSx

t

5

t

16

t

17

t

6

t

39

t

41

t

26

t

28

t

18

t

21

t

15

t

47

t

13

t

49

t

22

t

24

t

13

t

49

t

9

t

43

t

43

t

9

t

50

t

51

t

55

t

68

t

57

BUS

(D15-D8)

D7-D0

BUS

(D15-D8)

D7-D0

20Dec96@09:25h Intermediate Version

Semiconductor Group 60

C167CR-16RM

AC Characteristics

CLKOUT and READY

VCC = 5 V ± 10 %; VSS = 0 V

TA = 0 to +70 °C for SAB-C167CR-16RM

TA = -40 to +85 °C for SAF-C167CR-16RM

TA = -40 to +125 °C for SAK-C167CR-16RM

CL (for PORT0, PORT1, Port 4, ALE, RD, WR, BHE, CLKOUT) = 100 pF

CL (for Port 6, C S) = 100 pF

Notes

1) Th e se timin g s a re giv en for tes t pu rpo se s on ly, in o rde r to assu re reco gn iti on a t a spec ific clo ck edg e .

2) Demultiplexed bus is the worst case. For multiplexed bus 2TCL are to be added to the maximum values. This

adds even more time for deactivating READY.

The 2tA and tC refer to the next following bus cycle, tF refers to the current bus cycle.

Parameter Symbol Max. CPU Clock

= 20 MHz Variable CPU Clo ck

1/2TC L = 1 to 20 MHz Unit

min. max. min. max.

CLKOUT cycle time t29 CC 50 50 2TCL 2TCL ns

CLKOUT high time t30 CC 20 – T CL – 5 – ns

CLKOUT low time t31 CC 15 – T C L – 10 – ns

CLKOUT rise time t32 CC–5– 5 ns

CLKOUT fall time t33 CC–5– 5 ns

CLKOUT rising edge to

ALE falling edge t34 CC 0 + tA10 + tA0 + tA10 + tAns

Synchronous READY

setup time to CLKOUT t35 SR 15 – 15 – ns

Synchronous READY

hold time after CLKOUT t36 SR0–0 – ns

Asynchronous READY

low time t37 SR 65 – 2 T C L + 15 – ns

Asynchronous READY

setup time 1) t58 SR 15 – 15 – ns

Asynchronous READY

hold time 1) t59 SR 0–0 – ns

Async. READY hold time

after RD , WR high

(Demultiplexed Bus) 2)

t60 SR 00

+ 2tA + tC

+ tF

2)

0 TCL - 25

+ 2tA + tC + tF

2)

ns

20D ec96 @09 :2 5h In ter med iate Version

61 Semiconductor Gr oup

C167CR-16RM

Figure 16

CLKOUT and READY

Notes

1) Cycle as programmed, including MCTC waitstates (Example shows 0 MCTC WS).

2) The leading edge of the respective command depends on RW-delay.

3) READY s amp le d HIG H at this sam p ling po int g en era te s a RE A DY cont ro lle d wa itst at e,

READY s amp le d LO W at this sam pling po int ter minate s th e cu rre nt ly ru nn in g bus cyc le.

4) READY may be deactivated in response to the trailin g (rising) edge of the corresponding command (RD or

WR).

5) If the Asynchronous READY signal does not fulfill the indicated setup and hold times with respect to CLKOUT

(eg. because CLKOUT is not enabled), it must fulfill

t

37 in ord er t o be s afel y syn ch roni ze d. This i s gu ara nteed ,

if READY is removed in reponse to the command (see Note 4)).

6) Multiplexed bus modes have a MUX waitstate added after a bus cycle, and an additional MTTC waitstate may

be inserted her e.

For a multiplexed bus with MTTC waits tate this delay is 2 CLKOUT c ycles, for a demultiplexed bus w ithout

MTTC waitstate this delay is zero.

7) The next external bus cycle may start here.

A

AA

A

AA

A

AAAA

AA

A

AA

A

AA

A

AA

A

AA

A

AA

A

CLKOUT

A

AA

ALE

t

30

t

34

Sync

READY

t

35

t

36

t

35

t

36

Async

READY

t

58

t

59

t

58

t

59

waitstate

READY MUX/Tristate 6)

t

32

t

33

t

29

Ru nning cycle 1)

t

31

t

37

3) 3)

5)

Command

RD, WR

t

60 4)

see 6)

2)

7)

3) 3)

20Dec96@09:25h Intermediate Version

Semiconductor Group 62

C167CR-16RM

AC Characteristics

External Bus Arbitration

VCC = 5 V ± 10 % ; VSS = 0 V

TA = 0 to +70 °C for SAB-C167CR-16RM

TA = -40 to +85 °C for SAF-C167CR-16RM

TA = -40 to +125 °C for SAK-C167CR-16RM

CL (for PORT0, PORT1, Port 4, ALE, RD, WR, BHE, CLKOUT) = 100 pF

CL (for Port 6, C S) = 100 pF

Parameter Symbol Max. CPU Clock

= 20 MHz Variable CPU Clo ck

1/2TC L = 1 to 20 MHz Unit

min. max. min. max.

HOLD input setup time

to CLKOUT t61 SR 20 – 20 – ns

CLKOUT to HLDA high

or BREQ low delay t62 CC – 20 – 20 ns

CLKOUT to HLDA low

or BREQ high delay t63 CC – 20 – 20 ns

CSx release t64 CC – 20 – 20 ns

CSx drive t65 CC -5 25 -5 25 ns

Other signals release t66 CC – 20 – 20 ns

Other signals drive t67 CC -5 25 -5 25 ns

20D ec96 @09 :2 5h In ter med iate Version

63 Semiconductor Gr oup

C167CR-16RM

Figure 17

External Bus Arbitration, Releasing the Bus

Notes

1) Th e C167C R- 1 6R M will comp let e th e curren tl y runn in g bus cyc le be fo r e gra nting bus acc es s.

2) Th is is th e first po ss ibilit y fo r B REQ to ge t ac tive .

3) The CS outputs will be resistive high (pullup) after

t

64.

AA

A

AA

A

AAA

A

AAA

A

AAA

A

AAA

A

AAA

A

AAA

A

AAA

A

AAA

A

AAA

A

AAA

A

AAA

A

AAA

A

AAA

A

AAA

A

AAA

A

AAA

A

AAA

A

AAA

A

AAA

A

AAA

A

AAA

A

AAA

A

AAA

A

AAA

A

AAA

A

AAA

A

AAA

A

AAA

A

AAA

A

AAA

A

AAA

A

AAA

A

AAA

A

AAA

A

AAA

A

AAA

A

AAA

A

AAA

A

AAA

A

AAA

A

AAA

A

AAA

A

AAA

A

AAA

A

AAA

A

AAA

A

AAA

A

AAA

A

AAA

A

AAA

A

AAA

A

AAA

A

AAA

A

AAA

A

AAA

A

AAA

A

AAA

A

AAA

A

AAA

A

AAA

A

AAA

A

AAA

A

AAA

A

AAA

A

AAA

A

AAA

A

AAA

A

AAA

A

AAA

A

AAA

A

AAA

A

AAA

A

AAA

A

AAA

A

AAA

A

AAA

A

AAA

A

AAA

A

AAA

A

AAA

A

AAA

A

AAA

A

AAA

A

AAA

A

AAA

A

AAA

A

AAA

A

AAA

AAAA

A

AA

CLKOUT

HOLD

t

61

HLDA

t

63

Other

Signals

t

66

A

AA

AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA

1)

CSx

(O n P 6.x )

t

64

1)

2)

BREQ

t

62

A

AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA

3)

20Dec96@09:25h Intermediate Version

Semiconductor Group 64

C167CR-16RM

Figure 18

External Bus Arbitration, (Regaining the Bus)

Notes

1) Th is is th e last cha n ce for BREQ to trigger the indicated regain-sequence.

E ve n if BR EQ is activated earlier, the regain-sequence is initiated by HOLD going high.

Please note that HOLD may also be deactivated without the C167CR-16RM requesting the bus.

2) The next C167CR-16RM driven bus cycle may start here.

AA

A

AA

A

AA

A

AA

CLKOUT

HOLD

HLDA

Other

Signals

t

62

AA

AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA

CSx

(O n P 6.x )

AA

AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA

t

67

t

62

1)

2)

t

65

t

61

BREQ

t

63

t

62

A

20D ec96 @09 :2 5h In ter med iate Version

65 Semiconductor Gr oup

C167CR-16RM

Package Outline

Figure 19

Sorts of Packin g

Package outlines for tubes, trays , etc. are contained in our

Data Book “Pac kage Information”

SMD = Surface Mounted Devic e Dimensions in mm

Plastic Package, P-MQFP-144-1 (SMD)

(Plastic Metric Quad Flat Package)