L99MC6 Configurable 6-channel device Features 3 independently self configuring high-/low-side channels 3 low-side channels RON = 0.7 (typ) at Tj = 25 C Current limit of each output at min. 0.6 A PWM direct mode Bulb mode with recovery mode LED mode with slew rate control Bridge mode with crosscurrent protection SPI interface for data communication Temperature warning All outputs overtemperature protected All outputs short-circuit protected Configurable open-load detection in off mode VCC supply voltage 3.0 V to 5.25 V The L99MC6 IC is a highly flexible monolithic medium current output driver that incorporates 3 dedicated low-side outputs (channels 4 to 6) and 3 independently self configuring outputs (channels 1 to 3) that can be used as either lowside or high-side drivers in any combination. The L99MC6 can control inductive loads, incandescent bulbs or LEDs. Very low current consumption in standby mode 5 A (typ) The L99MC6 can be used in a half bridge configuration with crosscurrent protection. Internal clamp diodes HS switches operate down to 3 V crank voltage Applications Relay driver LED driver Motor driver Mirror adjustment Table 1. PowerSSO-16 Description The channel 2 can be controlled directly via the IN/PWM pin for PWM applications. The IN/PWM signal can be applied to any other output. The integrated 16-bit standard serial peripheral interface (SPI) controls all outputs and provides diagnostic information: normal operation, openload in off-state, overcurrent, temperature warning, overtemperature. Device summary Order codes Package PowerSSO-16 November 2009 Part number (tube) Part number (tape & reel) L99MC6-LF L99MC6TR-LF Doc ID 16523 Rev 1 1/55 www.st.com 1 Contents L99MC6 Contents 1 2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 1.1 Application diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 1.2 Block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.1 Dual power supply: VS and VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.1.1 Channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.2 Standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.3 Inductive loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.4 Diagnostic functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.4.1 Direct input IN/PWM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.4.2 Temperature warning and thermal shutdown . . . . . . . . . . . . . . . . . . . . . 14 2.4.3 Open-load detection in off-state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.4.4 Overload detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.5 Bridge mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.6 LED mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.7 Bulb mode (programmable soft start function to drive loads with higher inrush current) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4 ESD protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 5.1 6 7 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 6.1 Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 6.2 Undervoltage detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 6.3 Channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 SPI electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 7.1 2/55 Temperature warning and thermal shutdown . . . . . . . . . . . . . . . . . . . . . . 19 DC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Doc ID 16523 Rev 1 L99MC6 8 Contents 7.2 AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 7.3 Dynamic characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 7.4 SPI timing parameter definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Functional description of the SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 8.1 8.2 9 Signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 8.1.1 Serial clock (SCK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 8.1.2 Serial data input (SDI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 8.1.3 Serial data output (SDO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 8.1.4 Chip select not (CSN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 SPI communication flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 8.2.1 General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 8.2.2 Command byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 8.2.3 Global status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 8.3 Write operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 8.4 Read operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 8.5 Read and Clear Status operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 8.6 Read Device Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 SPI control and status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 9.1 RAM memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 9.2 ROM memory map (access with OC0 and OC1 set to `1') . . . . . . . . . . . . 34 9.3 Control and status registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 9.4 9.3.1 Channel configuration decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 9.3.2 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 9.4.1 Example 1:Switch on channel 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 9.4.2 Example 2: Bridge mode configuration . . . . . . . . . . . . . . . . . . . . . . . . . 38 9.4.3 Example 3: Open-load detection in off-state in bridge configuration . . . 40 10 Maximum demagnetization energy . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 11 Application examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 12 Package and PCB thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 12.1 PowerSSO-16 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Doc ID 16523 Rev 1 3/55 Contents 13 L99MC6 Package and packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 13.1 ECOPACK(R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 13.2 PowerSSO-16 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 13.3 Packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Appendix A Acronyms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 4/55 Doc ID 16523 Rev 1 L99MC6 List of tables List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Table 33. Table 34. Table 35. Table 36. Table 37. Table 38. Table 39. Table 40. Table 41. Table 42. Table 43. Table 44. Table 45. Table 46. Table 47. Table 48. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Pin functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 ESD protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Temperature warning and thermal shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Undervoltage detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Channels. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 DC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Dynamic characteristic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Command byte - general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Data byte - general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Command byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Operating code definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Global status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Global status register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Command byte for Write mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Command byte for Read mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Command byte for Read and Clear Status operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Command byte for Read Device Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 RAM memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 ROM memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Control register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Control register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Control register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Status register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Status register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Channel configuration decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Command byte - example 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Data byte - example 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Data byte description - example 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Command byte 1 - example 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Data byte 1 - example 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Data byte description 1 - example 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Command byte 2 - example 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Data byte 2 - example 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Data byte description 2 - example 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Command byte 1 - example 3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Data byte 1 - example 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Data byte description 1 - example 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Command byte 2 - example 3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Data byte 2 - example 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Data byte description 2 - example 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Auto and mutual thermal resistance - footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Auto and mutual thermal resistance - 2 cm2 of Cu heatsink. . . . . . . . . . . . . . . . . . . . . . . . 48 Auto and mutual thermal resistance - 8 cm2 of Cu heatsink. . . . . . . . . . . . . . . . . . . . . . . . 49 Doc ID 16523 Rev 1 5/55 List of tables Table 49. Table 50. Table 51. 6/55 L99MC6 PowerSSO-16 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Acronyms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Doc ID 16523 Rev 1 L99MC6 List of figures List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Application diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Configuration diagram (top view) not in scale. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Output voltage clamping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Example of bridge configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Example of programmable soft start function for inductive loads and incandescent bulbs. 16 Serial input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Serial input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Output turn on/off delays and slew rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Clock polarity and clock phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 SPI frame structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Indication of the global error flag on DO when CSN is low and SCK is stable . . . . . . . . . . 31 Bridge mode drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Open-load in bridge mode drawing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Configurable switch HSD - maximum turn-off current versus inductance. . . . . . . . . . . . . . 42 Configurable switch LSD - maximum turn-off current versus inductance . . . . . . . . . . . . . . 43 Fixed LSD switch - maximum turn-off current versus inductance. . . . . . . . . . . . . . . . . . . . 44 L99MC6 as driver for incandescent bulb, LEDs and high-side or low-side relays . . . . . . . 45 L99MC6 as motor driver (for example, for mirror adjustment) . . . . . . . . . . . . . . . . . . . . . . 46 L99MC6 as driver for unipolar stepper motor driver, relay and LEDs. . . . . . . . . . . . . . . . . 47 PowerSSO-16 PC board(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 PowerSSO-16 package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 PowerSSO-16 tube shipment (no suffix) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 PowerSSO-16 tape and reel shipment (suffix "TR") . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Doc ID 16523 Rev 1 7/55 Introduction L99MC6 1 Introduction 1.1 Application diagram Figure 1. Application diagram VBat Active reverse polarity protection VREG Charge Pump Driver and Protections OL Config. OUT1 Vcc PWM / IN Driver and Protections M OL Config. OUT2 Driver and Protections CONTROL LOGIC OL Config. OUT3 Driver and Protections Microcontroller OL LSD OUT4 Driver and Protections OL LSD OUT5 CSN SCK DI DO Driver and Protections SPI LSD OUT6 GND 8/55 Doc ID 16523 Rev 1 OL L99MC6 Introduction 1.2 Block diagram and pin description Figure 2. Block diagram Charge Pump VCP VDrive1-3 Open Load Drain [Out1] VOLD 1 VDrive1-3 OL DRN1 ON/OFF [Out1] Short Circuit [Out1] Open Load Source [Out1] SRC1 VOLS 1 VCC Open Load Drain [Out2] ON/OFF [Out2] IN/PWM VOLD 2 VDrive1-3 OL DRN2 =1 Short Circuit [Out2] Open Load Source [Out2] Open Load Drain [Out3] SRC2 VOLS2 VOLD 3 VDrive1-3 OL DRN3 ON/OFF [Out3] Short Circuit [Out3] Open Load Source [Out3] SRC3 VOLS 3 CONTROL LOGIC VCC Open Load Drain [Out4] DRN4 VOLD 4 VCC OL VOLD 5 VCC OL DRN5 OL DRN6 ON/OFF [Out4] CSN Short Circuit [Out4] SCK SPI Open Load Drain [Out5] ON/OFF [Out5] DI Short Circuit [Out5] 0 DO Open Load Drain [Out6] VOLD 6 VCC ON/OFF [Out6] Short Circuit [Out6] GND Doc ID 16523 Rev 1 9/55 Introduction Table 2. 10/55 L99MC6 Pin functions Pin Symbol Function 1 / TAB GND 6 IN/PWM IN/PWM direct mode: Direct input for channel 2. Other channels can be driven in PWM mode via SPI. 8 VCC Logic voltage supply 3.3 V/5 V: For this input a ceramic capacitor as close as possible to GND is recommended 3 SRC1 Source of configurable channel 1 4 DRN1 Drain of self configurable channel 1, in HS mode also VS supply 5 DRN2 Drain of self configurable channel 2 15 SRC2 Source of self configurable channel 2 12 DRN3 Drain of self configurable channel 3 13 SRC3 Source of self configurable channel 3 2 DRN4 Drain of channel 4 16 DRN5 Drain of channel 5 14 DRN6 Drain of channel 6 Ground: Reference potential 11 DI SPI data in: The input requires CMOS logic levels and receives serial data from the microcontroller. The data is a 16-bit control word and the most significant bit (MSB, bit 7) is transferred first. 9 DO SPI data out: The diagnosis data is available via the SPI and this tristate-output. The output remains in tristate, if the chip is not selected by the input CSN (CSN = high). 7 CSN SPI chip select not (active low): This input is low active and requires CMOS logic levels. The serial data transfer between the L99MC6 and microcontroller is enabled by pulling the input CSN to low-level. 10 SCK SPI serial clock input: This input controls the internal shift register of the SPI and requires CMOS logic levels. Doc ID 16523 Rev 1 L99MC6 Introduction Figure 3. Configuration diagram (top view) not in scale GND 1 16 DRN5 DRN4 2 15 SRC2 SRC1 3 14 DRN6 DRN1 4 13 SRC3 DRN2 5 12 DRN3 PWM/IN 6 11 DI CSN 7 8 SCK VCC 8 9 DO PowerSSO-16 The tab must be connected to GND TAB = GND Doc ID 16523 Rev 1 11/55 Description L99MC6 2 Description 2.1 Dual power supply: VS and VCC The supply voltage VCC (3.3 V/5 V) supplies the whole device. In case of power-on (VCC increases from undervoltage to VPOR OFF = 2.7 V, typical) the circuit is initialized by an internally generated power-on reset (POR). If the voltage VCC decreases under the minimum threshold (VPOR ON = 2.4 V, typical), the outputs are switched-off (highimpedance) and the status registers are cleared (see Figure 4). Figure 4. Power-on reset VCC VPOR OFF VPOR hyst. VPOR ON IC is disabled All Status Registers are cleared 2.1.1 Channels The channels 1 to 3 are self configuring high-side or low-side n-channel mosfets. This flexibility allows the user to connect loads in high-side or low-side configuration in any combination. In order to provide low Rdson values for high-side configured switches (channels 1 to 3), a charge pump (CP) to drive the internal gate voltage(s) is implemented. If the charge pump is activated (ENCP1 = 1, DISCP2 = 0, see Section 9.3: Control and status registers), the internal charge-pump uses VS from the drain of channel 1, as its power source. Otherwise VCC is used to drive all channels. The channels 4 to 6 are n-channel low-side drivers. The source of the respective mosfet are internally connected to the device GND. Caution: For any high-side configuration, channel 1 must be used as a high-side switch. If channel 1 is configured as low-side, the charge pump has to be deactivated to avoid charge pump current from the drain. Caution: The charge pump may not be deactivated (see Section 9.3: Control and status registers) if one of the channels is in high-side configuration, while a short-circuit from the source to the battery is present. If these conditions occur, the voltage of the shorted source is applied to the VCC pin. 12/55 Doc ID 16523 Rev 1 L99MC6 2.2 Description Standby mode The standby mode of the L99MC6 is activated by SPI command (EN bit of CTRL 0 reset to 0, see Section 9.3.2: Register description). The inputs and outputs are switched-off. The status registers are cleared and the control registers are reset to their default values. In the standby mode the current consumption is 5 A (typical value). A SPI command is needed to switch the L99MC6 in normal mode. 2.3 Inductive loads Each switch is built by a power DMOS transistor. For low-side configured outputs an internal zener clamp from the drain to gate with a breakdown of 31 V minimum provides for fast turnoff of inductive loads. For high-side configured outputs, an internal zener clamp with a breakdown of -15 V maximum provides for fast turn-off of inductive loads (Figure 5). The maximum clamping energy is specified in Chapter 10. Figure 5. Output voltage clamping High Side Configuration Low Side Configuration Output Current Drain Clamp Voltage Output Current (VDRN_CL1-6) = 35V) Drain Voltage VS GND Time VS Time Source Clamp Voltage (VSRC_CL1-3) = -19V) GND 2.4 Source Voltage Diagnostic functions All diagnostic functions (overload, open-load, temperature warning and thermal shutdown) are internally filtered and the condition has to be valid for at least 32 s (open-load: typ. 400 s, respectively) before the corresponding status bit in the status registers are set. The filters are used to improve the noise immunity of the device. Open-load and temperature warning function are intended for information purpose and do not change the state of the output drivers. On contrary, the overload and thermal shutdown condition disable the corresponding driver (overload) or all drivers (thermal shutdown), respectively. Without setting the overcurrent recovery bit in the input data register to logic high, the microcontroller has to clear the overcurrent status bit to reactivate the corresponding driver. (All switches have a corresponding overcurrent recovery bit) If this bit is set, the device automatically switches-on the outputs again after a short recovery time. With this feature the device can drive loads with start-up currents higher than the overcurrent limits (that is inrush current of incandescent lamps, cold resistance of motors and heaters, Figure 7). Doc ID 16523 Rev 1 13/55 Description 2.4.1 L99MC6 Direct input IN/PWM The IN/PWM input allows channel 2 to be enabled without the use of SPI. The IN/PWM pin is OR-ed with the SPI command bit. This pin can be left open if the channel 2 is controlled only via the SPI. This input has an internal pull-down. The IN/PWM signal can also be applied to any other switches by the activation of the PWM mode. This input is suited for non-inductive loads that are pulse width modulated. This allows PWM control without further use of the SPI. 2.4.2 Temperature warning and thermal shutdown If the junction temperature rises above Tj TW a temperature warning flag is set and is detectable via the SPI. If the junction temperature increases above the second threshold Tj SD, the thermal shutdown bit is set and power DMOS transistors of all output stages are switched-off to protect the device. Temperature warning flag and thermal shutdown bits are latched. In order to reactivate the output stages, the junction temperature must decrease below Tj SD - Tj SD HYS and the thermal shutdown bit has to be cleared by the microcontroller. 2.4.3 Open-load detection in off-state The open-load detection monitors the load at each output stage in off mode. A current source of 150 A (IOLD1-6, IOLS 1-3) is connected between drain and source or GND. An open-load failure is detected if the drain or source voltage reaches an internal VOLD/S (2.0 V) for at least 3 ms (tdOL typ.). The corresponding open-load bit is set in the status register. In LED mode the open-load detection is disabled and the current source is switched-off, which avoids a turn-on of the LEDs in off-state. 2.4.4 Overload detection In case of an overcurrent condition, a flag is set in the corresponding status register. If the overcurrent signal is valid for at least tISC = 32 s, the overcurrent flag is set and the corresponding driver is switched-off to reduce the power dissipation and to protect the integrated circuit. If the overcurrent recovery bit of the output is zero the microcontroller has to clear the status bit to reactivate the corresponding driver. 2.5 Bridge mode The L99MC6 can be configured as bridge driver. Up to three half bridges can be used. In Bridge mode the device is crosscurrent protected by an internal delay time. If one driver (LS or HS) is turned-off the activation of the other driver of the same half bridge is automatically delayed by the crosscurrent protection time. After the crosscurrent protection time is expired the slew rate limited switch-off phase of the driver is changed to a fast turn-off phase and the opposite driver is turned-on with slew-rate limitation. Due to this behavior it is always guaranteed that the previously activated driver is totally turned-off before the opposite driver starts to conduct. Due to the built-in reverse diodes of the output transistors, inductive loads can be driven at the outputs without external free-wheeling diodes. 14/55 Doc ID 16523 Rev 1 L99MC6 Description The following combination must be used: channel 1 + 4, channel 2 + 5, channel 3 + 6 (Figure 6). A VS voltage exceeding the low-side clamping voltage (VDRN_CL1-6) , while the high one of the high-side drivers is turned on, may cause a destruction of the device. Caution: In bridge mode using channels 2 and 5, the IN/PWM pin has to be grounded. Therefore PWM mode on other channels is not possible. Figure 6. Example of bridge configuration VDD 5V VS 12V Out1 Out2 IN/PWM =1 M GND Out3 M Control Out4 SCK CSN DO Out5 SPI Out6 DI GND 2.6 LED mode Open-load detection in off-state can be deactivated to avoid the turn on of the LEDs by the current source (150 A typ.) when the channel is switched-off. Moreover, it is possible to select a high slew rate to support PWM operations with small duty cycle (see Section 9.3.1: Channel configuration decoding). Doc ID 16523 Rev 1 15/55 Description 2.7 L99MC6 Bulb mode (programmable soft start function to drive loads with higher inrush current) Loads with start-up currents higher than the overcurrent limits (for example inrush current of lamps, start current of motors and cold resistance of heaters) can be driven by using the programmable soft start function (that is overcurrent recovery mode). Each driver has a corresponding overcurrent recovery bit. If this bit is set, the device automatically switches-on the outputs again after a fixed recovery time. The PWM modulated current provides sufficient average current to power up the load (for example heat up the bulb) until the load reaches operating condition (Figure 6). The device itself cannot distinguish between a real overload and a non linear load like a light bulb. A real overload condition can only be qualified by time. As an example the microcontroller can switch-on light bulbs by setting the overcurrent recovery bit for the first 50 ms. After clearing the recovery bit, the output is automatically disabled if the overload condition still exits. Figure 7. Example of programmable soft start function for inductive loads and incandescent bulbs Load Current Unlimited Inrush Current Load Current Limited Inrush Current in overcurrent recovery mode with inductive load t 16/55 Doc ID 16523 Rev 1 Unlimited Inrush Current Limited Inrush Current in overcurrent recovery mode with incandescent bulb t L99MC6 3 Absolute maximum ratings Absolute maximum ratings Stressing the device above the rating listed in Table 3 may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronicsTM SURE program and other relevant quality document. Table 3. Absolute maximum ratings Symbol Parameter Value Unit -0.3 to 28 V 40 V Single pulse tmax < 400 ms in bridge mode VDRN_CL1-6 V Stabilized supply voltage, logic supply -0.3 to 5.5 V -0.3 to VCC + 0.3 V DC supply voltage VS (DRN1 HS Single pulse tmax < 400 ms in HS or LS config) configuration with Rload min = 40 (1) VCC DI, DO, SCK, CSN, IN Digital input/output voltage DRN 1-6 Output current capability 1,65 A SRC 1-3 Output current capability 1,65 A Current capability 3,30 A -40 to 150 C GND Tj Operating junction temperature 1. The device requires a minimum load impedance of 40 to sustain a load dump pulse of 40 V according to the ISO 7637 pulse 5b. All maximum ratings are absolute ratings. Leaving the limitation of any of these values may cause an irreversible damage of the integrated circuit. Doc ID 16523 Rev 1 17/55 ESD protection 4 L99MC6 ESD protection Table 4. ESD protection Parameter Value Unit All pins 2(1) kV Output pins: DRN1 - DRN6; SRC1, SRC3, SRC5 4(2) kV Machine model (CDF-AEC-Q100-03 rev. F) 200 V Charged device model (CDF-AEC-Q100-011 Rev. F) 1500 V 1. HBM according to MIL 883C, Method 3015.7 or EIA/JESD22-A114-A 2. HBM with all unzapped pins grounded 18/55 Doc ID 16523 Rev 1 L99MC6 Thermal data 5 Thermal data 5.1 Temperature warning and thermal shutdown Table 5. Temperature warning and thermal shutdown Item Symbol Parameter Min. 5.2.1 TjTW ON Temperature warning threshold junction temperature Tj increasing 5.2.2 TjTW OFF Temperature warning threshold junction temperature Tj decreasing 5.2.3 TjTW HYS Temperature warning hysteresis 5.2.4 TjSD ON Thermal shutdown threshold junction temperature Tj increasing 5.2.5 TjSD OFF Thermal shutdown threshold junction temperature Tj decreasing 5.2.6 TjSD HYS Thermal shutdown hysteresis Max. Unit 150 C 130 - - Typ. C 5 K 170 C 150 C 5 K For additional information, please refer to Chapter 12: Package and PCB thermal data. Doc ID 16523 Rev 1 19/55 Electrical characteristics 6 L99MC6 Electrical characteristics VS = 6 V to 16 V, VCC = 3.0 V to 5.3 V, Tj = -40 C to 150 C, unless otherwise specified. The voltages are referred to GND and currents are assumed positive, when the current flows into the pin. 6.1 Supply Table 6. Supply Item Symbol 6.1.1 VS 6.1.2 6.1.3 6.1.4 IS IVS VCC 6.1.5 ICC 6.1.6 Parameter Test condition Max. Unit 28 V 1.5 2.0 mA VS = 13 V, VCC = 5 V standby mode DRN1 = VS TTest = -40 C, 25 C Outputs floating 3 10 A TTest =130 C 6 20 A 5.3 V Operating supply voltage range VS = 13 V, VCC = 5.0 V active mode DRN1 = VS Outputs floating VS DC supply current VS quiescent supply current Operating supply voltage range 3.0 VCC DC supply current VS = 13 V, VCC = 5.0 V active mode 1.3 2 mA VCC quiescent supply current VS = 13 V, VCC = 5.0 V CSN = VCC standby mode Outputs floating 5 20 A Typ. Max. Unit 3.0 V Undervoltage detection Table 7. Undervoltage detection Symbol Parameter Test Condition 6.2.1 VPOR OFF Power-on reset threshold VCC increasing 6.2.2 VPOR ON Power-on reset threshold VCC decreasing 6.2.3 VPOR hyst Power-on reset hysteresis VPOR OFF - VPOR ON 20/55 Typ. 6 6.2 Item Min. Doc ID 16523 Rev 1 Min. 2.2 V 0.3 V L99MC6 Electrical characteristics 6.3 Channels Table 8. Channels Item 6.3.1 6.3.2 6.3.3 Symbol rON SWI1-3 rON SWI1-6 ISC1-6 Parameter Test condition On resistance drain to source in HS configuration On resistance drain to source or GND, in LS configuration Overcurrent protection Min. Typ. Max. Unit VS=13.5 V, Tj = 25 C, CP on, Iload = 250 mA - 700 900 m VS=13.5 V, Tj = 125 C, CP on, Iload = 250 mA - 1100 1500 m VS = 6.0 V Tj = 25 C, CP on, Iload = 125 mA - 700 900 m VS = 6.0 V, Tj = 125 C, CP on, Iload = 125 mA - 1100 1500 m VS = 4.5 V Tj = 25 C, CP on, Iload = 125 mA - 800 1500 m VS = 4.5 V, Tj = 125 C, CP on, Load = 125 mA - 1300 2000 m VS = 3 V, Tj = 25 C, CP on, Iload = 125 mA - 1600 2600 m VCC=5.0 V, Tj = 25 C, Load = 250 mA - 750 1000 m VCC = 5.0 V, Tj = 125 C, Iload = 250 mA - 1100 1500 m VCC = 3.3 V, Tj = 25 C, Iload = 250 mA - 900 1250 m VCC = 3.3 V, Tj = 125 C, Iload = 250 mA - 1400 1800 m Channels 1 to 3 0.7 1.0 1.4 A Channels 4 to 6 0.6 0.8 1.0 A 6.3.4 td ON1-6 Output delay time, switch-on VS = 13.5 V, VCC = 5.0 V - 50 100 s 6.3.5 td OFF1-6 Output delay time, switch-off VS = 13.5 V, VCC = 5.0 V - 50 100 s 6.3.6 td ONLED1-6 Output delay time, switch-on LED VS = 13.5 V, VCC = 5.0 V - 15 40 s 6.3.7 tdOFFLED1-6 Output delay time, switch-off LED VS = 13.5 V, VCC = 5.0 V - 15 40 s 6.3.8 tDHL Crosscurrent protection time Only in Bridge mode - 200 500 s VDRN2-6 = VS, LED mode, CP off 0 - 5 A IQLD Switched-off output current DRN 1-6 VDRN1 - 20 6.3.9 Doc ID 16523 Rev 1 A 21/55 Electrical characteristics Table 8. L99MC6 Channels (continued) Item Symbol Parameter Min. Typ. Max. Unit 6.3.10 IQLS Switched-off output current SRC 1-3 - -15 -25 A 6.3.11 VOLD1-6 Drain open-load detection voltage on drain 1,1 2,0 2,5 V 6.3.12 IOLD1-6 Open-load detection current on drain 80 190 280 A 6.3.13 VOLS1-3 Source open-load detection voltage on source 1,1 2,0 2,5 V 6.3.14 IOLS1-3 Open-load detection current on source @ VOLS -80 -190 -280 A 6.3.15 tdOL Minimum duration of openload condition to set the status bit Guaranteed by design 2 3 4 ms 6.3.16 tISC Minimum duration of overcurrent condition to switch-off the driver Guaranteed by design 10 - 100 s 6.3.17 dVOUT1/dt Slew rate of channel 1 to 6 VS = 13.5 V, VCC = 5.0 V Iload = 54 0.1 0.25 0.4 V/s 6.3.18 dVOUT1LED/dt Slew rate of channel 1 to 6 in LED mode VS = 13.5 V, VCC = 5.0 V Iload = 54 0.5 1.25 2.0 V/s 6.3.19 VDRN_CL1-6 Drain clamp voltage (low-side) Source = GND Iload = 0.25 A 31 35 39 V Drain = VS, Iload = 0.25 A -19 -15 V VSRC_CL1-3 Source clamp voltage (high-side) -22 6.3.20 Standby -22 10 -1,5 V 22/55 Test condition VSRC1-3 = GND, LED mode @ VOLD Doc ID 16523 Rev 1 L99MC6 7 SPI electrical characteristics SPI electrical characteristics VS = 6 V to 16 V, VCC = 3.0 V to 5.3 V, Tj = -40 C to 150 C, unless otherwise specified. The voltages are referred to GND and currents are assumed positive, when the current flows into the pin 7.1 DC characteristics Table 9. DC characteristics Symbol Parameter Test condition Min Typ Max Unit 0.3VDD V DI, SCK, CSN, PWM VIL Low-level input voltage - VIH High-level input voltage - 0.7VDD RCSN in Pull-up resistor at input CSN - 20 50 80 k RCLK in Pull-down resistor at input CLK - 20 50 80 k Pull-down resistor at input DI - 20 50 80 k 0.3VDD V RDI in V DO VOL Low-level output voltage IOUT = 5 mA VOH High-level output voltage IOUT = 5 mA 0.7VDD Test condition Min Typ Max Unit VOUT = 0 to 5 V - - 10 pF Input capacitance (DI) VIN = 0 to 5 V - - 10 pF Input capacitance (other pins) VIN = 0 to 5 V - - 10 pF 7.2 AC characteristics Table 10. AC characteristics Symbol Parameter V DI, DO, SCK, CSN COUT CIN Output capacitance (DO) Doc ID 16523 Rev 1 23/55 SPI electrical characteristics L99MC6 7.3 Dynamic characteristics Table 11. Dynamic characteristic Symbol fC Parameter Test condition Min Typ Max Unit - - - 1 MHz Clock frequency tSCSN CSN low setup time see Figure 8 120 - - ns tHCSN CSN high setup time see Figure 8 1 - - s tCSNQV CSN falling until DO valid - 5 130 250 ns tCSNQT CSN rising until DO tristate - 150 650 1000 ns tSSCK SCK setup time before CSN rising - 200 - - ns tSSDI Data in setup time see Figure 8 20 - - ns tCHDX Data hold setup time see Figure 8 30 - - ns tHSCK SCK high time see Figure 8 115 - - ns tLSCK SCK low time see Figure 8 115 - - ns tSCKQV Clock high to output valid COUT = 100 pF - 150 - ns tQLQH Output rise time COUT = 100 pF - 110 - ns tQHQL Output fall time COUT = 100 pF - 110 - ns tenDOtriH DO enable time from tristate to high-level COUT = 100 pF, IOUT = -1 mA, pull-down load to GND - 100 250 ns tenDOtriL DO enable time from tristate to low-level COUT = 100 pF, IOUT=1 mA, pull-up load to VCC - 100 250 ns tdisDOHtri DO disable time from high-level to tristate COUT = 100 pF, IOUT = -4 mA, pull-down load to GND - 625 720 ns tdisDOLtri DO disable time from low-level to tristate COUT = 100 pF, IOUT = 4 mA, pull-up load to VCC - 540 620 ns 24/55 Doc ID 16523 Rev 1 L99MC6 SPI electrical characteristics 7.4 SPI timing parameter definition Figure 8. Serial input timing tHCSN CSN tCSNQV tCSNQT Data out Data out SDO t SCKQV tSCSN t SSCK SCK t SSDI SDI Figure 9. tHSCK tLSCK Data in Data in Serial input timing CSN SDO pull-up load to VC C CL=100pF tenD O t ri L td isD O L t ri tenD O t ri H td isD O H t ri SDO pull-down load to GN D CL=100pF Doc ID 16523 Rev 1 25/55 SPI electrical characteristics L99MC6 Figure 10. Output turn on/off delays and slew rates VINIPWM VDD VIN/PWM VDD 50% 50% GND GND Vsource X Vsource X 90% Lowside 90% Lowside 80% 20% 10% GND Vdrain X GND Vdrain X 80% High Side 10% High Side 90% 80% 20% 20% GND Tdoff1-6 Tdon1-6 dVout1x/dt dVout1x/dt 26/55 20% Doc ID 16523 Rev 1 L99MC6 Functional description of the SPI 8 Functional description of the SPI 8.1 Signal description 8.1.1 Serial clock (SCK) This input signal provides the timing of the serial interface. Data present at serial data input (SDI) is latched on the rising edge of serial clock (SCK). Data on serial data output (SDO) is shifted out at the falling edge of serial clock (see Figure 11). The SPI can be driven by a microcontroller with its SPI peripherals running in following mode: CPOL = 0 and CPHA = 0 (see Figure 11). 8.1.2 Serial data input (SDI) This input is used to transfer data serially into the device. It receives the data to be written. Values are latched on the rising edge of serial clock (SCK). 8.1.3 Serial data output (SDO) This output signal is used to transfer data serially out of the device. Data is shifted out on the falling edge of serial clock (SCK). DO also reflects the status of the <Global Error Flag> (<Global Status Register>, bit 7) while CSN is low and no clock signal is present 8.1.4 Chip select not (CSN) When this input signal is high, the device is deselected and serial data output (SDO) is highimpedance. Driving this input low enables the communication. The communication must start and stop on a low-level of serial clock (SCK). Figure 11. Clock polarity and clock phase Doc ID 16523 Rev 1 27/55 Functional description of the SPI L99MC6 Figure 12. SPI frame structure SPI-Frame Structure Write Operation CS N S DI MSB Comm a nd Byte (8 bit) Data (8, 16 or 24 bit) LSB L SB Data Glob al Status Byte (8 b it) S DO MSB (previous content of register) M SB LSB Read Operation CS N S DI S DO 28/55 MSB Com m and Byte (8 b it) Glob al Status Byte (8 b it) Do n't care (8, 16 or 24 bit) LSB MSB L SB Data (8, 16 or 24 bit) M SB Doc ID 16523 Rev 1 LSB L99MC6 Functional description of the SPI 8.2 SPI communication flow 8.2.1 General description The proposed SPI communication is based on a standard SPI interface structure using CSN (chip select not), SDI (serial data in), SDO (serial data out/error) and SCK (serial clock) signal lines. At the beginning of each communication the master reads the <SPI-frame-ID> register (ROM address 3EH) of the slave device. This 8-bit register indicates the SPI frame length (16 bit for the L99MC6) and the availability of additional features. Each communication frame consists of an instruction byte which is followed by 1 data byte (see Figure 12). The data returned on SDO within the same frame always starts with the <Global Status> register. It provides general status information about the device. It is followed by 1 byte (that is `In-frame-response', see Figure 12). For Write cycles the <Global Status> register is followed by the previous content of the addressed register. For Read cycles the <Global Status> register is followed by the content of the addressed register. Table 12. Command byte - general description MSB LSB Operating code OC1 Table 13. Address OC0 A5 A4 A3 A2 A1 Data byte - general description MSB Bit7 8.2.2 A0 LSB Bit6 Bit5 Bi4 Bit3 Bit2 Bit1 Bit0 Command byte Each communication frame starts with a command byte. It consists of an operating code which specifies the type of operation (<Read>, <Write>, <Read and Clear Status>, <Read Device Information>) and a 6-bit address. Table 14. Command byte MSB LSB Operating code OC1 OC0 Address A5 A4 Doc ID 16523 Rev 1 A3 A2 A1 A0 29/55 Functional description of the SPI L99MC6 Operating code definition Table 15. Operating code definition OC1 OC0 Meaning 0 0 <Write mode> 0 1 <Read mode> 1 0 <Read and Clear Status> 1 1 <Read Device Information> The <Write mode> and <Read mode> operations allow access to the RAM of the device, that is write to control registers or read status information. A <Read and Clear Status> operation addressed to a device specific status register reads back and subsequently clear this status register. A <Read and Clear Status> operation with address 3FH clears all status registers at a time. A <Read and Clear Status> operation addressed to an unused RAM address or configuration register address is identical to a <Read mode> operation (in case of unused RAM address, the second byte is equal to 00H). <Read Device Information> allows access to the ROM area which contains device related information such as the product family, product name, silicon version and register width. 8.2.3 Global status register Table 16. Global status register Bit 7 Bit 6 Global error flag (GEF) Bit 3 Bit 2 Bit 1 Bit 0 Global status register description Description Polarity Comment 0 Unused Active high Always returns `0' 1 Overcurrent detected Active high Set by any overcurrent event 2 Open-load detected Active high Set by any open-load event 3 Temperature warning Active high - 4 Thermal shutdown / chip overload Active high - Active low Activated by all internal reset events that change device state or configuration registers (for example software reset, VCC undervoltage, etc.). The bit is cleared after a valid communication with any register. This bit is initially `0' and is set to `1' by a valid SPI communication 5 30/55 Bit 4 Communication TSD Temperature Open-load Overcurrent Chip reset Unused error Chip overload warning detected detected Table 17. Bit Bit 5 Chip reset Doc ID 16523 Rev 1 L99MC6 Functional description of the SPI Table 17. Bit Global status register description (continued) Description Polarity Comment 6 Communication error Active high Bit is set if the number of clock cycles during CSN = low does not match with the specified frame width or if an invalid bus condition is detected (DI always 1). DI always 0 automatically leads to clearing the enable bit in CTRL0 and is not signaled as communication error. 7 Global Error flag Active high Logic OR combination of all failures in the <Global Status Byte>. The <Global Error Flag> is generated by an OR-combination of all failure events of the device (that is <Global Status Register>, [0:6]). Figure 13. Indication of the global error flag on DO when CSN is low and SCK is stable 1. The last transferred SPI command is still valid in the input shift register. If SCK is stable (high or low) during a CSN low pulse, at the rising edge of CSN the last transferred SPI command is still valid in the input shift register and is repeated. Therefore, it is recommended to send a complete SPI frame to monitor the status of the L99MC6. Writing to the selected data input register is only enabled if exactly one frame length is transmitted within one communication frame (that is CSN low). If more or less clock pulses are counted within one frame, the complete frame is ignored and a SPI frame error is signaled in the Global Status register. This safety function is implemented to avoid an unwanted activation of output stages by a wrong communication frame. Doc ID 16523 Rev 1 31/55 Functional description of the SPI L99MC6 For Read operations, the <communication error> bit in the <Global Status Register> is set, but the register to be read is still transferred to the DO pin. If the number of clock cycles is smaller than the frame width, the data at DO is truncated. If the number of clock cycles is larger than the frame width, the data at DO is filled with `0' bits. Due to this safety functionality a daisy chaining of SPI is not possible. Instead, a parallel operation of the SPI bus by controlling the CSN signal of the connected ICs is recommended. Note: If the frame width is greater than 16 bits, initial Read of <SPI-frame-ID> using a 16-bit communication sets the <communication Error bit> of the <Global Status> register. A subsequent correct length transaction is necessary to correct this bit. 8.3 Write operation OC0, OC1: operating code (00 for `Write' mode) Table 18. Command byte for Write mode MSB LSB Operating code 0 0 Address A5 A4 A3 A2 A1 A0 The Write operation starts with a command byte followed by 1 data byte. For Write cycles the <Global Status> register is followed by the previous content of the addressed register. The RAM memory area consists of 8-bit registers. All unused RAM addresses are read as `0'. Failures are indicated by activating the corresponding bit of the <Global Status> register. Note: The register definition for RAM address 00H is device specific. A register value of all 0 causes a device reset (interpreted as `Data-in short to GND'). 8.4 Read operation OC0, OC1: operating code (01 for `Read' mode) Table 19. Command byte for Read mode MSB LSB Operating code 0 1 Address A5 A4 A3 A2 A1 A0 The Read operation starts with a command byte followed by 1 data byte. The content of the data byte is `do not care'. The content of the addressed register is shifted out at SDO within the same frame (`in-frame response'). The returned data byte represents the content of the register to be read. Failures are indicated by activating the corresponding bit of the <Global Status> register. 32/55 Doc ID 16523 Rev 1 L99MC6 8.5 Functional description of the SPI Read and Clear Status operation OC0, OC1: operating code (10 for `Read and Clear Status' mode) Table 20. Command byte for Read and Clear Status operation MSB LSB Operating code 1 0 Address A5 A4 A3 A2 A1 A0 The `Read and Clear Status' operation starts with a command byte followed by 1 data byte. The content of the data byte is `do not care'. The content of the addressed status register is transferred to SDO within the same frame (`in-frame response') and is subsequently cleared. A <Read and Clear Status> operation with address 3FH clears all status registers simultaneously. A <Read and Clear Status> operation addressed to an unused RAM address or to the configuration register (3FH) is identical to a <Read mode> operation (in case of unused RAM address, the second byte is equal to 00H). The returned data byte represents the content of the register to be read. Failures are indicated by activating the corresponding bit of the <Global Status> register. 8.6 Read Device Information OC0, OC1: operating code (11 for `Read Device Information' mode) Table 21. Command byte for Read Device Information MSB LSB Operating code 1 1 Address A5 A4 A3 A2 A1 A0 The device information is stored at the ROM. In the ROM memory area, the first 8 bits are used. All unused ROM addresses is read as `0'. Note: ROM address 3FH is unused. An attempt to access this address is recognized as a communication line error (`Data-in stuck to VCC') and the standby mode is automatically entered (all internal registers are cleared). Doc ID 16523 Rev 1 33/55 SPI control and status register L99MC6 9 SPI control and status register 9.1 RAM memory map Table 22. 9.2 RAM memory map Address Name Access Content 00h CTRL 0 Read/Write Global enable, channels 3 and 6 control register 01h CTRL 1 Read/Write CP, channels 2 and 5 control register 02h CTRL 2 Read/Write CP, channels 1 and 4 control register 03h Unused - 04h STAT 0 Read only Open-load / thermal status register 05h STAT 1 Read only Overcurrent / thermal status register - ROM memory map (access with OC0 and OC1 set to `1') Table 23. ROM memory map Address Name Access Content 00h ID Header Read only 42h (device class ASSP, 2 additional information bytes) 01h Product ID Read only 06H 02h Category / Version Read only 18h (multi channel driver, last 3 LSB = 0: engineering samples) 3Eh SPI-Frame ID Read only 01h (no burst mode, no watchdog, 16 bit frame SPI) 9.3 Control and status registers Table 24. Control register 0 Data Byte Adress Access Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Global enable, Channel 3&6 control 00h R/W Default 34/55 EN CH6 [2] CH6 [1] CH6 [0] Bridge 3&6 CH3 [2] CH3 [1] CH3 [0] 0 0 0 0 0 0 0 0 Doc ID 16523 Rev 1 L99MC6 Table 25. SPI control and status register Control register 1 Data Byte Adress Access Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Channel 2&5 control 01h R/W Default Table 26. ENCP CH5 [2] CH5 [1] CH5 [0] Bridge 2&5 CH2 [2] CH2 [1] CH2 [0] 1 0 0 0 0 0 0 0 Bit 3 Bit 2 Bit 1 Bit 0 Control register 2 Data Byte Adress Access Bit 7 Bit 6 Bit 5 Bit 4 Channel 1&4 control 02h R/W Default Table 27. DISCP CH4 [2] CH4 [1] CH4 [0] Bridge 1&4 CH1 [2] CH1 [1] CH1 [0] 0 0 0 0 0 0 0 0 Bit 3 Bit 2 Bit 1 Bit 0 OL CH3 OL CH2 OL CH1 Bit 2 Bit 1 Bit 0 OC CH3 OC CH2 OC CH1 Status register 0 Data Byte Adress Access Bit 7 Bit 6 Bit 5 Bit 4 Open-load, thermal status 04h Table 28. R TSD TWARN OL CH6 OL CH5 OL CH4 Status register 1 Data Byte Adress Access Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Overcurrent, thermal status 05h R TSD TWARN OC CH6 OC CH5 Doc ID 16523 Rev 1 OC CH4 35/55 SPI control and status register L99MC6 9.3.1 Channel configuration decoding Table 29. Channel configuration decoding CHx CHx CHx [2] [1] [0] PWM CHx mode Overcurrent recovery Slew Rate Open-load detection No - High Off 0 0 0 Off(1) 1 1 1 Off(1) No - Low On 0 0 1 On No No High - 0 1 0 On No No Low - 0 1 1 On No Yes Low - 1 0 1 IN/PWM(2) Yes No High Off 0 (2) Yes No Low On 1 1 IN/PWM 1. The state of the channel 2 is according to the IN/PWM signal 2. The output state is according to the IN/PWM signal, note that bridge mode and PWM mode may not be activated at the same time for channels 2 and 5. 9.3.2 Register description Table 30. Register description(1) Name Comment EN Global device enable bit. If this bit is reset, the device goes in standby mode. CHx [2:0] Channel output configuration (see Figure 29). Note that channel 2 is directly driven by the external IN/PWM pin and thus can not be configured independently from the PWM configuration of other channels. Bridge Activate Bridge mode between channels 3 and 6, channels 2 and 5, channels 1 and 4. Any polarity change is delayed by masking time of cross conduction protection If wrong SPI commands try to turn on the channels 3 and 6, channels 2 and 5, channels 1 and 4 simultaneously, the high-side (channels 3, 2, 1) has the priority whereas channels 6, 5, 4 is (or stay) deactivated. ENCP This bit is preset to `1' at startup. To deactivate the internal charge pump ENCP has to be reset together with setting DISCP (CTRL 2). This mechanism avoids unwanted charge pump deactivation after an undetected communication error. It is recommended to check the state of the charge pump deactivation bits at every access of CTRL 1 and CTRL 2. DISCP This bit is reset to `0' at startup. To deactivate the internal charge pump DISCP has to be set together with resetting ENCP (CTRL 1) TSD Overtemperature detected: all the drivers are shutdown TWARN Overtemperature warning level detected, information only OL [6:1] Open-load error detected, information only OC [6:1] Overcurrent error detected, drivers are deactivated and re-enabled cyclically when bulb mode is configured. Note: in order to detect a real overload condition, the application software must make sure, that the corresponding OC bit remains cleared after a maximum heat up time of the load. 1. Every output stage is protected against overtemperature and overcurrent. While still configured as ON, the output stage can be deactivated by the corresponding error bits in the status registers. In order to reactivate the drivers, the status registers have to be cleared by a specific SPI command. 36/55 Doc ID 16523 Rev 1 L99MC6 SPI control and status register 9.4 Examples 9.4.1 Example 1:Switch on channel 1 It is assumed that the charge pump is already activated (ENCP1 = 1 and DISCP2 = 0, POR default) Table 31. Command byte - example 1 MSB LSB Operating code 0 Table 32. Address 0 0 0 0 0 1 0 Data byte - example 1 MSB LSB 0 0 0 0 0 0 0 1 From Table 31 and Table 32 follow that the value 01h is written at RAM address 02h (control register 2). Table 33 describe more in detail the data byte structure. Table 33. DISCP 0 Data byte description - example 1 CH1 CH1 CH1 [0] Bridge 1&4 [2] [1] [0] 0 0 0 0 1 CH4 CH4 CH4 [2] [1] 0 0 Hereafter the actions linked to each value of bit or group of bits: DISCP = 0: Charge pump stays activated CH4[2:0] = 000b: Channel 4 is off, open-load detection in off-state disabled BRIDGE_1&4 = 0: Bridge mode disabled CH4[2:0] = 001b: Channel 1 is on, high slew rate, PWM not activated, overcurrent recovery deactivated. Doc ID 16523 Rev 1 37/55 SPI control and status register 9.4.2 L99MC6 Example 2: Bridge mode configuration Table 34. Command byte 1 - example 2 MSB LSB Operating code 0 Table 35. Address 0 0 0 0 0 0 1 Data byte 1 - example 2 MSB LSB 1 0 1 0 1 0 0 0 From Table 34 and Table 35 follow that the value A8h is written at RAM address 01h (control register 1). Table 36 describe more in detail the data byte structure. Table 36. ENCP 1 Data byte description 1 - example 2 CH5 CH5 CH5 CH2 CH2 [1] [0] Bridge 2&5 CH2 [2] [2] [1] [0] 0 1 0 1 0 0 0 Hereafter the actions linked to each value of bit or group of bits: ENCP = 1: Charge pump stays activated CH5[2:0] = 010b: Channel 5 is on, PWM disabled, overcurrent recovery mode disabled, low slew rate BRIDGE_2&5 = 1: Bridge mode for channel 2 and channel 5 activated CH2[2:0] = 000b: Channel 2 is off, open-load detection in off-state disabled Table 37. Command byte 2 - example 2 MSB LSB Operating code 0 Table 38. Address 0 0 0 0 0 1 Data byte 2 - example 2 MSB 0 0 LSB 0 0 0 1 0 1 0 From Table 37 and Table 38 follow that the value 0Ah is written at RAM address 02h (control register 2). Table 39 describe more in detail the data byte structure. 38/55 Doc ID 16523 Rev 1 L99MC6 SPI control and status register Table 39. DISCP Data byte description 2 - example 2 CH1 CH1 CH1 [0] Bridge 1&4 [2] [1] [0] 0 1 0 1 0 CH4 CH4 CH4 [2] [1] 0 0 0 Hereafter the actions linked to each value of bit or group of bits: DISCP = 0: Charge pump stays activated CH4[2:0] = 000b: Channel 4 is off, open-load detection in off-state disabled BRIDGE_1&4 = 1: Bridge mode for channel 1 and channel 4 activated CH4[2:0] = 010b: Channel 1 is on, PWM disabled, overcurrent recovery mode disabled, low slew rate Figure 14. Bridge mode drawing Vs CH 2 OFF CH1 ON M CH4 OFF CH 5 ON Doc ID 16523 Rev 1 39/55 SPI control and status register 9.4.3 L99MC6 Example 3: Open-load detection in off-state in bridge configuration Table 40. Command byte 1 - example 3 MSB LSB Operating code 0 Table 41. Address 0 0 0 0 0 0 1 Data byte 1 - example 3 MSB LSB 1 1 1 1 1 0 0 0 From Table 40 and Table 41 follow that the value F8h is written at RAM address 01h (control register 1). Table 42 describe more in detail the data byte structure. Table 42. ENCP 1 Data byte description 1 - example 3 CH5 CH5 CH5 CH2 CH2 [1] [0] Bridge 2&5 CH2 [2] [2] [1] [0] 1 1 1 1 0 0 0 Hereafter the actions linked to each value of bit or group of bits: ENCP = 1: Charge pump stays activated CH5[2:0] = 111b: Channel 5 is off, open-load detection in off-state enabled BRIDGE_2&5 = 1: Bridge mode for channel 2 and channel 5 activated CH2[2:0] = 000b: Channel 2 is off, open-load detection in off-state disabled Table 43. Command byte 2 - example 3 MSB LSB Operating code 0 Table 44. Address 0 0 0 0 0 1 Data byte 2 - example 3 MSB 0 0 LSB 0 0 0 1 0 1 0 From Table 43 and Table 44 follow that the value 0Ah is written at RAM address 02h (control register 2). Table 45 describe more in detail the data byte structure. 40/55 Doc ID 16523 Rev 1 L99MC6 SPI control and status register Table 45. DISCP 0 Data byte description 2 - example 3 CH1 CH1 CH1 [0] Bridge 1&4 [2] [1] [0] 0 1 0 1 0 CH4 CH4 CH4 [2] [1] 0 0 Hereafter the actions linked to each value of bit or group of bits: DISCP = 0: Charge pump stays activated CH4[2:0] = 000b: Channel 4 is off, open-load detection in off-state disabled BRIDGE_1&4 = 1: Bridge mode for channel 1 and channel 4 activated CH1[2:0] = 010b: Channel 1 is on, PWM disabled, overcurrent recovery mode disabled, low slew rate Figure 15. Open-load in bridge mode drawing Vs CH2 OFF OL detection OFF CH1 ON OL detection OFF M CH4 OFF OL detection OFF CH5 OFF OL detection ON There are two operating conditions: Case 1: The motor is connected, drain of channel 5 is pulled up by channel 1 (on) through the motor, then no open-load detected on channel 5 Case 2: The motor is not connected and the drain voltage of channel 5 is below the open-load threshold, then open-load detected on channel 5 Doc ID 16523 Rev 1 41/55 Maximum demagnetization energy 10 L99MC6 Maximum demagnetization energy Figure 16. Configurable switch HSD - maximum turn-off current versus inductance 1 B A I (A) C 0.1 100 L (mH) A: Single pulse, Tj = 150 C B: Repetitive pulse, Tj = 100 C C: Repetitive pulse, Tj = 125 C 42/55 Doc ID 16523 Rev 1 1000 L99MC6 Maximum demagnetization energy Figure 17. Configurable switch LSD - maximum turn-off current versus inductance 1 A B I (A) C 0.1 100 L (mH) 1000 A: Single pulse, Tj = 150 C B: Repetitive pulse, Tj = 100 C C: Repetitive pulse, Tj = 125 C Doc ID 16523 Rev 1 43/55 Maximum demagnetization energy L99MC6 Figure 18. Fixed LSD switch - maximum turn-off current versus inductance 1 A I (A) B C 0.1 100 L (mH) A: Single pulse, Tj = 150 C B: Repetitive pulse, Tj = 100 C C: Repetitive pulse, Tj = 125 C 44/55 Doc ID 16523 Rev 1 1000 L99MC6 11 Application examples Application examples Figure 19. L99MC6 as driver for incandescent bulb, LEDs and high-side or low-side relays VDD 5V V S 12V Out1 Out2 IN/PWM =1 Out3 Control Out4 SCK CSN Out5 DO SPI DI Out6 GND Doc ID 16523 Rev 1 45/55 Application examples L99MC6 Figure 20. L99MC6 as motor driver (for example, for mirror adjustment) VDD 5V VS 12V Out1 Out2 IN/PWM =1 M GND Out3 M Control Out4 SCK CSN DO Out5 SPI Out6 DI GND 46/55 Doc ID 16523 Rev 1 L99MC6 Application examples Figure 21. L99MC6 as driver for unipolar stepper motor driver, relay and LEDs VDD 5V VS 12V Out1 Out2 =1 IN/PWM Out3 Control Out4 SCK SM CSN DO Out5 SPI Out6 DI GND Doc ID 16523 Rev 1 47/55 Package and PCB thermal data L99MC6 12 Package and PCB thermal data 12.1 PowerSSO-16 thermal data Figure 22. PowerSSO-16 PC board(1) . 1. Layout condition of thermal resistance measurements (PCB: double layer, thermal vias, FR4 area = 77 mm x 86 mm, PCB thickness =1.6 mm, Cu thickness = 70 m (front and back side) thermal vias separation 1.2 mm, thermal via diameter 0.3 mm +/- 0.08 mm, Cu thickness on vias 25 m, footprint dimension 2.5 mm x 4.2 mm ). Table 46. HSD 1 HSD 2 HSD 3 LSD 4 LSD 5 LSD 6 HSD 1 89.57 85.83 84.41 88.89 87.06 85.84 HSD 2 85.83 89.57 84.41 87.06 88.89 87.06 HSD 3 84.41 84.41 89.57 85.84 87.06 88.89 LSD 4 88.89 87.06 85.84 93.58 90.54 89.08 LSD 5 87.06 88.89 87.06 90.54 93.58 90.54 LSD 5 85.84 87.06 88.89 89.08 90.54 93.58 Table 47. 48/55 Auto and mutual thermal resistance - footprint Auto and mutual thermal resistance - 2 cm2 of Cu heatsink HSD 1 HSD 2 HSD 3 LSD 4 LSD 5 LSD 6 HSD 1 59.96 55.06 54.23 58.25 56.08 54.71 HSD 2 55.06 59.96 54.23 56.08 58.25 56.08 HSD 3 54.23 54.23 59.96 54.71 56.08 58.25 LSD 4 58.25 56.08 54.71 61.80 60.37 59.45 LSD 5 56.08 58.25 56.08 60.37 61.80 60.37 LSD 5 54.71 56.08 58.25 59.45 60.37 61.80 Doc ID 16523 Rev 1 L99MC6 Package and PCB thermal data Table 48. Auto and mutual thermal resistance - 8 cm2 of Cu heatsink HSD 1 HSD 2 HSD 3 LSD 4 LSD 5 LSD 6 HSD 1 46.51 43.16 41.49 45.19 43.06 42.08 HSD 2 43.16 46.51 41.49 43.06 45.19 43.06 HSD 3 41.49 41.49 46.51 42.08 43.06 45.19 LSD 4 45.19 43.06 42.08 47.19 46.31 45.19 LSD 5 43.06 45.19 43.06 46.31 47.19 46.31 LSD 5 42.08 43.06 45.19 45.19 46.31 47.19 Equation 1 represents Tj-amb calculation of a full loaded device for the HSD1 junction. Equation 1 THSD1 = RthHSD1 PdHSD1 + RthHSD1, HSD2 PdHSD2 + RthHSD1, HSD3 PdHSD3 + + RthHSD1, LSD 4 PdLSD 4 + RthHSD1, LSD5 PdLSD5 + RthHSD1, LSD 6 PdLSD6 Doc ID 16523 Rev 1 49/55 Package and packing information L99MC6 13 Package and packing information 13.1 ECOPACK(R) In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK(R) packages, depending on their level of environmental compliance. ECOPACK(R) specifications, grade definitions and product status are available at: www.st.com. ECOPACK(R) is an ST trademark. 13.2 PowerSSO-16 package information Figure 23. PowerSSO-16 package dimensions 50/55 Doc ID 16523 Rev 1 L99MC6 Package and packing information PowerSSO-16 mechanical data(1) Table 49. Symbol Millimeters Min. Typ. Max. A 1.25 - 1.72 A1 0.00 - 0.10 A2 1.10 - 1.62 B 0.18 - 0.36 C 0.19 - 0.25 D(2) 4.80 - 5.00 E 3.80 - 4.00 e - 0.50 - H 5.80 - 6.20 h 0.25 - 0.50 L 0.40 - 1.27 k 0d - 8d X 1.90 - 2.50 Y 3.60 - 4.20 - 0.10 ddd 1. Drawings dimensions include single and matrix versions. 2. Dimensions D does not include mold flash protrusions or gate burrs. Mold flash protrusions or gate burrs shall not exceed 0.15 mm in total (both side). Doc ID 16523 Rev 1 51/55 Package and packing information 13.3 L99MC6 Packing information Figure 24. PowerSSO-16 tube shipment (no suffix) B Base Q.ty Bulk Q.ty Tube length ( 0.5) A B C ( 0.1) C A 100 2000 532 1.85 6.75 0.6 All dimensions are in mm. Figure 25. PowerSSO-16 tape and reel shipment (suffix "TR") REEL DIMENSIONS Base q.ty Bulk q.ty A (max) B (min) C ( 0.2) F G (+ 2 / -0) N (min) T (max) 2500 2500 330 1.5 13 20.2 12.4 60 18.4 TAPE DIMENSIONS According to Electronic Industries Association (EIA) Standard 481 rev. A, Feb. 1986 Tape width Tape hole spacing Component spacing Hole diameter Hole diameter Hole position Compartment depth Hole spacing W P0 ( 0.1) P D ( 0.05) D1 (min) F ( 0.1) K (max) P1 ( 0.1) 12 4 8 1.5 1.5 5.5 4.5 2 End All dimensions are in mm. Start Top cover tape No components Components No components 500mm min Empty components pockets saled with cover tape. User direction of feed 52/55 Doc ID 16523 Rev 1 500mm min L99MC6 Acronyms Appendix A Acronyms Table 50. Acronyms Acronym Name CSN Chip select not CTRL Control register POR Power-on reset SCK Serial clock SDI Serial data input SDO Serial data output SPI Serial peripheral interface SR Slew rate STAT Status register Doc ID 16523 Rev 1 53/55 Revision history L99MC6 Revision history Table 51. 54/55 Document revision history Date Revision 18-Nov-2009 1 Changes Initial release. Doc ID 16523 Rev 1 L99MC6 Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries ("ST") reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST's terms and conditions of sale. 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