November 2009 Doc ID 16523 Rev 1 1/55
1
L99MC6
Configurable 6-channel device
Features
■3 independently self configuring high-/low-side
channels
■3 low-side channels
■RON =0.7 Ω (typ) at Tj = 25 °C
■Current limit of each output at min. 0.6 A
■PWM direct mode
■Bulb mode with recovery mode
■LED mode with slew rate control
■Bridge mode with crosscurrent protection
■SPI interface for data communication
■Temperature warning
■All outputs overtemperature protected
■All outputs short-circuit protected
■Configurable open-load detection in off mode
■VCC supply voltage 3.0 V to 5.25 V
■Very low current consumption in standby mode
5 µA (typ)
■Internal clamp diodes
■HS switches operate down to 3 V crank voltage
Applications
■Relay driver
■LED driver
■Motor driver
■Mirror adjustment
Description
The L99MC6 IC is a highly flexible monolithic
medium current output driver that incorporates 3
dedicated low-side outputs (channels 4 to 6) and
3 independently self configuring outputs
(channels 1 to 3) that can be used as either low-
side or high-side drivers in any combination. The
L99MC6 can control inductive loads,
incandescent bulbs or LEDs.
The L99MC6 can be used in a half bridge
configuration with crosscurrent protection.
The channel 2 can be controlled directly via the
IN/PWM pin for PWM applications. The IN/PWM
signal can be applied to any other output.
The integrated 16-bit standard serial peripheral
interface (SPI) controls all outputs and provides
diagnostic information: normal operation, open-
load in off-state, overcurrent, temperature
warning, overtemperature.
PowerSSO-16
Table 1. Device summary
Package
Order codes
Part number (tube) Part number (tape & reel)
PowerSSO-16 L99MC6-LF L99MC6TR-LF
www.st.com
Contents L99MC6
2/55 Doc ID 16523 Rev 1
Contents
1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
1.1 Application diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
1.2 Block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.1 Dual power supply: VS and VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.1.1 Channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.2 Standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.3 Inductive loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.4 Diagnostic functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.4.1 Direct input IN/PWM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.4.2 Temperature warning and thermal shutdown . . . . . . . . . . . . . . . . . . . . . 14
2.4.3 Open-load detection in off-state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.4.4 Overload detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.5 Bridge mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.6 LED mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.7 Bulb mode (programmable soft start function to drive loads with higher
inrush current) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4 ESD protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
5.1 Temperature warning and thermal shutdown . . . . . . . . . . . . . . . . . . . . . . 19
6 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
6.1 Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
6.2 Undervoltage detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
6.3 Channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
7 SPI electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
7.1 DC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
L99MC6 Contents
Doc ID 16523 Rev 1 3/55
7.2 AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
7.3 Dynamic characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
7.4 SPI timing parameter definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
8 Functional description of the SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
8.1 Signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
8.1.1 Serial clock (SCK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
8.1.2 Serial data input (SDI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
8.1.3 Serial data output (SDO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
8.1.4 Chip select not (CSN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
8.2 SPI communication flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
8.2.1 General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
8.2.2 Command byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
8.2.3 Global status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
8.3 Write operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
8.4 Read operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
8.5 Read and Clear Status operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
8.6 Read Device Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
9 SPI control and status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
9.1 RAM memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
9.2 ROM memory map (access with OC0 and OC1 set to ‘1’) . . . . . . . . . . . . 34
9.3 Control and status registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
9.3.1 Channel configuration decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
9.3.2 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
9.4 Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
9.4.1 Example 1:Switch on channel 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
9.4.2 Example 2: Bridge mode configuration . . . . . . . . . . . . . . . . . . . . . . . . . 38
9.4.3 Example 3: Open-load detection in off-state in bridge configuration . . . 40
10 Maximum demagnetization energy . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
11 Application examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
12 Package and PCB thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
12.1 PowerSSO-16 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Contents L99MC6
4/55 Doc ID 16523 Rev 1
13 Package and packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
13.1 ECOPACK® . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
13.2 PowerSSO-16 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
13.3 Packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Appendix A Acronyms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
L99MC6 List of tables
Doc ID 16523 Rev 1 5/55
List of tables
Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Table 2. Pin functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 3. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 4. ESD protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 5. Temperature warning and thermal shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 6. Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 7. Undervoltage detection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 8. Channels. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 9. DC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 10. AC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 11. Dynamic characteristic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 12. Command byte - general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 13. Data byte - general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 14. Command byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 15. Operating code definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 16. Global status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 17. Global status register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 18. Command byte for Write mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 19. Command byte for Read mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 20. Command byte for Read and Clear Status operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 21. Command byte for Read Device Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 22. RAM memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 23. ROM memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 24. Control register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 25. Control register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Table 26. Control register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Table 27. Status register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Table 28. Status register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Table 29. Channel configuration decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 30. Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 31. Command byte - example 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Table 32. Data byte - example 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Table 33. Data byte description - example 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Table 34. Command byte 1 - example 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Table 35. Data byte 1 - example 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Table 36. Data byte description 1 - example 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Table 37. Command byte 2 - example 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Table 38. Data byte 2 - example 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Table 39. Data byte description 2 - example 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Table 40. Command byte 1 - example 3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Table 41. Data byte 1 - example 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Table 42. Data byte description 1 - example 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Table 43. Command byte 2 - example 3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Table 44. Data byte 2 - example 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Table 45. Data byte description 2 - example 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Table 46. Auto and mutual thermal resistance - footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Table 47. Auto and mutual thermal resistance - 2 cm2 of Cu heatsink. . . . . . . . . . . . . . . . . . . . . . . . 48
Table 48. Auto and mutual thermal resistance - 8 cm2 of Cu heatsink. . . . . . . . . . . . . . . . . . . . . . . . 49
List of tables L99MC6
6/55 Doc ID 16523 Rev 1
Table 49. PowerSSO-16 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Table 50. Acronyms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Table 51. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
L99MC6 List of figures
Doc ID 16523 Rev 1 7/55
List of figures
Figure 1. Application diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 2. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 3. Configuration diagram (top view) not in scale. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 4. Power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 5. Output voltage clamping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 6. Example of bridge configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 7. Example of programmable soft start function for inductive loads and incandescent bulbs. 16
Figure 8. Serial input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 9. Serial input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 10. Output turn on/off delays and slew rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 11. Clock polarity and clock phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 12. SPI frame structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 13. Indication of the global error flag on DO when CSN is low and SCK is stable . . . . . . . . . . 31
Figure 14. Bridge mode drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Figure 15. Open-load in bridge mode drawing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Figure 16. Configurable switch HSD - maximum turn-off current versus inductance. . . . . . . . . . . . . . 42
Figure 17. Configurable switch LSD - maximum turn-off current versus inductance . . . . . . . . . . . . . . 43
Figure 18. Fixed LSD switch - maximum turn-off current versus inductance. . . . . . . . . . . . . . . . . . . . 44
Figure 19. L99MC6 as driver for incandescent bulb, LEDs and high-side or low-side relays . . . . . . . 45
Figure 20. L99MC6 as motor driver (for example, for mirror adjustment) . . . . . . . . . . . . . . . . . . . . . . 46
Figure 21. L99MC6 as driver for unipolar stepper motor driver, relay and LEDs. . . . . . . . . . . . . . . . . 47
Figure 22. PowerSSO-16 PC board(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Figure 23. PowerSSO-16 package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Figure 24. PowerSSO-16 tube shipment (no suffix) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Figure 25. PowerSSO-16 tape and reel shipment (suffix “TR”) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Introduction L99MC6
8/55 Doc ID 16523 Rev 1
1 Introduction
1.1 Application diagram
Figure 1. Application diagram
DI SPI
CONTROL
LOGIC
GND
CSN
SCK
DO
VBat
PWM / IN
Driver and
Protections
Config. OUT1
OL
Driver and
Protections
Config. OUT2
OL
Driver and
Protections
Config. OUT3
OL
Driver and
Protections
LSD OUT4
OL
Driver and
Protections
LSD OUT5
OL
Driver and
Protections
LSD OUT6
OL
Charge
Pump
VREG
Microcontroller
Vcc M
Active reverse
polarity protection
L99MC6 Introduction
Doc ID 16523 Rev 1 9/55
1.2 Block diagram and pin description
Figure 2. Block diagram
0
DI
CSN
SCK
DO
VCC
VCC
IN/PWM
OL
VOLD 1
OL
=1
OL
OL
OL
OL
SPI
GND
DRN1
SRC1
DRN2
SRC2
DRN3
SRC3
DRN4
DRN5
DRN6
VOLD 2
VOLD 3
VOLD 4
VOLD 5
VOLD 6
VOLS 1
VOLS 2
VOLS 3
Open Load Drain [Out1]
Open Load Source [Out1]
Short Circuit [Out1]
ON/OFF [Out1]
Open Load Drain [Out2]
Open Load Source [Out2]
Short Circuit [Out2]
ON/OFF [Out2]
Open Load Drain [Out3]
Open Load Source [Out3]
Short Circuit [Out3]
ON/OFF [Out3]
Open Load Drain [Out4]
Short Circuit [Out4]
ON/OFF [Out4]
Open Load Drain [Out5]
Short Circuit [Out5]
ON/OFF [Out5]
Open Load Drain [Out6]
Short Circuit [Out6]
ON/OFF [Out6]
CONTROL LOGIC
Charge
Pump
VCP
VCC
VCC
VCC
VDrive1 -3 VDrive1 -3
VDrive1-3
VDrive1-3
Introduction L99MC6
10/55 Doc ID 16523 Rev 1
Table 2. Pin functions
Pin Symbol Function
1 / TAB GND Ground:
Reference potential
6IN/PWM
IN/PWM direct mode:
Direct input for channel 2. Other channels can be driven in PWM mode via SPI.
8VCC
Logic voltage supply 3.3 V/5 V:
For this input a ceramic capacitor as close as possible to GND is recommended
3 SRC1 Source of configurable channel 1
4 DRN1 Drain of self configurable channel 1, in HS mode also VS supply
5 DRN2 Drain of self configurable channel 2
15 SRC2 Source of self configurable channel 2
12 DRN3 Drain of self configurable channel 3
13 SRC3 Source of self configurable channel 3
2 DRN4 Drain of channel 4
16 DRN5 Drain of channel 5
14 DRN6 Drain of channel 6
11 DI
SPI data in:
The input requires CMOS logic levels and receives serial data from the
microcontroller. The data is a 16-bit control word and the most significant bit
(MSB, bit 7) is transferred first.
9DO
SPI data out:
The diagnosis data is available via the SPI and this tristate-output. The output
remains in tristate, if the chip is not selected by the input CSN (CSN = high).
7CSN
SPI chip select not (active low):
This input is low active and requires CMOS logic levels. The serial data transfer
between the L99MC6 and microcontroller is enabled by pulling the input CSN to
low-level.
10 SCK
SPI serial clock input:
This input controls the internal shift register of the SPI and requires CMOS logic
levels.
L99MC6 Introduction
Doc ID 16523 Rev 1 11/55
Figure 3. Configuration diagram (top view) not in scale
GND
DRN4
SRC1
DRN1
DRN2
PWM/IN
CSN
VCC
DRN5
SRC2
SRC3
DRN3
DI
SCK
DO
DRN6
1
2
3
4
5
7
8
6
16
15
14
13
12
8
9
11
The tab must be connected to GND
TAB = GND
PowerSSO-16
Description L99MC6
12/55 Doc ID 16523 Rev 1
2 Description
2.1 Dual power supply: VS and VCC
The supply voltage VCC (3.3 V/5 V) supplies the whole device. In case of power-on (VCC
increases from undervoltage to VPOR OFF = 2.7 V, typical) the circuit is initialized by an
internally generated power-on reset (POR). If the voltage VCC decreases under the
minimum threshold (VPOR ON = 2.4 V, typical), the outputs are switched-off (high-
impedance) and the status registers are cleared (see Figure 4).
Figure 4. Power-on reset
2.1.1 Channels
The channels 1 to 3 are self configuring high-side or low-side n-channel mosfets. This
flexibility allows the user to connect loads in high-side or low-side configuration in any
combination.
In order to provide low Rdson values for high-side configured switches (channels 1 to 3), a
charge pump (CP) to drive the internal gate voltage(s) is implemented. If the charge pump is
activated (ENCP1 = 1, DISCP2 = 0, see Section 9.3: Control and status registers), the
internal charge-pump uses VS from the drain of channel 1, as its power source. Otherwise
VCC is used to drive all channels.
The channels 4 to 6 are n-channel low-side drivers. The source of the respective mosfet are
internally connected to the device GND.
Caution: For any high-side configuration, channel 1 must be used as a high-side switch.
If channel 1 is configured as low-side, the charge pump has to be deactivated to avoid
charge pump current from the drain.
Caution: The charge pump may not be deactivated (see Section 9.3: Control and status registers) if
one of the channels is in high-side configuration, while a short-circuit from the source to the
battery is present. If these conditions occur, the voltage of the shorted source is applied to
the VCC pin.
VPOR hyst.
IC is disabled
All Status Registers are cleared
VPOR OFF
VPOR ON
VCC
L99MC6 Description
Doc ID 16523 Rev 1 13/55
2.2 Standby mode
The standby mode of the L99MC6 is activated by SPI command (EN bit of CTRL 0 reset to
0, see Section 9.3.2: Register description). The inputs and outputs are switched-off. The
status registers are cleared and the control registers are reset to their default values.
In the standby mode the current consumption is 5 µA (typical value). A SPI command is
needed to switch the L99MC6 in normal mode.
2.3 Inductive loads
Each switch is built by a power DMOS transistor. For low-side configured outputs an internal
zener clamp from the drain to gate with a breakdown of 31 V minimum provides for fast turn-
off of inductive loads.
For high-side configured outputs, an internal zener clamp with a breakdown of -15 V
maximum provides for fast turn-off of inductive loads (Figure 5).
The maximum clamping energy is specified in Chapter 10.
Figure 5. Output voltage clamping
2.4 Diagnostic functions
All diagnostic functions (overload, open-load, temperature warning and thermal shutdown)
are internally filtered and the condition has to be valid for at least 32 µs (open-load: typ.
400 µs, respectively) before the corresponding status bit in the status registers are set. The
filters are used to improve the noise immunity of the device. Open-load and temperature
warning function are intended for information purpose and do not change the state of the
output drivers. On contrary, the overload and thermal shutdown condition disable the
corresponding driver (overload) or all drivers (thermal shutdown), respectively. Without
setting the overcurrent recovery bit in the input data register to logic high, the microcontroller
has to clear the overcurrent status bit to reactivate the corresponding driver. (All switches
have a corresponding overcurrent recovery bit) If this bit is set, the device automatically
switches-on the outputs again after a short recovery time. With this feature the device can
drive loads with start-up currents higher than the overcurrent limits (that is inrush current of
incandescent lamps, cold resistance of motors and heaters, Figure 7).
Time
Low Side Configuration
GND
Drain Clamp
Voltage
(VDRN_CL1-6) = 35V)
VS
Output Current
Drain Voltage
Time
High Side Configuration
VS
Source Voltage
Output Current
GND
Source Clamp
Voltage
(VSRC_CL1-3) = -19V)
Description L99MC6
14/55 Doc ID 16523 Rev 1
2.4.1 Direct input IN/PWM
The IN/PWM input allows channel 2 to be enabled without the use of SPI. The IN/PWM pin
is OR-ed with the SPI command bit. This pin can be left open if the channel 2 is controlled
only via the SPI. This input has an internal pull-down.
The IN/PWM signal can also be applied to any other switches by the activation of the PWM
mode.
This input is suited for non-inductive loads that are pulse width modulated. This allows PWM
control without further use of the SPI.
2.4.2 Temperature warning and thermal shutdown
If the junction temperature rises above Tj TW a temperature warning flag is set and is
detectable via the SPI. If the junction temperature increases above the second threshold
TjSD
, the thermal shutdown bit is set and power DMOS transistors of all output stages are
switched-off to protect the device. Temperature warning flag and thermal shutdown bits are
latched. In order to reactivate the output stages, the junction temperature must decrease
below TjSD-TjSDHYS
and the thermal shutdown bit has to be cleared by the
microcontroller.
2.4.3 Open-load detection in off-state
The open-load detection monitors the load at each output stage in off mode. A current
source of 150 µA (IOLD1-6, IOLS 1-3) is connected between drain and source or GND. An
open-load failure is detected if the drain or source voltage reaches an internal VOLD/S (2.0 V)
for at least 3 ms (tdOL typ.). The corresponding open-load bit is set in the status register. In
LED mode the open-load detection is disabled and the current source is switched-off, which
avoids a turn-on of the LEDs in off-state.
2.4.4 Overload detection
In case of an overcurrent condition, a flag is set in the corresponding status register. If the
overcurrent signal is valid for at least tISC = 32 µs, the overcurrent flag is set and the
corresponding driver is switched-off to reduce the power dissipation and to protect the
integrated circuit. If the overcurrent recovery bit of the output is zero the microcontroller has
to clear the status bit to reactivate the corresponding driver.
2.5 Bridge mode
The L99MC6 can be configured as bridge driver. Up to three half bridges can be used. In
Bridge mode the device is crosscurrent protected by an internal delay time. If one driver (LS
or HS) is turned-off the activation of the other driver of the same half bridge is automatically
delayed by the crosscurrent protection time. After the crosscurrent protection time is expired
the slew rate limited switch-off phase of the driver is changed to a fast turn-off phase and the
opposite driver is turned-on with slew-rate limitation. Due to this behavior it is always
guaranteed that the previously activated driver is totally turned-off before the opposite driver
starts to conduct.
Due to the built-in reverse diodes of the output transistors, inductive loads can be driven at
the outputs without external free-wheeling diodes.
L99MC6 Description
Doc ID 16523 Rev 1 15/55
The following combination must be used: channel 1 + 4, channel 2 + 5, channel 3 + 6
(Figure 6).
A VS voltage exceeding the low-side clamping voltage (VDRN_CL1-6) , while the high one of
the high-side drivers is turned on, may cause a destruction of the device.
Caution: In bridge mode using channels 2 and 5, the IN/PWM pin has to be grounded. Therefore
PWM mode on other channels is not possible.
Figure 6. Example of bridge configuration
2.6 LED mode
Open-load detection in off-state can be deactivated to avoid the turn on of the LEDs by the
current source (150 µA typ.) when the channel is switched-off.
Moreover, it is possible to select a high slew rate to support PWM operations with small duty
cycle (see Section 9.3.1: Channel configuration decoding).
Control
VDD 5V
SPI
=1
Out1
Out2
Out3
Out4
Out5
Out6
GND
IN/PWM
VS12V
M
GND
SCK
CSN
DO
DI
M
Description L99MC6
16/55 Doc ID 16523 Rev 1
2.7 Bulb mode (programmable soft start function to drive loads
with higher inrush current)
Loads with start-up currents higher than the overcurrent limits (for example inrush current of
lamps, start current of motors and cold resistance of heaters) can be driven by using the
programmable soft start function (that is overcurrent recovery mode). Each driver has a
corresponding overcurrent recovery bit. If this bit is set, the device automatically switches-on
the outputs again after a fixed recovery time. The PWM modulated current provides
sufficient average current to power up the load (for example heat up the bulb) until the load
reaches operating condition (Figure 6).
The device itself cannot distinguish between a real overload and a non linear load like a light
bulb. A real overload condition can only be qualified by time. As an example the
microcontroller can switch-on light bulbs by setting the overcurrent recovery bit for the first
50 ms. After clearing the recovery bit, the output is automatically disabled if the overload
condition still exits.
Figure 7. Example of programmable soft start function for inductive loads and incandescent
bulbs
Load Current
Unlimited Inrush Current
Limited Inrush Current in
overcurrent recovery
mode with inductive load
t
Load Current
Unlimited Inrush Current
Limited Inrush Current in
overcurrent recovery mode
with incandescent bulb
t
L99MC6 Absolute maximum ratings
Doc ID 16523 Rev 1 17/55
3 Absolute maximum ratings
Stressing the device above the rating listed in Ta b l e 3 may cause permanent damage to the
device. These are stress ratings only and operation of the device at these or any other
conditions above those indicated in the operating sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect device
reliability. Refer also to the STMicroelectronics™ SURE program and other relevant quality
document.
All maximum ratings are absolute ratings. Leaving the limitation of any of these values may
cause an irreversible damage of the integrated circuit.
Table 3. Absolute maximum ratings
Symbol Parameter Value Unit
VS (DRN1 HS
config)
DC supply voltage -0.3 to 28 V
Single pulse tmax < 400 ms in HS or LS
configuration with Rload min = 40 Ω(1)
1. The device requires a minimum load impedance of 40 Ω to sustain a load dump pulse of 40 V according to
the ISO 7637 pulse 5b.
40 V
Single pulse tmax < 400 ms in bridge mode VDRN_CL1-6 V
VCC Stabilized supply voltage, logic supply -0.3 to 5.5 V
DI, DO, SCK,
CSN, IN Digital input/output voltage -0.3 to VCC + 0.3 V
DRN 1-6 Output current capability ±1,65 A
SRC 1-3 Output current capability ±1,65 A
GND Current capability 3,30 A
TjOperating junction temperature -40 to 150 °C
ESD protection L99MC6
18/55 Doc ID 16523 Rev 1
4 ESD protection
Table 4. ESD protection
Parameter Value Unit
All pins ±2(1)
1. HBM according to MIL 883C, Method 3015.7 or EIA/JESD22-A114-A
kV
Output pins: DRN1 – DRN6; SRC1, SRC3, SRC5 ±4(2)
2. HBM with all unzapped pins grounded
kV
Machine model (CDF-AEC-Q100-03 rev. F) ±200 V
Charged device model (CDF-AEC-Q100-011 Rev. F) ±1500 V
L99MC6 Thermal data
Doc ID 16523 Rev 1 19/55
5 Thermal data
5.1 Temperature warning and thermal shutdown
For additional information, please refer to Chapter 12: Package and PCB thermal data.
Table 5. Temperature warning and thermal shutdown
Item Symbol Parameter Min. Typ. Max. Unit
5.2.1 TjTW ON
Temperature warning threshold
junction temperature Tj increasing 150 °C
5.2.2 TjTW OFF
Temperature warning threshold
junction temperature Tj decreasing 130 °C
5.2.3 TjTW HYS Temperature warning hysteresis - 5 K
5.2.4 TjSD ON
Thermal shutdown threshold
junction temperature Tj increasing 170 °C
5.2.5 TjSD OFF
Thermal shutdown threshold
junction temperature Tj decreasing 150 °C
5.2.6 TjSD HYS Thermal shutdown hysteresis - 5 K
Electrical characteristics L99MC6
20/55 Doc ID 16523 Rev 1
6 Electrical characteristics
VS=6V to16V,VCC = 3.0 V to 5.3 V, Tj= -40 °C to 150 °C, unless otherwise specified.
The voltages are referred to GND and currents are assumed positive, when the current
flows into the pin.
6.1 Supply
6.2 Undervoltage detection
Table 6. Supply
Item Symbol Parameter Test condition Min. Typ. Max. Unit
6.1.1 VS
Operating supply voltage
range 628V
6.1.2 ISVS DC supply current
VS=13V, V
CC =5.0V
active mode
DRN1 = VS
Outputs floating
1.5 2.0 mA
6.1.3 IVS VS quiescent supply current
VS=13V, V
CC =5V
standby mode
DRN1 = VS
TTes t = -40 °C, 25 °C
Outputs floating
310μA
TTes t =130 °C 6 20 μA
6.1.4 VCC
Operating supply voltage
range 3.0 5.3 V
6.1.5
ICC
VCC DC supply current VS=13V, V
CC =5.0V
active mode 1.3 2 mA
6.1.6 VCC quiescent supply
current
VS=13V, V
CC =5.0V
CSN = VCC
standby mode
Outputs floating
520µA
Table 7. Undervoltage detection
Item Symbol Parameter Test Condition Min. Typ. Max. Unit
6.2.1 VPOR OFF Power-on reset threshold VCC increasing 3.0 V
6.2.2 VPOR ON Power-on reset threshold VCC decreasing 2.2 V
6.2.3 VPOR hyst Power-on reset hysteresis VPOR OFF - VPOR ON 0.3 V
L99MC6 Electrical characteristics
Doc ID 16523 Rev 1 21/55
6.3 Channels
Table 8. Channels
Item Symbol Parameter Test condition Min. Typ. Max. Unit
6.3.1 rON SWI1-3
On resistance drain to
source in HS configuration
VS=13.5 V, Tj=25°C,
CP on, Iload =250mA - 700 900 mΩ
VS=13.5 V, Tj=125°C,
CP on, Iload =250mA - 1100 1500 mΩ
VS=6.0V T
j=25°C,
CP on, Iload =125mA - 700 900 mΩ
VS=6.0V, T
j=125°C,
CP on, Iload =125mA - 1100 1500 mΩ
VS=4.5V T
j=25°C,
CP on, Iload =125mA - 800 1500 mΩ
VS=4.5V, T
j=125°C,
CP on, Load = 125 mA - 1300 2000 mΩ
VS=3V, T
j=25°C,
CP on, Iload =125mA - 1600 2600 mΩ
6.3.2 rON SWI1-6
On resistance drain to
source or GND,
in LS configuration
VCC=5.0 V, Tj=25°C,
Load = 250 mA - 750 1000 mΩ
VCC = 5.0 V, Tj=125°C,
Iload =250mA - 1100 1500 mΩ
VCC = 3.3 V, Tj=25°C,
Iload =250mA - 900 1250 mΩ
VCC = 3.3 V, Tj=125°C,
Iload =250mA - 1400 1800 mΩ
6.3.3 ISC1-6 Overcurrent protection Channels 1 to 3 0.7 1.0 1.4 A
Channels 4 to 6 0.6 0.8 1.0 A
6.3.4 td ON1-6
Output delay time,
switch-on VS= 13.5 V, VCC = 5.0 V - 50 100 μs
6.3.5 td OFF1-6
Output delay time,
switch-off VS= 13.5 V, VCC = 5.0 V - 50 100 μs
6.3.6 td ONLED1-6
Output delay time,
switch-on LED VS= 13.5 V, VCC =5.0V - 15 40 μs
6.3.7 tdOFFLED1-6
Output delay time,
switch-off LED VS= 13.5 V, VCC =5.0V - 15 40 μs
6.3.8 tDHL
Crosscurrent protection
time Only in Bridge mode - 200 500 μs
6.3.9 IQLD
Switched-off output current
DRN 1-6
VDRN2-6 =V
S, LED mode,
CP off 0-5µA
VDRN1 -20 µA
Electrical characteristics L99MC6
22/55 Doc ID 16523 Rev 1
6.3.10 IQLS
Switched-off output current
SRC 1-3
VSRC1-3 =GND,
LED mode --15-25µA
6.3.11 VOLD1-6
Drain open-load detection
voltage on drain 1,1 2,0 2,5 V
6.3.12 IOLD1-6
Open-load detection
current on drain @ VOLD 80 190 280 µA
6.3.13 VOLS1-3
Source open-load detection
voltage on source 1,1 2,0 2,5 V
6.3.14 IOLS1-3
Open-load detection
current on source @ VOLS -80 -190 -280 µA
6.3.15 tdOL
Minimum duration of open-
load condition to set the
status bit
Guaranteed by design 2 3 4 ms
6.3.16 tISC
Minimum duration of
overcurrent condition to
switch-off the driver
Guaranteed by design 10 - 100 µs
6.3.17 dVOUT1/dt Slew rate of channel 1 to 6 VS=13.5V, V
CC =5.0V
Iload =54Ω0.1 0.25 0.4 V/µs
6.3.18 dVOUT1LED/dt Slew rate of channel 1 to 6
in LED mode
VS=13.5V, V
CC =5.0V
Iload =54 Ω0.5 1.25 2.0 V/µs
6.3.19 VDRN_CL1-6
Drain clamp voltage
(low-side)
Source = GND
Iload =0.25A 31 35 39 V
6.3.20 VSRC_CL1-3
Source clamp voltage
(high-side)
Drain = VS, Iload = 0.25 A -22 -19 -15 V
Standby -22 10 -1,5 V
Table 8. Channels (continued)
Item Symbol Parameter Test condition Min. Typ. Max. Unit
L99MC6 SPI electrical characteristics
Doc ID 16523 Rev 1 23/55
7 SPI electrical characteristics
VS=6V to16V,VCC = 3.0 V to 5.3 V, Tj= -40 °C to 150 °C, unless otherwise specified.
The voltages are referred to GND and currents are assumed positive, when the current
flows into the pin
7.1 DC characteristics
7.2 AC characteristics
Table 9. DC characteristics
Symbol Parameter Test condition Min Typ Max Unit
DI, SCK, CSN, PWM
VIL Low-level input voltage - 0.3VDD V
VIH High-level input voltage - 0.7VDD V
RCSN in Pull-up resistor at input CSN - 20 50 80 kΩ
RCLK in Pull-down resistor at input CLK - 20 50 80 kΩ
RDI in Pull-down resistor at input DI - 20 50 80 kΩ
DO
VOL Low-level output voltage IOUT = 5 mA 0.3VDD V
VOH High-level output voltage IOUT = 5 mA 0.7VDD V
Table 10. AC characteristics
Symbol Parameter Test condition Min Typ Max Unit
DI, DO, SCK, CSN
COUT Output capacitance (DO) VOUT = 0 to 5 V - - 10 pF
CIN
Input capacitance (DI) VIN = 0 to 5 V - - 10 pF
Input capacitance (other pins) VIN = 0 to 5 V - - 10 pF
SPI electrical characteristics L99MC6
24/55 Doc ID 16523 Rev 1
7.3 Dynamic characteristics
Table 11. Dynamic characteristic
Symbol Parameter Test condition Min Typ Max Unit
fCClock frequency - - - 1 MHz
tSCSN CSN low setup time see Figure 8 120 - - ns
tHCSN CSN high setup time see Figure 8 1--μs
tCSNQV CSN falling until DO valid - 5 130 250 ns
tCSNQT CSN rising until DO tristate - 150 650 1000 ns
tSSCK
SCK setup time before CSN
rising - 200 - - ns
tSSDI Data in setup time see Figure 8 20 - - ns
tCHDX Data hold setup time see Figure 8 30 - - ns
tHSCK SCK high time see Figure 8 115 - - ns
tLSCK SCK low time see Figure 8 115 - - ns
tSCKQV Clock high to output valid COUT = 100 pF - 150 - ns
tQLQH Output rise time COUT = 100 pF - 110 - ns
tQHQL Output fall time COUT = 100 pF - 110 - ns
tenDOtriH
DO enable time from tristate to
high-level
COUT = 100 pF, IOUT = -1 mA,
pull-down load to GND - 100 250 ns
tenDOtriL
DO enable time from tristate to
low-level
COUT = 100 pF, IOUT=1 mA,
pull-up load to VCC
- 100 250 ns
tdisDOHtri
DO disable time from high-level
to tristate
COUT = 100 pF, IOUT = -4 mA,
pull-down load to GND - 625 720 ns
tdisDOLtri
DO disable time from low-level
to tristate
COUT = 100 pF, IOUT =4mA,
pull-up load to VCC
- 540 620 ns
L99MC6 SPI electrical characteristics
Doc ID 16523 Rev 1 25/55
7.4 SPI timing parameter definition
Figure 8. Serial input timing
Figure 9. Serial input timing
CSN
SDO Data out
tCSNQT
tSCKQV
SCK
Data out
tHSCK tLSCK
tSCSN
tHCSN
Data in Data in
tSSDI
SDI
tCSNQV
tSSCK
tdisDO H tri
tenD O tri H
tdisDO L tri
tenD O tri L
CSN
SDO
pull-up load to VCC
CL=100pF
SDO
pull-down load to GND
CL=100pF
SPI electrical characteristics L99MC6
26/55 Doc ID 16523 Rev 1
Figure 10. Output turn on/off delays and slew rates
50%
90%
10%
VINIPWM VDD
GND
GND
GND
Lowside
High Side
Vsource X
Vdrain X
20%
80%
20%
Tdon1-6
80%
dVout1x/dt
50%
90%
VIN/PWM
VDD
GND
GND
Lowside
High Side
Vsource X
Vdrain X
20%
10%
Tdoff1-6
dVout1x/dt
90% 80%
20%
L99MC6 Functional description of the SPI
Doc ID 16523 Rev 1 27/55
8 Functional description of the SPI
8.1 Signal description
8.1.1 Serial clock (SCK)
This input signal provides the timing of the serial interface. Data present at serial data input
(SDI) is latched on the rising edge of serial clock (SCK). Data on serial data output (SDO) is
shifted out at the falling edge of serial clock (see Figure 11).
The SPI can be driven by a microcontroller with its SPI peripherals running in following
mode: CPOL = 0 and CPHA = 0 (see Figure 11).
8.1.2 Serial data input (SDI)
This input is used to transfer data serially into the device. It receives the data to be written.
Values are latched on the rising edge of serial clock (SCK).
8.1.3 Serial data output (SDO)
This output signal is used to transfer data serially out of the device. Data is shifted out on the
falling edge of serial clock (SCK).
DO also reflects the status of the <Global Error Flag> (<Global Status Register>, bit 7) while
CSN is low and no clock signal is present
8.1.4 Chip select not (CSN)
When this input signal is high, the device is deselected and serial data output (SDO) is high-
impedance. Driving this input low enables the communication. The communication must
start and stop on a low-level of serial clock (SCK).
Figure 11. Clock polarity and clock phase
Functional description of the SPI L99MC6
28/55 Doc ID 16523 Rev 1
Figure 12. SPI frame structure
CSN
SDO
SDI Command Byte
(8 bit)
SPI-Frame Structure
Global Status Byte
(8 bit)
Data
(8, 16 or 24 bit)
MSB MSB LSBLSB
Data
(previous content of regi ster)
Write Operation
CSN
SDO
SDI Command Byte
(8 bit)
Global Status Byte
(8 bit)
Don’t care
(8, 16 or 24 bit)
MSB MSB LSBLSB
Data
(8, 16 or 24 bit)
Read Operation
MSB LSB
MSB LSB
L99MC6 Functional description of the SPI
Doc ID 16523 Rev 1 29/55
8.2 SPI communication flow
8.2.1 General description
The proposed SPI communication is based on a standard SPI interface structure using CSN
(chip select not), SDI (serial data in), SDO (serial data out/error) and SCK (serial clock)
signal lines.
At the beginning of each communication the master reads the <SPI-frame-ID> register
(ROM address 3EH) of the slave device. This 8-bit register indicates the SPI frame length
(16 bit for the L99MC6) and the availability of additional features.
Each communication frame consists of an instruction byte which is followed by 1 data byte
(see Figure 12).
The data returned on SDO within the same frame always starts with the <Global Status>
register. It provides general status information about the device. It is followed by 1 byte (that
is ‘In-frame-response’, see Figure 12).
For Write cycles the <Global Status> register is followed by the previous content of the
addressed register.
For Read cycles the <Global Status> register is followed by the content of the addressed
register.
8.2.2 Command byte
Each communication frame starts with a command byte. It consists of an operating code
which specifies the type of operation (<Read>, <Write>, <Read and Clear Status>, <Read
Device Information>) and a 6-bit address.
Table 12. Command byte - general description
MSB LSB
Operating code Address
OC1 OC0 A5 A4 A3 A2 A1 A0
Table 13. Data byte - general description
MSB LSB
Bit7 Bit6 Bit5 Bi4 Bit3 Bit2 Bit1 Bit0
Table 14. Command byte
MSB LSB
Operating code Address
OC1 OC0 A5 A4 A3 A2 A1 A0
Functional description of the SPI L99MC6
30/55 Doc ID 16523 Rev 1
Operating code definition
The <Write mode> and <Read mode> operations allow access to the RAM of the device,
that is write to control registers or read status information.
A <Read and Clear Status> operation addressed to a device specific status register reads
back and subsequently clear this status register. A <Read and Clear Status> operation with
address 3FH clears all status registers at a time.
A <Read and Clear Status> operation addressed to an unused RAM address or
configuration register address is identical to a <Read mode> operation (in case of unused
RAM address, the second byte is equal to 00H).
<Read Device Information> allows access to the ROM area which contains device related
information such as the product family, product name, silicon version and register width.
8.2.3 Global status register
Table 15. Operating code definition
OC1 OC0 Meaning
0 0 <Write mode>
0 1 <Read mode>
1 0 <Read and Clear Status>
1 1 <Read Device Information>
Table 16. Global status register
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Global error flag
(GEF)
Communication
error Chip reset TSD
Chip overload
Temperature
warning
Open-load
detected
Overcurrent
detected Unused
Table 17. Global status register description
Bit Description Polarity Comment
0 Unused Active high Always returns ‘0’
1 Overcurrent detected Active high Set by any overcurrent event
2 Open-load detected Active high Set by any open-load event
3 Temperature warning Active high -
4Thermal shutdown / chip
overload Active high -
5 Chip reset Active low
Activated by all internal reset events that change
device state or configuration registers (for
example software reset, VCC undervoltage, etc.).
The bit is cleared after a valid communication
with any register. This bit is initially ‘0’ and is set
to ‘1’ by a valid SPI communication
L99MC6 Functional description of the SPI
Doc ID 16523 Rev 1 31/55
The <Global Error Flag> is generated by an OR-combination of all failure events of the
device (that is <Global Status Register>, [0:6]).
Figure 13. Indication of the global error flag on DO when CSN is low and SCK is stable
1. The last transferred SPI command is still valid in the input shift register. If SCK is stable (high or low) during a CSN low
pulse, at the rising edge of CSN the last transferred SPI command is still valid in the input shift register and is repeated.
Therefore, it is recommended to send a complete SPI frame to monitor the status of the L99MC6.
Writing to the selected data input register is only enabled if exactly one frame length is
transmitted within one communication frame (that is CSN low). If more or less clock pulses
are counted within one frame, the complete frame is ignored and a SPI frame error is
signaled in the Global Status register. This safety function is implemented to avoid
an unwanted activation of output stages by a wrong communication frame.
6 Communication error Active high
Bit is set if the number of clock cycles during
CSN = low does not match with the specified
frame width or if an invalid bus condition is
detected (DI always 1).
DI always 0 automatically leads to clearing the
enable bit in CTRL0 and is not signaled as
communication error.
7 Global Error flag Active high Logic OR combination of all failures in the
<Global Status Byte>.
Table 17. Global status register description (continued)
Bit Description Polarity Comment
Functional description of the SPI L99MC6
32/55 Doc ID 16523 Rev 1
For Read operations, the <communication error> bit in the <Global Status Register> is set,
but the register to be read is still transferred to the DO pin. If the number of clock cycles is
smaller than the frame width, the data at DO is truncated. If the number of clock cycles is
larger than the frame width, the data at DO is filled with ‘0’ bits.
Due to this safety functionality a daisy chaining of SPI is not possible. Instead, a parallel
operation of the SPI bus by controlling the CSN signal of the connected ICs is
recommended.
Note: If the frame width is greater than 16 bits, initial Read of <SPI-frame-ID> using a 16-bit
communication sets the <communication Error bit> of the <Global Status> register. A
subsequent correct length transaction is necessary to correct this bit.
8.3 Write operation
OC0, OC1: operating code (00 for ‘Write’ mode)
The Write operation starts with a command byte followed by 1 data byte.
For Write cycles the <Global Status> register is followed by the previous content of the
addressed register.
The RAM memory area consists of 8-bit registers. All unused RAM addresses are read as
‘0’.
Failures are indicated by activating the corresponding bit of the <Global Status> register.
Note: The register definition for RAM address 00H is device specific.
A register value of all 0 causes a device reset (interpreted as ‘Data-in short to GND’).
8.4 Read operation
OC0, OC1: operating code (01 for ‘Read’ mode)
The Read operation starts with a command byte followed by 1 data byte. The content of the
data byte is ‘do not care’. The content of the addressed register is shifted out at SDO within
the same frame (‘in-frame response’).
The returned data byte represents the content of the register to be read.
Failures are indicated by activating the corresponding bit of the <Global Status> register.
Table 18. Command byte for Write mode
MSB LSB
Operating code Address
0 0 A5 A4 A3 A2 A1 A0
Table 19. Command byte for Read mode
MSB LSB
Operating code Address
0 1 A5 A4 A3 A2 A1 A0
L99MC6 Functional description of the SPI
Doc ID 16523 Rev 1 33/55
8.5 Read and Clear Status operation
OC0, OC1: operating code (10 for ‘Read and Clear Status’ mode)
The ‘Read and Clear Status’ operation starts with a command byte followed by 1 data byte.
The content of the data byte is ‘do not care’. The content of the addressed status register is
transferred to SDO within the same frame (‘in-frame response’) and is subsequently
cleared.
A <Read and Clear Status> operation with address 3FH clears all status registers
simultaneously.
A <Read and Clear Status> operation addressed to an unused RAM address or to the
configuration register (3FH) is identical to a <Read mode> operation (in case of unused
RAM address, the second byte is equal to 00H).
The returned data byte represents the content of the register to be read.
Failures are indicated by activating the corresponding bit of the <Global Status> register.
8.6 Read Device Information
OC0, OC1: operating code (11 for ‘Read Device Information’ mode)
The device information is stored at the ROM. In the ROM memory area, the first 8 bits are
used.
All unused ROM addresses is read as ‘0’.
Note: ROM address 3FH is unused. An attempt to access this address is recognized as a
communication line error (‘Data-in stuck to VCC’) and the standby mode is automatically
entered (all internal registers are cleared).
Table 20. Command byte for Read and Clear Status operation
MSB LSB
Operating code Address
1 0 A5 A4 A3 A2 A1 A0
Table 21. Command byte for Read Device Information
MSB LSB
Operating code Address
1 1 A5 A4 A3 A2 A1 A0
SPI control and status register L99MC6
34/55 Doc ID 16523 Rev 1
9 SPI control and status register
9.1 RAM memory map
9.2 ROM memory map (access with OC0 and OC1 set to ‘1’)
9.3 Control and status registers
Table 22. RAM memory map
Address Name Access Content
00h CTRL 0 Read/Write Global enable, channels 3 and 6 control register
01h CTRL 1 Read/Write CP, channels 2 and 5 control register
02h CTRL 2 Read/Write CP, channels 1 and 4 control register
03h Unused - -
04h STAT 0 Read only Open-load / thermal status register
05h STAT 1 Read only Overcurrent / thermal status register
Table 23. ROM memory map
Address Name Access Content
00h ID Header Read only 42h (device class ASSP, 2 additional information bytes)
01h Product ID Read only 06H
02h Category /
Version Read only 18h (multi channel driver,
last 3 LSB = 0: engineering samples)
3Eh SPI-Frame ID Read only 01h (no burst mode, no watchdog, 16 bit frame SPI)
Table 24. Control register 0
Adress Access
Data Byte
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Global enable, Channel 3&6 control
00h R/W EN CH6
[2]
CH6
[1]
CH6
[0]
Bridge
3&6
CH3
[2]
CH3
[1]
CH3
[0]
Default 00000000
L99MC6 SPI control and status register
Doc ID 16523 Rev 1 35/55
Table 25. Control register 1
Adress Access
Data Byte
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Channel 2&5 control
01h R/W ENCP CH5
[2]
CH5
[1]
CH5
[0]
Bridge
2&5
CH2
[2]
CH2
[1]
CH2
[0]
Default 10000000
Table 26. Control register 2
Adress Access
Data Byte
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Channel 1&4 control
02h R/W DISCP CH4
[2]
CH4
[1]
CH4
[0]
Bridge
1&4
CH1
[2]
CH1
[1]
CH1
[0]
Default 00000000
Table 27. Status register 0
Adress Access
Data Byte
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Open-load, thermal status
04h R TSD TWARN OL
CH6
OL
CH5
OL
CH4
OL
CH3
OL
CH2
OL
CH1
Table 28. Status register 1
Adress Access
Data Byte
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Overcurrent, thermal status
05h R TSD TWARN OC
CH6
OC
CH5
OC
CH4
OC
CH3
OC
CH2
OC
CH1
SPI control and status register L99MC6
36/55 Doc ID 16523 Rev 1
9.3.1 Channel configuration decoding
9.3.2 Register description
Table 29. Channel configuration decoding
CHx
[2]
CHx
[1]
CHx
[0] CHx PWM
mode
Overcurrent
recovery Slew Rate Open-load
detection
000Off
(1) No - High Off
111Off
(1) No - Low On
001 On No NoHigh -
010 On No NoLow -
011 On NoYesLow -
101IN/PWM
(2) Yes No High Off
110IN/PWM
(2) Ye s N o L ow O n
1. The state of the channel 2 is according to the IN/PWM signal
2. The output state is according to the IN/PWM signal, note that bridge mode and PWM mode may not be activated at the
same time for channels 2 and 5.
Table 30. Register description(1)
Name Comment
EN Global device enable bit. If this bit is reset, the device goes in standby mode.
CHx
[2:0]
Channel output configuration (see Figure 29).
Note that channel 2 is directly driven by the external IN/PWM pin and thus can not be configured
independently from the PWM configuration of other channels.
Bridge
Activate Bridge mode between channels 3 and 6, channels 2 and 5, channels 1 and 4. Any
polarity change is delayed by masking time of cross conduction protection
If wrong SPI commands try to turn on the channels 3 and 6, channels 2 and 5, channels 1 and 4
simultaneously, the high-side (channels 3, 2, 1) has the priority whereas channels 6, 5, 4 is (or
stay) deactivated.
ENCP
This bit is preset to ‘1’ at startup. To deactivate the internal charge pump ENCP has to be reset
together with setting DISCP (CTRL 2). This mechanism avoids unwanted charge pump
deactivation after an undetected communication error.
It is recommended to check the state of the charge pump deactivation bits at every access of
CTRL 1 and CTRL 2.
DISCP This bit is reset to ‘0’ at startup. To deactivate the internal charge pump DISCP has to be set
together with resetting ENCP (CTRL 1)
TSD Overtemperature detected: all the drivers are shutdown
TWARN Overtemperature warning level detected, information only
OL [6:1] Open-load error detected, information only
OC [6:1]
Overcurrent error detected, drivers are deactivated and re-enabled cyclically when bulb mode is
configured. Note: in order to detect a real overload condition, the application software must make
sure, that the corresponding OC bit remains cleared after a maximum heat up time of the load.
1. Every output stage is protected against overtemperature and overcurrent. While still configured as ON, the output stage
can be deactivated by the corresponding error bits in the status registers. In order to reactivate the drivers, the status
registers have to be cleared by a specific SPI command.
L99MC6 SPI control and status register
Doc ID 16523 Rev 1 37/55
9.4 Examples
9.4.1 Example 1:Switch on channel 1
It is assumed that the charge pump is already activated (ENCP1 = 1 and DISCP2 = 0, POR
default)
From Ta b l e 3 1 and Ta bl e 3 2 follow that the value 01h is written at RAM address 02h (control
register 2).
Ta bl e 3 3 describe more in detail the data byte structure.
Hereafter the actions linked to each value of bit or group of bits:
●DISCP = 0: Charge pump stays activated
●CH4[2:0] = 000b: Channel 4 is off, open-load detection in off-state disabled
●BRIDGE_1&4 = 0: Bridge mode disabled
●CH4[2:0] = 001b: Channel 1 is on, high slew rate, PWM not activated, overcurrent
recovery deactivated.
Table 31. Command byte - example 1
MSB LSB
Operating code Address
00000010
Table 32. Data byte - example 1
MSB LSB
0 0 000 0 0 1
Table 33. Data byte description - example 1
DISCP CH4
[2]
CH4
[1]
CH4
[0]
Bridge
1&4
CH1
[2]
CH1
[1]
CH1
[0]
00000001
SPI control and status register L99MC6
38/55 Doc ID 16523 Rev 1
9.4.2 Example 2: Bridge mode configuration
From Ta b l e 3 4 and Tab l e 3 5 follow that the value A8h is written at RAM address 01h (control
register 1).
Ta bl e 3 6 describe more in detail the data byte structure.
Hereafter the actions linked to each value of bit or group of bits:
●ENCP = 1: Charge pump stays activated
●CH5[2:0] = 010b: Channel 5 is on, PWM disabled, overcurrent recovery mode
disabled, low slew rate
●BRIDGE_2&5 = 1: Bridge mode for channel 2 and channel 5 activated
●CH2[2:0] = 000b: Channel 2 is off, open-load detection in off-state disabled
From Ta b l e 3 7 and Tab l e 3 8 follow that the value 0Ah is written at RAM address 02h (control
register 2).
Ta bl e 3 9 describe more in detail the data byte structure.
Table 34. Command byte 1 - example 2
MSB LSB
Operating code Address
00000001
Table 35. Data byte 1 - example 2
MSB LSB
1 0 101 0 0 0
Table 36. Data byte description 1 - example 2
ENCP CH5
[2]
CH5
[1]
CH5
[0]
Bridge
2&5
CH2
[2]
CH2
[1]
CH2
[0]
10101000
Table 37. Command byte 2 - example 2
MSB LSB
Operating code Address
00000010
Table 38. Data byte 2 - example 2
MSB LSB
0 0 001 0 1 0
L99MC6 SPI control and status register
Doc ID 16523 Rev 1 39/55
Hereafter the actions linked to each value of bit or group of bits:
●DISCP = 0: Charge pump stays activated
●CH4[2:0] = 000b: Channel 4 is off, open-load detection in off-state disabled
●BRIDGE_1&4 = 1: Bridge mode for channel 1 and channel 4 activated
●CH4[2:0] = 010b: Channel 1 is on, PWM disabled, overcurrent recovery mode
disabled, low slew rate
Figure 14. Bridge mode drawing
Table 39. Data byte description 2 - example 2
DISCP CH4
[2]
CH4
[1]
CH4
[0]
Bridge
1&4
CH1
[2]
CH1
[1]
CH1
[0]
00001010
M
Vs
CH4 OFF
CH1 ON CH 2 OFF
CH 5 ON
SPI control and status register L99MC6
40/55 Doc ID 16523 Rev 1
9.4.3 Example 3: Open-load detection in off-state in bridge configuration
From Ta b l e 4 0 and Ta bl e 4 1 follow that the value F8h is written at RAM address 01h (control
register 1).
Ta bl e 4 2 describe more in detail the data byte structure.
Hereafter the actions linked to each value of bit or group of bits:
●ENCP = 1: Charge pump stays activated
●CH5[2:0] = 111b: Channel 5 is off, open-load detection in off-state enabled
●BRIDGE_2&5 = 1: Bridge mode for channel 2 and channel 5 activated
●CH2[2:0] = 000b: Channel 2 is off, open-load detection in off-state disabled
From Ta b l e 4 3 and Tab l e 4 4 follow that the value 0Ah is written at RAM address 02h (control
register 2).
Ta bl e 4 5 describe more in detail the data byte structure.
Table 40. Command byte 1 - example 3
MSB LSB
Operating code Address
00000001
Table 41. Data byte 1 - example 3
MSB LSB
1 1 111 0 0 0
Table 42. Data byte description 1 - example 3
ENCP CH5
[2]
CH5
[1]
CH5
[0]
Bridge
2&5
CH2
[2]
CH2
[1]
CH2
[0]
11111000
Table 43. Command byte 2 - example 3
MSB LSB
Operating code Address
00000010
Table 44. Data byte 2 - example 3
MSB LSB
0 0 001 0 1 0
L99MC6 SPI control and status register
Doc ID 16523 Rev 1 41/55
Hereafter the actions linked to each value of bit or group of bits:
●DISCP = 0: Charge pump stays activated
●CH4[2:0] = 000b: Channel 4 is off, open-load detection in off-state disabled
●BRIDGE_1&4 = 1: Bridge mode for channel 1 and channel 4 activated
●CH1[2:0] = 010b: Channel 1 is on, PWM disabled, overcurrent recovery mode
disabled, low slew rate
Figure 15. Open-load in bridge mode drawing
There are two operating conditions:
●Case 1: The motor is connected, drain of channel 5 is pulled up by channel 1 (on)
through the motor, then no open-load detected on channel 5
●Case 2: The motor is not connected and the drain voltage of channel 5 is below the
open-load threshold, then open-load detected on channel 5
Table 45. Data byte description 2 - example 3
DISCP CH4
[2]
CH4
[1]
CH4
[0]
Bridge
1&4
CH1
[2]
CH1
[1]
CH1
[0]
00001010
M
Vs
CH4 OFF
OL detection OFF
CH1 ON
OL detection OFF
CH2 OFF
OL detection OFF
CH5 OFF
OL detection ON
Maximum demagnetization energy L99MC6
42/55 Doc ID 16523 Rev 1
10 Maximum demagnetization energy
Figure 16. Configurable switch HSD - maximum turn-off current versus inductance
A: Single pulse, Tj = 150 °C
B: Repetitive pulse, Tj = 100 °C
C: Repetitive pulse, Tj = 125 °C
0.1
1
100 1000
L (mH)
I (A)
A
B
C
L99MC6 Maximum demagnetization energy
Doc ID 16523 Rev 1 43/55
Figure 17. Configurable switch LSD - maximum turn-off current versus inductance
0.1
1
100 1000
L (mH)
I (A)
A
B
C
A: Single pulse, Tj = 150 °C
B: Repetitive pulse, Tj = 100 °C
C: Repetitive pulse, Tj = 125 °C
Maximum demagnetization energy L99MC6
44/55 Doc ID 16523 Rev 1
Figure 18. Fixed LSD switch - maximum turn-off current versus inductance
0.1
1
100 1000
L (mH)
I (A)
A: Single pulse, Tj = 150 °C
B: Repetitive pulse, Tj = 100 °C
C: Repetitive pulse, Tj = 125 °C
A
B
C
L99MC6 Application examples
Doc ID 16523 Rev 1 45/55
11 Application examples
Figure 19. L99MC6 as driver for incandescent bulb, LEDs and high-side or low-side
relays
Control
VDD 5V
SPI
=1
Out1
Out2
Out3
Out4
Out5
Out6
GND
IN/PWM
VS12V
SCK
CSN
DO
DI
Application examples L99MC6
46/55 Doc ID 16523 Rev 1
Figure 20. L99MC6 as motor driver (for example, for mirror adjustment)
Control
VDD 5V
SPI
=1
Out1
Out2
Out3
Out4
Out5
Out6
GND
IN/PWM
VS12V
M
GND
SCK
CSN
DO
DI
M
L99MC6 Application examples
Doc ID 16523 Rev 1 47/55
Figure 21. L99MC6 as driver for unipolar stepper motor driver, relay and LEDs
Control
VDD 5V
SPI
Out1
Out2
Out3
Out4
Out5
Out6
GND
IN/PWM
VS12V
SCK
CSN
DO
DI
SM
=1
Package and PCB thermal data L99MC6
48/55 Doc ID 16523 Rev 1
12 Package and PCB thermal data
12.1 PowerSSO-16 thermal data
Figure 22. PowerSSO-16 PC board(1)
1. Layout condition of thermal resistance measurements (PCB: double layer, thermal vias,
FR4 area = 77 mm x 86 mm, PCB thickness =1.6 mm, Cu thickness = 70 µm (front and back side) thermal
vias separation 1.2 mm, thermal via diameter 0.3 mm +/- 0.08 mm, Cu thickness on vias 25 µm,
footprint dimension 2.5 mm x 4.2 mm ).
Table 46. Auto and mutual thermal resistance - footprint
HSD 1 HSD 2 HSD 3 LSD 4 LSD 5 LSD 6
HSD 1 89.57 85.83 84.41 88.89 87.06 85.84
HSD 2 85.83 89.57 84.41 87.06 88.89 87.06
HSD 3 84.41 84.41 89.57 85.84 87.06 88.89
LSD 4 88.89 87.06 85.84 93.58 90.54 89.08
LSD 5 87.06 88.89 87.06 90.54 93.58 90.54
LSD 5 85.84 87.06 88.89 89.08 90.54 93.58
Table 47. Auto and mutual thermal resistance - 2 cm2 of Cu heatsink
HSD 1 HSD 2 HSD 3 LSD 4 LSD 5 LSD 6
HSD 1 59.96 55.06 54.23 58.25 56.08 54.71
HSD 2 55.06 59.96 54.23 56.08 58.25 56.08
HSD 3 54.23 54.23 59.96 54.71 56.08 58.25
LSD 4 58.25 56.08 54.71 61.80 60.37 59.45
LSD 5 56.08 58.25 56.08 60.37 61.80 60.37
LSD 5 54.71 56.08 58.25 59.45 60.37 61.80
.
L99MC6 Package and PCB thermal data
Doc ID 16523 Rev 1 49/55
Equation 1 represents ΔTj-amb calculation of a full loaded device for the HSD1 junction.
Equation 1
Table 48. Auto and mutual thermal resistance - 8 cm2 of Cu heatsink
HSD 1 HSD 2 HSD 3 LSD 4 LSD 5 LSD 6
HSD 1 46.51 43.16 41.49 45.19 43.06 42.08
HSD 2 43.16 46.51 41.49 43.06 45.19 43.06
HSD 3 41.49 41.49 46.51 42.08 43.06 45.19
LSD 4 45.19 43.06 42.08 47.19 46.31 45.19
LSD 5 43.06 45.19 43.06 46.31 47.19 46.31
LSD 5 42.08 43.06 45.19 45.19 46.31 47.19
661551441
331221111
LSDLSD,HSDLSDLSD,HSDLSDLSD,HSD
HSDHSD,HSDHSDHSD,HSDHSDHSDHSD
PdRthPdRthPdRth
PdRthPdRthPdRthT
∗+∗+∗+
+∗
+
∗
+
∗=Δ
Package and packing information L99MC6
50/55 Doc ID 16523 Rev 1
13 Package and packing information
13.1 ECOPACK®
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.
13.2 PowerSSO-16 package information
Figure 23. PowerSSO-16 package dimensions
L99MC6 Package and packing information
Doc ID 16523 Rev 1 51/55
Table 49. PowerSSO-16 mechanical data(1)
1. Drawings dimensions include single and matrix versions.
Symbol
Millimeters
Min. Typ. Max.
A 1.25 - 1.72
A1 0.00 - 0.10
A2 1.10 - 1.62
B 0.18 - 0.36
C 0.19 - 0.25
D(2)
2. Dimensions D does not include mold flash protrusions or gate burrs.
Mold flash protrusions or gate burrs shall not exceed 0.15 mm in total (both side).
4.80 - 5.00
E 3.80 - 4.00
e-0.50-
H 5.80 - 6.20
h 0.25 - 0.50
L 0.40 - 1.27
k0d-8d
X 1.90 - 2.50
Y 3.60 - 4.20
ddd - 0.10
Package and packing information L99MC6
52/55 Doc ID 16523 Rev 1
13.3 Packing information
Figure 24. PowerSSO-16 tube shipment (no suffix)
Figure 25. PowerSSO-16 tape and reel shipment (suffix “TR”)
All dimensions are in mm.
Base Q.ty 100
Bulk Q.ty 2000
Tube length (± 0.5) 532
A1.85
B6.75
C (± 0.1) 0.6
A
C
B
Base q.ty 2500
Bulk q.ty 2500
A (max) 330
B (min) 1.5
C (± 0.2) 13
F20.2
G (+ 2 / -0) 12.4
N (min) 60
T (max) 18.4
REEL DIMENSIONS
TAPE DIMENSIONS
According to Electronic Industries Association
(EIA) Standard 481 rev. A, Feb. 1986
All dimensions are in mm.
Tape width W 12
Tape hole spacing P0 (± 0.1) 4
Component spacing P 8
Hole diameter D (± 0.05) 1.5
Hole diameter D1 (min) 1.5
Hole position F (± 0.1) 5.5
Compartment depth K (max) 4.5
Hole spacing P1 (± 0.1) 2
Top
cover
tape
End
Start
No componentsNo components Components
500mm min 500mm min
Empty components pockets
saled with cover tape.
User direction of feed
L99MC6 Acronyms
Doc ID 16523 Rev 1 53/55
Appendix A Acronyms
Table 50. Acronyms
Acronym Name
CSN Chip select not
CTRL Control register
POR Power-on reset
SCK Serial clock
SDI Serial data input
SDO Serial data output
SPI Serial peripheral interface
SR Slew rate
STAT Status register
Revision history L99MC6
54/55 Doc ID 16523 Rev 1
Revision history
Table 51. Document revision history
Date Revision Changes
18-Nov-2009 1 Initial release.
L99MC6
Doc ID 16523 Rev 1 55/55
Please Read Carefully:
Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the
right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any
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