Tactical Grade, Six Degrees of Freedom Inertial Sensor ADIS16497 Data Sheet FEATURES GENERAL DESCRIPTION Triaxial, digital gyroscope 125/sec, 450/sec, 2000/sec range options 0.05 axis to axis misalignment error 0.25 (maximum) axis to package misalignment error 0.8/hr in-run bias stability (ADIS16497-1) 0.09/hr angular random walk (ADIS16497-1) Triaxial, digital accelerometer, 40 g 13 g in run bias stability Triaxial, delta angle and delta velocity outputs Factory calibrated sensitivity, bias, and axial alignment Calibration temperature range: -40C to +85C SPI compatible Programmable operation and control Automatic and manual bias correction controls Configurable FIR filters Digital I/O: data ready, external clock Sample clock options: internal, external, or scaled On demand self test of inertial sensors Single-supply operation: 3.0 V to 3.6 V 1500 g mechanical shock survivability Operating temperature range: -40C to +105C The ADIS16497 is a complete inertial system that includes a triaxis gyroscope and a triaxis accelerometer. Each inertial sensor in the ADIS16497 combines industry leading iMEMS(R) technology with signal conditioning that optimizes dynamic performance. The factory calibration characterizes each sensor for sensitivity, bias, alignment, and linear acceleration (gyroscope bias). As a result, each sensor has its own dynamic compensation formulas that provide accurate sensor measurements. The ADIS16497 provides a simple, cost effective method for integrating accurate, multiaxis inertial sensing into industrial systems, especially when compared with the complexity and investment associated with discrete designs. All necessary motion testing and calibration are part of the production process at the factory, greatly reducing system integration time. Tight orthogonal alignment simplifies inertial frame alignment in navigation systems. The serial peripheral interface (SPI) and register structure provide a simple interface for data collection and configuration control. The footprint and connector system of the ADIS16497 enable a simple upgrade from the ADIS16375, ADIS16480, ADIS16485, ADIS16488A, and ADIS16490. The ADIS16497 is available in an aluminum package that is approximately 47 mm x 44 mm x 14 mm and includes a standard connector interface. APPLICATIONS Precision instrumentation, stabilization Guidance, navigation, control Avionics, unmanned vehicles Precision autonomous machines, robotics FUNCTIONAL BLOCK DIAGRAM SELF TEST POWER MANAGEMENT I/O OUTPUT DATA REGISTERS TRIAXIAL GYROSCOPE TRIAXIAL ACCELEROMETER TEMPERATURE SENSOR VDD CONTROLLER CALIBRATION AND FILTERS GND CS SPI USER CONTROL REGISTERS CLOCK ADIS16497 SCLK DIN DOUT 15061-001 DIO1 DIO2 DIO3 DIO4 RST Figure 1. Rev. D Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 (c)2017-2020 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com ADIS16497 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Cyclical Redundancy Check (CRC-32) ................................... 25 Applications ...................................................................................... 1 Delta Angles ................................................................................ 26 General Description ......................................................................... 1 Delta Velocity ............................................................................. 27 Functional Block Diagram .............................................................. 1 User Bias/Scale Adjustment...................................................... 29 Revision History ............................................................................... 2 Scratch Registers, USER_SCR_x .............................................. 32 Specifications .................................................................................... 4 Timing Specifications .................................................................. 6 Flash Memory Endurance Counter, FLSHCNT_LOW, FLSHCNT_HIGH ...................................................................... 32 Absolute Maximum Ratings ........................................................... 9 Global Commands, GLOB_CMD ........................................... 33 Thermal Resistance ...................................................................... 9 Auxiliary I/O Line Configuration, FNCTIO_CTRL ............. 34 ESD Caution.................................................................................. 9 General-Purpose I/O Control, GPIO_CTRL ......................... 35 Pin Configuration and Function Descriptions .......................... 10 Miscellaneous Configuration, CONFIG ................................. 35 Typical Performance Characteristics ........................................... 11 Linear Acceleration on Effect on Gyroscope Bias ................. 35 Theory of Operation ...................................................................... 13 Decimation Filter, DEC_RATE ............................................... 35 Inertial Sensor Signal Chain ..................................................... 13 Continuous Bias Estimation (CBE), NULL_CNFG .............. 36 Register Structure ....................................................................... 14 Scaling the Input Clock (PPS Mode), SYNC_SCALE........... 36 Serial Peripheral Interface ......................................................... 15 FIR Filters .................................................................................... 37 Data Ready .................................................................................. 15 Firmware Revision, FIRM_REV .............................................. 39 Reading Sensor Data .................................................................. 16 Firmware Revision Year, FIRM_Y .......................................... 39 Device Configuration ................................................................ 17 Boot Revision Number, BOOT_REV...................................... 39 User Register Memory Map .......................................................... 18 Continuous SRAM Testing....................................................... 39 User Register Defintions ............................................................... 21 Applications Information ............................................................. 41 Page Number (PAGE_ID) ........................................................ 21 Mounting Best Practices ........................................................... 41 Data/Sample Counter (DATA_CNT) ..................................... 21 Preventing Misinsertion ............................................................ 41 Status/Error Flag Indicators (SYS_E_FLAG) ......................... 21 Evaluation Tools......................................................................... 41 Self Test Error Flags (DIAG_STS) ........................................... 22 Power Supply Considerations .................................................. 41 Internal Temperature (TEMP_OUT) ..................................... 22 CRC32 Coding Example ........................................................... 42 Gyroscope Data .......................................................................... 22 Outline Dimensions ....................................................................... 43 Acceleration Data ....................................................................... 24 Ordering Guide .......................................................................... 43 Time Stamp ................................................................................. 25 REVISION HISTORY 7/2020--Rev. C to Rev. D Changes to Table 1 ........................................................................... 5 Changes to Table 2 ........................................................................... 6 Changes to Flash Memory Update Section and On Demand Self Test (ODST) Section ...................................................................... 33 Changes to Data Ready Indicator Section .................................. 34 Changes to Scaling the Input Clock (PPS Mode), SYNC_SCALE ................................................................................. 36 1/2020--Rev. B to Rev. C Changes to Accelerometers, Sensitivity Parameter, Table 1 .......1 6/2019--Rev. A to Rev. B Changes to Features Section ............................................................1 Changes to Specifications Section and Table 1 .............................4 Changes to Figure 5 and Figure 6 ...................................................7 Changes to Table 6 ............................................................................9 Changes to Figure 12 ..................................................................... 10 Rev. D | Page 2 of 43 Data Sheet ADIS16497 Added Figure 13 and Figure 14; Renumbered Sequentially .....10 Added Figure 15, Figure 16, Figure 17, Figure 18, Figure 19, and Figure 20 ...................................................................................11 Changes to Theory of Operation Section ....................................12 Change to Serial Peripheral Interface Section.............................14 Changes to Burst Read Function Section and Table 10 .............15 Changes to Table 11 ........................................................................16 Changes to Table 12 ........................................................................17 Changes to Model Column, Table 24...........................................21 Change to Delta Angle Measurement Range Section and Model Column, Table 60 ............................................................................25 Changes to Delta Velocity Section................................................26 Changes to Continuous Bias Estimation (CBE), NULL_CNFG Section and Description Column, Table 156 .............................. 35 Added CRC32 Coding Example, Table 195, and Table 196; Renumbered Sequentially .............................................................. 41 11/2017--Rev. 0 to Rev. A Changes to Table 1 ............................................................................ 3 Changed t2 Parameter, Table 2; GLOB_CMD, Bit 3 Parameter, GLOB_CMD, Bit 6 Parameter, and GLOB_CMD, Bit 7 Parameter, Table 3 ................................................................................................ 5 10/2017--Revision 0: Initial Version Rev. D | Page 3 of 43 ADIS16497 Data Sheet SPECIFICATIONS TC = 25C, VDD = 3.3 V, angular rate = 0/sec, ADIS16497-1 model, 1 g, unless otherwise noted. Table 1. Parameter GYROSCOPES Dynamic Range Sensitivity Error Over Temperature Misalignment Nonlinearity 1 Bias Repeatability 2 In Run Bias Stability Angular Random Walk Error over Temperature Linear Acceleration Effect Vibration Rectification Error Noise Output Noise Rate Noise Density3 -3 dB Bandwidth Test Conditions/Comments Min ADIS16497-1 ADIS16497-2 ADIS16497-3 ADIS16497-1, 32-bit ADIS16497-2, 32-bit ADIS16497-3, 32-bit ADIS16497-1, -40C TC +85C, 1 ADIS16497-2, -40C TC +85C, 1 ADIS16497-3, -40C TC +85C, 1 Axis to axis, -40C TC +85C, 1 Axis to package, -40C TC +85C 1 , ADIS16497-1, FS = 125/sec 1 , ADIS16497-2, FS = 450/sec 1 , ADIS16497-3, FS = 2000/sec 125 450 2000 Typ Max Unit 0.2 0.2 0.25 /sec /sec /sec LSB//sec LSB//sec LSB//sec % % % Degrees Degrees % FS % FS % FS -40C TC +85C, 1 1 , ADIS16497-1 1 , ADIS16497-2 1 , ADIS16497-3 1 , ADIS16497-1 1 , ADIS16497-2 1 , ADIS16497-3 -40C TC +85C, 1 Any axis, 1 (CONFIG register, Bit 7 = 1) Any axis, 1 (CONFIG register, Bit 7 = 0) 1 , ADIS16497-1 1 , ADIS16497-2 1 , ADIS16497-3 0.07 0.8 1.6 3.3 0.09 0.1 0.18 0.1 0.006 0.015 0.0003 0.0004 0.0009 /sec /hr /hr /hr /hr /hr /hr /sec /sec/g /sec/g /sec/g2 /sec/g2 /sec/g2 No filtering, ADIS16497-1 No filtering, ADIS16497-2 No filtering, ADIS16497-3 1 , ADIS16497-1 1 , ADIS16497-2 1 , ADIS16497-3 ADIS16497-1 ADIS16497-2, ADIS16497-3 0.051 0.058 0.112 0.002 0.0022 0.0042 480 550 65 /sec rms /sec rms /sec rms /sec/Hz rms /sec/Hz rms /sec/Hz rms Hz Hz kHz Sensor Resonant Frequency Rev. D | Page 4 of 43 480 10485760 2621440 655360 0.1 0.2 0.2 0.05 0.25 Data Sheet Parameter ACCELEROMETERS4 Dynamic Range Sensitivity Error Over Temperature Misalignment Nonlinearity Bias In Run Bias Stability Velocity Random Walk Error over Temperature Repeatability Noise Output Noise Noise Density -3 dB Bandwidth Sensor Resonant Frequency TEMPERATURE SENSOR Scale Factor LOGIC INPUTS5 Input Voltage High, VIH Low, VIL RST Pulse Width Input Current Logic 1, IIH Logic 0, IIL All Pins Except RST, CS RST, CS Pins6 Input Capacitance, CIN DIGITAL OUTPUTS5 Output Voltage High, VOH Low, VOL FLASH MEMORY Data Retention8 FUNCTIONAL TIMES9 Power-On Start-Up Time Reset Recovery Time10 Flash Memory Update Time Clear User Calibration Self Test Time ADIS16497 Test Conditions/Comments Each axis Min Typ Max Unit 32-bit data format -40C TC +85C, 1 Axis to axis, -40C TC +85C, 1 Axis to package, -40C TC +85C Best fit straight line, 10 g Best fit straight line, 20 g Best fit straight line, 40 g 52,428,800 0.01 0.05 0.02 0.4 1.5 g LSB/g % Degrees Degrees % FS % FS % FS 1 1 -40C TC +85C, 1 -40C TC +85C, 1 13 0.04 0.5 6 g m/sec/hr mg mg No filtering 10 Hz to 40 Hz, no filtering 2.6 88 750 5.5 mg rms g/Hz rms Hz kHz Output = 0x0000 at 25C (5C) 0.0125 C/LSB 40 0.25 2.0 0.8 V V s 10 A 10 A mA pF 1 VIH = 3.3 V VIL = 0 V 0.33 10 ISOURCE = 0.5 mA ISINK = 2.0 mA Endurance7 TJ = 85C Time until data is available, -40C TC +85C, 1 2.4 0.4 100,000 20 V V Cycles Years GLOB_CMD, Bit 7 = 1 (see Table 142) RST pulled low, then restored to high 265 225 265 ms ms ms GLOB_CMD, Bit 3 = 1 (see Table 142) GLOB_CMD, Bit 6 = 1 (see Table 142) GLOB_CMD, Bit 1 = 1 (see Table 142) 1300 350 30 ms s ms Rev. D | Page 5 of 43 ADIS16497 Data Sheet Parameter CONVERSION RATE Initial Clock Accuracy Temperature Coefficient Sync Input Clock Pulse Per Second (PPS) Mode POWER SUPPLY, VDD Power Supply Current11 Test Conditions/Comments Min Typ 4.25 0.02 40 Max 3.0 1 3.0 Operating voltage range Normal mode, VDD = 3.3 V, + Unit kSPS % ppm/C kHz Hz V mA 4.5 128 3.6 89 1 FS = full scale, FS = 125/sec (ADIS16497-1), FS = 450/sec (ADIS16497-2), FS = 2000/sec (ADIS16497-3). Bias repeatability provides an estimate for long-term drift in the bias, as observed during 500 hours of high temperature operating life (HTOL) at +105C. 3 Magnitude between 10 and 40 Hz, sample rate is 4250 SPS (nominal), no digital filtering. 4 All specifications associated with the accelerometers relate to the full-scale range of 40 g. 5 The digital I/O signals use a 3.3 V system. 6 RST and CS pins are connected to the VDD pin through 10 k pull-up resistors. 7 Endurance is qualified as per JEDEC Standard 22, Method A117, measured at -40C, +25C, +85C, and +125C. 8 The data retention specification assumes a junction temperature (TJ) of 85C per JEDEC Standard 22, Method A117. Data retention lifetime decreases with TJ. 9 These times do not include thermal settling and internal filter response times, which can affect overall accuracy. 10 The RST line must be in a low state for at least 10 s to ensure a proper reset initiation and recovery. 11 Supply current transients can reach 250 mA during initial startup or reset recovery. 2 TIMING SPECIFICATIONS TC = 25C, VDD = 3.3 V, unless otherwise noted. Table 2. Parameter fSCLK tSTALL2 tCLS tCHS tCS Description SCLK frequency Stall period between data SCLK low period SCLK high period CS to SCLK edge tDAV tDSU tDHD tDR, tDF tDSOE tHD tSFS tDSHI tNV t1 t2 t3 DOUT valid after SCLK edge DIN setup time before SCLK rising edge DIN hold time after SCLK rising edge DOUT rise/fall times, 100 pF loading CS assertion to DOUT active SCLK edge to DOUT invalid Last SCLK edge to CS deassertion CS deassertion to DOUT high impedance Data invalid time Input sync pulse width Input sync to data invalid Input sync period4 Min1 0.01 5 31 31 32 Normal Mode Typ Max1 15 Burst Read Function Min Typ Max1 6.5 N/A3 31 31 32 10 2 2 10 2 2 3 0 0 32 0 8 11 9 3 0 0 32 0 20 5 222.2 1 9 20 5 306 306 222.2 Guaranteed by design and characterization, but not tested in production. See Table 3 for exceptions to the stall time rating. Note that an insufficient stall time results in reading all 0s for the register attempting to be read. 3 N/A means not applicable. 4 This measurement represents the inverse of the maximum frequency for the input sample clock: 4500 Hz. 2 Rev. D | Page 6 of 43 8 11 Unit MHz s ns ns ns ns ns ns ns ns ns ns ns s s s s Data Sheet ADIS16497 Register Specific Stall Times Table 3. Parameter STALL TIME FNCTIO_CTRL FILTR_BNK_0 FILTR_BNK_1 NULL_CNFG SYNC_SCALE DEC_RATE GPIO_CTRL CONFIG GLOB_CMD, Bit 1 GLOB_CMD, Bit 3 GLOB_CMD, Bit 6 GLOB_CMD, Bit 7 1 Description Min1 Configure the DIOx functions Enable/select finite impulse response (FIR) filter banks Enable/select FIR filter banks Configure autonull bias function Configure input clock scale factor Configure decimation rate Configure general-purpose input/output (I/O) lines Configure miscellaneous functions On demand self test Flash memory update Clear user calibration Software reset 340 65 65 71 340 340 45 45 20 1120 350 210 Typ Max Unit s s s s s s s s ms ms s ms Monitoring the data ready signal (see Table 144 for FNCTIO_CTRL configuration) for the return of regular pulsing can help minimize system wait times. Timing Diagrams CS tCHS 1 SCLK 2 tDSOE MSB DOUT 3 4 R/W 5 DB14 A6 tSFS 6 tDAV 15 tHD DB13 tDSU DIN tCLS DB12 DB11 tDR DB10 tDSHI DB2 DB1 tDHD A5 16 LSB tDF A4 A3 A2 D2 D1 15061-002 tCS LSB Figure 2. SPI Timing and Sequence tSTALL 15061-003 CS SCLK Figure 3. Stall Time and Data Rate t3 t2 DATA READY OUTPUT REGISTERS t1 tNV DATA VALID DATA VALID Figure 4. Input Clock Timing Diagram, FNCTIO_CTRL, Bits[7:4] = 0xFD Rev. D | Page 7 of 43 15061-004 DIO4 (SYNC CLOCK) ADIS16497 Data Sheet CS SCLK 7C00 DOUT 0000 BURST_ID X_GYRO_OUT CRC_UPR 1 2 3 19 0 15061-005 DIN Figure 5. Burst Read Function Sequence Diagram, 19 Segments CS SCLK DOUT 0x7C00 0000 BURST_ID BURST_ID X_GYRO_LOW CRC_UPR 1 2 3 4 20 Figure 6. Burst Read Function Sequence Diagram, 20 Segments Rev. D | Page 8 of 43 15061-006 DIN Data Sheet ADIS16497 ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE Table 4. Parameter Mechanical Shock Survivability Any Axis, Unpowered Any Axis, Powered VDD to GND Digital Input Voltage to GND Digital Output Voltage to GND Operating Temperature Range Storage Temperature Range1 Barometric Pressure 1 Thermal performance is directly linked to printed circuit board (PCB) design and operating environment. Pay careful attention to PCB thermal design. Rating 1500 g 1500 g -0.3 V to +3.6 V -0.3 V to VDD + 0.2 V -0.3 V to VDD + 0.2 V -40C to +105C -55C to +150C 2 bar JA is the natural convection junction to ambient thermal resistance measured in a one cubic foot sealed enclosure. JC is the junction to case thermal resistance. Extended exposure to temperatures that are lower than -40C or higher than +105C can adversely affect the accuracy of the factory calibration. Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. The ADIS16497 is a multichip module, which includes many active components. The values in Table 5 identify the thermal response of the hottest component inside of the ADIS16497, with respect to the overall power dissipation of the module. This approach enables a simple method for predicting the temperature of the hottest junction, based on either ambient or case temperature. For example, when TA = 70C, the hottest junction inside of the ADIS16497 is 76.7C. TJ = JA x VDD x IDD + 70C TJ = 22.8C/W x 3.3 V x 0.089 A + 70C TJ = 76.7C Table 5. Package Characteristics Package Type ML-24-91 1 JA 30.7C/W JC 20.9C/W Device Weight 42 g Thermal impedance simulated values come from a case with 4 M2 x 0.4 mm machine screws (torque = 20 inch ounces). Secure the ADIS16497 to the PCB. ESD CAUTION Rev. D | Page 9 of 43 ADIS16497 Data Sheet PIN CONFIGURATION AND FUNCTION DESCRIPTIONS ADIS16497 DNC DNC DNC DNC GND NO PIN VDD RST CS DOUT DIO4 24 22 20 18 16 14 12 10 8 6 4 2 21 19 17 15 13 11 9 7 5 3 1 DNC DNC DNC NO PIN GND VDD DIO2 DIO1 DIN SCLK DIO3 NOTES 1. THIS REPRESENTATION DISPLAYS THE TOP VIEW PINOUT FOR THE MATING SOCKET CONNECTOR. 2. THE ACTUAL CONNECTOR PINS ARE NOT VISIBLE FROM THE TOP VIEW. 3. MATING CONNECTOR: SAMTEC CLM-112-02 OR EQUIVALENT. 4. DNC = DO NOT CONNECT. 5. PIN 12 AND PIN 15 ARE NOT PHYSICALLY PRESENT. 15061-007 23 DNC PIN 23 PIN 1 PIN 1 PIN 2 15061-008 DNC TOP VIEW (Not to Scale) Figure 8. Axial Orientation (Top Side Facing Up) Figure 7. Pin Configuration Table 6. Pin Function Descriptions Pin No. 1 2 3 4 5 6 7 8 9 10, 11 12, 15 13, 14 16 to 22, 24 23 Mnemonic DIO3 DIO4 SCLK DOUT DIN CS DIO1 RST DIO2 VDD NO PIN GND DNC DNC Type Input/output Input/output Input Output Input Input Input/output Input Input/output Supply Not applicable Supply Not applicable Not applicable Description Configurable Digital Input/Output 3. Configurable Digital Input/Output 4. SPI Serial Clock. SPI Data Output. Clocks output on the SCLK falling edge. SPI Data Input. Clocks input on the SCLK rising edge. SPI Chip Select. Configurable Digital Input/Output 1. Reset. Configurable Digital Input/Output 2. Power Supply. No Pin. These pins are not physically present. Power Ground. Do Not Connect. Do not connect to these pins. Do Not Connect. Do not connect to this pin. This pin can tolerate connection to the VDD supply. Rev. D | Page 10 of 43 Data Sheet ADIS16497 TYPICAL PERFORMANCE CHARACTERISTICS 1000 ALLAN DEVIATION (g) 100 10 1 0.1 0.001 0.01 0.1 1 10 100 1000 10000 100000 INTEGRATION PERIOD (Seconds) X-AXIS Y-AXIS Z-AXIS 100 10 1 0.1 0.001 0.01 0.1 1 10 100 10000 100000 1000 INTEGRATION PERIOD (Seconds) Figure 12. Accelerometer Allan Deviation Figure 9. Gyroscope Allan Deviation, ADIS16497-1 0.15 100 10 1 0.01 0.1 1 10 100 1000 10000 100000 INTEGRATION PERIOD (Seconds) GYROSCOPE SENSITIVITY ERROR (%) 1 1 10 100 1000 10000 100000 INTEGRATION PERIOD (Seconds) -0.10 -20 0 20 40 60 80 TEMPERATURE (C) 15061-011 ALLAN DEVIATION (Degrees/hour) 10 0.1 -0.05 0.05 100 0.01 0 Figure 13. Gyroscope Sensitivity Error vs. Temperature, Cold to Hot, ADIS16497-2 X-AXIS Y-AXIS Z-AXIS 0.1 0.001 0.05 -0.15 -40 Figure 10. Gyroscope Allan Deviation, ADIS16497-2 1000 0.10 0 -0.05 -0.10 -0.15 -0.20 -0.25 -40 MEAN + 1 MEAN MEAN - 1 -20 0 20 40 60 80 TEMPERATURE (C) Figure 14. Gyroscope Sensitivity Error vs. Temperature, Hot to Cold, ADIS16497-2 Figure 11. Gyroscope Allan Deviation, ADIS16497-3 Rev. D | Page 11 of 43 15061-114 0.1 0.001 MEAN + 1 MEAN MEAN - 1 15061-113 GYROSCOPE SENSITIVITY ERROR (%) X-AXIS Y-AXIS Z-AXIS 15061-010 ALLAN DEVIATION (Degrees/hour) 1000 15061-012 X-AXIS Y-AXIS Z-AXIS 15061-009 ALLAN DEVIATION (Degrees/hour) 1000 ADIS16497 Data Sheet 0 0.010 0.005 0 -0.005 -0.010 MEAN + 1 MEAN MEAN - 1 -20 0 20 40 60 80 TEMPERATURE (C) -0.14 -0.16 MEAN + 1 MEAN MEAN - 1 -0.18 -20 0 20 40 ACCELEROMETER SENSITIVITY ERROR (%) 0.015 0.010 0.005 0 -0.005 -0.010 MEAN + 1 MEAN MEAN - 1 -0.015 -20 0 20 40 60 80 Figure 16. Accelerometer Sensitivity vs. Temperature, Hot to Cold, ADIS16497-2 0.03 0.02 0.01 0 -0.01 -0.02 -0.03 -0.04 -20 0 20 40 ACCELEROMETER SENSITIVITY ERROR (%) -0.04 -0.06 -0.08 -0.10 -0.12 -0.14 -0.16 40 60 80 TEMPERATURE (C) Figure 17. Gyroscope Sensitivity Error vs. Temperature, Cold to Hot, ADIS16497-3 MEAN + 1 MEAN MEAN - 1 0.08 0.06 0.04 0.02 0 -0.02 -0.04 -0.06 -0.08 -0.10 -40 15061-117 MEAN + 1 MEAN MEAN - 1 20 80 Figure 19. Accelerometer Sensitivity Error vs. Temperature, Cold to Hot, ADIS16497-3 -0.02 0 60 TEMPERATURE (C) 0.10 -20 80 MEAN + 1 MEAN MEAN - 1 0.04 -0.05 -40 0 -0.18 60 Figure 18. Gyroscope Sensitivity Error vs. Temperature, Hot to Cold, ADIS16497-3 15061-116 ACCELEROMETER SENSITIVITY (%) -0.12 0.05 TEMPERATURE (C) GYROSCOPE SENSITIVITY ERROR (%) -0.10 TEMPERATURE (C) 0.020 -0.20 -40 -0.08 -0.20 -40 Figure 15. Accelerometer Sensitivity vs. Temperature, Cold to Hot, ADIS16497-2 -0.020 -40 -0.06 15061-119 -0.020 -40 -0.04 -20 0 20 40 TEMPERATURE (C) 60 80 15061-120 -0.015 -0.02 15061-118 GYROSCOPE SENSITIVITY ERROR (%) 0.015 15061-115 ACCELEROMETER SENSITIVITY (%) 0.020 Figure 20. Accelerometer Sensitivity Error vs. Temperature, Hot to Cold, ADIS16497-3 Rev. D | Page 12 of 43 Data Sheet ADIS16497 THEORY OF OPERATION INERTIAL SENSOR SIGNAL CHAIN MEMS SENSORS CALIBRATION OUTPUT DATA REGISTERS FILTERING The ADIS16497 offers two modes of operation to control data production with an external clock: sync mode and PPS mode. In sync mode, the external clock directly controls the data sampling and production clock (fSM in Figure 22 and Figure 23). In PPS mode, the user can provide a lower input clock rate (1 Hz to 128 Hz) and use a scale factor (SYNC_SCALE register, see Table 154) to establish a data collection and processing rate that is between 3000 Hz and 4250 Hz for best performance. Inertial Sensor Calibration The calibration function for the gyroscopes and the accelerometers has two components: factory calibration and user calibration (see Figure 24). 15061-013 Figure 21 shows the basic signal chain for the inertial sensors in the ADIS16497, which processes data at a rate of 4250 SPS when using the internal sample clock. Using one of the external clock options in FNCTIO_CTRL, Bits[7:4] (see Table 144) can provide flexibility in selecting this rate. External Clock Options FROM SENSORS FACTORY CALIBRATION USER CALIBRATION TO FILTERING 15061-016 The ADIS16497 is an autonomous sensor system. A power-on self test begins automatically after the voltage on the power supply pins reaches a minimum safe level as defined by Table 1. After the automatic power-on self test, the ADIS16497 begins sampling, processing, and loading calibrated sensor data into the output registers which are accessible using the SPI port. Figure 24. Gyroscope Calibration Processing Figure 21. Signal Processing Diagram, Inertial Sensors Gyroscope Data Sampling Gyroscope Factory Calibration The ADIS16497 produces angular rate measurements around three orthogonal axes (x, y, and z). Figure 22 shows the basic signal flow for the production of x-axis gyroscope data (same as y-axis and z-axis). This signal chain contains two digital MEMS gyroscopes (XG1 and XG2), which have their own ADC and sample clocks (fSGX1 and fSGX2 = 4100 Hz) that produce data independently from each other. The sensor to sensor tolerance on this sample rate is 200 samples per second (SPS). Processing these data starts with combining (summation and rescale) the most recent sample from each gyroscope together by using an independent sample master frequency (fSM) clock (fSM = 4250 Hz, see Figure 22), which drives the rest of the digital signal processing (calibration, alignment, and filtering) for the gyroscopes and accelerometers. Gyroscope factory calibration applies the following correction formula to the data of each gyroscope: ADC X-AXIS RATE DATA SAMPLE 1 X-AXIS ANGULAR RATE DATA PROCESSING fSGX1 = 4100Hz MEMS GYROSCOPE XG2 ADC X-AXIS RATE DATA SAMPLE 2 fSGX2 = 4100Hz 15061-014 MEMS GYROSCOPE XG1 fSM = 4250Hz Figure 22. Gyroscope Data Sampling Accelerometer Data Sampling The ADIS16497 produces linear acceleration measurements along the same orthogonal axes (x, y, and z) as the gyroscopes, using the same clock (fSM, see Figure 22 and Figure 23) that triggers data acquisition and subsequent processing of the gyroscope data. ADC g 11 g 21 g 31 g 13 a ' X g 23 a 'Y g 33 a ' Z (1) All the correction factors in each matrix/array are derived from direct observation of the response of each gyroscope to a variety of rotation rates at multiple temperatures across the calibration temperature range (-40C TC +85C). These correction factors are stored in the flash memory bank, but they are not available for observation. Register CONFIG, Bit 7 provides an on/off control for the linear g compensation (see Table 148). See Figure 45 for more details on the user calibration options that are available for the gyroscopes. X-AXIS ACCELERATION DATA PROCESSING fSM = 4250SPS g 12 g 22 g 32 where: XC, YC, and ZC are the postcalibration gyroscope data. m11, m12, m13, m21, m22, m23, m31, m32, and m33 are the scale and alignment correction factors. X, Y, and Z are the precalibration gyroscope data. bX, bY, and bZ are the bias correction factors. g11, g12, g13, g21, g22, g23, g31, g32, and g33 are the linear g correction factors. a'X, a'Y, and a'Z are the postcalibration accelerometer data. 15061-015 X-AXIS MEMS ACCELEROMETER b X m11 m12 m13 XC X YC m 21 m 22 m 23 Y bY b m31 m32 m33 Z Z ZC Figure 23. Accelerometer Data Sampling Rev. D | Page 13 of 43 ADIS16497 Data Sheet Accelerometer Factory Calibration The decimation filter averages multiple samples together to produce each register update. In this type of filter structure, the number of samples in the average is equal to the reduction in the update rate for the output data registers. See the DEC_RATE register for the user controls for this filter (see Table 150). The accelerometer factory calibration applies the following correction formulas to the data of each accelerometer: p12 0 p32 m32 m13 a X b X m23 aY bY m33 a Z bZ REGISTER STRUCTURE (2) p13 2XC 2 p 23 YC 0 2ZC where: a'X, a'Y, and a'Z are the postcalibration accelerometer data. m11, m12, m13, m21, m22, m23, m31, m32, and m33 are the scale and alignment correction factors. aX, aY, and aZ are the precalibration accelerometer data. bX, bY, and bZ are the bias correction factors. 0, p12, p13, p21, p23, p31, and p32 are the point of percussion correction factors 2XC, 2YC, and 2ZC are the postcalibration gyroscope data (squared). All the correction factors in each matrix/array are derived from direct observation of the response of each accelerometer to a variety of inertial test conditions at multiple temperatures across the calibration temperature range (-40C TC +85C). These correction factors are stored in the flash memory bank, but they are not available for observation. Register CONFIG, Bit 6 provides an on/off control for the point of percussion alignment (see Table 148). See Figure 46 for more details on the user calibration options that are available for the accelerometers. Filtering FROM CALIBRATION FIR FILTER DECIMATION FILTER TO DATA REGISTERS 15061-017 After calibration, the data of each inertial sensor passes through two digital filters, both of which have user configurable attributes: FIR and decimation (see Figure 25). Figure 25. Inertial Sensor Filtering The FIR filter includes four banks of coefficients that have 120 taps each. Register FILTR_BNK_0 (see Table 158) and Register FILTR_BNK_1 (see Table 160) provide the configuration options for the use of the FIR filters of each inertial sensor. Each FIR filter bank includes a preconfigured filter, but the user can design their own filters and write over these values using the register of each coefficient. For example, Table 163 provides the details for the FIR_COEF_A071 register, which contains Coefficient 71 in FIR Bank A. Refer to Figure 49 for the frequency response of the factory default filters. These filters do not represent any specific application environment; they are only examples. All communication with the ADIS16497 involves accessing its user registers. The register structure contains both output data and control registers. The output data registers include the latest sensor data, error flags, and identification data. The control registers include sample rate, filtering, I/O, calibration, and diagnostic configuration options. All communication between the ADIS16497 and an external processor involves either reading or writing to one of the user registers. TRIAXIAL GYROSCOPE ADC DSP OUTPUT REGISTERS TRIAXIAL ACCELEROMETER TEMPERATURE SENSOR CONTROLLER CONTROL REGISTERS 15061-018 0 p 21 p31 m12 m22 SPI a' X m11 a'Y m21 a ' Z m31 Figure 26. Basic Operation The register structure uses a paged addressing scheme that contains 13 pages, with each page containing 64 register locations. Each register is 16 bits wide, with each byte having its own unique address within the memory map of that page. The SPI port has access to one page at a time, using the bit sequence in Figure 27. Select the page to activate for SPI access by writing its code to the PAGE_ID register. Read the PAGE_ID register to determine which page is currently active. Table 7 displays the PAGE_ID contents for each page and their basic functions. The PAGE_ID register is located at Address 0x00 on every page. Table 7. User Register Page Assignments Page 0 1 2 3 4 PAGE_ID 0x00 0x01 0x02 0x03 0x04 5 6 7 8 9 10 11 12 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C Rev. D | Page 14 of 43 Function Output data, clock, identification Reserved Calibration Control: sample rate, filtering, I/O Serial number, cyclic redundancy check (CRC) values FIR Filter Bank A, Coefficient 0 to Coefficient 59 FIR Filter Bank A, Coefficient 60 to Coefficient 119 FIR Filter Bank B, Coefficient 0 to Coefficient 59 FIR Filter Bank B, Coefficient 60 to Coefficient 119 FIR Filter Bank C, Coefficient 0 to Coefficient 59 FIR Filter Bank C, Coefficient 60 to Coefficient 119 FIR Filter Bank D, Coefficient 0 to Coefficient 59 FIR Filter Bank D, Coefficient 60 to Coefficient 119 Data Sheet ADIS16497 CS DIN R/W D15 DOUT A6 A5 A4 A3 A2 A1 A0 DC7 DC6 DC5 DC4 DC3 DC2 DC1 DC0 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 R/W D15 A6 A5 D14 D13 NOTES 1. DOUT BITS ARE PRODUCED ONLY WHEN THE PREVIOUS 16-BIT DIN SEQUENCE STARTS WITH R/W = 0. 2. WHEN CS IS HIGH, DOUT IS IN A THREE-STATE, HIGH IMPEDANCE MODE, WHICH ALLOWS MULTIFUNCTIONAL USE OF THE LINE FOR OTHER DEVICES. 15061-019 SCLK Figure 27. SPI Communication Bit Sequence DATA READY The SPI provides access to all of the user accessible registers (see Table 8) and typically connects to a compatible port on an embedded processor platform. See Figure 28 for a diagram that provides the most common connections between the ADIS16497 and an embedded processor. The factory default configuration provides the user with a data ready (DR) signal on the DIO2 pin, which pulses low when the output data registers are updating (see Figure 29). In this configuration, connect DIO2 to an interrupt service pin on the embedded processor, which triggers data collection, when this signal pulses high. Register FNCTIO_CTRL, Bits[3:0] (see Table 144), provides user configuration options for this function. I/O LINES ARE COMPATIBLE WITH 3.3V LOGIC LEVELS 3.3V VDD 10 CS SCLK 3 SCLK MOSI 5 DIN MISO 4 DOUT IRQ 9 DIO2 DIO2 ADIS16497 ACTIVE 13 14 During the start-up and reset recovery processes, the DR signal can exhibit transient behavior before data production begins. Figure 30 provides an example of the DR behavior during startup, and Figure 31 and Figure 32 provide examples of the DR behavior during recovery from reset commands. Figure 28. Electrical Connection Diagram TIME THAT VDD > 3V Table 8. Generic Master Processor Pin Names and Functions Mnemonic SS IRQ MOSI MISO SCLK INACTIVE Figure 29. Data Ready, when FNCTIO_CTRL, Bits[3:0] = 1101 (default) VDD Function Slave select Interrupt request Master output, slave input Master input, slave output Serial clock PULSING INDICATES DATA PRODUCTION DR START-UP TIME Embedded processors typically use control registers to configure their serial ports for communicating with SPI slave devices such as the ADIS16497. Table 9 provides a list of settings that describe the SPI protocol of the ADIS16497. The initialization routine of the master processor typically establishes these settings using firmware commands to write them into its serial control registers. Figure 30. Data Ready Response During Startup SOFTWARE RESET COMMAND GLOB_CMD[7] = 1 DR PULSING RESUMES DR RESET RECOVERY TIME Table 9. Generic Master Processor SPI Settings Processor Setting Master SCLK 15 MHz SPI Mode 3 MSB First Mode 16-Bit Mode 15061-022 6 Figure 31. Data Ready Response During Software Reset (Register GLOB_CMD, Bit 7 = 1) Recovery Description ADIS16497 operates as slave Maximum serial clock rate CPOL = 1 (polarity), CPHA = 1 (phase) Bit sequence, see Figure 27 for coding Shift register/data length Rev. D | Page 15 of 43 15061-023 SS 11 15061-020 SYSTEM PROCESSOR SPI MASTER 15061-021 SERIAL PERIPHERAL INTERFACE ADIS16497 Data Sheet Burst Read Function RST PIN RELEASED RST DR PULSING RESUMES 15061-024 DR RESET RECOVERY TIME Figure 32. Data Ready Response During Reset (RST = 0) Recovery READING SENSOR DATA DIN DOUT 0x1A00 0x1800 NEXT ADDRESS Z_GYRO_OUT Z_GYRO_LOW 15061-025 Reading a single register requires two 16-bit cycles on the SPI: one to request the contents of a register and another to receive those contents. The 16-bit command code (see Figure 27) for a read request on the SPI has three parts: the read bit (R/W = 0), the 7-bit address code for either address (upper or lower) of the register, Bits[A6:A0], and eight don't care bits, Bits[DC7:DC0]. Figure 33 provides an example that includes two register reads in succession. This example starts with DIN = 0x1A00, to request the contents of the Z_GYRO_OUT register, and follows with 0x1800, to request the contents of the Z_GYRO_LOW register (assuming PAGE_ID already equals 0x0000). The sequence in Figure 33 also shows full duplex mode of operation, which means that the ADIS16497 can receive requests on DIN while also transmitting data out on DOUT within the same 16-bit SPI cycle. Figure 33. SPI Read Example Figure 34 provides an example of the four SPI signals when reading the PROD_ID register (see Table 92) in a repeating pattern. This pattern can be helpful when troubleshooting the SPI interface setup and communications. CS SCLK DIN = 0111 1110 0000 0000 = 0x7E00 DOUT DOUT = 0100 0000 0111 0001 = 0x4071 = 16497 (PROD_ID) Figure 34. SPI Read Example, Second 16-Bit Sequence 15061-026 DIN The burst read function (BRF) provides a method for reading a batch of data (status, temperature, gyroscopes, accelerometers, time stamp/data counter, and CRC code), which does not require a stall time between each 16-bit segment and only requires one command on the DIN line to initiate. System processors can execute the BRF by reading the BURST_CMD register (DIN = 0x7C00) and then reading each segment of data in the response, while holding the CS line in a low state, until after reading the last 16-bit segment of data. If the CS line goes high before the completion of all data acquisition, the data from that read request is lost. The BRF response (on the DOUT line) contains either 19 or 20 data segments (16-bits each), after the BRF request (DIN = 0x7C00) depending on the SCLK rate. Figure 5 and Table 10 illustrate the 19-segment case, while Figure 6 and in Table 11 illustrate the 20-segment case. To manage that variation, use the transition from the BURST_ID code (0xA5A5 in Table 10 and Table 11) to the SYS_E_FLAG register, which is not equal to 0xA5A5, as an identifier for when the ADIS16497 BRF response is starting. Table 10. BRF Data Format (fSCLK < 3 MHz)1 Segment DIN DOUT 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 0x7C00 N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A 18 19 N/A N/A N/A 0x0000 0xA5A5 (BURST_ID) SYS_E_FLAG TEMP_OUT X_GYRO_LOW X_GYRO_OUT Y_GYRO_LOW Y_GYRO_OUT Z_GYRO_LOW Z_GYRO_OUT X_ACCL_LOW X_ACCL_OUT Y_ACCL_LOW Y_ACCL_OUT Z_ACCL_LOW Z_ACCL_OUT DATA_CNT (FNCTIO_CTRL, Bits[8:7] 11) TIME_STAMP (FNCTIO_CTRL, Bits[8:7] = 11) CRC_LWR CRC_UPR 1 N/A means not applicable. Rev. D | Page 16 of 43 Data Sheet ADIS16497 CS Table 11. BRF Data Format (fSCLK > 3.6 MHz)1 Segment DIN DOUT 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 0x7C00 N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A 19 20 N/A N/A N/A 0x0000 0xA5A5 (BURST_ID) 0xA5A5 (BURST_ID) SYS_E_FLAG TEMP_OUT X_GYRO_LOW X_GYRO_OUT Y_GYRO_LOW Y_GYRO_OUT Z_GYRO_LOW Z_GYRO_OUT X_ACCL_LOW X_ACCL_OUT Y_ACCL_LOW Y_ACCL_OUT Z_ACCL_LOW Z_ACCL_OUT DATA_CNT (FNCTIO_CTRL, Bits[8:7] 11) TIME_STAMP (FNCTIO_CTRL, Bits[8:7] = 11) CRC_LWR CRC_UPR N/A means not applicable. DEVICE CONFIGURATION 0x90DC 15061-027 DIN 0x91FE Figure 35. SPI Sequence for Writing 0xFEDC to XG_BIAS_LOW Dual Memory Structure The ADIS16497 uses a dual memory structure (see Figure 36), with static random access memory (SRAM) supporting realtime operation and flash memory storing operational code, calibration coefficients, and user configurable register settings. The manual flash update command (GLOB_CMD, Bit 3, see Table 142) provides a single-command method for storing user configuration settings into flash memory, for automatic recall during the next power-on or reset recovery process. This portion of the flash memory bank has two independent banks that operate in a ping pong manner, alternating with every flash update. During power-on or reset recovery, the ADIS16497 performs a CRC on the SRAM and compares it to a CRC computation from the same memory locations in flash memory. If this memory test fails, the ADIS16497 resets and boots up from the other flash memory location. SYS_E_FLAG, Bit 2 (see Table 18) provides an error flag for detecting when the backup flash memory supported the last power-on or reset recovery. Table 12 provides a memory map for the user registers in the ADIS16497, which includes flash backup support (indicated by yes or no in the flash column). Each register contains 16 bits (two bytes); Bits[7:0] contain the low byte and Bits[15:8] contain the high byte. Each byte has its own unique address in the user register map (see Table 12). Updating the contents of a register requires writing to its low byte first and its high byte second. There are three parts to coding a SPI command (see Figure 27), which writes a new byte of data to a register: the write bit (R/W = 1), the 7-bit address code for the byte that this command is updating, and the new data for that location, Bits[DC7:DC0]. Figure 35 provides a coding example for writing 0xFEDC to the XG_BIAS_LOW register (see Table 106), assuming PAGE_ID already equals 0x0002. Rev. D | Page 17 of 43 MANUAL FLASH BACKUP NONVOLATILE FLASH MEMORY VOLATILE SRAM (NO SPI ACCESS) SPI ACCESS START-UP RESET Figure 36. SRAM and Flash Memory Diagram 15061-028 1 SCLK ADIS16497 Data Sheet USER REGISTER MEMORY MAP Table 12. User Register Memory Map1 Register Name PAGE_ID Reserved DATA_CNT Reserved SYS_E_FLAG DIAG_STS Reserved TEMP_OUT X_GYRO_LOW X_GYRO_OUT Y_GYRO_LOW Y_GYRO_OUT Z_GYRO_LOW Z_GYRO_OUT X_ACCL_LOW X_ACCL_OUT Y_ACCL_LOW Y_ACCL_OUT Z_ACCL_LOW Z_ACCL_OUT TIME_STAMP CRC_LWR CRC_UPR Reserved X_DELTANG_LOW X_DELTANG_OUT Y_DELTANG_LOW Y_DELTANG_OUT Z_DELTANG_LOW Z_DELTANG_OUT X_DELTVEL_LOW X_DELTVEL_OUT Y_DELTVEL_LOW Y_DELTVEL_OUT Z_DELTVEL_LOW Z_DELTVEL_OUT Reserved BURST_CMD PROD_ID Reserved PAGE_ID Reserved X_GYRO_SCALE Y_GYRO_SCALE Z_GYRO_SCALE X_ACCL_SCALE Y_ACCL_SCALE Z_ACCL_SCALE XG_BIAS_LOW XG_BIAS_HIGH R/W R/W N/A R N/A R R N/A R R R R R R R R R R R R R R R R N/A R R R R R R R R R R R R N/A R R N/A R/W N/A R/W R/W R/W R/W R/W R/W R/W R/W Flash Backup No N/A No N/A No No N/A No No No No No No No No No No No No No No No No N/A No No No No No No No No No No No No N/A No Yes N/A No N/A Yes Yes Yes Yes Yes Yes Yes Yes PAGE_ID 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x01 0x02 0x02 0x02 0x02 0x02 0x02 0x02 0x02 0x02 0x02 Address 0x00, 0x01 0x02, 0x03 0x04, 0x05 0x06, 0x07 0x08, 0x09 0x0A, 0x0B 0x0C, 0x0D 0x0E, 0x0F 0x10, 0x11 0x12, 0x13 0x14, 0x15 0x16, 0x17 0x18, 0x19 0x1A, 0x1B 0x1C, 0x1D 0x1E, 0x1F 0x20, 0x21 0x22, 0x23 0x24, 0x25 0x26, 0x27 0x28, 0x29 0x2A, 0x2B 0x2C, 0x2D 0x2E to 0x3F 0x40, 0x41 0x42, 0x43 0x44, 0x45 0x46, 0x47 0x48, 0x49 0x4A, 0x4B 0x4C, 0x4D 0x4E, 0x4F 0x50, 0x51 0x52, 0x53 0x54, 0x55 0x56, 0x57 0x58 to 0x7B 0x7C, 0x7D 0x7E, 0x7F 0x00 to 0x7F 0x00, 0x01 0x02, 0x03 0x04, 0x05 0x06, 0x07 0x08, 0x09 0x0A, 0x0B 0x0C, 0x0D 0x0E, 0x0F 0x10, 0x11 0x12, 0x13 Default 0x0000 N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A 0x4071 N/A 0x0000 N/A 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 Rev. D | Page 18 of 43 Register Description Page identifier Reserved Data counter Reserved Output, system error flags (0x0000 if no errors) Output, self test error flags (0x0000 if no errors) Reserved Output, temperature Output, x-axis gyroscope, low word Output, x-axis gyroscope, high word Output, y-axis gyroscope, low word Output, y-axis gyroscope, high word Output, z-axis gyroscope, low word Output, z-axis gyroscope, high word Output, x-axis accelerometer, low word Output, x-axis accelerometer, high word Output, y-axis accelerometer, low word Output, y-axis accelerometer, high word Output, z-axis accelerometer, low word Output, z-axis accelerometer, high word Output, time stamp Output, CRC-32 (32 bits), lower word Output, CRC-32, upper word Reserved Output, x-axis delta angle, low word Output, x-axis delta angle, high word Output, y-axis delta angle, low word Output, y-axis delta angle, high word Output, z-axis delta angle, low word Output, z-axis delta angle, high word Output, x-axis delta velocity, low word Output, x-axis delta velocity, high word Output, y-axis delta velocity, low word Output, y-axis delta velocity, high word Output, z-axis delta velocity, low word Output, z-axis delta velocity, high word Reserved Burst-read command Output, product identification (16497d) Reserved Page identifier Reserved Calibration, scale, x-axis gyroscope Calibration, scale, y-axis gyroscope Calibration, scale, z-axis gyroscope Calibration, scale, x-axis accelerometer Calibration, scale, y-axis accelerometer Calibration, scale, z-axis accelerometer Calibration, bias, gyroscope, x-axis, low word Calibration, bias, gyroscope, x-axis, high word Data Sheet Register Name YG_BIAS_LOW YG_BIAS_HIGH ZG_BIAS_LOW ZG_BIAS_HIGH XA_BIAS_LOW XA_BIAS_HIGH YA_BIAS_LOW YA_BIAS_HIGH ZA_BIAS_LOW ZA_BIAS_HIGH Reserved USER_SCR_1 USER_SCR_2 USER_SCR_3 USER_SCR_4 FLSHCNT_LOW FLSHCNT_HIGH PAGE_ID GLOB_CMD Reserved FNCTIO_CTRL GPIO_CTRL CONFIG DEC_RATE NULL_CNFG SYNC_SCALE RANG_MDL Reserved FILTR_BNK_0 FILTR_BNK_1 Reserved FIRM_REV FIRM_DM FIRM_Y BOOT_REV PAGE_ID Reserved CAL_SIGTR_LWR CAL_SIGTR_UPR CAL_DRVTN_LWR CAL_DRVTN_UPR CODE_SIGTR_LWR CODE_SIGTR_UPR CODE_DRVTN_LWR CODE_DRVTN_UPR Reserved SERIAL_NUM Reserved PAGE_ID Reserved FIR_COEF_Axxx3 PAGE_ID Reserved ADIS16497 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W N/A R/W R/W R/W R/W R R R/W W N/A R/W R/W R/W R/W R/W R/W R N/A R/W R/W N/A R R R R R/W N/A R R R R R R R R N/A R N/A R/W N/A R/W R/W N/A Flash Backup Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes N/A Yes Yes Yes Yes Yes Yes No No N/A Yes Yes Yes Yes Yes Yes N/A N/A Yes Yes N/A Yes Yes Yes Yes No N/A Yes Yes No No Yes Yes No No N/A Yes N/A No N/A Yes No N/A PAGE_ID 0x02 0x02 0x02 0x02 0x02 0x02 0x02 0x02 0x02 0x02 0x02 0x02 0x02 0x02 0x02 0x02 0x02 0x03 0x03 0x03 0x03 0x03 0x03 0x03 0x03 0x03 0x03 0x03 0x03 0x03 0x03 0x03 0x03 0x03 0x03 0x04 0x04 0x04 0x04 0x04 0x04 0x04 0x04 0x04 0x04 0x04 0x04 0x04 0x05 0x05 0x05 0x06 0x06 Address 0x14, 0x15 0x16, 0x17 0x18, 0x19 0x1A, 0x1B 0x1C, 0x1D 0x1E, 0x1F 0x20, 0x21 0x22, 0x23 0x24, 0x25 0x26, 0x27 0x28 to 0x73 0x74, 0x75 0x76, 0x77 0x78, 0x79 0x7A, 0x7B 0x7C, 0x7D 0x7E, 07F 0x00, 0x01 0x02, 0x03 0x04, 0x05 0x06, 0x07 0x08, 0x09 0x0A, 0x0B 0x0C, 0x0D 0x0E, 0x0F 0x10, 0x11 0x12, 0x13 0x14, 0x15 0x16, 0x17 0x18, 0x19 0x1A to 0x77 0x78, 0x79 0x7A, 0x7B 0x7C, 0x7D 0x7E, 0x7F 0x00, 0x01 0x02, 0x03 0x04, 0x05 0x06, 0x07 0x08, 0x09 0x0A, 0x0B 0x0C, 0x0D 0x0E, 0x0F 0x10, 0x11 0x12, 0x13 0x14 to 0x1F 0x20, 0x21 0x22 to 0x7F 0x00, 0x01 0x02 to 0x07 0x08 to 0x7F 0x00, 0x01 0x02 to 0x07 Default 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 N/A N/A 0x0000 N/A N/A 0x000D 0x00X02 0x00C0 0x0000 0x070A 0x109A N/A N/A 0x0000 0x0000 N/A N/A N/A N/A N/A 0x0000 N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A 0x0000 N/A N/A 0x0000 N/A Rev. D | Page 19 of 43 Register Description Calibration, bias, gyroscope, y-axis, low word Calibration, bias, gyroscope, y-axis, high word Calibration, bias, gyroscope, z-axis, low word Calibration, bias, gyroscope, z-axis, high word Calibration, bias, accelerometer, x-axis, low word Calibration, bias, accelerometer, x-axis, high word Calibration, bias, accelerometer, y-axis, low word Calibration, bias, accelerometer, y-axis, high word Calibration, bias, accelerometer, z-axis, low word Calibration, bias, accelerometer, z-axis, high word Reserved User Scratch Register 1 User Scratch Register 2 User Scratch Register 3 User Scratch Register 4 Diagnostic, flash memory count, low word Diagnostic, flash memory count, high word Page identifier Control, global commands Reserved Control, I/O pins, functional definitions Control, I/O pins, general-purpose Control, clock, and miscellaneous correction Control, output sample rate decimation Control, automatic bias correction configuration Control, input clock scaling (PPS mode) Measurement range (model-specific) Identifier Reserved Filter selection Filter selection Reserved Firmware revision Firmware programming date (day/month) Firmware programming date (year) Boot loader revision Page identifier Reserved Signature CRC, calibration coefficients, low word Signature CRC, calibration coefficients, high word Real-time CRC, calibration coefficients, low word Real-time CRC, calibration coefficients, high word Signature CRC, program code, low word Signature CRC, program code, high word Real-time CRC, program code, low word Real-time CRC, program code, high word Reserved Serial number Reserved Page identifier Reserved FIR Filter Bank A: Coefficient 0 through Coefficient 59 Page identifier Reserved ADIS16497 Register Name FIR_COEF_Axxx3 PAGE_ID Reserved FIR_COEF_Bxxx4 PAGE_ID Reserved FIR_COEF_Bxxx4 PAGE_ID Reserved FIR_COEF_Cxxx5 PAGE_ID Reserved FIR_COEF_Cxxx5 PAGE_ID Reserved FIR_COEF_Dxxx6 PAGE_ID Reserved FIR_COEF_Dxxx6 Data Sheet R/W R/W R/W N/A R/W R/W N/A R/W R/W N/A R/W R/W N/A R/W R/W N/A R/W R/W N/A R/W Flash Backup Yes No N/A Yes No N/A Yes No N/A Yes No N/A Yes No N/A Yes No N/A Yes PAGE_ID 0x06 0x07 0x07 0x07 0x08 0x08 0x08 0x09 0x09 0x09 0x0A 0x0A 0x0A 0x0B 0x0B 0x0B 0x0C 0x0C 0x0C Address 0x08 to 0x7F 0x00, 0x01 0x02 to 0x07 0x08 to 0x7F 0x00, 0x01 0x02 to 0x07 0x08 to 0x7F 0x00, 0x01 0x02 to 0x07 0x08 to 0x7F 0x00, 0x01 0x02 to 0x07 0x08 to 0x7F 0x00, 0x01 0x02 to 0x07 0x08 to 0x7F 0x00, 0x01 0x02 to 0x07 0x08 to 0x7F Default N/A 0x0000 N/A N/A 0x0000 N/A N/A 0x0000 N/A N/A 0x0000 N/A N/A 0x0000 N/A N/A 0x0000 N/A N/A 1 N/A means not applicable. The GPIO_CTRL[7:4] bits reflect the logic levels on the DIOx lines and do not have a default setting. 3 See the FIR Filter Bank A, FIR_COEF_A000 to FIR_COEF_A119 section for additional information. 4 See the FIR Filter Bank B, FIR_COEF_B000 to FIR_COEF_B119 section for additional information. 5 See the FIR Filter Bank C, FIR_COEF_C000 to FIR_COEF_C119 section for additional information. 6 See the FIR Filter Bank D, FIR_COEF_D000 to FIR_COEF_D119 section for additional information. 2 Rev. D | Page 20 of 43 Register Description FIR Filter Bank A: Coefficient 60 through Coefficient 119 Page identifier Reserved FIR Filter Bank B: Coefficient 0 through Coefficient 59 Page identifier Reserved FIR Filter Bank B: Coefficient 60 through Coefficient 119 Page identifier Reserved FIR Filter Bank C: Coefficient 0 through Coefficient 59 Page identifier Reserved FIR Filter Bank C: Coefficient 60 through Coefficient 119 Page identifier Reserved FIR Filter Bank D: Coefficient 0 through Coefficient 59 Page identifier Reserved FIR Filter Bank D: Coefficient 60 through Coefficient 119 Data Sheet ADIS16497 USER REGISTER DEFINTIONS PAGE NUMBER (PAGE_ID) The contents in the PAGE_ID register (see Table 13 and Table 14) contain the current page setting, and provide a control for selecting another page for SPI access. For example, set DIN = 0x8002 to select Page 2 for SPI-based user access. See Table 12 for the page assignments associated with each user accessible register. Table 18. SYS_E_FLAG Bit Descriptions Bits 15 [14:9] 8 Table 13. PAGE_ID Register Definition Page 0x00 Addresses 0x00, 0x01 Default 0x0000 Access R/W Flash Backup No 7 Table 14. PAGE_ID Bit Descriptions Bits [15:0] Description Page number, binary numerical format 6 DATA/SAMPLE COUNTER (DATA_CNT) The DATA_CNT register (see Table 15 and Table 16) is a continuous, real-time, sample counter. It starts at 0x0000, increments every time the output data registers update, and wraps around from 0xFFFF (65,535 decimal) to 0x0000 (0 decimal). 4 3 Table 15. DATA_CNT Register Definition Page 0x00 Addresses 0x04, 0x05 Default Not applicable Access R Flash Backup No Table 16. DATA_CNT Bit Descriptions Bits [15:0] 5 2 Description Data counter, binary format STATUS/ERROR FLAG INDICATORS (SYS_E_FLAG) The SYS_E_FLAG register (see Table 17 and Table 18) provides various error flags. Reading this register causes all of its bits to return to 0, with the exception of Bit 7. If an error condition persists, its flag (bit) automatically returns to an alarm value of 1. 1 0 Table 17. SYS_E_FLAG Register Definition Page 0x00 Addresses 0x08, 0x09 Default 0x0000 Access R Flash Backup No Rev. D | Page 21 of 43 Description Watchdog timer flag. A 1 indicates the ADIS16497 automatically resets itself to clear an issue. Not used. Sync error. A 1 indicates the sample timing is not scaling correctly, when operating in PPS mode (FNCTIO_CTRL, Bit 8 = 1, see Table 144). When this error occurs, verify that the input sync frequency is correct and that SYNC_SCALE (see Table 154) has the correct value. Processing overrun. A 1 indicates the occurrence of a processing overrun. Initiate a reset to recover. Replace the ADIS16497 if this error persists. Flash memory update failure. A 1 indicates that the most recent flash memory update failed (GLOB_CMD, Bit 3, see Table 142). Repeat the test and replace the ADIS16497 if this error persists. Sensor failure. A 1 indicates failure in at least one of the inertial sensors. Read the DIAG_STS register (see Table 20) to determine which sensor is failing. Replace the ADIS16497 if the error persists, when it is operating in static inertial conditions. Not used. SPI communication error. A 1 indicates that the total number of SCLK cycles is not equal to an integer multiple of 16. Repeat the previous communication sequence to recover. Persistence in this error can indicate a weakness in the SPI service from the master processor. SRAM error condition. A 1 indicates a failure in the CRC (period = 20 ms) between the SRAM and flash memory. Initiate a reset to recover. Replace the ADIS16497 if this error persists. Boot memory failure. A 1 indicates that the device booted up using code from the backup memory bank. Replace the ADIS16497 if this error occurs. Not used. ADIS16497 Data Sheet SELF TEST ERROR FLAGS (DIAG_STS) GYROSCOPE DATA SYS_E_FLAG, Bit 5 (see Table 18) contains the pass/fail result (0 = pass) for the on demand self test (ODST) operations, whereas the DIAG_STS register (see Table 19 and Table 20) contains pass/fail flags (0 = pass) for each inertial sensor. Reading the DIAG_STS register causes all of its bits to restore to 0. The bits in DIAG_STS return to 1 if the error conditions persists. The gyroscopes in the ADIS16497 measure the angular rate of rotation around three orthogonal axes (x, y, and z). Figure 38 shows the orientation of each gyroscope axis, which defines the direction of rotation that produces a positive response in each of the angular rate measurements. Page 0x00 Addresses 0x0A, 0x0B Default 0x0000 Access R Flash Backup No X_GYRO_OUT Bits [15:6] 5 4 3 2 1 0 Description (Default = 0x0000) Not used Self test failure, z-axis accelerometer (1 means failure) Self test failure, y-axis accelerometer (1 means failure) Self test failure, x-axis accelerometer (1 means failure) Self test failure, z-axis gyroscope (1 means failure) Self test failure, y-axis gyroscope (1 means failure) Self test failure, x-axis gyroscope (1 means failure) INTERNAL TEMPERATURE (TEMP_OUT) The TEMP_OUT register (see Table 21 and Table 22) provides a coarse measurement of the temperature inside of the ADIS16497, and is useful for monitoring relative changes in the thermal environment. Table 23 provides several examples of the data format for the TEMP_OUT register. Table 21. TEMP_OUT Register Definition Page 0x00 Addresses 0x0E, 0x0F Default Not applicable X_GYRO_LOW 15 Table 20. DIAG_STS Bit Descriptions Access R Flash Backup No 0 15 0 X-AXIS GYROSCOPE DATA 15061-029 Table 19. DIAG_STS Register Definition Each gyroscope has two output data registers. Figure 37 shows how these two registers combine to support a 32-bit, twos complement data format for the x-axis gyroscope measurements. This format also applies to the y-axis and z-axis as well. Figure 37. Gyroscope Output Data Structure Gyroscope Measurement Range/Scale Factor Table 24 provides the range and scale factor (KG) for the angular rate (gyroscope) measurements in each ADIS16497 model. Table 24. Gyroscope Measurement Range and Scale Factors Model ADIS16497-1 ADIS16497-2 ADIS16497-3 Range 125/sec 450/sec 2000/sec Scale Factor, KG 0.00625/sec/LSB 0.025/sec/LSB 0.1/sec/LSB Gyroscope Data Formatting Table 25 and Table 26 offer various numerical examples that demonstrate the format of the rotation rate data in both 16-bit and 32-bit formats. See Table 24 for the scale factor (KG) associated with each ADIS16497 model. Table 25. 16-Bit Gyroscope Data Format Examples Table 22. TEMP_OUT Bit Definitions Bits [15:0] Description Temperature data; twos complement, 1C per 80 LSB, 25C = 0x0000 Table 23. TEMP_OUT Data Format Examples Temperature (C) +85 +25 + 2/80 +25 + 1/80 +25 +25 - 1/80 +25 - 2/80 -40 Decimal +4800 +2 +1 0 -1 -2 -5200 Hex 0x12C0 0x0002 0x0001 0x0000 0xFFFF 0xFFFE 0xEBB0 Binary 0001 0010 1100 0000 0000 0000 0000 0010 0000 0000 0000 0001 0000 0000 0000 0000 1111 1111 1111 1111 1111 1111 1111 1110 1110 1011 1011 0000 Rotation Rate (/sec) +10000 KG +2 KG +KG 0/sec -KG -2 KG -10000 KG Decimal +10,000 +2 +1 0 -1 -2 -10,000 Hex 0x2710 0x0002 0x0001 0x0000 0xFFFF 0xFFFE 0xD8F0 Binary 0010 0111 0001 0000 0000 0000 0000 0010 0000 0000 0000 0001 0000 0000 0000 0000 1111 1111 1111 1111 1111 1111 1111 1110 1101 1000 1111 0000 Table 26. 32-Bit Gyroscope Data Format Examples Rotation Rate (/sec) +10000 KG +KG/215 +KG/216 0 -KG /216 -KG /215 -10000 KG Rev. D | Page 22 of 43 Decimal +655,360,000 +2 +1 0 -1 -2 -655,360,000 Hexadecimal 0x27100000 0x00000002 0x00000001 0x0000000 0xFFFFFFFF 0xFFFFFFFE 0xD8F00000 Data Sheet ADIS16497 Z-AXIS Z X-AXIS Y-AXIS Y PIN 23 15061-030 X PIN 1 Figure 38. Gyroscope Axis and Polarity Assignments X-Axis Gyroscope (X_GYRO_LOW, X_GRYO_OUT) Table 32. Y_GYRO_LOW Bit Descriptions The X_GYRO_LOW (see Table 27 and Table 28) and X_GRYO_ OUT (see Table 29 and Table 30) registers contain the gyroscope data for the x-axis. Bits [15:0] Table 27. X_GYRO_LOW Register Definition Table 33. Y_GYRO_OUT Register Definition Page 0x00 Addresses 0x10, 0x11 Default Not applicable Access R Flash Backup No Page 0x00 Description Y-axis gyroscope data; low word Addresses 0x16, 0x17 Default Not applicable Access R Table 28. X_GYRO_LOW Bit Descriptions Table 34. Y_GYRO_OUT Bit Descriptions Bits [15:0] Bits [15:0] Description X-axis gyroscope data; low word Addresses 0x12, 0x13 Default Not applicable Access R Flash Backup No Table 30. X_GYRO_OUT Bit Descriptions Bits [15:0] Description X-axis gyroscope data; high word; twos complement, 0/sec = 0x0000, see Table 24 for scale factor The Y_GYRO_LOW (see Table 31 and Table 32) and Y_GRYO_ OUT (see Table 33 and Table 34) registers contain the gyroscope data for the y-axis. Default Not applicable Access R Table 35. Z_GYRO_LOW Register Definition Page 0x00 Addresses 0x18, 0x19 Default Not applicable Access R Flash Backup No Bits [15:0] Description Z-axis gyroscope data; additional resolution bits Table 37. Z_GYRO_OUT Register Definition Table 31. Y_GYRO_LOW Register Definition Addresses 0x14, 0x15 The Z_GYRO_LOW (see Table 35 and Table 36) and Z_GRYO_ OUT (see Table 37 and Table 38) registers contain the gyroscope data for the z-axis. Table 36. Z_GYRO_LOW Bit Descriptions Y-Axis Gyroscope (Y_GYRO_LOW, Y_GYRO_OUT) Page 0x00 Description Y-axis gyroscope data; high word; twos complement, 0/sec = 0x0000, see Table 24 for scale factor Z-Axis Gyroscope (Z_GYRO_LOW, Z_GYRO_OUT) Table 29. X_GYRO_OUT Register Definition Page 0x00 Flash Backup No Flash Backup No Page 0x00 Addresses 0x1A, 0x1B Default Not applicable Access R Flash Backup No Table 38. Z_GYRO_OUT Bit Descriptions Bits [15:0] Rev. D | Page 23 of 43 Description Z-axis gyroscope data; high word; twos complement, 0/sec = 0x0000, see Table 24 for scale factor ADIS16497 Data Sheet Z-AXIS aZ X-AXIS Y-AXIS aX PIN 23 15061-031 aY PIN 1 Figure 39. Accelerometer Axis and Polarity Assignments ACCELERATION DATA Y-Axis Accelerometer (Y_ACCL_LOW, Y_ACCL_OUT) The accelerometers in the ADIS16497 measure both dynamic and static (response to gravity) acceleration along three orthogonal axes (x, y, and z). Figure 39 shows the orientation of each accelerometer axis, which defines the direction of linear acceleration that produces a positive response in each of the angular rate measurements. The Y_ACCL_LOW (see Table 43 and Table 44) and Y_ACCL_ OUT (see Table 45 and Table 46) registers contain the accelerometer data for the y-axis. Each accelerometer has two output data registers. Figure 40 shows how these two registers combine to support a 32-bit, twos complement data format for the x-axis accelerometer measurements. This format also applies to the y-axis and z-axis. Page 0x00 Addresses 0x20, 0x21 Default Not applicable Access R Flash Backup No Table 44. Y_ACCL_LOW Bit Descriptions Bits [15:0] Description Y-axis accelerometer data; low word X_ACCL_LOW 0 15 0 X-AXIS ACCELEROMETER DATA 15061-032 X_ACCL_OUT 15 Table 43. Y_ACCL_LOW Register Definition Table 45. Y_ACCL_OUT Register Definition Page 0x00 Figure 40. Accelerometer Output Data Structure Addresses 0x22, 0x23 Default Not applicable Access R Flash Backup No X-Axis Accelerometer (X_ACCL_LOW, X_ACCL_OUT) The X_ACCL_LOW (see Table 39 and Table 40) and X_ACCL_ OUT (see Table 41 and Table 42) registers contain the accelerometer data for the x-axis. Table 46. Y_ACCL_OUT Bit Descriptions Bits [15:0] Table 39. X_ACCL_LOW Register Definition Page 0x00 Addresses 0x1C, 0x1D Default Not applicable Access R Flash Backup No Description Y-axis accelerometer data, high word; twos complement, 40 g range; 0 g = 0x0000, 1 LSB = 1.25 mg Z-Axis Accelerometer (Z_ACCL_LOW, Z_ACCL_OUT) Table 40. X_ACCL_LOW Bit Descriptions The Z_ACCL_LOW (see Table 47 and Table 48) and Z_ACCL_ OUT (see Table 49 and Table 50) registers contain the accelerometer data for the z-axis. Bits [15:0] Table 47. Z_ACCL_LOW Register Definition Description X-axis accelerometer data; low word Page 0x00 Table 41. X_ACCL_OUT Register Definition Page 0x00 Addresses 0x1E, 0x1F Default Not applicable Access R Flash Backup No Bits [15:0] Default Not applicable Access R Table 48. Z_ACCL_LOW Bit Descriptions Bits [15:0] Table 42. X_ACCL_OUT Descriptions Addresses 0x24, 0x25 Description X-axis accelerometer data, high word; twos complement, 40 g range; 0 g = 0x0000, 1 LSB = 1.25 mg Rev. D | Page 24 of 43 Description Z-axis accelerometer data; low word Flash Backup No Data Sheet ADIS16497 Table 49. Z_ACCL_OUT Register Definition Page 0x00 Addresses 0x26, 0x27 Default Not applicable Access R Flash Backup No Table 50. Z_ACCL_OUT Bit Descriptions Bits [15:0] Description Z-axis accelerometer data, high word; twos complement, 40 g range; 0 g = 0x0000, 1 LSB = 1.25 mg Accelerometer Resolution Table 51 and Table 52 offer various numerical examples that demonstrate the format of the linear acceleration data in both 16-bit and 32-bit formats. Table 51. 16-Bit Accelerometer Data Format Examples Acceleration +40 g +2.5 mg +1.25 mg 0 mg -1.25 mg -2.5 mg -40 g Decimal +32,000 +2 +1 0 -1 -2 -32,000 Hex 0x7D00 0x0002 0x0001 0x0000 0xFFFF 0xFFFE 0x8300 Binary 0111 1101 0000 0000 0000 0000 0000 0010 0000 0000 0000 0001 0000 0000 0000 0000 1111 1111 1111 1111 1111 1111 1111 1110 1000 0011 0000 0000 Table 52. 32-Bit Accelerometer Data Format Examples Acceleration +40 g +1.25/215 mg +1.25/216 mg 0 mg -1.25/216 mg -1.25/215 mg -40 g Decimal +2,097,152,000 +2 +1 0 -1 -2 -2,097,152,000 Hexadecimal 0x7D000000 0x00000002 0x00000001 0x00000000 0xFFFFFFFF 0xFFFFFFFE 0x83000000 When using the decimation filter (DEC_RATE > 0x0000) the value in the TIME_STAMP register represents the time of the first sample (taken at the rate of fSM, per Figure 22 and Figure 23). For example, when DEC_RATE = 0x0003, the decimation filter reduces the update by a factor of four and the TIME_STAMP register updates to 1 (decimal) during the first data update, then to 5 on the second update, 9 on the third update, for example; until the next clock signal pulse. CYCLICAL REDUNDANCY CHECK (CRC-32) The ADIS16497 performs a CRC-32 computation, using the data registers that are shown in Table 55. Table 55. CRC-32 Source Data and Example Values Register SYS_E_FLAG TEMP_OUT X_GYRO_LOW X_GYRO_OUT Y_GYRO_LOW Y_GYRO_OUT Z_GYRO_LOW Z_GYRO_OUT X_ACCL_LOW X_ACCL_OUT Y_ACCL_LOW Y_ACCL_OUT Z_ACCL_LOW Z_ACCL_OUT TIME_STAMP Example Value 0x0000 0x083A 0x0000 0xFFF7 0x0000 0xFFFE 0x0000 0x0001 0x5001 0x0003 0xE00A 0x0015 0xC009 0x0320 0x8A54 The CRC_LWR (see Table 56 and Table 57) and CRC_UPR (see Table 58 and Table 59) registers contain the result of the CRC-32 computation. For the example, the register values from Table 55 are, CRC_LWR = 0x15B4 TIME STAMP CRC_UPR = 0xB6C8 When using PPS mode (FNCTIO_CTRL, Bits[8:7] = 11 (binary), see Table 144), the TIME_STAMP register (see Table 53 and Table 54) provides the time between the most recent pulse on the input clock signal and the most recent data update. Table 53. TIME_STAMP Register Definition Page 0x00 Addresses 0x28, 0x29 Default Not applicable Access R Flash Backup No Table 54. TIME_STAMP Bit Descriptions Bits [15:0] Description Time stamp, binary format. 1 LSB = 1/fSM (see Figure 22, Figure 23, and Table 154). The leading edge of the input clock pulse resets the value in this register to 0x0000. Table 56. CRC_LWR Register Definition Page 0x00 Addresses 0x2A, 0x2B Default Not applicable Access R Flash Backup No Table 57. CRC_LWR Bit Descriptions Bits [15:0] Description CRC-32 code from most recent BRF, lower word Table 58. CRC_UPR Register Definition Page 0x00 Addresses 0x2C, 0x2D Default Not applicable Access R Flash Backup No Table 59. CRC_UPR Bit Descriptions Bits [15:0] Rev. D | Page 25 of 43 Description CRC-32 code from most recent BRF, upper word ADIS16497 Data Sheet Z-AXIS Z X-AXIS Y-AXIS Y PIN 23 15061-034 X PIN 1 Figure 41. Delta Angle Axis and Polarity Assignments Delta Angle Measurement Range DELTA ANGLES In addition to the angular rate of rotation (gyroscope) measurements around each axis (x, y, and z), the ADIS16497 also provides delta angle measurements that represent a computation of angular displacement between each sample update. Figure 41 shows the orientation of each delta angle output, which defines the direction of rotation that produces a positive response in each of the angular displacement (delta angle) measurements. The delta angle outputs represent an integration of the gyroscope measurements and use the following formula for all three axes (x-axis displayed): x , n D 1 D 1 x,n D d x,n D d 1 2 fS d 0 where: X is the delta angle measurement for the x-axis D is the decimation rate = DEC_RATE + 1 (see Table 150). fS is the sample rate. d is the incremental variable in the summation formula. x is the x-axis rate of rotation (gyroscope). n is the sample time, prior to the decimation filter. X_DELTANG_LOW X-AXIS DELTA ANGLE DATA 0 Measurement Range, MAX 360 720 2160 X-Axis Delta Angle (X_DELTANG_LOW, X_DELTANG_OUT) The X_DELTANG_LOW (see Table 61 and Table 62) and X_DELTANG_OUT (see Table 63 and Table 64) registers contain the delta angle data for the x-axis. Addresses 0x40, 0x41 Default Not applicable Access R Flash Backup No Table 62. X_DELTANG_LOW Bit Descriptions Bits [15:0] Description X-axis delta angle data; low word Table 63. X_DELTANG_OUT Register Definitions Page 0x00 Addresses 0x42, 0x43 Default Not applicable Access R Flash Backup No Table 64. X_DELTANG_OUT Bit Descriptions Bits [15:0] Description X-axis delta angle data; twos complement, 0 = 0x0000, 1 LSB = MAX/215 (see Table 60 for MAX) Y-Axis Delta Angle (Y_DELTANG_LOW, Y_DELTANG_OUT) The Y_DELTANG_LOW (see Table 65 and Table 66) and Y_DELTANG_OUT (see Table 67 and Table 68) registers contain the delta angle data for the y-axis. Table 65. Y_DELTANG_LOW Register Definitions 15061-033 0 15 Model ADIS16497-1 ADIS16497-2 ADIS16497-3 Page 0x00 Each axis of the delta angle measurements has two output data registers. Figure 42 shows how these two registers combine to support a 32-bit, twos complement data format for the x-axis delta angle measurements. This format also applies to the y-axis and z-axis. X_DELTANG_OUT Table 60. Delta Angle Measurement Range and Scale Factor Table 61. X_DELTANG_LOW Register Definitions When using the internal sample clock, fS is equal to 4250 SPS. When using the external clock option, fS is equal to the frequency of the external clock. The range in the delta angle registers accommodates the maximum rate of rotation (100/sec), the nominal sample rate (4250 SPS), and an update rate of 1 Hz (DEC_RATE = 0x1099; divide by 4249 plus 1, see Table 150), all at the same time. When using an external clock that is higher than 4250 SPS, reduce the DEC_RATE setting to avoid over-ranging the delta angle registers. 15 Table 60 offers the measurement range and scale factor for each ADIS16497 model. Page 0x00 Figure 42. Delta Angle Output Data Structure Rev. D | Page 26 of 43 Addresses 0x44, 0x45 Default Not applicable Access R Flash Backup No Data Sheet ADIS16497 Table 66. Y_DELTANG_LOW Bit Descriptions Table 74. 32-Bit Delta Angle Data Format Examples Description Y-axis delta angle data; low word Table 68. Y_DELTANG_OUT Bit Descriptions Delta Angle () +MAX x (231 - 1)/231 +MAX/230 +MAX2000/231 0 -MAX/231 -MAX/230 -MAX Bits [15:0] DELTA VELOCITY Table 67. Y_DELTANG_OUT Register Definitions Page 0x00 Addresses 0x46, 0x47 Default Not applicable Access R Flash Backup No Description Y-axis delta angle data; twos complement, 0 = 0x0000, 1 LSB = MAX/215 (see Table 60 for MAX) Z-Axis Delta Angle (Z_DELTANG_LOW, Z_DELTANG_OUT) The Z_DELTANG_LOW (see Table 69 and Table 70) and Z_DELTANG_OUT (see Table 71 and Table 72) registers contain the delta angle data for the z-axis. Table 69. Z_DELTANG_LOW Register Definitions Page 0x00 Addresses 0x48, 0x49 Default Not applicable Access R Flash Backup No The delta velocity outputs represent an integration of the acceleration measurements and use the following formula for all three axes (x-axis displayed): Vx ,n D Description Z-axis delta angle data; low word Table 71. Z_DELTANG_OUT Register Definitions Page 0x00 Addresses 0x4A, 0x4B Default Not applicable Access R Flash Backup No Table 72. Z_DELTANG_OUT Bit Descriptions Bits [15:0] Description Z-axis delta angle data; twos complement, 0 = 0x0000, 1 LSB = MAX/215 (see Table 60 for MAX) Delta Angle Resolution Table 73 and Table 74 show various numerical examples that demonstrate the format of the delta angle data in both 16-bit and 32-bit formats. Table 73. 16-Bit Delta Angle Data Format Examples Delta Angle () MAX x (215-1)/215 +MAX/214 +MAX/215 0 -MAX/215 -MAX/214 -MAX Decimal +32,767 +2 +1 0 -1 -2 -32,768 Hex 0x7FFF 0x0002 0x0001 0x0000 0xFFFF 0xFFFE 0x8000 Binary 0111 1111 1110 1111 0000 0000 0000 0010 0000 0000 0000 0001 0000 0000 0000 0000 1111 1111 1111 1111 1111 1111 1111 1110 1000 0000 0000 0000 Hexadecimal 0x7FFFFFFF 0x00000002 0x00000001 0x00000000 0xFFFFFFFF 0xFFFFFFFE 0x80000000 In addition to the linear acceleration measurements along each axis (x, y, and z), the ADIS16497 also provides delta velocity measurements that represent a computation of linear velocity change between each sample update. Figure 44 shows the orientation of each delta-velocity measurement, which defines the direction of linear velocity increase that produces a positive response in each of the delta velocity rate measurements. Table 70. Z_DELTANG_LOW Bit Descriptions Bits [15:0] Decimal +2,147,483,647 +2 +1 0 -1 -2 -2,147,483,648 1 D 1 a x ,n D d a x ,n D d 1 2 f S d 0 where: VX is the delta velocity measurement for the x-axis. D is the decimation rate = DEC_RATE + 1 (see Table 150). fS is the sample rate. d is the incremental variable in the summation formula. ax is the x-axis rate of acceleration (accelerometer). n is the sample time, prior to the decimation filter. When using the internal sample clock, fS is equal to 4250 SPS. When using the external clock option, fS is equal to the frequency of the external clock. The range in the delta velocity registers accommodates the maximum linear acceleration (8 g), the nominal sample rate (4250 SPS), and an update rate of 1 Hz (DEC_RATE = 0x1099; divide by 4249 plus 1, see Table 150), all at the same time. When using an external clock that is higher than 4250 SPS, reduce the DEC_RATE setting to avoid overranging the delta velocity registers. Each axis of the delta velocity measurements has two output data registers. Figure 43 shows how these two registers combine to support 32-bit, twos complement data format for the delta velocity measurements along the x-axis. This format also applies to the y-axis and x-axis. X_DELTVEL_OUT 15 X_DELTVEL_LOW 0 15 X-AXIS DELTA ANGLE DATA Figure 43. Delta Angle Output Data Structure Rev. D | Page 27 of 43 0 15061-035 Bits [15:0] Data Sheet ADIS16497 Z-AXIS VZ X-AXIS Y-AXIS VX PIN 23 15061-036 VY PIN 1 Figure 44. Delta Velocity Axis and Polarity Assignments X-Axis Delta Velocity (X_DELTVEL_LOW, X_DELTVEL_OUT) The X_DELTVEL_LOW (see Table 75 and Table 76) and X_DELTVEL_OUT (see Table 77 and Table 78) registers contain the delta velocity data for the x-axis. Table 81. Y_DELTVEL_OUT Register Definitions Page 0x00 Addresses 0x52, 0x53 Default Not applicable Access R Table 75. X_DELTVEL_LOW Register Definitions Table 82. Y_DELTVEL_OUT Bit Descriptions Page 0x00 Bits [15:0] Addresses 0x4C, 0x4D Default Not applicable Access R Flash Backup No Table 76. X_DELTVEL_LOW Bit Descriptions Bits [15:0] Description X-axis delta angle data; low word Flash Backup No Description Y-axis delta velocity data; high word; twos complement, 400 m/sec range, 0 m/sec = 0x0000; 1 LSB = 400 m/sec / 215 = ~12.208 mm/sec Z-Axis Delta Velocity (Z_DELTVEL_LOW, Z_DELTVEL_OUT) Table 77. X_DELTVEL_OUT Register Definitions The Z_DELTVEL_LOW (see Table 83 and Table 84) and Z_DELTVEL_OUT (see Table 85 and Table 86) registers contain the delta velocity data for the z-axis. Page 0x00 Table 83. Z_DELTVEL_LOW Register Definitions Addresses 0x4E, 0x4F Default Not applicable Access R Flash Backup No Page 0x00 Table 78. X_DELTVEL_OUT Bit Descriptions Bits [15:0] Description X-axis delta velocity data; high word; twos complement, 400 m/sec range, 0 m/sec = 0x0000; 1 LSB = 400 m/sec / 215 = ~12.208 mm/sec Y-Axis Delta Velocity (Y_DELTVEL_LOW, Y_DELTVEL_OUT) The Y_DELTVEL_LOW (see Table 79 and Table 80) and Y_DELTVEL_OUT (see Table 81 and Table 82) registers contain the delta velocity data for the y-axis. Addresses 0x54, 0x55 Default Not applicable Access R Table 84. Z_DELTVEL_LOW Bit Descriptions Bits [15:0] Description Z-axis delta angle data; low word Table 85. Z_DELTVEL_OUT Register Definitions Page 0x00 Addresses 0x56, 0x57 Default Not applicable Access R Table 79. Y_DELTVEL_LOW Register Definitions Table 86. Z_DELTVEL_OUT Bit Descriptions Page 0x00 Bits [15:0] Addresses 0x50, 0x51 Default Not applicable Access R Flash Backup No Table 80. Y_DELTVEL_LOW Bit Descriptions Bits [15:0] Flash Backup No Description Y-axis delta angle data; low word Rev. D | Page 28 of 43 Flash Backup No Description Z-axis delta velocity data; high word; twos complement, 400 m/sec range, 0 m/sec = 0x0000; 1 LSB = 400 m/sec / 215 = ~12.208 mm/sec Data Sheet ADIS16497 USER BIAS/SCALE ADJUSTMENT Table 87 and Table 88 show various numerical examples that demonstrate the format of the delta angle data in both 16-bit and 32-bit formats. Table 87. 16-Bit Delta Velocity Data Format Examples Velocity (m/sec) +400 x (215 - 1)/215 +400/214 +400/215 0 -400/215 -400/214 -400 Decimal +32,767 +2 +1 0 -1 -2 -32,768 Hex 0x7FFF 0x0002 0x0001 0x0000 0xFFFF 0xFFFE 0x8000 Binary 0111 1111 1110 1111 0000 0000 0000 0010 0000 0000 0000 0001 0000 0000 0000 0000 1111 1111 1111 1111 1111 1111 1111 1110 1000 0000 0000 0000 Table 88. 32-Bit Delta Angle Data Format Examples Velocity (m/sec) +400 x (231 - 1)/231 +400/230 +400/231 0 -400/231 -400/230 -400 Decimal +2,147,483,647 +2 +1 0 -1 -2 -2,147,483,648 Hex 0x7FFFFFFF 0x00000002 0x00000001 0x00000000 0xFFFFFFFF 0xFFFFFFFE 0x80000000 The signal chain of each inertial sensor (accelerometers, gyroscopes) includes application of unique correction formulas that come from extensive characterization of bias, sensitivity, alignment, and response to linear acceleration (gyroscopes) over a temperature range of -40C to +85C for the ADIS16497. These correction formulas are not accessible, but the user does have the opportunity to adjust the bias and the scale factor, for each sensor individually, through user accessible registers. These correction factors follow immediately after the factory derived correction formulas in the signal chain, which processes at a rate of 4250 Hz when using the internal sample clock (see fSM in Figure 22 and Figure 23). Gyroscope Scale Adjustment, X_GYRO_SCALE The X_GYRO_SCALE register (see Table 93 and Table 94) provides the user with the opportunity to adjust the scale factor for the x-axis gyroscopes. See Figure 45 for an illustration of how this scale factor influences the x-axis gyroscope data. Table 93. X_GYRO_SCALE Register Definitions Page 0x02 Reading the BURST_CMD register (see Table 89 and Table 90) starts the BRF. See Table 10, Table 11, Figure 5, and Figure 6 for more information on the BRF function. Table 89. BURST_CMD Register Definitions Page 0x00 Addresses 0x7C, 0x7D Default Not Applicable Access R Flash Backup No Default 0x0000 Access R/W Flash Backup Yes Table 94. X_GYRO_SCALE Bit Descriptions Bits [15:0] Burst Read Command, BURST_CMD Addresses 0x04, 0x05 Description X-axis gyroscope scale correction; twos complement, 0x0000 = unity gain, 1 LSB = 1 / 215 = ~0.003052% 1 + X_GYRO_SCALE X-AXIS GYRO FACTORY CALIBRATION AND FILTERING X_GYRO_OUT XG_BIAS_HIGH X_GYRO_LOW 15061-037 Delta Velocity Resolution XG_BIAS_LOW Figure 45. User Bias/Scale Adjustment Registers in Gyroscope Signal Path Table 90. BURST_CMD Bit Descriptions Bits [15:0] Gyroscope Scale Adjustment, Y_GYRO_SCALE Description Burst read command register Product Identification, PROD_ID The PROD_ID register (see Table 91 and Table 92) contains the numerical portion of the device number (16,497). See Figure 34 for an example of how to use a looping read of this register to validate the integrity of the communication. Table 91. PROD_ID Register Definitions Page 0x00 Addresses 0x7E, 0x7F Default 0x4071 Access R Table 92. PROD_ID Bit Descriptions Bits [15:0] Flash Backup Yes The Y_GYRO_SCALE register (see Table 95 and Table 96) allows the user to adjust the scale factor for the y-axis gyroscopes. This register influences the y-axis gyroscope measurements in the same manner that X_GYRO_SCALE influences the x-axis gyroscope measurements (see Figure 45). Table 95. Y_GYRO_SCALE Register Definitions Page 0x02 Addresses 0x06, 0x07 Default 0x0000 Access R/W Flash Backup Yes Table 96. Y_GYRO_SCALE Bit Descriptions Bits [15:0] Description Product identification = 0x4071 Rev. D | Page 29 of 43 Description Y-axis gyroscope scale correction; twos complement, 0x0000 = unity gain, 1 LSB = 1 / 215 = ~0.003052% ADIS16497 Data Sheet Gyroscope Scale Adjustment, Z_GYRO_SCALE The Z_GYRO_SCALE register (see Table 97 and Table 98) allows the user to adjust the scale factor for the z-axis gyroscopes. This register influences the z-axis gyroscope measurements in the same manner that X_GYRO_SCALE influences the x-axis gyroscope measurements (see Figure 45). Addresses 0x08, 0x09 Default 0x0000 Access R/W Flash Backup Yes Table 98. Z_GYRO_SCALE Bit Descriptions Bits [15:0] Bits [15:0] Description Y-axis accelerometer scale correction; twos complement, 0x0000 = unity gain, 1 LSB = 1 / 215 = ~0.003052% Accelerometer Scale Adjustment, Z_ACCL_SCALE The Z_ACCL_SCALE register (see Table 103 and Table 104) allows the user to adjust the scale factor for the z-axis accelerometers. This register influences the z-axis accelerometer measurements in the same manner that X_ACCL_SCALE influences the x-axis accelerometer measurements (see Figure 46). Table 97. Z_GYRO_SCALE Register Definitions Page 0x02 Table 102. Y_ACCL_SCALE Bit Descriptions Description Z-axis gyroscope scale correction; twos complement, 0x0000 = unity gain, 1 LSB = 1 / 215 = ~0.003052% Table 103. Z_ACCL_SCALE Register Definitions Page 0x02 Accelerometer Scale Adjustment, X_ACCL_SCALE The X_ACCL_SCALE register (see Table 99 and Table 100) allows the user to adjust the scale factor for the x-axis accelerometers. See Figure 46 for an illustration of how this scale factor influences the x-axis accelerometer data. Addresses 0x0E, 0x0F Default 0x0000 Access R/W Flash Backup Yes Table 104. Z_ACCL_SCALE Bit Descriptions Bits [15:0] Description Z-axis accelerometer scale correction; twos complement, 0x0000 = unity gain, 1 LSB = 1 / 215 = ~0.003052% Table 99. X_ACCL_SCALE Register Definitions Page 0x02 Addresses 0x0A, 0x0B Default 0x0000 Access R/W Gyroscope Bias Adjustment, XG_BIAS_LOW, XG_BIAS_HIGH Flash Backup Yes The XG_BIAS_LOW (see Table 105 and Table 106) and XG_ BIAS_HIGH (see Table 107 and Table 108) registers combine to allow the user to adjust the bias of the x-axis gyroscopes. The digital format examples in Table 25 also apply to the XG_BIAS_ HIGH register, and the digital format examples in Table 26 apply to the number that comes from combining the XG_BIAS_LOW and XG_BIAS_HIGH registers. See Figure 45 for an illustration of how these two registers combine and influence the x-axis gyroscope measurements. Table 100. X_ACCL_SCALE Bit Descriptions Bits [15:0] Description X-axis accelerometer scale correction; twos complement, 0x0000 = unity gain, 1 LSB = 1 / 215 = ~0.003052% 1 + X_ACCL_SCALE X_ACCL_OUT XA_BIAS_HIGH X_ACCL_LOW 15061-038 X-AXIS ACCL FACTORY CALIBRATION AND FILTERING XA_BIAS_LOW Figure 46. User Bias/Scale Adjustment Registers in Accelerometer Signal Path Table 105. XG_BIAS_LOW Register Definitions Page 0x02 Addresses 0x10, 0x11 Default 0x0000 Access R/W Flash Backup Yes Accelerometer Scale Adjustment, Y_ACCL_SCALE The Y_ACCL_SCALE register (see Table 101 and Table 102) allows the user to adjust the scale factor for the y-axis accelerometers. This register influences the y-axis accelerometer measurements in the same manner that X_ACCL_SCALE influences the x-axis accelerometer measurements (see Figure 46). Table 101. Y_ACCL_SCALE Register Definitions Page 0x02 Addresses 0x0C, 0x0D Default 0x0000 Access R/W Flash Backup Yes Table 106. XG_BIAS_LOW Bit Descriptions Bits [15:0] Description X-axis gyroscope offset correction, low word; twos complement, 0/sec = 0x0000, 1 LSB = KG / 216 (see Table 24) Table 107. XG_BIAS_HIGH Register Definitions Page 0x02 Addresses 0x12, 0x13 Default 0x0000 Access R/W Flash Backup Yes Table 108. XG_BIAS_HIGH Bit Descriptions Bits [15:0] Rev. D | Page 30 of 43 Description X-axis gyroscope offset correction, high word twos complement, 0/sec = 0x0000, 1 LSB = KG (see Table 24) Data Sheet ADIS16497 Table 115. ZG_BIAS_HIGH Register Definitions Gyroscope Bias Adjustment, YG_BIAS_LOW, YG_BIAS_HIGH The YG_BIAS_LOW (see Table 109 and Table 110) and YG_ BIAS_HIGH (see Table 111 and Table 112) registers combine to allow the user to adjust the bias of the y-axis gyroscopes. The digital format examples in Table 25 also apply to the YG_BIAS_ HIGH register, and the digital format examples in Table 26 apply to the number that comes from combining the YG_BIAS_LOW and YG_BIAS_HIGH registers. These registers influences the y-axis gyroscope measurements in the same manner that the XG_BIAS_LOW and XG_BIAS_HIGH registers influence the x-axis gyroscope measurements (see Figure 45). Table 109. YG_BIAS_LOW Register Definitions Page 0x02 Addresses 0x14, 0x15 Default 0x0000 Access R/W Flash Backup Yes Table 110. YG_BIAS_LOW Bit Descriptions Bits [15:0] Description Y-axis gyroscope offset correction, low word; twos complement, 0/sec = 0x0000, 1 LSB = 0.005/sec / 216 Page 0x02 Addresses 0x1A, 0x1B Default 0x0000 Access R/W Flash Backup Yes Table 116. ZG_BIAS_HIGH Bit Definitions Bits [15:0] Description Z-axis gyroscope offset correction, high word twos complement, 0/sec = 0x0000, 1 LSB = 0.005/sec Accelerometer Bias Adjustment, XA_BIAS_LOW, XA_BIAS_HIGH The XA_BIAS_LOW (see Table 117 and Table 118) and XA_ BIAS_HIGH (see Table 119 and Table 120) registers combine to allow the user to adjust the bias of the x-axis accelerometers. The digital format examples in Table 51 also apply to the XA_BIAS_HIGH register and the digital format examples in Table 52 apply to the number that comes from combining the XA_BIAS_LOW and XA_BIAS_HIGH registers. See Figure 46 for an illustration of how these two registers combine and influence the x-axis accelerometer measurements. Table 117. XA_BIAS_LOW Register Definitions Table 111. YG_BIAS_HIGH Register Definitions Page 0x02 Addresses 0x16, 0x17 Default 0x0000 Access R/W Page 0x02 Flash Backup Yes Addresses 0x1C, 0x1D Default 0x0000 Access R/W Flash Backup Yes Table 118. XA_BIAS_LOW Bit Descriptions Table 112. YG_BIAS_HIGH Bit Descriptions Bits [15:0] Bits [15:0] Description Y-axis gyroscope offset correction, high word; twos complement, 0/sec = 0x0000, 1 LSB = 0.005/sec Table 119. XA_BIAS_HIGH Register Definitions Gyroscope Bias Adjustment, ZG_BIAS_LOW, ZG_BIAS_HIGH The ZG_BIAS_LOW (see Table 113 and Table 114) and ZG_ BIAS_HIGH (see Table 115 and Table 116) registers combine to allow the user to adjust the bias of the z-axis gyroscopes. The digital format examples in Table 25 also apply to the ZG_BIAS_ HIGH register, and the digital format examples in Table 26 apply to the number that comes from combining the ZG_BIAS_LOW and ZG_BIAS_HIGH registers. These registers influence the z-axis gyroscope measurements in the same manner that the XG_BIAS_LOW and XG_BIAS_HIGH registers influence the xaxis gyroscope measurements (see Figure 45). Table 113. ZG_BIAS_LOW Register Definitions Page 0x02 Addresses 0x18, 0x19 Default 0x0000 Access R/W Flash Backup Yes Table 114. ZG_BIAS_LOW Bit Descriptions Bits [15:0] Description X-axis accelerometer offset correction, low word, twos complement, 0 g = 0x0000, 1 LSB = 1.25 mg / 216 Description Z-axis gyroscope offset correction, low word; twos complement, 0/sec = 0x0000, 1 LSB = 0.005/sec / 216 Page 0x02 Addresses 0x1E, 0x1F Default 0x0000 Access R/W Flash Backup Yes Table 120. XA_BIAS_HIGH Bit Descriptions Bits [15:0] Description X-axis accelerometer offset correction, high word, twos complement, 0 g = 0x0000, 1 LSB = 1.25 mg Accelerometer Bias Adjustment, YA_BIAS_LOW, YA_BIAS_HIGH The YA_BIAS_LOW (see Table 121 and Table 122) and YA_ BIAS_HIGH (see Table 123 and Table 124) registers combine to allow the user to adjust the bias of the y-axis accelerometers. The digital format examples in Table 51 also apply to the YA_BIAS_HIGH register, and the digital format examples in Table 52 apply to the number that comes from combining the YA_BIAS_LOW and YA_BIAS_HIGH registers. These registers influence the y-axis accelerometer measurements in the same manner that the XA_BIAS_LOW and XA_BIAS_HIGH registers influence the x-axis accelerometer measurements (see Figure 46). Rev. D | Page 31 of 43 ADIS16497 Data Sheet Table 121. YA_BIAS_LOW Register Definitions Page 0x02 Addresses 0x20, 0x21 Default 0x0000 Access R/W SCRATCH REGISTERS, USER_SCR_X Flash Backup Yes Table 122. YA_BIAS_LOW Bit Descriptions Bits [15:0] Description Y-axis accelerometer offset correction, low word, twos complement, 0 g = 0x0000, 1 LSB = 1.25 mg / 216 Addresses 0x22, 0x23 Default 0x0000 Access R/W Flash Backup Yes Addresses 0x74, 0x75 Default 0x0000 Access R/W Flash Backup Yes Table 130. USER_SCR_1 Bit Descriptions Bits [15:0] Table 124. YA_BIAS_HIGH Bit Descriptions Bits [15:0] Table 129. USER_SCR_1 Register Definitions Page 0x02 Table 123. YA_BIAS_HIGH Register Definitions Page 0x02 The USER_SCR_1 (see Table 129 and Table 130), USER_SCR_2 (see Table 131 and Table 132), USER_SCR_3 (see Table 133 and Table 134), and the USER_SCR_4 (see Table 135 and Table 136) registers provide four locations for the user to store information. Description Y-axis accelerometer offset correction, high word, twos complement, 0 g = 0x0000, 1 LSB = 1.25 mg Description User defined Table 131. USER_SCR_2 Register Definitions Page 0x02 Accelerometer Bias Adjustment, ZA_BIAS_LOW, ZA_BIAS_HIGH The ZA_BIAS_LOW (see Table 125 and Table 126) and ZA_ BIAS_HIGH (see Table 127 and Table 128) registers combine to allow the user to adjust the bias of the z-axis accelerometers. The digital format examples in Table 51 also apply to the ZA_BIAS_ HIGH register and the digital format examples in Table 52 apply to the number that comes from combining the ZA_BIAS_LOW and ZA_BIAS_HIGH registers. These registers influence the zaxis accelerometer measurements in the same manner that the XA_BIAS_LOW and XA_BIAS_HIGH registers influence the xaxis accelerometer measurements (see Figure 46). Addresses 0x76, 0x77 Default 0x0000 Access R/W Flash Backup Yes Table 132. USER_SCR_2 Bit Descriptions Bits [15:0] Description User defined Table 133. USER_SCR_3 Register Definitions Page 0x02 Addresses 0x78, 0x79 Default 0x0000 Access R/W Flash Backup Yes Table 134. USER_SCR_3 Bit Descriptions Table 125. ZA_BIAS_LOW Register Definitions Bits [15:0] Page 0x02 Table 135. USER_SCR_4 Register Definitions Addresses 0x24, 0x25 Default 0x0000 Access R/W Flash Backup Yes Description User defined Table 126. ZA_BIAS_LOW Bit Descriptions Page 0x02 Bits [15:0] Table 136. USER_SCR_4 Bit Descriptions Description Z-axis accelerometer offset correction, low word, twos complement, 0 g = 0x0000, 1 LSB = 1.25 mg / 216 Bits [15:0] Addresses 0x7A, 0x7B Default 0x0000 Access R/W Flash Backup Yes Description User defined Table 127. ZA_BIAS_HIGH Register Definitions Page 0x02 Addresses 0x26, 0x27 Default 0x0000 Access R/W Flash Backup Yes Table 128. ZA_BIAS_HIGH Bit Descriptions Bits [15:0] Description Z-axis accelerometer offset correction, high word, twos complement, 0 g = 0x0000, 1 LSB = 1.25 mg FLASH MEMORY ENDURANCE COUNTER, FLSHCNT_LOW, FLSHCNT_HIGH The FLSHCNT_LOW (see Table 137 and Table 138) and FLSHCNT_HIGH (see Table 139 and Table 140) registers combine to provide a 32-bit, binary counter that tracks the number of flash memory write cycles. In addition to the number of write cycles, the flash memory has a finite service lifetime, which depends on the junction temperature. Figure 47 provides guidance for estimating the retention life for the flash memory at specific junction temperatures. The junction temperature is approximately 7C above the case temperature. Rev. D | Page 32 of 43 Data Sheet ADIS16497 Table 137. FLSHCNT_LOW Register Definitions Software Reset Page 0x02 Select Page 3 (DIN = 0x8003) and then set GLOB_CMD, Bit 7 = 1 (DIN = 0x8280, then DIN = 0x8300) to initiate a reset in the operation of the ADIS16497. This reset removes all data, initializes all registers from their flash settings, and restarts data sampling and processing. This function provides a firmware alternative to providing a low pulse on the RST pin (see Table 6, Pin 8). Addresses 0x7C, 0x7D Default Not applicable Access R Flash Backup Yes Table 138. FLSHCNT_LOW Bit Descriptions Bits [15:0] Description Flash memory write counter, low word Table 139. FLSHCNT_HIGH Register Definitions Clear User Calibration Page 0x02 Select Page 3 (DIN = 0x8003) and then set GLOB_CMD, Bit 6 = 1 (DIN = 0x8240, then DIN = 0x8300) to clear all user bias/scale adjustments for each accelerometer and gyroscope. This command writes 0x0000 to the following registers: X_GYRO_SCALE, Y_GYRO_SCALE, Z_GYRO_SCALE, X_ACCL_SCALE, Y_ ACCL_ SCALE, Z_ACCL_SCALE, XG_BIAS_LOW, XG_BIAS_HIGH, YG_BIAS_LOW, YG_BIAS_HIGH, ZG_BIAS_LOW, ZG_BIAS_HIGH, XA_BIAS_LOW, XA_BIAS_HIGH, YA_BIAS_LOW, YA_BIAS_ HIGH, ZA_BIAS_LOW, and ZA_BIAS_HIGH. Addresses 0x7E, 0x7F Default Not applicable Access R Flash Backup Yes Table 140. FLSHCNT_HIGH Bit Descriptions Bits [15:0] Description Flash memory write counter, high word 600 RETENTION (Years) Flash Memory Update Select Page 3 (DIN = 0x8003) and then set GLOB_CMD, Bit 3 = 1 (DIN = 0x8208, DIN = 0x8300) to initiate a manual flash update. SYS_E_FLAG, Bit 6 (see Table 18) identifies success (0) or failure (1) in completing this process. 450 300 0 30 40 55 70 85 100 125 JUNCTION TEMPERATURE (C) 135 150 15061-039 150 Figure 47. Flash Memory Retention GLOBAL COMMANDS, GLOB_CMD The GLOB_CMD register (see Table 141 and Table 142) provides trigger bits for several operations. Write a 1 to the appropriate bit in GLOB_CMD to start a particular function. Note that the user must not poll the status registers while waiting for the update to complete because the serial port is disabled during the update. Rather, the user must either wait the prescribed amount of time found in Table 3 or wait for the data ready indicator pin to begin toggling. On Demand Self Test (ODST) Select Page 3 (DIN = 0x8003) and then set GLOB_CMD, Bit 1 = 1 (DIN = 0x8202, then DIN = 0x8300) to run the ODST routine, which executes the following steps: 1. 2. Table 141. GLOB_CMD Register Definitions Page 0x03 Addresses 0x02, 0x03 Default Not applicable Access W Flash Backup No 3. 4. 5. Table 142. GLOB_CMD Bit Descriptions Bits [15:8] 7 6 [5:4] 3 2 1 0 Description Not used Software reset Clear user calibration Not used Flash memory update Not used Self test Bias correction update 6. 7. Measure the output on each sensor. Activate an internal force on the mechanical elements of each sensor, which simulates the force associated with actual inertial motion. Measure the output response on each sensor. Deactivate the internal force on each sensor. Calculate the difference between the force on and normal operating conditions (force off). Compare the difference with internal pass/fail criteria. Report the pass/fail results for each sensor in DIAG_STS (see Table 20) and the overall pass/fail flag in SYS_E_FLAG, Bit 5 (see Table 18). False positive results are possible when the executing the ODST while the device is in motion. Note that the user must not poll the status registers while waiting for the test to complete. Rather, the user must either wait the prescribed amount of time found in Table 3 or wait for the data ready indicator pin to begin toggling. Rev. D | Page 33 of 43 ADIS16497 Data Sheet Bias Correction Update Data Ready Indicator Select Page 3 (DIN = 0x8003) and set GLOB_CMD, Bit 0 = 1 (DIN = 0x8201, then DIN = 0x8300) to update the user offset registers with the correction factors of the continuous bias estimation (CBE) (see Table 152). Ensure that the inertial platform is stable during the entire average time for optimal bias estimates. AUXILIARY I/O LINE CONFIGURATION, FNCTIO_CTRL The FNCTIO_CTRL register (see Table 143 and Table 144) provides configuration control for each I/O pin (DIO1, DIO2, DIO3, and DIO4). Each DIOx pin supports only one function at a time. When a single pin has two assignments, the enable bit for the lower priority function automatically resets to zero (disabling the lower priority function). The order of priority is as follows, from highest priority to lowest priority: data ready, sync clock input, and general-purpose. The ADIS16497 can take up to 20 ms to execute a write command to the FNCTIO_CTRL register. During this time, the operational state and the contents of the register remain unchanged, but the SPI interface supports normal communication (for accessing other registers). Table 143. FNCTIO_CTRL Register Definitions Page 0x03 Addresses 0x06, 0x07 Default 0x000D Access R/W Flash Backup Yes Table 144. FNCTIO_CTRL Bit Descriptions Bits [15:9] 8 7 6 [5:4] 3 2 [1:0] Description Not used Sync clock mode 1 = PPS 0 = sync Sync clock input enable 1 = enabled 0 = disabled Sync clock input polarity 1 = rising edge 0 = falling edge Sync clock input line selection 00 = DIO1 01 = DIO2 10 = DIO3 11 = DIO4 Data ready enable: 1 = enabled 0 = disabled Data ready polarity: 1 = positive 0 = negative Data ready line selection 00 = DIO1 01 = DIO2 10 = DIO3 11 = DIO4 The FNCTIO_CTRL, Bits[3:0] provide three configuration options for the data ready function: on/off, polarity, and DIOx line. The primary purpose this signal is to drive the interrupt control line of an embedded processor, which can synchronize data collection and minimize latency. The data ready indicator is useful to determine if the controller inside the ADIS16497 is busy with a task (for example, a flash memory update) because data ready stops togging while these tasks are performed and resumes on completion. The factory default assigns DIO2 as a positive polarity, data ready signal, which means the data in the output registers is valid when the DIO2 line is high (see Figure 29). This configuration works well when DIO2 drives an interrupt service pin that activates on a low to high pulse. Use the following sequence to change this assignment to DIO3 with negative polarity: 1. 2. Select Page 3 (DIN = 0x8003). Set FNCTIO_CTRL, Bits[3:0] = 1000 (DIN = 0x860A, then DIN = 0x8700). The timing jitter on the data ready signal is typically within 1.4 s. When using DIO1 to support the data ready function, this signal can experience premature data ready pulses during the ADIS16497 start-up, However, these pulses do not indicate that data production has started. If it is necessary to use DIO1 for this function, use it in conjunction with a delay or other control mechanism to prevent premature data acquisition activity during the start-up process. Input Sync/Clock Control The FNCTIO_CTRL, Bits[8:4] provide several configuration options for using one of the DIOx lines as an external clock signal and for controlling inertial sensor data collection and processing. For example, use the following sequence to establish DIO4 as a positive polarity, input clock pin that operates in sync mode and preserves the factory default setting for the data ready function: 1. 2. 3. Select Page 3 (DIN = 0x8003). Set FNCTIO_CTRL, Bits[7:0] = 0xFD (DIN = 0x86FD). Set FNCTIO_CTRL, Bits[15:8] = 0x00 (DIN = 0x8700). In sync mode, the ADIS16497 disables its internal sample clock, and the frequency of the external clock signal establishes the rate of data collection and processing (fSM in Figure 22 and Figure 23). When using the PPS mode (FNCTIO_CTRL, Bit 8 = 1) the rate of data collection and production (fSM) is equal to the product of the external clock frequency and scale factor (KECSF) in the SYNC_SCALE register (see Table 154). Rev. D | Page 34 of 43 Data Sheet ADIS16497 GENERAL-PURPOSE I/O CONTROL, GPIO_CTRL Point of Percussion When FNCTIO_CTRL does not configure a DIOx pin, the GPIO_CTRL register (see Table 145 and Table 146) provides user controls for general-purpose use of the DIOx pins. GPIO_CTRL, Bits[3:0], provide I/O assignment controls for each line. When the DIOx lines are inputs, monitor their level by reading GPIO_CTRL, Bits[7:4]. When the DIOx lines are used as outputs, set their level by writing to GPIO_CTRL, Bits[7:4]. CONFIG, Bit 6 offers a point of percussion alignment function that maps the accelerometer sensors to the corner of the package identified in Figure 48. To activate this feature, select Page 3 (DIN = 0x8003), then set CONFIG, Bit 6 = 1 (DIN = 0x8A40, then DIN = 0x8B00). Table 145. GPIO_CTRL Register Definitions Page 0x03 1 Addresses 0x08, 0x09 Default 0x00X0 Access R/W POINT OF PERCUSSION ALIGNMENT REFERENCE POINT. SEE CONFIG[6]. Flash Backup Yes Figure 48. Point of Percussion Reference Point 1 0 1 LINEAR ACCELERATION ON EFFECT ON GYROSCOPE BIAS The ADIS16497 includes first-order compensation for the linear g effect in the gyroscopes, which uses the following model: Table 146. GPIO_CTRL Bit Descriptions 1 2 PIN 1 1 The GPIO_CTRL, Bits[7:4] reflect the logic levels on the DIOx lines and do not have a default setting. Bits [15:8] 7 6 5 4 3 PIN 23 15061-040 For example, use the following sequence to set DIO1 and DIO3 as high and low output lines, respectively, and set DIO2 and DIO4 as input lines. Select Page 3 (DIN = 0x8003) and set GPIO_ CTRL, Bits[7:0] = 0x15 (DIN = 0x8815, then DIN = 0x8900). Description Don't care General-Purpose I/O Line 4 (DIO4) data level General-Purpose I/O Line 3 (DIO3) data level General-Purpose I/O Line 2 (DIO2) data level General-Purpose I/O Line 1 (DIO1) data level General-Purpose I/O Line 4 (DIO4) direction control (1 = output, 0 = input) General-Purpose I/O Line 3 (DIO3) direction control (1 = output, 0 = input) General-Purpose I/O Line 2 (DIO2) direction control (1 = output, 0 = input) General-Purpose I/O Line 1 (DIO1) direction control (1 = output, 0 = input) LG11 LG12 LG13 AX XC XPC YC LG21 LG22 LG23 AY YPC LG ZC 31 LG32 LG33 AZ ZPC The linear g correction factors, LGXY, apply correction for linear acceleration in all three directions to the data path of each gyroscope (XPC, YPC, and ZPC) at the rate of the data samples (4250 SPS when using the internal clock). CONFIG, Bit 7, provides an on/off control for this compensation. The factory default value for this bit activates this compensation. The GPIO_CTRL, Bits[7:4] reflect the logic levels on the DIOx lines and do not have a default setting. To turn it off, select Page 3 (DIN = 0x8003) and set CONFIG, Bit 7 = 0 (DIN = 0x8A40, then DIN = 0x8B00). This command sequence also preserves the default setting for the point of percussion alignment function (on). MISCELLANEOUS CONFIGURATION, CONFIG DECIMATION FILTER, DEC_RATE The CONFIG register (see Table 147 and Table 148) provides configuration options for the linear g compensation in the gyroscopes (on/off) and the point of percussion alignment for the accelerometers (on/off). The DEC_RATE register (see Table 149 and Table 150) provides user control for the final filter stage (see Figure 25), which averages and decimates the accelerometers and gyroscopes data, and extends the time that the delta angle and delta velocity track between each update. The output sample rate is equal to 4250/(DEC_RATE + 1). For example, select Page 3 (DIN = 0x8003), and set DEC_RATE = 0x2A (DIN = 0x8C2A, then DIN = 0x8D00) to reduce the output sample rate to ~98.8 SPS (4250 / 43). Table 147. CONFIG Register Definitions Page 0x03 Addresses 0x0A, 0x0B Default 0x00C0 Access R/W Flash Backup Yes Table 148. CONFIG Bit Descriptions Bits [15:8] 7 6 [5:0] Description Not used Linear g compensation for gyroscopes (1 = enabled) Point of percussion alignment (1 = enabled) Not used Table 149. DEC_RATE Register Definitions Page 0x03 Rev. D | Page 35 of 43 Addresses 0x0C, 0x0D Default 0x0000 Access R/W Flash Backup Yes ADIS16497 Data Sheet SCALING THE INPUT CLOCK (PPS MODE), SYNC_SCALE Table 150. DEC_RATE Bit Descriptions Bits [15:11] [10:0] Description Don't care Decimation rate, binary format, maximum = 4249 CONTINUOUS BIAS ESTIMATION (CBE), NULL_CNFG The NULL_CNFG register (see Table 151 and Table 152) provides the configuration controls for the CBE, which associates with the bias correction update command in GLOB_CMD, Bit 0 (see Table 142). NULL_CNFG, Bits[3:0], establishes the total average time (tA) for the bias estimates and NULL_CNFG, Bits[13:8], provide on/off controls for each sensor. The factory default configuration for NULL_CNFG enables the bias null command for the gyroscopes, disables the bias null command for the accelerometers, and sets the average time to ~15.42 seconds. tB = 2TBC/4250 = 210/4250 = ~0.241 seconds tA = 64 x tB = 64 x 0.241 = 15.42 seconds where: tB is the time base. tA is the averaging time. The PPS mode (FNCTIO_CTRL, Bit 8 = 1, see Table 144) supports the use of an input sync frequency that is slower than the data sample rates of the inertial sensors. This mode supports a frequency range of 1 Hz to 128 Hz for the input sync mode. In this mode, the data sample rate is equal to the product of the value in the SYNC_SCALE register (see Table 153 and Table 154) and the input sync frequency. For example, the following command sequence sets the data collection and processing rate (fSM in Figure 22 and Figure 23) to 4000 Hz (SYNC_SCALE = 0x0FA0) when using a 1 Hz signal on the DIO3 line as the external clock input, and preserves the factory default configuration for the data ready signal: 1. 2. 3. 4. 5. Select Page 3 (DIN = 0x8003). Set SYNC_SCALE, Bits[7:0] = 0xA0 (DIN = 0x90A0). Set SYNC_SCALE, Bits[15:8] = 0x0F (DIN = 0x910F). Set FNCTIO_CTRL, Bits[7:0] = 0xFD (DIN = 0x86ED). Set FNCTIO_CTRL, Bits[15:8] = 0x00 (DIN = 0x8701). Note that the data ready indicator pin does not begin to toggle until at least two external clock edges (with valid time period between them) are detected by the ADIS16497. When a sensor bit in NULL_CNFG is active (equal to 1), setting GLOB_CMD, Bit 0 = 1 (DIN sequence: 0x8003, 0x8201, 0x8300) causes its bias correction register to automatically update with a value that corrects for its present bias error (from the CBE). For example, setting NULL_CNFG, Bit 8 equal to 1 causes an update in the XG_BIAS_LOW (see Table 106) and XG_BIAS_HIGH (see Table 108) registers. Table 153. SYNC_SCALE Register Definitions Page 0x03 Addresses 0x10, 0x11 Default 0x109A Access R/W Flash Backup Yes Table 154. SYNC_SCALE Bit Descriptions Bits [15:0] Description External clock scale factor (KECSF), binary format Table 151. NULL_CNFG Register Definitions Page 0x03 Addresses 0x0E, 0x0F Default 0x070A Access R/W Flash Backup Yes Measurement Range Identifier, RANG_MDL The RANG_MDL register (see Table 155 and Table 156) provides a convenient method for identifying the model (and gyroscope measurement range) of the ADIS16497. Table 152. NULL_CNFG Bit Descriptions Bits [15:14] 13 12 11 10 9 8 [7:4] [3:0] Description Not used Z-axis acceleration bias correction enable (1 = enabled) Y-axis acceleration bias correction enable (1 = enabled) X-axis acceleration bias correction enable (1 = enabled) Z-axis gyroscope bias correction enable (1 = enabled) Y-axis gyroscope bias correction enable (1 = enabled) X-axis gyroscope bias correction enable (1 = enabled) Not used Time base control (TBC), range: 0 to 13 (default = 10); tB = 2TBC/4250, time base; tA = 64 x tB, average time Table 155. RANG_MDL Register Definitions1 Page 0x03 1 Addresses 0x12, 0x13 Default N/A Access R N/A means not applicable. Table 156. RANG_MDL Bit Descriptions Bits [15:3] [3:0] Rev. D | Page 36 of 43 Description Not used 0011 = ADIS16497-1 (125/sec) 0111 = ADIS16497-2 (450/sec) 1111 = ADIS16497-3 (2000/sec) Flash Backup N/A Data Sheet ADIS16497 Table 160. FILTR_BNK_1 Bit Descriptions FIR FILTERS FIR Filters Control, FILTR_BNK_0, FILTR_BNK_1 The FILTR_BNK_0 (see Table 157 and Table 158) and FILTR_ BNK_1 (see Table 159 and Table 160) registers provide the configuration controls for the FIR filter bank in the signal chain of each sensor (see Figure 25). These registers provide on/off control for the FIR bank for each inertial sensor, along with the FIR bank (A, B, C, or D) that each sensor uses. Table 157. FILTR_BNK_0 Register Definitions Page 0x03 Addresses 0x16, 0x17 Default 0x0000 Access R/W Flash Backup Yes Table 158. FILTR_BNK_0 Bit Descriptions Bits 15 14 [13:12] 11 [10:9] 8 [7:6] 5 [4:3] 2 [1:0] Description (Default = 0x0000) Don't care Y-axis accelerometer filter enable (1 = enabled) Y-axis accelerometer filter bank selection 00 = Bank A 01 = Bank B 10 = Bank C 11 = Bank D X-axis accelerometer filter enable (1 = enabled) X-axis accelerometer filter bank selection 00 = Bank A 01 = Bank B 10 = Bank C 11 = Bank D Z-axis gyroscope filter enable (1 = enabled) Z-axis gyroscope filter bank selection 00 = Bank A 01 = Bank B 10 = Bank C 11 = Bank D Y-axis gyroscope filter enable (1 = enabled) Y-axis gyroscope filter bank selection 00 = Bank A 01 = Bank B 10 = Bank C 11 = Bank D X-axis gyroscope filter enable (1 = enabled) X-axis gyroscope filter bank selection 00 = Bank A 01 = Bank B 10 = Bank C 11 = Bank D Bits [15:3] 2 [1:0] Description Don't care Z-axis accelerometer filter enable (1 = enabled) Z-axis accelerometer filter bank selection: 00 = Bank A 01 = Bank B 10 = Bank C 11 = Bank D FIR Filter Bank Memory Maps The ADIS16497 provides four FIR filter banks to configure and select for each individual inertial sensor using the FILTR_BNK_0 (see Table 158) and FILTR_BNK_1 (see Table 160) registers. Each FIR filter bank (A, B, C, and D) has 120 taps that consume two pages of memory. The coefficient associated with each tap, in each filter bank, has its own dedicated register that uses a 16-bit, twos complement format. The FIR filter has unity gain when the sum of all of the coefficients is equal to 32,768. For filter designs that require less than 120 taps, write 0x0000 to all unused registers to eliminate the latency associated with that particular tap. FIR Filter Bank A, FIR_COEF_A000 to FIR_COEF_A119 Table 161. FIR Filter Bank A Memory Map Page 5 5 5 5 5 PAGE_ID 0x05 0x05 0x05 0x05 0x05 Addresses 0x00, 0x01 0x02 to 0x07 0x08, 0x09 0x0A, 0x0B 0x0C to 0x7D 5 6 6 6 6 6 0x05 0x06 0x06 0x06 0x06 0x06 0x7E, 0x07F 0x00, 0x01 0x02 to 0x07 0x08, 0x09 0x0A, 0x0B 0x0C to 0x7D 6 0x06 0x7E, 0x7F Register PAGE_ID Not used FIR_COEF_A000 FIR_COEF_A001 FIR_COEF_A002 to FIR_COEF_A058 FIR_COEF_A059 PAGE_ID Not used FIR_COEF_A060 FIR_COEF_A061 FIR_COEF_A062 to FIR_COEF_A118 FIR_COEF_A119 Table 162 and Table 163 provide detailed register and bit definitions for one of the FIR coefficient registers in Bank A, FIR_COEF_ A071. Table 164 provides a configuration example, which sets this register to a decimal value of -169 (0xFF57). Table 162. FIR_COEF_A071 Register Definitions Page 0x06 Addresses 0x1E, 0x1F Default Not applicable Access R/W Flash Backup Yes Table 159. FILTR_BNK_1 Register Definitions Page 0x03 Addresses 0x18, 0x19 Default 0x0000 Access R/W Flash Backup Yes Table 163. FIR_COEF_A071 Bit Descriptions Bits [15:0] Rev. D | Page 37 of 43 Description FIR Bank A, Coefficient 71, twos complement ADIS16497 Data Sheet Table 164. Configuration Example, FIR Coefficient FIR Filter Bank D, FIR_COEF_D000 to FIR_COEF_D119 Description Select Page 6 FIR_COEF_A071, Bits[7:0] = 0x57 FIR_COEF_A071, Bits[15:8] = 0xFF Table 167. Filter Bank D Memory Map FIR Filter Bank B, FIR_COEF_B000 to FIR_COEF_B119 Table 165. Filter Bank B Memory Map Page 7 7 7 7 7 PAGE_ID 0x07 0x07 0x07 0x07 0x07 Addresses 0x00, 0x01 0x02 to 0x07 0x08, 0x09 0x0A, 0x0B 0x0C to 0x7D 7 8 8 8 8 8 0x07 0x08 0x08 0x08 0x08 0x08 0x7E, 0x07F 0x00, 0x01 0x02 to 0x07 0x08, 0x09 0x0A, 0x0B 0x0C to 0x7D 8 0x08 0x7E, 0x7F Register PAGE_ID Not used FIR_COEF_B000 FIR_COEF_B001 FIR_COEF_B002 to FIR_COEF_B058 FIR_COEF_B059 PAGE_ID Not used FIR_COEF_B060 FIR_COEF_B061 FIR_COEF_B062 to FIR_COEF_B118 FIR_COEF_B119 PAGE_ID 0x09 0x09 0x09 0x09 0x09 Addresses 0x00, 0x01 0x02 to 0x07 0x08, 0x09 0x0A, 0x0B 0x0C to 0x7D 9 10 10 10 10 10 0x09 0x0A 0x0A 0x0A 0x0A 0x0A 0x7E, 0x07F 0x00, 0x01 0x02 to 0x07 0x08, 0x09 0x0A, 0x0B 0x0C to 0x7D 10 0x0A 0x7E, 0x7F Register PAGE_ID Not used FIR_COEF_C000 FIR_COEF_C001 FIR_COEF_C002 to FIR_COEF_C058 FIR_COEF_C059 PAGE_ID Not used FIR_COEF_C060 FIR_COEF_C061 FIR_COEF_C062 to FIR_COEF_C118 FIR_COEF_C119 Addresses 0x00, 0x01 0x02 to 0x07 0x08, 0x09 0x0A, 0x0B 0x0C to 0x7D 11 12 12 12 12 12 0x0B 0x0C 0x0C 0x0C 0x0C 0x0C 0x7E, 0x07F 0x00, 0x01 0x02 to 0x07 0x08, 0x09 0x0A, 0x0B 0x0C to 0x7D 12 0x0C 0x7E, 0x7F Register PAGE_ID Not used FIR_COEF_D000 FIR_COEF_D001 FIR_COEF_D002 to FIR_COEF_D058 FIR_COEF_D059 PAGE_ID Not used FIR_COEF_D060 FIR_COEF_D061 FIR_COEF_D062 to FIR_COEF_D118 FIR_COEF_D119 The FIR filter banks have factory programmed filter designs that are all low-pass filters that have unity dc gain. Table 168 provides a summary of each filter design, and Figure 49 shows the frequency response characteristics. The phase delay is equal to 1/2 of the total number of taps. Table 168. FIR Filter Descriptions, Default Configuration FIR Filter Bank A B C D Taps 120 120 32 32 -3 dB Frequency (Hz) 300 100 300 100 0 -10 -20 MAGNITUDE (dB) Page 9 9 9 9 9 PAGE_ID 0x0B 0x0B 0x0B 0x0B 0x0B Default Filter Performance FIR Filter Bank C, FIR_COEF_C000 to FIR_COEF_C119 Table 166. Filter Bank C Memory Map Page 11 11 11 11 11 B D A NO FIR FILTERING C -30 -40 -50 -60 -70 -80 -90 -100 0 200 400 600 800 1000 FREQUENCY (Hz) Figure 49. FIR Filter Frequency Response Curves Rev. D | Page 38 of 43 1200 15061-041 DIN Command 0x8006 0x9E57 0x9FFF Data Sheet ADIS16497 FIRMWARE REVISION, FIRM_REV The FIRM_DM register (see Table 171 and Table 172) contains the month and day of the factory configuration date. Register FIRM_DM, Bits[15:12] and Register FIRM_DM, Bits[11:8] contain digits that represent the month of the factory configuration in a binary coded decimal (BCD) format. For example, November is the 11th month in a year and is represented by Register FIRM_DM, Bits[15:8] = 0x11. Register FIRM_DM, Bits[7:4] and Register FIRM_DM, Bits[3:0], contain digits that represent the day of factory configuration in a BCD format. For example, the 27th day of the month is represented by FIRM_DM, Bits[7:0] = 0x27. Addresses 0x78, 0x79 Default Not applicable Access R Bits [15:12] [11:8] [7:4] [3:0] Description Factory configuration year BCD code, thousands digit, numerical format = 4-bit binary, range = 0 to 9 Factory configuration year BCD code, hundreds digit, numerical format = 4-bit binary, range = 0 to 9 Factory configuration year BCD code, tens digit, numerical format = 4-bit binary, range = 0 to 3 Factory configuration year BCD code, ones digit, numerical format = 4-bit binary, range = 0 to 9 BOOT REVISION NUMBER, BOOT_REV Table 175. BOOT_REV Register Definitions Table 169. FIRM_REV Register Definitions Page 0x03 Table 174. FIRM_Y Bit Descriptions Flash Backup Yes Page 0x03 Addresses 0x7E, 0x7F Default Not applicable Access R Table 170. FIRM_REV Bit Descriptions Table 176. BOOT_REV Bit Definitions Bits [15:12] Bits [15:8] [7:0] [11:8] [7:4] [3:0] Description Firmware revision BCD code, tens digit, numerical format = 4-bit binary, range = 0 to 9 Firmware revision BCD code, ones digit, numerical format = 4-bit binary, range = 0 to 9 Firmware revision BCD code, tenths digit, numerical format = 4-bit binary, range = 0 to 9 Firmware revision BCD code, hundredths digit, numerical format = 4-bit binary, range = 0 to 9 Table 171. FIRM_DM Register Definitions Page 0x03 Addresses 0x7A, 0x7B Default Not applicable Access R Flash Backup Yes Table 172. FIRM_DM Bit Descriptions Bits [15:12] [11:8] [7:4] [3:0] Description Factory configuration month BCD code, tens digit, numerical format = 4-bit binary, range = 0 to 2 Factory configuration month BCD code, ones digit, numerical format = 4-bit binary, range = 0 to 9 Factory configuration day BCD code, tens digit, numerical format = 4-bit binary, range = 0 to 3 Factory configuration day BCD code, ones digit, numerical format = 4-bit binary, range = 0 to 9 FIRMWARE REVISION YEAR, FIRM_Y The FIRM_Y register (see Table 173 and Table 174) contains the year of the factory configuration date. For example, the year 2013 is represented by FIRM_Y = 0x2013. Addresses 0x7C, 0x7D Default Not applicable Access R Description Binary, major revision number Binary, minor revision number CONTINUOUS SRAM TESTING This device employs a CRC function on the SRAM memory blocks that contain the program code (CODE_SIGTR_xxx) and the calibration coefficients (CAL_DRVTN_xxx). This process operates in the background and generates real-time, 32-bit CRC values for the program code and calibration coefficients, respectively. At the conclusion of each cycle, the processor writes these calculated values in the CAL_DRVTN_xxx and CODE_DRVTN_xxx registers (see Table 183, Table 184, Table 190, and Table 192) and compares them with the signature values, which reflect the state of these memory locations at the time of factory configuration. When the calculation results do not match the signature values, Register SYS_E_FLAG, Bit 2 increases to a 1. The respective signature values are available for user access through the CAL_SIGTR_xxx and CODE_SIGTR_xxx registers (see Table 177, Table 178, Table 179, Table 180, Table 186, and Table 188). The following conditions must be met for Register SYS_E_FLAG, Bit 2 to remain at the zero level: Table 173. FIRM_Y Register Definitions Page 0x03 Flash Backup Yes Flash Backup Yes Rev. D | Page 39 of 43 CAL_SIGTR_LWR = CAL_DRVTN_LWR CAL_SIGTR_UPR = CAL_DRVTN_UPR CODE_SIGTR_LWR = CODE_DRVTN_LWR CODE_SIGTR_UPR = CODE_DRVTN_UPR ADIS16497 Data Sheet Signature CRC, Calibration Values, CAL_SIGTR_LWR Signature CRC, Program Code, CODE_SIGTR_UPR Table 177. CAL_SIGTR_LWR Register Definitions Page 0x04 Addresses 0x04, 0x05 Default Not applicable Access R Flash Backup Yes Table 178. CAL_SIGTR_LWR Bit Descriptions Bits [15:0] Description Factory programmed CRC value for the program code, low word Signature CRC, Calibration Values, CAL_SIGTR_UPR Addresses 0x06, 0x07 Default Not applicable Access R Flash Backup Yes Table 180. CAL_SIGTR_UPR Bit Descriptions Bits [15:0] Page 0x04 Addresses 0x0E, 0x0F Default Not applicable Access R Flash Backup Yes Table 188. CODE_SIGTR_UPR Bit Descriptions Bits [15:0] Description Factory programmed CRC value for the calibration coefficients, high word Derived CRC, Program Code, CODE_DRVTN_LWR Table 179. CAL_SIGTR_UPR Register Definitions Page 0x04 Table 187. CODE_SIGTR_UPR Register Definitions Description Factory programmed CRC value for the program code, high word Table 189. CODE_DRVTN_LWR Register Definitions Page 0x04 Addresses 0x10, 0x11 Default Not applicable Access R Flash Backup No Table 190. CODE_DRVTN_LWR Bit Descriptions Bits [15:0] Description Calculated CRC value for the calibration coefficients, low word Derived CRC, Calibration Values, CAL_DRVTN_LWR Derived CRC, Program Code, CODE_DRVTN_UPR Table 181. CAL_DRVTN_LWR Register Definitions Page 0x04 Addresses 0x08, 0x09 Default Not applicable Access R Flash Backup No Table 191. CODE_DRVTN_LWR Register Definitions Page 0x04 Addresses 0x12, 0x13 Default Not applicable Access R Flash Backup No Table 182. CAL_DRVTN_LWR Bit Descriptions Bits [15:0] Description Calculated CRC value for the program code, low word Table 192. CODE_DRVTN_UPR Bit Descriptions Bits [15:0] Derived CRC, Calibration Values, CAL_DRVTN_UPR Table 183. CAL_DRVTN_UPR Register Definitions Page 0x04 Addresses 0x0A, 0x0B Default Not applicable Access R Flash Backup No Bits [15:0] Lot Specific Serial Number, SERIAL_NUM Table 193. SERIAL_NUM Register Definitions Page 0x04 Table 184. CAL_DRVTN_UPR Bit Descriptions Description Calculated CRC value for the program code, high word Table 185. CODE_SIGTR_LWR Register Definitions Page 0x04 Addresses 0x0C, 0x0D Default Not applicable Access R Flash Backup Yes Table 186. CODE_SIGTR_LWR Bit Descriptions Bits [15:0] Addresses 0x20, 0x21 Default Not applicable Access R Table 194. SERIAL_NUM Bit Descriptions Bits [15:0] Signature CRC, Program Code, CODE_SIGTR_LWR Description Calculated CRC value for the calibration coefficients, high word Description Factory programmed CRC value for the calibration coefficients, low word Rev. D | Page 40 of 43 Description Lot specific serial number Flash Backup Yes Data Sheet ADIS16497 APPLICATIONS INFORMATION MOUNTING BEST PRACTICES PREVENTING MISINSERTION For the best performance, follow these guidelines when installing the ADIS16497 into a system: The ADIS16497 connector uses the same pattern as the ADIS16485, but with Pin 12 and Pin 15 missing. This pin configuration enables a mating connector to plug these holes, which helps prevent misconnection with the ADIS16497. Samtec has a custom part number that provides this type of mating socket: ASP-193371-04. Eliminate opportunity for translational force (x- and y-axis direction, per Figure 39) application on the electrical connector. Use uniform mounting forces on all four corners. The suggested torque setting is 40 inch ounces (0.285 Nm). When the ADIS16497 rests on the PCB, which contains the mating connector (see Figure 50), use a diameter of at least 2.85 mm for the passthrough holes. EVALUATION TOOLS Breakout Board, ADIS16IMU1/PCBZ The ADIS16IMU1/PCBZ (sold separately) provides a breakout board function for the ADIS16497, which means that it provides access to the ADIS16497 through larger connectors that support standard 1 mm ribbon cabling. It also provides four mounting holes for attachment of the ADIS16497 to the breakout board. These guidelines help prevent irregular force profiles, which can warp the package and introduce bias errors in the sensors. Figure 50 and Figure 51 provide details for mounting hole and connector alignment pin drill locations. PC-Based Evaluation, EVAL-ADIS2 39.600 BSC Use the EVAL-ADIS2 and ADIS16IMU1/PCBZ to evaluate the ADIS16497 on a PC-based platform. 19.800 BSC PASSTHROUGH HOLE FOR MOUNTING SCREWS POWER SUPPLY CONSIDERATIONS DIAMETER OF THE HOLE MUST ACCOMODATE DIMENSIONAL TOLERANCE BETWEEN THE CONNECTOR AND HOLES The VDD power supply must charge 46 F of capacitance (inside of the ADIS16497, across the VDD and GND pins) during its initial ramp and settling process. When VDD reaches 2.85 V, the ADIS16497 begins its internal start-up process, which generates additional transient current demand. See Figure 52 for a typical current profile during the start-up process. The first peak in Figure 52 relates to charging the 46 F capacitor bank, whereas the other transient activity relates to numerous functions turning on during the initialization process of the ADIS16497. 21.300 BSC 1.642 BSC 42.600 DEVICE OUTLINE 0.560 BSC 2x ALIGNMENT HOLES FOR MATING SOCKET 5 BSC 5 BSC NOTES 1. ALL DIMENSIONS IN UNITS OF MILLIMETERS (mm). 2. IN THIS CONFIGURATION, THE CONNECTOR IS FACING DOWN AND ITS PINS ARE NOT VISIBLE. a 15061-042 T b a 1.608ms 92.00mA b 159.8ms 152.0mA 158.2ms 60.00mA Figure 50. Suggested PCB Layout Pattern, Connector Down 0.4334 [11.0] 0.0240 [0.610] 3 0.054 [1.37] 2 0.0394 [1.00] 0.1800 [4.57] 0.0394 [1.00] 15061-043 0.022 DIA (TYP) NONPLATED 0.022 DIA THROUGH HOLE (TYP) THROUGH HOLE 2x NONPLATED THROUGH HOLE 4 Figure 51. Suggested Layout and Mechanical Design When Using Samtec CLM-112-02-G-D-A for the Mating Connector Rev. D | Page 41 of 43 VDD DR CURRENT CH2 2.0V BW CH3 2.0V BW CH4 100mA BW M40.0ms T 20.10% A CH3 3.00V 12.5MS/s 5M pts Figure 52. Transient Current Demand, Startup 15061-044 0.019685 [0.5000] (TYP) ADIS16497 Data Sheet CRC32 CODING EXAMPLE This section contains sample code and values for computing the cyclic redundancy check (CRC) for the ADIS16497 register readback values. In this coding example, the 32-bit CRC is first initialized with 0xFFFFFFFF. Next, each 16-bit word passes through the CRC computation in ascending order. Finally, the CRC is Xor'ed with 0xFFFFFFFF. The ADIS16497 updates the CRC value for each data ready cycle. The registers listed in Table 195 are used as inputs for computing the CRC32 checksum. The registers can either be read individually in normal SPI mode or in burst mode, provided that all registers are all read during the same data ready cycle. Table 195. Sample Input Data for CRC Computation1 Register Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 1 Register STATUS TEMP_OUT X_GYRO_LOW X_GYRO_OUT Y_GYRO_LOW Y_GYRO_OUT Z_GYRO_LOW Z_GYRO_OUT X_ACCL_LOW X_ACCL_OUT Y_ACCL_LOW Y_ACCL_OUT Z_ACCL_LOW Z_ACCL_OUT TIME_STAMP Input Value 0x0000 0x083A 0x0000 0xFFF7 0x0000 0xFFFE 0x0000 0x0001 0x5001 0x0003 0xE00A 0x0015 0xC009 0x0320 0x8A54 This information is contained in the array data in the coding example. Table 196. Output Results for CRC Sample Computation1 Register Number 1 2 1 Register CRC_LWR CRC_UPR Output Value 0x15B4 0xB6C8 Based on the input shown in Table 195. The following is the CRC initialization code: /* Initialize CRC */ crc = 0xFFFFFFFFU; /* Compute CRC in the order of bytes low-high starting at 0-14, BurstID, STATUS - TIME_STAMP */ crc = crc32_block(crc, DATA, 15); /* Final operation per IEEE-802.3 */ crc ^= 0xFFFFFFFFU; The crc32_block function accepts an array of 16-bit numbers and computes the CRC byte-by-byte: unsigned long crc32_block( unsigned long crc, const unsigned short data[], int n ) { unsigned long long_c; int i; /* cycle through memory */ for ( i=0; i<n; i++ ) { /* Get lower byte */ long_c = 0x000000ff & (unsigned long)data[i]; /* Process with CRC */ crc = ((crc>>8) & 0x00ffffff) ^ crc_tab32[(crc^long_c)&0xff]; /* Get upper byte */ long_c = (0x000000ff & ((unsigned long)data[i]>>8); /* Process with CRC */ crc = ((crc>>8) & 0x00ffffff) ^ crc_tab32[(crc^long_c)&0xff]; } return crc; } The CRC table (crc_tab32) is computed with the following function: void init_crc32_table( void ) { unsigned long P_32; int i, j; unsigned long crc; /* CRC32 polynomial defined by IEEE-802.3 */ P_32 = 0xEDB88320 /* 8 bits require 256 entries in Table */ for (i=0; i<256; i++) { /* start with table entry number */ crc = (unsigned long) i; /* cycle through all bits in entry number */ for (j=0; j<8; j++) { /* LSBit set? */ if ((crc&(unsigned long)0x00000001)!=(unsigned long)0) { /* process for bit set */ crc = (crc>>1) ^ P_32; } else { /* process for bit clear */ crc = (crc>>1); } } /* Store calculated value into table */ crc_tab32[i] = crc; } } Rev. D | Page 42 of 43 Data Sheet ADIS16497 OUTLINE DIMENSIONS 44.254 44.000 43.746 39.800 39.600 39.400 20.00 19.80 19.60 7.350 7.225 7.100 2.20 BSC 2.065 O 2.040 2.015 2.20 BSC 34.600 34.575 34.550 2.325 2.200 2.075 1.142 BSC 42.800 42.600 42.400 37.598 37.573 37.548 47.254 47.000 46.746 3.70 3.50 3.30 O 2.40 BSC BOTTOM VIEW TOP VIEW 47.479 47.379 47.279 DETAIL A 13.750 REF 0.250 BSC FRONT VIEW DETAIL A 14.200 14.000 13.800 2.84 BSC 5.50 BSC 3.454 3.200 2.946 5.50 BSC 1.00 BSC PITCH 0.30 SQ BSC 05-31-2018-A 0.250 BSC 2.065 2.040 2.015 Figure 53. 24-Lead Module with Connector Interface [MODULE] (ML-24-9) Dimensions shown in millimeters ORDERING GUIDE Model1 ADIS16497-1BMLZ ADIS16497-2BMLZ ADIS16497-3BMLZ 1 Temperature Range -40C to +105C -40C to +105C -40C to +105C Description 24-Lead Module with Connector Interface [MODULE] 24-Lead Module with Connector Interface [MODULE] 24-Lead Module with Connector Interface [MODULE] Z = RoHS Compliant Part. (c)2017-2020 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D15061-7/20(D) Rev. D | Page 43 of 43 Package Option ML-24-9 ML-24-9 ML-24-9