1. General description
The PCA9543A/43B is a bidirectional translating switch, controlled by the I2C-bus. The
SCL/SDA upstream pair fans out to two downstream pairs, or channels. Any individual
SCx/SDx channels or combin atio n of ch a nnels can be selected, determined by the
contents of the program m ab le co ntrol register. Two interrupt inpu ts, INT0 and INT1, one
for each of the downstream pairs, are provided. One interrupt output, INT, which acts as
an AND of the two interrupt inputs, is provided.
An active LOW reset input allows the PCA9543X to reco ver from a situation wher e one o f
the downstream I2C-buses is stuck in a LOW state. Pulling the RESET pin LOW resets
the I2C-bus state machine and causes all the channels to be deselected, as does the
internal power-on reset function.
The pa ss g ates of the switch es are co nstructed such th at the V DD pin can be used to limit
the maximum high volt age which wi ll be pa ssed by the PCA9543X. This allows the use of
different bus voltages on each SCx/SDx pair, so that 1.8 V, 2.5 V, or 3.3 V parts can
communicate with 5 V parts without any additional protection. Extern a l pull- up res isto rs
pull the bus up to the desired voltage level for each channel. All I/O pins are 5 V tolerant.
The PCA9543A and PCA9543B are identical except for the fixed portion of the slave
address.
2. Features and benefits
1-of-2 bidirectional translating switches
I2C-bus interface logic; compatible with SMBus standards
2 active LOW interrupt inputs
Active LOW interrupt output
Active LOW reset input
2 address pins allowing up to 4 devices on the I2C-bus
Alternate address versions A and B allow up to a total of 12 devices on the bus for
larger systems or to resolve address conflicts
Channel selection via I2C-bus, in any combination
Power-up with all switch channels deselected
Low Ron switches
Allows voltage level translation between 1.8 V, 2.5 V, 3.3 V and 5 V buses
No glitch on power-up
Supports hot insertion
Low standby current
Operating power supply voltage range of 2.3 V to 5.5 V
PCA9543A/43B
2-channel I2C-bus switch with interrupt logic and reset
Rev. 8 — 3 April 2014 Product data sheet
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Product data sheet Rev. 8 — 3 April 2014 2 of 28
NXP Semiconductors PCA9543A/43B
2-channel I2C-bus switch with interrupt logic and reset
5 V tolerant inputs
0 Hz to 400 kHz clock frequency
ESD protection exceeds 2000 V HBM per JESD22-A114 and 1000 V CDM per
JESD22-C101
Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA
Packages offered: SO14, TSSOP14
3. Ordering information
3.1 Ordering options
Table 1. Ordering information
Type number Topside
marking Package
Name Description Version
PCA9543AD PCA9543A SO14 plastic small outline package; 14 leads; body width 3.9 mm SOT108-1
PCA9543APW PA9543A TSSOP14 plastic thin shrink small outline package; 14 leads;
body width 4.4 mm SOT402-1
PCA9543BPW PA9543B TSSOP14 plastic thin shrink small outline package; 14 leads;
body width 4.4 mm SOT402-1
Table 2. Ordering options
Type number Orderable
part number Package Packing method Minimum
order
quantity
Temperature
PCA9543AD PCA9543AD,112 SO14 Standard marking
* IC’s tube - DSC bulk pack 1140 Tamb =40 Cto+85C
PCA9543AD,118 SO14 Reel 13” Q1/T1
*standard mark SMD 2500 Tamb =40 Cto+85C
PCA9543APW PCA9543APW,112 TSSOP14 Standard marking
* IC’s tube - DSC bulk pack 2400 Tamb =40 Cto+85C
PCA9543APW,118 TSSOP14 Reel 13” Q1/T1
*standard mark SMD 2500 Tamb =40 Cto+85C
PCA9543BPW PCA9543BPW,118 TSSOP14 Reel 13” Q1/T1
*standard mark SMD 2500 Tamb =40 Cto+85C
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Product data sheet Rev. 8 — 3 April 2014 3 of 28
NXP Semiconductors PCA9543A/43B
2-channel I2C-bus switch with interrupt logic and reset
4. Block diagram
Fig 1. Block diagram of PCA9543A/43B
SWITCH CONTROL LOGIC
PCA9543A/43B
POWER-ON
RESET
002aab180
SC0
SC1
SD0
SD1
VSS
VDD
RESET
I2C-BUS
CONTROL
INPUT
FILTER
SCL
SDA
A0
A1
INTERRUPT LOGIC
INT0
to
INT1
INT
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Product data sheet Rev. 8 — 3 April 2014 4 of 28
NXP Semiconductors PCA9543A/43B
2-channel I2C-bus switch with interrupt logic and reset
5. Pinning information
5.1 Pinning
5.2 Pin description
Fig 2. Pin configuration for SO14 Fig 3. Pin configuration for TSSOP14
PCA9543AD
A0 VDD
A1 SDA
RESET SCL
INT0 INT
SD0 SC1
SC0 SD1
VSS INT1
002aab178
1
2
3
4
5
6
7 8
10
9
12
11
14
13
VDD
SDA
SCL
INT
SC1
SD1
INT1
A0
A1
RESET
INT0
SD0
SC0
VSS
PCA9543APW
PCA9543BPW
002aab179
1
2
3
4
5
6
78
10
9
12
11
14
13
Table 3. Pin description
Symbol Pin Description
A0 1 address input 0
A1 2 address input 1
RESET 3 active LOW reset input
INT0 4 active LOW interrupt input 0
SD0 5 serial data 0
SC0 6 serial clock 0
VSS 7 supply ground
INT1 8 active LOW interrupt input 1
SD1 9 serial data 1
SC1 10 serial clock 1
INT 11 active LOW interrupt output
SCL 12 serial clock line
SDA 13 serial data line
VDD 14 supply voltage
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Product data sheet Rev. 8 — 3 April 2014 5 of 28
NXP Semiconductors PCA9543A/43B
2-channel I2C-bus switch with interrupt logic and reset
6. Functional description
Refer to Figure 1 “Block dia gram of PCA9543A/43B”.
6.1 Device address
Following a START condition, the bus master must output the ad dr ess of the slave it is
accessing. The address of the PCA9543A/43B is shown in Figure 4. To conserve power,
no internal pull-up resisto rs are incorporated on the hard ware selectab le address pins and
they must be pulled HIGH or LOW.
The last bit of the slave address defines the operation to be performed. When set to
logic 1 a read is selected, while a logic 0 selects a write operation.
The PCA9543B is an alternate address version, if needed for larger systems or to resolve
address conflicts. The data sheet will reference the PCA9543A, but the PCA9543B
functions identically except for the slave address.
6.1.1 Address maps
Fig 4. Slave address PCA9543A
Fig 5. Slave address PCA9543B
002aab169
1 1 1 0 0 A1 A0 R/W
fixed hardware
selectable
002aab799
1 1 1 1 0 A1 A0 R/W
fixed hardware
selectable
Table 4. PCA9543A address map
Pin connectivity Address of PCA9543A Address byte value 7-bit
hexadecimal
address
without R/W
A1 A0 A6 A5 A4 A3 A2 A1 A0 R/W Write Read
VSS VSS 1110000 - E0h E1h 70h
VSS VDD 1110001 - E2h E3h 71h
VDD VSS 1110010 - E4h E5h 72h
VDD VDD 1110011 - E6h E7h 73h
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Product data sheet Rev. 8 — 3 April 2014 6 of 28
NXP Semiconductors PCA9543A/43B
2-channel I2C-bus switch with interrupt logic and reset
6.2 Control register
Following the successful acknowledgement of the slave address, the bus master will send
a byte to the PCA9543A/43B, which will be stored in the control register. If multiple bytes
are received by the PCA9543A/43B, it will save the last byte received. This register can
be written and read via the I2C-bus.
6.2.1 Control register definition
One or several SCx/SDx downstream pair, or channel, is selected by the contents of the
control register. This reg ister is written after the PCA9543A/43B has bee n addressed. The
2 LSBs of the control byte are used to determine which channel is to be selected. When a
channel is selected, the channel will become active after a STOP condition has been
placed on the I2C-bus. This ensures that all SCx/SDx lines will be in a HIGH state when
the channel is made active, so that no false conditions are generated at the time of
connection.
Bits INT0, INT1, D6 and D7 are all writable, but will read the chip status. INT0 and INT1
indicate the state of the corresponding interrupt inpu t. D7 and D6 always read 0.
See Section 6.2.2.
Table 5. PCA9543B address map
Pin connectivity Address of PCA9543B Address byte value 7-bit
hexadecimal
address
without R/W
A1 A0 A6 A5 A4 A3 A2 A1 A0 R/W Write Read
VSS VSS 1111000 - F0h F1h 78h
VSS VDD 1111001 - F2h F3h 79h
VDD VSS 1111010 - F4h F5h 7Ah
VDD VDD 1111011 - F6h F7h 7Bh
Fig 6. Control register
002aab181
X X INT
1INT
0X X B1 B0
channel selection bits
(read/write)
76543210
interrupt bits (read/write),
but reads back chip status;
bit 6 and bit 7 always read 0
channel 0
channel 1
INT0
INT1
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Product data sheet Rev. 8 — 3 April 2014 7 of 28
NXP Semiconductors PCA9543A/43B
2-channel I2C-bus switch with interrupt logic and reset
Remark: Channel 0 and channel 1 can be enabled at the same time. Care should be
taken not to exceed the maximum bus capacitance.
6.2.2 Interrupt handling
The PCA9543A/43B provides 2 interrupt inputs, one for each channel, and one
open-drain interrupt output. When an interrupt is generated by any device, it will be
detected by the PCA9543A/43B and the interrupt output will be driven LOW. The channel
need not be active for detection of the interrupt. A bit is also set in the control register.
Bit 4 and bit 5 of the control register corresponds to the INT0 and INT1 inputs of the
PCA9543A/43B, respectively. Therefore, if an interrupt is generated by any device
connected to channel 1, the state of the interrupt inputs is loaded into the control register
when a read is accomplished. Likewise, an interrupt on any device connected to
channel 0 would cause bit 4 of the control register to be set on the read. The master can
then address the PCA9543A/43B and read the contents of the control register to
determine which channel contains the device generating the interrupt. The master can
then reconfigure the PCA9543A/43B to select this channel, and locate the device
generating the interrupt and clear it.
It should be noted that more than one device can provide an interrupt on a ch annel, so it is
up to the master to ensure that all devices on a channel ar e interrogated for an interrupt.
The interrupt inputs may be used as general-purpose inputs if the interrupt function is not
required.
If unused, interrupt input(s) must be connected to VDD through a pu ll-u p resis tor.
Remark: Two interr u pts can be activ e at the sa me time . D6 an d D7 always re ad 0.
6.3 RESET input
The RESET input is an active LOW signal which may be used to recover from a bus fault
condition. By asserting this signal LOW for a minimum of tw(rst)L, the PCA9543A/43B will
reset its registers and I2C-bus state machine and will deselect all channels. The RESET
input must be connected to VDD through a pull-up resistor.
Table 6. Control register: Write — channel selection; Read — channel status
D7 D6 INT1 INT0 D3 D2 B1 B0 Command
XXXXXXX0 channel 0 disabled
1 channel 0 enabled
XXXXXX0Xchannel 1 disabled
1 ch annel 1 enabled
00000000no channel selected;
power-up/reset default state
Table 7. Control register: Read — interrupt
7 6 INT1 INT0 3 2 B1 B0 Command
00X0XXXX
no interrupt on channel 0
1 interrupt on channel 0
000XXXXX
no interrupt on channel 1
1 interrupt on channel 1
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Product data sheet Rev. 8 — 3 April 2014 8 of 28
NXP Semiconductors PCA9543A/43B
2-channel I2C-bus switch with interrupt logic and reset
6.4 Power-on reset
When power is applied to VDD, an internal Power-On Reset (POR) holds the
PCA9543A/43B in a reset condition until VDD has reached VPOR. At this point, the reset
condition is release d an d th e PCA9543 A /4 3B re gisters and I2C-bus state machine are
initialized to their default states (all zeroes) causing all the channels to be deselected.
Thereafter, VDD must be lowered below 0.2 V for at least 5 s in orde r to reset the device.
6.5 Voltage translation
The pass gate transistors of the PCA9543A/43B are constructed such that the VDD
voltage can be used to limit the maximum voltage that will be passed from one I2C-bus to
another.
Figure 7 shows the volt age characteristics of the p ass gate transistors (note that the graph
was generated using the data specified in Section 11 “Static characteristics” of this data
sheet). In order for the PCA9543A/43B to act as a voltage translator, the Vo(sw) voltage
should be equal to, or lower than the lowest bus voltage. For examp le, if the main bus was
running at 5 V, and the downstream buses were 3.3 V and 2.7 V, then Vo(sw) should be
equal to or below 2.7 V to effectively clamp the downstream bus voltages. Lo ok ing at
Figure 7, we see that Vo(sw)(max) will be at 2.7 V when the PCA9543A/43B supply voltage
is 3.5 V or lower, so the PCA9543A/43B supply voltage could be set to 3.3 V. Pull-up
resistors can then be used to bring the bus voltages to their appropriate levels (see
Figure 14).
More Information can be found in Application Note AN262: PCA954X family of I2C/SMBus
multiplexers and switches.
(1) maximum
(2) typical
(3) minimum
Fig 7. Pass gate voltage versus supply voltage
VDD (V)
2.0 5.54.53.0 4.0
002aaa964
3.0
2.0
4.0
5.0
Vo(sw)
(V)
1.0 3.5 5.02.5
(1)
(2)
(3)
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Product data sheet Rev. 8 — 3 April 2014 9 of 28
NXP Semiconductors PCA9543A/43B
2-channel I2C-bus switch with interrupt logic and reset
7. Characteristics of the I2C-bus
The I2C-bus is for 2 -way, 2-line co mmunication between dif ferent ICs or modules. The two
lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be
connected to a positive supply via a pull-up resistor when connected to the output stages
of a device. Data transfer may be initiated only when the bus is not busy.
7.1 Bit transfer
One data bi t is transferred durin g each clock pulse . The data o n the SDA line must remain
stable during the HIGH period of the clock pulse as changes in the data line at this time
will be interpreted as control signals (see Figure 8).
7.2 START and STOP conditions
Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW
transition of the data line while the clock is HIGH is defined as the START condition (S).
A LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the STOP
condition (P) (see Figure 9).
Fig 8. Bit transfer
mba607
data line
stable;
data valid
change
of data
allowed
SDA
SCL
Fig 9. Definition of START and STOP conditions
mba608
SDA
SCL P
STOP condition
S
START condition
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Product data sheet Rev. 8 — 3 April 2014 10 of 28
NXP Semiconductors PCA9543A/43B
2-channel I2C-bus switch with interrupt logic and reset
7.3 System configuration
A device generating a message is a ‘transmitter’, a device receiving is the ‘receiver’. The
device that controls the message is the ‘master’ and the devices which are controlled by
the master are the ‘slaves’ (see Figure 10).
7.4 Acknowledge
The number of data bytes transferre d between the START and the STOP cond itions from
transmitter to receiver is not limited. Each byte of eight bits is followed by one
acknowledge bit. The acknowledge bit is a HIGH level put on the bus by the transmitter,
whereas the master generates an extra acknowledge related clock pulse.
A slave receiver which is addresse d must gener ate an acknowledg e af ter the reception of
each byte. Also, a master must generate an ackno wledge af ter the reception of each byte
that has been clocke d ou t of th e sla ve tr an smitter. The device that acknowledges has to
pull down the SDA line during the acknowledge cl ock pulse , so that the SDA line is st able
LOW during the HIGH period of the acknowledge related clock pulse; set-up and hold
times must be taken into account.
A master receiver must signal an end of data to the transmitter by not generating an
acknowledge on the last byte that has been clocked out of the slave. In this event, the
transmitter mus t leave the data line HIGH to enable the master to generate a STOP
condition.
Fig 10. System configuratio n
002aaa966
MASTER
TRANSMITTER/
RECEIVER
SLAVE
RECEIVER SLAVE
TRANSMITTER/
RECEIVER
MASTER
TRANSMITTER MASTER
TRANSMITTER/
RECEIVER
SDA
SCL
I2C-BUS
MULTIPLEXER
SLAVE
Fig 11. Acknowl edgement on the I2C-bus
002aaa987
S
START
condition
9821
clock pulse for
acknowledgement
not acknowledge
acknowledge
data output
by transmitter
data output
by receiver
SCL from master
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Product data sheet Rev. 8 — 3 April 2014 11 of 28
NXP Semiconductors PCA9543A/43B
2-channel I2C-bus switch with interrupt logic and reset
7.5 Bus transactions
Data is transmitted to the PCA9 543A/43B contro l register us ing the W rite mode as shown
in Figure 12.
Data is read from PCA9543A/43B using the Read mode as shown in Figure 13.
Fig 12. Write control register
Fig 13. Read co ntrol register
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Product data sheet Rev. 8 — 3 April 2014 12 of 28
NXP Semiconductors PCA9543A/43B
2-channel I2C-bus switch with interrupt logic and reset
8. Application design-in information
(1) If the device generating the interrupt has an open-drain output structure or can be 3-stated, a
pull-up resistor is required.
If the device generating the interrupt has a totem pole output structure and cannot be 3-stated, a
pull-up resistor is not required.
The interrupt inputs should not be left floating.
Fig 14. Typical application
PCA9543A
SD0
SC0
A1
A0
VSS
SDA
SCL
RESET
VDD = 3.3 V
VDD = 2.7 V to 5.5 V
I2C/SMBus master
002aab184
SDA
SCL channel 0
V = 2.7 V to 5.5 V
INT INT0
see note (1)
SD1
SC1 channel 1
V = 2.7 V to 5.5 V
INT1
see note (1)
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Product data sheet Rev. 8 — 3 April 2014 13 of 28
NXP Semiconductors PCA9543A/43B
2-channel I2C-bus switch with interrupt logic and reset
9. Limiting values
[1] The performance capability of a high-performance integrated circuit in conjunction with its thermal
environment can create junction temperatures which ar e detrimental to reliability. The maximum junction
temperature of this integrated circuit should not exceed 125 C.
10. Thermal characteristics
Table 8. Limiting values
In accordance with the Absolute Maximum Rating Syste m (IEC 60134). Voltages are referenced to
VSS (ground = 0 V).
Symbol Parameter Conditions Min Max Unit
VDD supply voltage 0.5 +7.0 V
VIinput voltage 0.5 +7.0 V
IIinput curr en t - 20 mA
IOoutput current - 25 mA
IDD supply current - 100 mA
ISS ground supply current - 100 mA
Ptot total power dissipation - 400 mW
Tj(max) maximum junction temperature [1] -125C
Tstg storage temperature 60 +150 C
Tamb ambient temperature operating 40 +85 C
Table 9. Thermal characteristics
Symbol Parameter Conditions Typ Unit
Rth(j-a) thermal resistance from junction
to ambient SO14 package 127 C/W
TSSOP14 package 175 C/W
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Product data sheet Rev. 8 — 3 April 2014 14 of 28
NXP Semiconductors PCA9543A/43B
2-channel I2C-bus switch with interrupt logic and reset
11. Static characteristics
[1] For operation between published voltage ranges, refer to the worst-case parameter in both ranges.
[2] VDD must be lowered to 0.2 V for at least 5 s in order to reset part.
Table 10. Static characteristics at VDD =2.3V to 3.6V
VSS =0V; T
amb =
40
C to +85
C; unless otherwise specified. See Table 11 on page 15 for VDD = 4.5 V to 5.5 V.[1]
Symbol Parameter Conditions Min Typ Max Unit
Supply
VDD supply voltage 2.3 - 3.6 V
IDD supply current operating mode; VDD = 3.6 V ; no load;
VI=V
DD or VSS; fSCL =100kHz - 40 100 A
Istb standby current St andby mode; VDD = 3.6 V; no load;
VI=V
DD or VSS; fSCL = 0 kHz -0.21 A
VPOR power-on reset voltage no load; VI=V
DD or VSS [2] -1.62.1V
Input SCL; input/outpu t S DA
VIL LOW-level input voltage 0.5 - +0.3VDD V
VIH HIGH-level input voltage 0.7VDD -6 V
IOL LOW- l e vel output cur r en t VOL =0.4V 3 - - mA
VOL =0.6V 6 - - mA
ILleakage current VI=V
DD or VSS 1-+1 A
Ciinput capacitance VI=V
SS - 9 10 pF
Select inputs A0, A1, INT0, INT1, RESET
VIL LOW-level input voltage 0.5 - +0.3VDD V
VIH HIGH-level input voltage 0.7VDD -6 V
ILI input leakage current VI=V
DD or VSS 1-+1 A
Ciinput capacitance VI=V
SS -1.63 pF
Pass gate
Ron ON-state resistance VDD = 3 .0 to 3.6 V; VO=0.4V;
IO=15mA 51130
VDD = 2.3 V to 2.7 V; VO=0.4V;
IO=10mA 71655
Vo(sw) switch output voltage Vi(sw) =V
DD = 3.3 V; Io(sw) =100 A- 1.9- V
Vi(sw) =V
DD = 3.0 V to 3.6 V;
Io(sw) =100 A1.6 - 2.8 V
Vi(sw) =V
DD = 2.5 V; Io(sw) =100 A- 1.5- V
Vi(sw) =V
DD = 2.5 V to 2.7 V;
Io(sw) =100 A1.1 - 2.0 V
ILleakage current VI=V
DD or VSS 1-+1 A
Cio input/output capacitance VI=V
SS -35 pF
INT output
IOL LOW- l e vel output cur r en t VOL =0.4V 3 - - mA
IOH HIGH-level output current - - +100 A
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Product data sheet Rev. 8 — 3 April 2014 15 of 28
NXP Semiconductors PCA9543A/43B
2-channel I2C-bus switch with interrupt logic and reset
[1] For operation between published voltage ranges, refer to the worst-case parameter in both ranges.
[2] VDD must be lowered to 0.2 V for at least 5 s in order to reset part.
Table 11. Static characteristics at VDD =4.5V to 5.5V
VSS = 0 V; Tamb =
40
C to +85
C; unless otherwise specified. See Table 10 on pa g e 14 for VDD = 2.3 V to 3.6 V.[1]
Symbol Parameter Conditions Min Typ Max Unit
Supply
VDD supply voltage 4.5 - 5.5 V
IDD supply current Operating mode; VDD =5.5V;
no load; VI=V
DD or VSS;
fSCL = 100 kHz
- 25 100 A
Istb standby current Standby mode; VDD =5.5V;
no load; VI=V
DD or VSS;
fSCL = 0 kHz
-0.21 A
VPOR power-on reset voltage no load; VI=V
DD or VSS [2] -1.72.1V
Input SCL; input/outpu t S DA
VIL LOW-level input voltage 0.5 - +0.3VDD V
VIH HIGH-level input voltage 0.7VDD -6 V
IOL LOW-level output current VOL =0.4V 3 - - mA
VOL =0.6V 6 - - mA
ILleakage current VI=V
DD or VSS 1- +1 A
Ciinput capacitance VI=V
SS - 9 10 pF
Select inputs A0, A1, INT0, INT1, RESET
VIL LOW-level input voltage 0.5 - +0.3VDD V
VIH HIGH-level input voltage 0.7VDD -6 V
ILI input leakage current VI=V
DD or VSS 1- +50A
Ciinput capacitance VI=V
SS -25 pF
Pass gate
Ron ON-state resistance VDD = 4.5 V to 5.5 V; VO=0.4V;
IO=15mA 4924
Vo(sw) switch output voltage Vi(sw) =V
DD =5.0V;
Io(sw) =100 A-3.6- V
Vi(sw) =V
DD = 4.5 V to 5.5 V;
Io(sw) =100 A2.6 - 4.5 V
ILleakage current VI=V
DD or VSS 1- +100A
Cio input/output capacitance VI=V
SS -35 pF
INT output
IOL LOW-level output current VOL =0.4V 3 - - mA
IOH HIGH-level output current - - +100 A
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Product data sheet Rev. 8 — 3 April 2014 16 of 28
NXP Semiconductors PCA9543A/43B
2-channel I2C-bus switch with interrupt logic and reset
12. Dynamic characteristics
[1] Pass gate propagation delay is calculated from the 20 typical Ron and the 15 pF load capacitance.
[2] Hold time (repeated) START condition. After this period, the first clock pulse is generated.
[3] A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the VIH(min) of the SCL signal) in order to
bridge the undefined region of the falling edge of SCL.
[4] Cb= total capacitance of one bus line in pF.
[5] Measurements taken with 1 k pull-up resistor and 50 pF load.
Table 12. Dynamic characteristics
Symbol Parameter Conditions Standard-mode
I2C-bus Fast-mode I2C-bus Unit
Min Max Min Max
tPD propagation delay from SDA to SDx,
or SCL to SCx -0.3
[1] -0.3
[1] ns
fSCL SCL clock frequency 0 100 0 400 kHz
tBUF bus free time between a STOP and
START condition 4.7 - 1.3 - s
tHD;STA hold time (repeated) START
condition [2] 4.0 - 0.6 - s
tLOW LOW period of the SCL clock 4.7 - 1.3 - s
tHIGH HIGH period of the SCL clock 4.0 - 0.6 - s
tSU;STA set-up time for a repeated START
condition 4.7 - 0.6 - s
tSU;STO set-up time for STOP condition 4.0 - 0.6 - s
tHD;DAT data hold time 0[3] 3.45 0[3] 0.9 s
tSU;DAT data set-up time 250 - 100 - ns
trrise time of both SDA and SCL
signals - 1000 20 + 0.1Cb[4] 300 ns
tffall time of both SDA and SCL signals - 300 20 + 0.1Cb[4] 300 ns
Cbcapacitive load for each bus line - 400 - 400 pF
tSP pulse width of spikes that must be
suppressed by the input filter - 50 - 50 ns
tVD;DAT d ata valid time HIGH-to-LOW [5] -1 - 1s
LOW-to-HIGH [5] -0.6 - 0.6s
tVD;ACK data valid acknowledge time - 1 - 1 s
INT
tv(INTnN-INTN) valid time from INTn to INT signal - 4 - 4 s
td(INTnN-INTN) delay time from INTn to INT inactive - 2 - 2 s
tw(rej)L LOW-level rejection time INTn inputs 1 - 1 - s
tw(rej)H HIGH-level rejection time INTn inputs 0.5 - 0.5 - s
RESET
tw(rst)L LOW-level reset time 4 - 4 - ns
trst reset time SDA clear 500 - 500 - ns
tREC;STA recovery time to START condition 0 - 0 - ns
PCA9543A_43B All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 8 — 3 April 2014 17 of 28
NXP Semiconductors PCA9543A/43B
2-channel I2C-bus switch with interrupt logic and reset
Fig 15. Definition of timing on the I2C-bus
t
SP
t
BUF
t
HD;STA
PP S
t
LOW
t
r
t
HD;DAT
t
f
t
HIGH
t
SU;DAT
t
SU;STA
Sr
t
HD;STA
t
SU;STO
SDA
SCL
002aaa986
0.7 × V
DD
0.3 × V
DD
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DD
0.3 × V
DD
Fig 16. Definitio n of RESET timing
SDA
SCL
002aac549
50 %
30 %
50 % 50 %
t
REC;STA
t
w(rst)L
RESET
START
t
rst
ACK or read cycle
Rise and fall times refer to VIL and VIH.
Fig 17. I2C-bus timing diag ra m
002aab175
protocol START
condition
(S)
bit 7
MSB
(A7)
bit 6
(A6) bit 0
(R/W) acknowledge
(A)
STOP
condition
(P)
SCL
SDA
tHD;STA tSU;DAT tHD;DAT
tf
tBUF
tSU;STA tLOW tHIGH
tVD;ACK tSU;STO
1 / fSCL
tr
tVD;DAT
0.3 × VDD
0.7 × VDD
0.3 × VDD
0.7 × VDD
PCA9543A_43B All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 8 — 3 April 2014 18 of 28
NXP Semiconductors PCA9543A/43B
2-channel I2C-bus switch with interrupt logic and reset
13. Package outline
Fig 18. Package outline SOT108-1 (SO14)
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PCA9543A_43B All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 8 — 3 April 2014 19 of 28
NXP Semiconductors PCA9543A/43B
2-channel I2C-bus switch with interrupt logic and reset
Fig 19. Package outline SOT402-1 (TSSOP14)
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PCA9543A_43B All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 8 — 3 April 2014 20 of 28
NXP Semiconductors PCA9543A/43B
2-channel I2C-bus switch with interrupt logic and reset
14. Soldering of SMD packages
This text provides a very brief insight into a complex technology. A more in-depth account
of soldering ICs can be found in Application Note AN10365 “Surface mount reflow
soldering description”.
14.1 Introduction to soldering
Soldering is one of the most common methods through which packages are attached to
Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both
the mechanical and the electrical connection. There is no single soldering method that is
ideal for all IC packages. Wave soldering is often preferred when through-hole and
Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not
suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high
densities that come with increased miniaturization.
14.2 Wave and reflow soldering
W ave soldering is a joinin g technology in which the joint s are made by solder coming from
a standing wave of liquid solder. The wave soldering process is suitable for the following:
•Through-hole components
•Leaded or leadless SMDs, which are glued to the surface of the printed circui t board
Not all SMDs can be wave soldered. Packages with solder balls, and some leadless
packages which have solder lands underneath the body, cannot be wave soldered. Also,
leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,
due to an increased probability of bridging.
The reflow soldering process involves applying solder paste to a board, followed by
component placement and exposure to a temperature profile. Leaded packages,
packages with solder balls, and leadless packages are all reflow solderable.
Key characteristics in both wave and reflow soldering are:
•Board specifications, including the board finish, solder masks and vias
•Package footprints, including solder thieves and orientation
•The moisture sensitivity level of the packages
•Package placement
•Inspection and repair
•Lead-free soldering versus SnPb soldering
14.3 Wave soldering
Key characteristics in wave soldering are:
•Process issues, such as application of adhesive and flux, clinching of leads, board
transport, the solder wave parameters, and the time during which components are
exposed to the wave
•Solder bath specifications, including temperature and impurities
PCA9543A_43B All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 8 — 3 April 2014 21 of 28
NXP Semiconductors PCA9543A/43B
2-channel I2C-bus switch with interrupt logic and reset
14.4 Reflow soldering
Key characteristics in reflow soldering are:
•Lead-free ve rsus SnPb soldering; note th at a lead-free reflow process usua lly leads to
higher minimum peak temperatures (see Figure 20) than a SnPb process, thus
reducing the process window
•Solder paste printing issues including smearing, release, and adjusting the process
window for a mix of large and small components on one board
•Reflow temperature profile; this profile includes preheat, reflow (in which the board is
heated to the peak temperature) and cooling down. It is imperative that the peak
temperature is high enoug h for the solder to make reliable solder joint s (a solder paste
characteristic). In addition, the peak temperature must be low enough that the
packages and/or boards are not damaged. The peak temperature of the package
depends on package thickness and volume and is classified in accordance with
Table 13 and 14
Moisture sensitivity precautions, as indicated on the packing, must be respected at all
times.
Studies have shown that small packages reach higher temperatures during reflow
soldering, see Figure 20.
Table 13. SnPb eutectic process (from J-STD-020D)
Package thickness (mm) Package reflow temperature (C)
Volume (mm3)
< 350 350
< 2.5 235 220
2.5 220 220
Table 14. Lead-free process (from J-STD-020D)
Package thickness (mm) Package reflow temperature (C)
Volume (mm3)
< 350 350 to 2000 > 2000
< 1.6 260 260 260
1.6 to 2.5 260 250 245
> 2.5 250 245 245
PCA9543A_43B All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 8 — 3 April 2014 22 of 28
NXP Semiconductors PCA9543A/43B
2-channel I2C-bus switch with interrupt logic and reset
For further information on temperature profiles, refer to Application Note AN10365
“Surface mount reflow soldering description”.
MSL: Moisture Sensitivity Level
Fig 20. Temperature profiles for large and small components
001aac844
temperature
time
minimum peak temperature
= minimum soldering temperature
maximum peak temperature
= MSL limit, damage level
peak
temperature
PCA9543A_43B All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 8 — 3 April 2014 23 of 28
NXP Semiconductors PCA9543A/43B
2-channel I2C-bus switch with interrupt logic and reset
15. Soldering: PCB footprints
Fig 21. PCB footprint for SOT108-1 (SO14); reflow soldering
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PCA9543A_43B All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 8 — 3 April 2014 24 of 28
NXP Semiconductors PCA9543A/43B
2-channel I2C-bus switch with interrupt logic and reset
Fig 22. PCB footprint for SOT402-1 (TSSOP14); reflow soldering
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PCA9543A_43B All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 8 — 3 April 2014 25 of 28
NXP Semiconductors PCA9543A/43B
2-channel I2C-bus switch with interrupt logic and reset
16. Abbreviations
17. Revision history
Table 15. Abbreviations
Acronym Description
CDM Charged-Device Model
ESD ElectroStatic Discharge
HBM Human Body Model
IC Integrated Circuit
I2C-bus Inter-Integrated Circuit bus
LSB Least Significant Bit
MSB Most Significant Bit
PCB Prin te d-Circuit Board
SMBus System Management Bus
Table 16. Revision history
Document ID Release date Data sheet status Change notice Supersedes
PCA9543A_43B v.8 20140403 Product data sheet - PCA9543A_43B v.7
Modifications: •Figure 6 “Control register” updated: corrected label above bits [7:4] from “(read only)”
to “(read/write) but reads back chip status; bit 6 and bit 7 always read 0”
•Section 6.2. 1 “ Control register definition”: added second paragraph
•Section 6.2. 2 “ Interrupt handling”:
–Table 7 “Control register: Read — interrupt” corrected: bits [7:6] corrected from “XX” to
“00” (for both channel 0 and channel 1)
–‘Remark’ paragraph: added second sentence
•Section 6.4 “Power-on reset”, first paragraph, third sentence corrected from “Thereafter,
VDD must be lowered below 0.2 V to reset the device.” to “Thereafter, VDD must be
lowered below 0.2 V for at least 5 s in order to reset the device.”
•Table 10 “S tatic characteristics at VDD =2.3V to 3.6V”, Table note [2]: inserted phrase “for
at least 5 s”
•Table 11 “S tatic characteristics at V DD = 4.5 V to 5.5 V”, Table note [2]: inserted phrase “for
at least 5 s”
PCA9543A_43B v.7 20130228 Product data sheet - PCA9543A_43B_43C v.6
PCA9543A_43B_43C v.6 20090615 Product data sheet - PCA9543A_43B_43C v.5
PCA9543A_43B_43C v.5 20081117 Product data sheet - PCA9 543A_43B_43C v.4
PCA9543A_43B_43C v.4 20061020 Product data sheet - PCA9543A v.3
PCA9543A v.3
(9397 750 14316) 20050321 Product data sheet - PCA9543A v.2
PCA9543A v.2
(9397 750 13988) 20040929 Objective data sheet - PCA9543A v.1
PCA9543A v.1
(9397 750 13299) 20040728 Objective data sheet - -
PCA9543A_43B All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 8 — 3 April 2014 26 of 28
NXP Semiconductors PCA9543A/43B
2-channel I2C-bus switch with interrupt logic and reset
18. Legal information
18.1 Data sheet status
[1] Please consult the most recently issued document before initiating or completing a design.
[2] The term ‘short data sheet’ is explained in section “Definitions”.
[3] The product status of de vice(s) d escribed in th is docume nt may have changed since this docume nt was pub lished and may dif fer in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
18.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liab ility for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and tit le. A short data sh eet is intended
for quick reference only and shou ld not be rel ied u pon to cont ain det ailed and
full information. For detailed and full informatio n see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall pre vail.
Product specificatio n — The information and data provided in a Product
data sheet shall define the specification of the product as agr eed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to off er functions and qualities beyond those described in the
Product data sheet.
18.3 Disclaimers
Limited warr a nty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Se miconductors takes no
responsibility for the content in this document if provided by an inf ormation
source outside of NXP Semiconductors.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequ ential damages (including - wit hout limitatio n - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregat e and cumulative liabil ity towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all informa tion supplied prior
to the publication hereof .
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors pro duct can reasonably be expected
to result in perso nal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconducto rs products in such equipment or
applications and ther efore such inclu sion and/or use is at the cu stomer’s own
risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty tha t such application s will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and ope ration of their applications
and products using NXP Semiconductors product s, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suit able and fit for the custome r’s applications and
products planned, as well as fo r the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with t heir
applications and products.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessa ry
testing for th e customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by cust omer’s third party
customer(s). NXP does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanent ly and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individua l agreement. In case an individual
agreement is concluded only the ter ms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby exp ressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by cust omer.
No offer to sell or license — Nothing i n this document may be interpreted or
construed as an of fer t o sell product s that is open for accept ance or t he grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property right s.
Document status[1][2] Product status[3] Definition
Objective [short] data sheet Development This document contains data from the objective specification for product development.
Preliminary [short] dat a sheet Qualification This document contains data from the pre liminary specification.
Product [short] dat a sheet Production This document contains the product specification.
PCA9543A_43B All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 8 — 3 April 2014 27 of 28
NXP Semiconductors PCA9543A/43B
2-channel I2C-bus switch with interrupt logic and reset
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for aut omo tive use. It i s neit her qua lif ied nor test ed
in accordance with automotive testing or application requirements. NXP
Semiconductors accepts no liability for inclusion and/or use of
non-automotive qualified products in automotive equipment or applicati ons.
In the event that customer uses the product for design-in and use in
automotive applications to automot ive specifications and standard s, customer
(a) shall use the product without NXP Semiconductors’ warranty of the
product for such automotive applications, use and specifications, and (b)
whenever customer uses the product for automotive applications beyond
NXP Semiconductors’ specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies NXP Semiconduct ors for an y
liability, damages or failed product cl aims resulting from custome r design and
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
18.4 Trademarks
Notice: All referenced b rands, produc t names, service names and trademarks
are the property of their respect i ve ow ners.
I2C-bus — logo is a trademark of NXP Semi conductors N.V.
19. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
NXP Semiconductors PCA9543A/43B
2-channel I2C-bus switch with interrupt logic and reset
© NXP Semiconductors N.V. 2014. All rights reserved.
For more information, please visit: http://www.nxp.co m
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 3 April 2014
Document identifier: P CA9543A_43B
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
20. Contents
1 General description. . . . . . . . . . . . . . . . . . . . . . 1
2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1
3 Ordering information. . . . . . . . . . . . . . . . . . . . . 2
3.1 Ordering options. . . . . . . . . . . . . . . . . . . . . . . . 2
4 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3
5 Pinning information. . . . . . . . . . . . . . . . . . . . . . 4
5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4
6 Functional description . . . . . . . . . . . . . . . . . . . 5
6.1 Devi ce address. . . . . . . . . . . . . . . . . . . . . . . . . 5
6.1.1 Address maps. . . . . . . . . . . . . . . . . . . . . . . . . . 5
6.2 Control register. . . . . . . . . . . . . . . . . . . . . . . . . 6
6.2.1 Control register definition . . . . . . . . . . . . . . . . . 6
6.2.2 Interrupt handling . . . . . . . . . . . . . . . . . . . . . . . 7
6.3 RESET input. . . . . . . . . . . . . . . . . . . . . . . . . . . 7
6.4 Power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . 8
6.5 Voltage translation . . . . . . . . . . . . . . . . . . . . . . 8
7 Characteristics of the I2C-bus . . . . . . . . . . . . . 9
7.1 Bit transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
7.2 START and STOP conditions. . . . . . . . . . . . . . 9
7.3 System configuration . . . . . . . . . . . . . . . . . . . 10
7.4 Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . 10
7.5 Bus transactions. . . . . . . . . . . . . . . . . . . . . . . 11
8 Application desi gn-in information . . . . . . . . . 12
9 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 13
10 Thermal characteristics . . . . . . . . . . . . . . . . . 13
11 Static characteristics. . . . . . . . . . . . . . . . . . . . 14
12 Dynamic characteristics . . . . . . . . . . . . . . . . . 16
13 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 18
14 Soldering of SMD packages . . . . . . . . . . . . . . 20
14.1 Introduction to soldering . . . . . . . . . . . . . . . . . 20
14.2 Wave and reflow soldering . . . . . . . . . . . . . . . 20
14.3 Wave soldering. . . . . . . . . . . . . . . . . . . . . . . . 20
14.4 Reflow soldering. . . . . . . . . . . . . . . . . . . . . . . 21
15 Soldering: PCB footprints. . . . . . . . . . . . . . . . 23
16 Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 25
17 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 25
18 Legal information. . . . . . . . . . . . . . . . . . . . . . . 26
18.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 26
18.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
18.3 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 26
18.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 27
19 Contact information. . . . . . . . . . . . . . . . . . . . . 27
20 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28