PSoC® 3: CY8C38 Family
Data Sheet
Programmable System-on-Chip (PSoC®)
Cypress Semiconductor Corporation • 198 Champion Court • San Jose,CA 95134-1709 • 408-943-2600
Document Number: 001-11729 Rev. *S Revised May 20, 2011
General Description
With its unique array of configurable blocks, PSoC® 3 is a true system level solution providing microcontroller unit (MCU), memory,
analog, and digital peripheral functions in a single chip. The CY8C38 family offers a modern method of signal acquisition, signal
processing, and control with high accuracy, high bandwidth, and high flexibility. Analog capability spans the range from thermocouples
(near DC voltages) to ultrasonic signals. The CY8C38 family can handle dozens of data acquisition channels and analog inputs on
every general-purpose input/output (GPIO) pin. The CY8C38 family is also a high-performance configurable digital system with some
part numbers including interfaces such as USB, multimaster inter-integrated circuit (I2C), and controller area network (CAN). In
addition to communication interfaces, the CY8C38 family has an easy to configure logic array, flexible routing to all I/O pins, and a
high-performance single cycle 8051 microprocessor core. You can easily create system-level designs using a rich library of prebuilt
components and boolean primitives using PSoC Creator™, a hierarchical schematic design entry tool. The CY8C38 family provides
unparalleled opportunities for analog and digital bill of materials integration while easily accommodating last minute design changes
through simple firmware updates.
Features
Single cycle 8051 CPU
DC to 67 MHz operation
Multiply and divide instructions
Flash program memory, up to 64 KB, 100,000 write cycles,
20 years retention, and multiple security features
Up to 8-KB flash error correcting code (ECC) or configuration
storage
Up to 8 KB SRAM
Up to 2 KB electrically erasable programmable read-only
memory (EEPROM), 1 M cycles, and 20 years retention
24-channel direct memory access (DMA) with multilayer
AHB[1] bus access
• Programmable chained descriptors and priorities
• High bandwidth 32-bit transfer support
Low voltage, ultra low-power
Wide operating voltage range: 0.5 V to 5.5 V
High efficiency boost regulator from 0.5-V input through 1.8-V
to 5.0-V output
0.8 mA at 3 MHz, 1.2 mA at 6 MHz, and 6.6 mA at 48 MHz
Low-power modes including:
• 1-µA sleep mode with real time clock and low-voltage
detect (LVD) interrupt
• 200-nA hibernate mode with RAM retention
Versatile I/O system
28 to 72 I/O (62 GPIOs, eight special input/outputs (SIO),
two USBIOs[2])
Any GPIO to any digital or analog peripheral routability
LCD direct drive from any GPIO, up to 46 × 16 segments[2]
CapSense® support from any GPIO[3]
1.2-V to 5.5-V I/O interface voltages, up to four domains
Maskable, independent IRQ on any pin or port
Schmitt-trigger transistor-transistor logic (TTL) inputs
All GPIO configurable as open drain high/low,
pull-up/pull-down, High Z, or strong output
Configurable GPIO pin state at power-on reset (POR)
25 mA sink on SIO
Digital peripherals
20 to 24 programmable logic device (PLD) based universal
digital blocks (UDB)
Full CAN 2.0b 16 Rx, 8 Tx buffers[2]
Full-speed (FS) USB 2.0 12 Mbps using internal oscillator[2]
Up to four 16-bit configurable timer, counter, and PWM blocks
67 MHz, 24-bit fixed point digital filter block (DFB) to
implement FIR and IIR filters
Library of standard peripherals
• 8-, 16-, 24-, and 32-bit timers, counters, and PWMs
• Serial peripheral interface (SPI), universal asynchronous
transmitter receiver (UART), and I2C
• Many others available in catalog
Library of advanced peripherals
• Cyclic redundancy check (CRC)
• Pseudo random sequence (PRS) generator
• Local interconnect network (LIN) bus 2.0
• Quadrature decoder
Analog peripherals (1.71 V ≤ VDDA ≤ 5.5 V)
1.024 V ± 0.1% internal voltage reference across –40 °C to
+85 °C (14 ppm/°C)
Configurable delta-sigma ADC with 8- to 20-bit resolution
• Sample rates up to 192 ksps
• Programmable gain stage: ×0.25 to ×16
• 12-bit mode, 192 ksps, 66-dB signal to noise and distortion
ratio (SINAD), ±1-bit INL/DNL
• 16-bit mode, 48 ksps, 84-dB SINAD, ±2-bit INL, ±1-bit DNL
Up to four 8-bit, 8-Msps IDACs or 1-Msps VDACs
Four comparators with 95-ns response time
Up to four uncommitted opamps with 25-mA drive capability
Up to four configurable multifunction analog blocks. Example
configurations are programmable gain amplifier (PGA),
transimpedance amplifier (TIA), mixer, and sample and hold
CapSense support
Programming, debug, and trace
JTAG (4-wire), serial wire debug (SWD) (2-wire), and single
wire viewer (SWV) interfaces
Eight address and one data breakpoint
4-KB instruction trace buffer
Bootloader programming supportable through I2C, SPI,
UART, USB, and other interfaces
Precision, programmable clocking
3- to 62-MHz internal oscillator over full temperature and
voltage range
4- to 25-MHz crystal oscillator for crystal PPM accuracy
Internal PLL clock generation up to 67 MHz
32.768-kHz watch crystal oscillator
Low-power internal oscillator at 1, 33, and 100 kHz
Temperature and packaging
–40°C to +85 °C degrees industrial temperature
48-pin SSOP, 48-pin QFN, 68-pin QFN, and 100-pin TQFP
package options
Notes
1. AHB – AMBA (advanced microcontroller bus architecture) high-performance bus, an ARM data transfer bus
2. This feature on select devices only. See Ordering Information on page 118 for details.
3. GPIOs with opamp outputs are not recommended for use with CapSense.
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PSoC® 3: CY8C38 Family
Data Sheet
Document Number: 001-11729 Rev. *S Page 2 of 130
Contents
1. Architectural Overview .....................................................3
2. Pinouts ...............................................................................5
3. Pin Descriptions ..............................................................10
4. CPU ...................................................................................11
4.1 8051 CPU .................................................................11
4.2 Addressing Modes ....................................................11
4.3 Instruction Set ..........................................................11
4.4 DMA and PHUB .......................................................15
4.5 Interrupt Controller ...................................................17
5. Memory .............................................................................21
5.1 Static RAM ...............................................................21
5.2 Flash Program Memory ............................................21
5.3 Flash Security ...........................................................21
5.4 EEPROM ..................................................................21
5.5 Nonvolatile Latches (NVLs) ......................................22
5.6 External Memory Interface .......................................23
5.7 Memory Map ............................................................24
6. System Integration ..........................................................26
6.1 Clocking System .......................................................26
6.2 Power System ..........................................................29
6.3 Reset ........................................................................32
6.4 I/O System and Routing ...........................................33
7. Digital Subsystem ...........................................................39
7.1 Example Peripherals ................................................40
7.2 Universal Digital Block ..............................................42
7.3 UDB Array Description .............................................46
7.4 DSI Routing Interface Description ............................46
7.5 CAN ..........................................................................48
7.6 USB ..........................................................................49
7.7 Timers, Counters, and PWMs ..................................50
7.8 I2C ............................................................................50
7.9 Digital Filter Block .....................................................51
8. Analog Subsystem ..........................................................51
8.1 Analog Routing .........................................................52
8.2 Delta-sigma ADC ......................................................54
8.3 Comparators .............................................................55
8.4 Opamps ....................................................................57
8.5 Programmable SC/CT Blocks ..................................57
8.6 LCD Direct Drive ......................................................58
8.7 CapSense .................................................................59
8.8 Temp Sensor ............................................................59
8.9 DAC ..........................................................................59
8.10 Up/Down Mixer .......................................................60
8.11 Sample and Hold ....................................................60
9. Programming, Debug Interfaces, Resources ................61
9.1 JTAG Interface .........................................................61
9.2 Serial Wire Debug Interface .....................................63
9.3 Debug Features ........................................................64
9.4 Trace Features .........................................................64
9.5 Single Wire Viewer Interface ....................................64
9.6 Programming Features .............................................64
9.7 Device Security ........................................................64
10. Development Support ...................................................65
10.1 Documentation .......................................................65
10.2 Online .....................................................................65
10.3 Tools .......................................................................65
11. Electrical Specifications ...............................................66
11.1 Absolute Maximum Ratings ....................................66
11.2 Device Level Specifications ....................................67
11.3 Power Regulators ...................................................71
11.4 Inputs and Outputs .................................................75
11.5 Analog Peripherals .................................................82
11.6 Digital Peripherals ................................................101
11.7 Memory ................................................................105
11.8 PSoC System Resources .....................................111
11.9 Clocking ................................................................114
12. Ordering Information ...................................................118
12.1 Part Numbering Conventions ...............................119
13. Packaging .....................................................................120
14. Acronyms .....................................................................123
15. Reference Documents .................................................124
16. Document Conventions ..............................................124
16.1 Units of Measure ..................................................124
17. Revision History ..........................................................126
18. Sales, Solutions, and Legal Information .................130
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PSoC® 3: CY8C38 Family
Data Sheet
Document Number: 001-11729 Rev. *S Page 3 of 130
1. Architectural Overview
Introducing the CY8C38 family of ultra low-power, flash Programmable System-on-Chip (PSoC®) devices, part of a scalable 8-bit
PSoC 3 and 32-bit PSoC 5 platform. The CY8C38 family provides configurable blocks of analog, digital, and interconnect circuitry
around a CPU subsystem. The combination of a CPU with a flexible analog subsystem, digital subsystem, routing, and I/O enables
a high level of integration in a wide variety of consumer, industrial, and medical applications.
Figure 1-1. Simplified Block Diagram
Figure 1-1 illustrates the major components of the CY8C38
family. They are:
8051 CPU subsystem
Nonvolatile subsystem
Programming, debug, and test subsystem
Inputs and outputs
Clocking
Power
Digital subsystem
Analog subsystem
PSoC’s digital subsystem provides half of its unique
configurability. It connects a digital signal from any peripheral to
any pin through the digital system interconnect (DSI). It also
provides functional flexibility through an array of small, fast,
low-power UDBs. PSoC Creator provides a library of prebuilt and
tested standard digital peripherals (UART, SPI, LIN, PRS, CRC,
timer, counter, PWM, AND, OR, and so on) that are mapped to
the UDB array. You can also easily create a digital circuit using
boolean primitives by means of graphical design entry. Each
UDB contains programmable array logic (PAL)/programmable
logic device (PLD) functionality, together with a small state
machine engine to support a wide variety of peripherals.
In addition to the flexibility of the UDB array, PSoC also provides
configurable digital blocks targeted at specific functions. For the
CY8C38 family these blocks can include four 16-bit timers,
counters, and PWM blocks; I2C slave, master, and multimaster;
FS USB; and Full CAN 2.0b.
Digital
Filter
Block
Analog System
LCD Direct
Drive
CapSense
Temperature
Sensor
4 x
Opamp
+
-
ADC
4 x DAC
1 x
Del Sig
ADC
4 x SC/CT Blocks
(TIA, PGA, Mixer etc)
4 x
CMP
+
-
CAN
2.0
I2C
Master/
Slave
Universal Digital Block Array (24 x UDB)
4 x
Timer
Counter
PWM
FS USB
2.0
System Wide
Resources
Digital System
Program
Debug &
Trace
Boundary
Scan
Program
&
Debug
8051 or
Cortex M3 CPU
Interrupt
Controller
PHUB
DMA
SRAM
FLASH
EEPROM
EMIF
CPU SystemMemory System
System Bus
Digital Interconnect
Analog Interconnect
1.71 to
5.5 V
0.5 to 5.5 V
( Optional)
425MHz
(Optional)
Xtal
Osc
32.768 KHz
( Optional)
RTC
Timer
IMO
Clock Tree
WDT
and
Wake
ILO
Clocking System
1.8 V LDO
SMP
POR and
LVD
Sleep
Power
Power Management
System
USB
PHY
3 per
Opamp
GPIOs
GPIOs GPIOs
GPIOs
GPIOs
GPIOsSIO
GPIOsSIOs
UDB
UDB
UDB
UDB
UDB
UDB
UDB UDB UDB
UDB
UDB
UDBUDB UDB UDB
UART
Logic
12-bit PWM
I2C Slave 8-bit SPI
12-bit SPI
Logic
8-bit
Timer
16-bit PRS
UDB
8-bit
Timer
Quadrature Decoder 16-bit
PWM
Sequencer
Usage Example for UDB
UDB
UDB
UDB
UDB
UDB
UDB
UDB
UDB
22 Ω
V
V
to
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PSoC® 3: CY8C38 Family
Data Sheet
Document Number: 001-11729 Rev. *S Page 4 of 130
For more details on the peripherals see the “Example
Peripherals” section on page 40 of this data sheet. For
information on UDBs, DSI, and other digital blocks, see the
“Digital Subsystem” section on page 39 of this data sheet.
PSoC’s analog subsystem is the second half of its unique
configurability. All analog performance is based on a highly
accurate absolute voltage reference with less than 0.1-percent
error over temperature and voltage. The configurable analog
subsystem includes:
Analog muxes
Comparators
Voltage references
Analog-to-digital converter (ADC)
Digital-to-analog converters (DACs)
Digital filter block (DFB)
All GPIO pins can route analog signals into and out of the device
using the internal analog bus. This allows the device to interface
up to 62 discrete analog signals. The heart of the analog
subsystem is a fast, accurate, configurable delta-sigma ADC
with these features:
Less than 100 µV offset
A gain error of 0.2 percent
INL less than ±2 LSB
DNL less than ±1 LSB
SINAD better than 84 dB in 16-bit mode
This converter addresses a wide variety of precision analog
applications, including some of the most demanding sensors.
The output of the ADC can optionally feed the programmable
DFB through the DMA without CPU intervention. You can
configure the DFB to perform IIR and FIR digital filters and
several user-defined custom functions. The DFB can implement
filters with up to 64 taps. It can perform a 48-bit
multiply-accumulate (MAC) operation in one clock cycle.
Four high-speed voltage or current DACs support 8-bit output
signals at an update rate of up to 8 Msps. They can be routed
out of any GPIO pin. You can create higher resolution voltage
PWM DAC outputs using the UDB array. This can be used to
create a pulse width modulated (PWM) DAC of up to 10 bits, at
up to 48 kHz. The digital DACs in each UDB support PWM, PRS,
or delta-sigma algorithms with programmable widths. In addition
to the ADC, DACs, and DFB, the analog subsystem provides
multiple:
Uncommitted opamps
Configurable switched capacitor/continuous time (SC/CT)
blocks. These support:
Transimpedance amplifiers
Programmable gain amplifiers
Mixers
Other similar analog components
See the “Analog Subsystem” section on page 51 of this data
sheet for more details.
PSoC’s 8051 CPU subsystem is built around a single cycle
pipelined 8051 8-bit processor running at up to 67 MHz. The
CPU subsystem includes a programmable nested vector
interrupt controller, DMA controller, and RAM. PSoC’s nested
vector interrupt controller provides low latency by allowing the
CPU to vector directly to the first address of the interrupt service
routine, bypassing the jump instruction required by other
architectures. The DMA controller enables peripherals to
exchange data without CPU involvement. This allows the CPU
to run slower (saving power) or use those CPU cycles to improve
the performance of firmware algorithms. The single cycle 8051
CPU runs ten times faster than a standard 8051 processor. The
processor speed itself is configurable, allowing you to tune active
power consumption for specific applications.
PSoC’s nonvolatile subsystem consists of flash, byte-writeable
EEPROM, and nonvolatile configuration options. It provides up
to 64 KB of on-chip flash. The CPU can reprogram individual
blocks of flash, enabling bootloaders. You can enable an error
correcting code (ECC) for high reliability applications. A powerful
and flexible protection model secures the user's sensitive
information, allowing selective memory block locking for read
and write protection. Up to 2 KB of byte-writeable EEPROM is
available on-chip to store application data. Additionally, selected
configuration options such as boot speed and pin drive mode are
stored in nonvolatile memory. This allows settings to activate
immediately after POR.
The three types of PSoC I/O are extremely flexible. All I/Os have
many drive modes that are set at POR. PSoC also provides up
to four I/O voltage domains through the Vddio pins. Every GPIO
has analog I/O, LCD drive[4], CapSense[5], flexible interrupt
generation, slew rate control, and digital I/O capability. The SIOs
on PSoC allow VOH to be set independently of Vddio when used
as outputs. When SIOs are in input mode they are high
impedance. This is true even when the device is not powered or
when the pin voltage goes above the supply voltage. This makes
the SIO ideally suited for use on an I2C bus where the PSoC may
not be powered when other devices on the bus are. The SIO pins
also have high current sink capability for applications such as
LED drives. The programmable input threshold feature of the
SIO can be used to make the SIO function as a general purpose
analog comparator. For devices with Full-Speed USB the USB
physical interface is also provided (USBIO). When not using
USB these pins may also be used for limited digital functionality
and device programming. All of the features of the PSoC I/Os are
covered in detail in the “I/O System and Routing” section on
page 33 of this data sheet.
The PSoC device incorporates flexible internal clock generators,
designed for high stability and factory trimmed for high accuracy.
The internal main oscillator (IMO) is the master clock base for
the system, and has 1-percent accuracy at 3 MHz. The IMO can
be configured to run from 3 MHz up to 62 MHz. Multiple clock
derivatives can be generated from the main clock frequency to
meet application needs. The device provides a PLL to generate
system clock frequencies up to 67 MHz from the IMO, external
crystal, or external reference clock.
Notes
4. This feature on select devices only. See Ordering Information on page 118 for details.
5. GPIOs with opamp outputs are not recommended for use with CapSense.
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PSoC® 3: CY8C38 Family
Data Sheet
Document Number: 001-11729 Rev. *S Page 5 of 130
It also contains a separate, very low-power internal low-speed
oscillator (ILO) for the sleep and watchdog timers. A 32.768-kHz
external watch crystal is also supported for use in real-time
clock (RTC) applications. The clocks, together with
programmable clock dividers, provide the flexibility to integrate
most timing requirements.
The CY8C38 family supports a wide supply operating range from
1.71 V to 5.5 V. This allows operation from regulated supplies
such as 1.8 V ± 5%, 2.5 V ±10%, 3.3 V ± 10%, or 5.0 V ± 10%,
or directly from a wide range of battery types. In addition, it
provides an integrated high efficiency synchronous boost
converter that can power the device from supply voltages as low
as 0.5 V. This enables the device to be powered directly from a
single battery or solar cell. In addition, you can use the boost
converter to generate other voltages required by the device,
such as a 3.3-V supply for LCD glass drive. The boost’s output
is available on the Vboost pin, allowing other devices in the
application to be powered from the PSoC.
PSoC supports a wide range of low-power modes. These include
a 200-nA hibernate mode with RAM retention and a 1-µA sleep
mode with RTC. In the second mode, the optional 32.768-kHz
watch crystal runs continuously and maintains an accurate RTC.
Power to all major functional blocks, including the programmable
digital and analog peripherals, can be controlled independently
by firmware. This allows low-power background processing
when some peripherals are not in use. This, in turn, provides a
total device current of only 1.2 mA when the CPU is running at
6 MHz, or 0.8 mA running at 3 MHz.
The details of the PSoC power modes are covered in the “Power
System” section on page 29 of this data sheet.
PSoC uses JTAG (4-wire) or SWD (2-wire) interfaces for
programming, debug, and test. The 1-wire SWV may also be
used for ‘printf’ style debugging. By combining SWD and SWV,
you can implement a full debugging interface with just three pins.
Using these standard interfaces you can debug or program the
PSoC with a variety of hardware solutions from Cypress or third
party vendors. PSoC supports on-chip break points and 4-KB
instruction and data race memory for debug. Details of the
programming, test, and debugging interfaces are discussed in
the “Programming, Debug Interfaces, Resources” section on
page 61 of this data sheet.
2. Pinouts
The Vddio pin that supplies a particular set of pins is indicated
by the black lines drawn on the pinout diagrams in Figure 2-1
through Figure 2-4. Using the Vddio pins, a single PSoC can
support multiple interface voltage levels, eliminating the need for
off-chip level shifters. Each Vddio may sink up to 100 mA total to
its associated I/O pins and opamps. On the 68-pin and 100-pin
devices each set of Vddio associated pins may sink up to
100 mA. The 48-pin device may sink up to 100 mA total for all
Vddio0 plus Vddio2 associated I/O pins and 100 mA total for all
Vddio1 plus Vddio3 associated I/O pins.
Figure 2-1. 48-pin SSOP Part Pinout
SSOP
Vssa(SIO) P12[3] 247
Vcca(OpAmp2out, GPIO) P0[0] 346
P15[3] (GPIO, kHz XTAL: Xi)(OpAmp0out, GPIO) P0[1] 445
P12[0] (SIO, I2C1: SCL)Vddio0 742
P12[1] (SIO, I2C1: SDA)
643
(OpAmp0-/Extref0, GPIO) P0[3]
P15[1] (GPIO, MHz XTAL: Xi)(OpAmp2-, GPIO) P0[5] 940
P15[0] (GPIO, MHz XTAL: Xo)(IDAC0, GPIO) P0[6] 10 39
Vccd(IDAC2, GPIO) P0[7] 11 38
VssdVccd 12 37
Vddd
Vssd 13 36
P15[7] (USBIO, D-, SWDCK)Vddd 14 35
P15[6] (USBIO, D+, SWDIO)
(GPIO) P2[3] 15 34
P1[7] (GPIO)
(GPIO) P2[4] 16 33
P1[6] (GPIO)
Vddio2 17 32
Vddio1
(GPIO) P2[5] 18 31
P1[5] (GPIO, nTRST)(GPIO) P2[6] 19 30
P1[4] (GPIO, TDI)
(GPIO) P2[7] 20 29
P1[3] (GPIO, TDO, SWV)
Vssb 21 28
Ind 22 27
P1[1] (GPIO, TCK, SWDCK)
Vboost 23 26
P1[0] (GPIO, TMS, SWDIO)
Vbat 24 25
Vdda(SIO) P12[2] 148
Vddio3(OpAmp2+, GPIO) P0[4] 841
P15[2] (GPIO, kHz XTAL: Xo)(OpAmp0+, GPIO) P0[2] 544
Lines show
Vddio to I/O
supply
association
P1[2] (GPIO, configurable XRES)
[6]
[6]
Note
6. Pins are Do Not Use (DNU) on devices without USB. The pin must be left floating.
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PSoC® 3: CY8C38 Family
Data Sheet
Document Number: 001-11729 Rev. *S Page 6 of 130
Figure 2-2. 48-pin QFN Part Pinout[7]
QFN
(Top View)
Vddio2
Vddio0
10
11
12
Vssb
Ind
Vb
Vbat
35
34
33
32
31
30
29
28
27
26
25
36
48
47
46
45
44
43
42
41
40
39
38
37
1
2
3
4
5
6
7
8
9
13
14
15
16
17
18
19
20
21
22
23
24
Vddio1
(GPIO) P1[6]
Vddd
Vssd
Vccd
(GPIO, MHz XTAL: Xo) P15[0]
Vddio3
Vccd
P2[5] (GPIO)
(GPIO) P1[7]
(GPIO, MHz XTAL: Xi) P15[1]
Vcca
Vssa
Vdda
Vddd
Vssd
P12[2] (SIO)
P12[3] (SIO)
P0[0] (OpAmp2out, GPIO)
P0[1] (OpAmp0out, GPIO)
P0[2] (OpAmp0+, GPIO)
P0[3] (OpAmp0-/Extref0, GPIO)
P0[4] (OpAmp2+, GPIO)
P0[5] (OpAmp2-, GPIO)
P0[6] (IDAC0, GPIO)
P0[7] (IDAC2, GPIO)
P2[3] (GPIO)
P2[4] (GPIO)
(GPIO) P2[6]
(GPIO) P2[7]
(GPIO, nTRST) P1[5]
(GPIO, TDI) P1[4]
(GPIO, TDO, SWV) P1[3]
(GPIO, TCK, SWDCK) P1[1]
(GPIO, TMS, SWDIO) P1[0]
(GPIO, Configurable XRES) P1[2]
(SIO, I2C1: SCL) P12[0]
P12[1] (SIO, I2C1: SDA)
P15[3] (GPIO, kHz XTAL: Xi)
P15[2] (GPIO, kHz XTAL: Xo)
(USBIO, D-, SWDCK) P15[7]
(USBIO, D+, SWDIO) P15[6]
Lines show
Vddio to I/O
supply
association
[8]
[8]
Notes
7. Pins are Do Not Use (DNU) on devices without USB. The pin must be left floating.
8. The center pad on the QFN package should be connected to digital ground (VSSD) for best mechanical, thermal, and electrical performance. If not connected to ground,
it should be electrically floated and not connected to any other signal.
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PSoC® 3: CY8C38 Family
Data Sheet
Document Number: 001-11729 Rev. *S Page 7 of 130
Figure 2-3. 68-pin QFN Part Pinout[9]
Notes
9. The center pad on the QFN package should be connected to digital ground (VSSD) for best mechanical, thermal, and electrical performance. If not connected to
ground, it should be electrically floated and not connected to any other signal.
10. Pins are Do Not Use (DNU) on devices without USB. The pin must be left floating.
[10]
[10]
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PSoC® 3: CY8C38 Family
Data Sheet
Document Number: 001-11729 Rev. *S Page 8 of 130
Figure 2-4. 100-pin TQFP Part Pinout
Figure 2-5 and Figure 2-6 show an example schematic and an example PCB layout, for the 100-pin TQFP part, for optimal analog
performance on a two-layer board.
The two pins labeled Vddd must be connected together.
The two pins labeled Vccd must be connected together, with capacitance added, as shown in Figure 2-5 and Power System on
page 29. The trace between the two Vccd pins should be as short as possible.
The two pins labeled Vssd must be connected together.
For information on circuit board layout issues for mixed signals, refer to the application note, AN57821 - Mixed Signal Circuit Board
Layout Considerations for PSoC® 3 and PSoC 5.
TQFP
(GPIO) P2[5]
(GPIO) P2[6]
(GPIO) P2[7]
(I2C0: SCL, SIO) P12[4]
(I2C0: SDA, SIO) P12[5]
(GPIO) P6[4]
(GPIO) P6[5]
(GPIO) P6[6]
(GPIO) P6[7]
Vssb
Ind
Vboost
Vbat
Vssd
XRES
(GPIO) P5[0]
(GPIO) P5[1]
(GPIO) P5[2]
(GPIO) P5[3]
(TMS, SWDIO, GPIO) P1[0]
(TCK, SWDCK, GPIO) P1[1]
(configurable XRES, GPIO) P1[2]
(TDO, SWV, GPIO) P1[3]
(TDI, GPIO) P1[4]
(nTRST, GPIO) P1[5]
Vddio1
(GPIO) P5[7]
NC
(OpAmp3-/Extref1, GPIO) P3[2]
(GPIO) P1[6]
(GPIO) P1[7]
(SIO) P12[6]
(SIO) P12[7]
(GPIO) P5[4]
(GPIO) P5[5]
(GPIO) P5[6]
(USBIO, D+, SWDIO) P15[6]
(USBIO, D-, SWDCK) P15[7]
Vddd
Vssd
Vccd
NC
(MHz XTAL: Xo, GPIO) P15[0]
(MHz XTAL: Xi, GPIO) P15[1]
(IDAC1, GPIO) P3[0]
(IDAC3, GPIO) P3[1]
(OpAmp3+, GPIO) P3[3]
(OpAmp1-, GPIO) P3[4]
(OpAmp1+, GPIO) P3[5]
Vddio3
Vddio0
P0[3] (GPIO, OpAmp0-/Extref0)
P0[2] (GPIO, OpAmp0+)
P0[1] (GPIO, OpAmp0out)
P0[0] (GPIO, OpAmp2out)
P4[1] (GPIO)
P4[0] (GPIO)
P12[3] (SIO)
P12[2] (SIO)
Vssd
Vdda
Vssa
Vcca
NC
NC
NC
NC
NC
NC
P15[3] (GPIO, kHz XTAL: Xi)
P15[2] (GPIO, kHz XTAL: Xo)
P12[1] (SIO, I2C1: SDA)
P12[0] (SIO, I2C1: SCL)
P3[7] (GPIO, OpAmp3out)
P3[6] (GPIO, OpAmp1out)
Vddio2
P2[4] (GPIO)
P2[3] (GPIO)
P2[2] (GPIO)
P2[1] (GPIO)
P2[0] (GPIO)
P15[5] (GPIO)
P15[4] (GPIO)
P6[3] (GPIO)
P6[2] (GPIO)
P6[1] (GPIO)
P6[0] (GPIO)
Vddd
Vssd
Vccd
P4[7] (GPIO)
P4[6] (GPIO)
P4[5] (GPIO)
P4[4] (GPIO)
P4[3] (GPIO)
P4[2] (GPIO)
P0[7] (GPIO, IDAC2)
P0[6] (GPIO, IDAC0)
P0[5] (GPIO, OpAmp2-)
P0[4] (GPIO, OpAmp2+)
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
1
2
3
4
5
6
7
8
9
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
50
49
Lines show Vddio
to I/O supply
association
[11]
[11]
Note
11. Pins are Do Not Use (DNU) on devices without USB. The pin must be left floating.
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Data Sheet
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Figure 2-5. Example Schematic for 100-pin TQFP Part with Power Connections
Note The two Vccd pins must be connected together with as short a trace as possible. A trace under the device is recommended, as
shown in Figure 2-6 on page 10.
Vssb
10
Ind
11
Vboost
12
Vbat
13
Vssd
14
XRES
15
Vddd
37
Vssd
38
Vccd
39
Vcca 63
Vssa 64
Vdda 65
Vssd 66
Vccd 86
Vssd 87
Vddd 88
SIO, P12[2] 67
SIO, P12[3] 68
P4[0] 69
P4[1] 70
OA2out, P0[0] 71
OA0out, P0[1] 72
OA0+, P0[2] 73
OA0-, REF0, P0[3] 74
Vddio0 75
OA2+, P0[4] 76
OA2-, P0[5] 77
IDAC0, P0[6] 78
IDAC2, P0[7] 79
P4[2] 80
P4[3] 81
P4[4] 82
P4[5] 83
P4[6] 84
P4[7] 85
P5[0]
16
P5[1]
17
P5[2]
18
P5[3]
19
P1[0], SWIO, TMS
20
P1[1], SWDIO, TCK
21
P1[2]
22
P1[3], SWV, TDO
23
P1[4], TDI
24
P1[5], nTRST
25
Vddio1
26
P1[6]
27
P1[7]
28
P12[6], SIO
29
P12[7], SIO
30
P5[4]
31
P5[5]
32
P5[6]
33
P5[7]
34
USB D+, P15[6]
35
USB D-, P15[7]
36
P6[7]
9
P6[0] 89
P6[1] 90
P6[2] 91
P6[3] 92
P15[4] 93
P15[5] 94
P2[0] 95
P2[1] 96
P2[2] 97
P2[3] 98
P2[4] 99
Vddio2 100
P2[5]
1
P2[6]
2
P2[7]
3
P12[4], SIO
4
P12[5], SIO
5
P6[4]
6
P6[5]
7
P6[6]
8
NC
40
NC
41
P15[0], MHzXout
42
P15[1], MHzXin
43
P3[0], IDAC1
44
P3[1], IDAC3
45
P3[2], OA3-, REF1
46
P3[3], OA3+
47
P3[4], OA1-
48
P3[5], OA1+
49
Vddio3
50
OA1out, P3[6] 51
OA3out, P3[7] 52
SIO, P12[0] 53
SIO, P12[1] 54
kHzXout, P15[2] 55
kHzXin, P15[3] 56
NC 57
NC 58
NC 59
NC 60
NC 61
NC 62
U2
CY8C55xx
Vssd
Vdda
Vcca
Vccd
Vssd
Vddd
Vssd
Vddd
Vddd
Vssd
P32
Vssa
Vssa
Vssd
Vssd
Vssd
Vssd
0.1 uF
C8
Vssd
Vddd
Vddd Vddd
Vddd
Vssa Vssa
Vddd
Vssd
1 uF
C9
0.1 uF
C10
0.1 uF
C11
0.1 uF
C14
0.1 uF
C16
0.1 uF
C12
0.1 uF
C6
0.1 uF
C2
1 uF
C15
1 uF
C1
Vssd
Vddd
Vssd
Vdda
Vssd
Vccd
10 uF, 6.3 V
C13
1 uF
C17
Vssa
Vdda
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Data Sheet
Document Number: 001-11729 Rev. *S Page 10 of 130
Figure 2-6. Example PCB Layout for 100-pin TQFP Part for Optimal Analog Performance
3. Pin Descriptions
IDAC0, IDAC1, IDAC2, IDAC3
Low resistance output pin for high current DACs (IDAC).
OpAmp0out, OpAmp1out, OpAmp2out, OpAmp3out
High current output of uncommitted opamp[12].
Extref0, Extref1
External reference input to the analog system.
OpAmp0–, OpAmp1–, OpAmp2–, OpAmp3–
Inverting input to uncommitted opamp.
OpAmp0+, OpAmp1+, OpAmp2+, OpAmp3+
Noninverting input to uncommitted opamp.
GPIO
General purpose I/O pin provides interfaces to the CPU, digital
peripherals, analog peripherals, interrupts, LCD segment drive,
and CapSense[12].
I2C0: SCL, I2C1: SCL
I2C SCL line providing wake from sleep on an address match.
Any I/O pin can be used for I2C SCL if wake from sleep is not
required.
I2C0: SDA, I2C1: SDA
I2C SDA line providing wake from sleep on an address match.
Any I/O pin can be used for I2C SDA if wake from sleep is not
required.
Ind
Inductor connection to boost pump.
kHz XTAL: Xo, kHz XTAL: Xi
32.768-kHz crystal oscillator pin.
MHz XTAL: Xo, MHz XTAL: Xi
4- to 25-MHz crystal oscillator pin.
nTRST
Optional JTAG test reset programming and debug port
connection to reset the JTAG connection.
SIO
Special I/O provides interfaces to the CPU, digital peripherals
and interrupts with a programmable high threshold voltage,
analog comparator, high sink current, and high impedance state
when the device is unpowered.
SWDCK
Serial wire debug clock programming and debug port
connection.
SWDIO
Serial wire debug input and output programming and debug port
connection.
SWV.
Single wire viewer debug output.
TCK
JTAG test clock programming and debug port connection.
TDI
JTAG test data in programming and debug port connection.
TDO
JTAG test data out programming and debug port connection.
Vddd Vssd Vdda
Vssa
Vssd
Plane
Vssa
Plane
Note
12. GPIOs with opamp outputs are not recommended for use with CapSense.
[+] Feedback
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Data Sheet
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TMS
JTAG test mode select programming and debug port connection.
USBIO, D+
Provides D+ connection directly to a USB 2.0 bus. May be used
as a digital I/O pin; it is powered from VDDD instead of from a
Vddio. Pins are Do Not Use (DNU) on devices without USB.
USBIO, D–
Provides D– connection directly to a USB 2.0 bus. May be used
as a digital I/O pin; it is powered from VDDD instead of from a
Vddio. Pins are Do Not Use (DNU) on devices without USB.
Vboost
Power sense connection to boost pump.
Vbat
Battery supply to boost pump.
Vcca
Output of analog core regulator and input to analog core.
Requires a 1-µF capacitor to VSSA. Regulator output not for
external use.
Vccd
Output of digital core regulator and input to digital core. The two
VCCD pins must be shorted together, with the trace between
them as short as possible, and a 1-µF capacitor to VSSD; see
Power System on page 29. Regulator output not for external use.
Vdda
Supply for all analog peripherals and analog core regulator.
Vdda must be the highest voltage present on the device. All
other supply pins must be less than or equal to Vdda.
Vddd
Supply for all digital peripherals and digital core regulator. Vddd
must be less than or equal to Vdda.
Vssa
Ground for all analog peripherals.
Vssb
Ground connection for boost pump.
Vssd
Ground for all digital logic and I/O pins.
Vddio0, Vddio1, Vddio2, Vddio3
Supply for I/O pins. Each Vddio must be tied to a valid operating
voltage (1.71 V to 5.5 V), and must be less than or equal to Vdda.
If the I/O pins associated with Vddio0, Vddio2, or Vddio3 are not
used then that Vddio should be tied to ground (Vssd or Vssa).
XRES (and configurable XRES)
External reset pin. Active low with internal pull-up. Pin P1[2] may
be configured to be a XRES pin; see “Nonvolatile Latches
(NVLs)” on page 22.
4. CPU
4.1 8051 CPU
The CY8C38 devices use a single cycle 8051 CPU, which is fully
compatible with the original MCS-51 instruction set. The
CY8C38 family uses a pipelined RISC architecture, which
executes most instructions in 1 to 2 cycles to provide peak
performance of up to 33 MIPS with an average of 2 cycles per
instruction. The single cycle 8051 CPU runs ten times faster than
a standard 8051 processor.
The 8051 CPU subsystem includes these features:
Single cycle 8051 CPU
Up to 64 KB of flash memory, up to 2 KB of EEPROM, and up
to 8 KB of SRAM
Programmable nested vector interrupt controller
DMA controller
Peripheral HUB (PHUB)
External memory interface (EMIF)
4.2 Addressing Modes
The following addressing modes are supported by the 8051:
Direct Addressing: The operand is specified by a direct 8-bit
address field. Only the internal RAM and the SFRs can be
accessed using this mode.
Indirect Addressing: The instruction specifies the register which
contains the address of the operand. The registers R0 or R1
are used to specify the 8-bit address, while the data pointer
(DPTR) register is used to specify the 16-bit address.
Register Addressing: Certain instructions access one of the
registers (R0 to R7) in the specified register bank. These
instructions are more efficient because there is no need for an
address field.
Register Specific Instructions: Some instructions are specific
to certain registers. For example, some instructions always act
on the accumulator. In this case, there is no need to specify the
operand.
Immediate Constants: Some instructions carry the value of the
constants directly instead of an address.
Indexed Addressing: This type of addressing can be used only
for a read of the program memory. This mode uses the Data
Pointer as the base and the accumulator value as an offset to
read a program memory.
Bit Addressing: In this mode, the operand is one of 256 bits.
4.3 Instruction Set
The 8051 instruction set is highly optimized for 8-bit handling and
Boolean operations. The types of instructions supported include:
Arithmetic instructions
Logical instructions
Data transfer instructions
Boolean instructions
Program branching instructions
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4.3.1 Instruction Set Summary
4.3.1.1 Arithmetic Instructions
Arithmetic instructions support the direct, indirect, register, immediate constant, and register-specific instructions. Arithmetic modes
are used for addition, subtraction, multiplication, division, increment, and decrement operations. Tab le 4 -1 lists the different arithmetic
instructions.
4.3.1.2 Logical Instructions
The logical instructions perform Boolean operations such as AND, OR, XOR on bytes, rotate of accumulator contents, and swap of
nibbles in an accumulator. The Boolean operations on the bytes are performed on the bit-by-bit basis. Table 4-2 shows the list of
logical instructions and their description.
Table 4-1. Arithmetic Instructions
Mnemonic Description Bytes Cycles
ADD A,Rn Add register to accumulator 1 1
ADD A,Direct Add direct byte to accumulator 2 2
ADD A,@Ri Add indirect RAM to accumulator 1 2
ADD A,#data Add immediate data to accumulator 2 2
ADDC A,Rn Add register to accumulator with carry 1 1
ADDC A,Direct Add direct byte to accumulator with carry 2 2
ADDC A,@Ri Add indirect RAM to accumulator with carry 1 2
ADDC A,#data Add immediate data to accumulator with carry 2 2
SUBB A,Rn Subtract register from accumulator with borrow 1 1
SUBB A,Direct Subtract direct byte from accumulator with borrow 2 2
SUBB A,@Ri Subtract indirect RAM from accumulator with borrow 1 2
SUBB A,#data Subtract immediate data from accumulator with borrow 2 2
INC A Increment accumulator 1 1
INC Rn Increment register 1 2
INC Direct Increment direct byte 2 3
INC @Ri Increment indirect RAM 1 3
DEC A Decrement accumulator 1 1
DEC Rn Decrement register 1 2
DEC Direct Decrement direct byte 2 3
DEC @Ri Decrement indirect RAM 1 3
INC DPTR Increment data pointer 1 1
MUL Multiply accumulator and B 1 2
DIV Divide accumulator by B 1 6
DAA Decimal adjust accumulator 1 3
Table 4-2. Logical Instructions
Mnemonic Description Bytes Cycles
ANL A,Rn AND register to accumulator 1 1
ANL A,Direct AND direct byte to accumulator 2 2
ANL A,@Ri AND indirect RAM to accumulator 1 2
ANL A,#data AND immediate data to accumulator 2 2
ANL Direct, A AND accumulator to direct byte 2 3
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4.3.1.3 Data Transfer Instructions
The data transfer instructions are of three types: the core RAM,
xdata RAM, and the lookup tables. The core RAM transfer
includes transfer between any two core RAM locations or SFRs.
These instructions can use direct, indirect, register, and
immediate addressing. The xdata RAM transfer includes only the
transfer between the accumulator and the xdata RAM location.
It can use only indirect addressing. The lookup tables involve
nothing but the read of program memory using the Indexed
addressing mode. Table 4-3 lists the various data transfer
instructions available.
4.3.1.4 Boolean Instructions
The 8051 core has a separate bit-addressable memory location.
It has 128 bits of bit addressable RAM and a set of SFRs that are
bit addressable. The instruction set includes the whole menu of
bit operations such as move, set, clear, toggle, OR, and AND
instructions and the conditional jump instructions. Ta b le 4 -4 lists
the available Boolean instructions.
ANL Direct, #data AND immediate data to direct byte 3 3
ORL A,Rn OR register to accumulator 1 1
ORL A,Direct OR direct byte to accumulator 2 2
ORL A,@Ri OR indirect RAM to accumulator 1 2
ORL A,#data OR immediate data to accumulator 2 2
ORL Direct, A OR accumulator to direct byte 2 3
ORL Direct, #data OR immediate data to direct byte 3 3
XRL A,Rn XOR register to accumulator 1 1
XRL A,Direct XOR direct byte to accumulator 2 2
XRL A,@Ri XOR indirect RAM to accumulator 1 2
XRL A,#data XOR immediate data to accumulator 2 2
XRL Direct, A XOR accumulator to direct byte 2 3
XRL Direct, #data XOR immediate data to direct byte 3 3
CLR A Clear accumulator 1 1
CPL A Complement accumulator 1 1
RL A Rotate accumulator left 1 1
RLC A Rotate accumulator left through carry 1 1
RR A Rotate accumulator right 1 1
RRC A Rotate accumulator right though carry 1 1
SWAP A Swap nibbles within accumulator 1 1
Table 4-2. Logical Instructions (continued)
Mnemonic Description Bytes Cycles
Table 4-3. Data Transfer Instructions
Mnemonic Description Bytes Cycles
MOV A,Rn Move register to accumulator 1 1
MOV A,Direct Move direct byte to accumulator 2 2
MOV A,@Ri Move indirect RAM to accumulator 1 2
MOV A,#data Move immediate data to accumulator 2 2
MOV Rn,A Move accumulator to register 1 1
MOV Rn,Direct Move direct byte to register 2 3
MOV Rn, #data Move immediate data to register 2 2
MOV Direct, A Move accumulator to direct byte 2 2
MOV Direct, Rn Move register to direct byte 2 2
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MOV Direct, Direct Move direct byte to direct byte 3 3
MOV Direct, @Ri Move indirect RAM to direct byte 2 3
MOV Direct, #data Move immediate data to direct byte 3 3
MOV @Ri, A Move accumulator to indirect RAM 1 2
MOV @Ri, Direct Move direct byte to indirect RAM 2 3
MOV @Ri, #data Move immediate data to indirect RAM 2 2
MOV DPTR, #data16 Load data pointer with 16 bit constant 3 3
MOVC A, @A+DPTR Move code byte relative to DPTR to accumulator 1 5
MOVC A, @A + PC Move code byte relative to PC to accumulator 1 4
MOVX A,@Ri Move external RAM (8-bit) to accumulator 1 4
MOVX A, @DPTR Move external RAM (16-bit) to accumulator 1 3
MOVX @Ri, A Move accumulator to external RAM (8-bit) 1 5
MOVX @DPTR, A Move accumulator to external RAM (16-bit) 1 4
PUSH Direct Push direct byte onto stack 2 3
POP Direct Pop direct byte from stack 2 2
XCH A, Rn Exchange register with accumulator 1 2
XCH A, Direct Exchange direct byte with accumulator 2 3
XCH A, @Ri Exchange indirect RAM with accumulator 1 3
XCHD A, @Ri Exchange low order indirect digit RAM with accumulator 1 3
Table 4-4. Boolean Instructions
Mnemonic Description Bytes Cycles
CLR C Clear carry 1 1
CLR bit Clear direct bit 2 3
SETB C Set carry 1 1
SETB bit Set direct bit 2 3
CPL C Complement carry 1 1
CPL bit Complement direct bit 2 3
ANL C, bit AND direct bit to carry 2 2
ANL C, /bit AND complement of direct bit to carry 2 2
ORL C, bit OR direct bit to carry 2 2
ORL C, /bit OR complement of direct bit to carry 2 2
MOV C, bit Move direct bit to carry 2 2
MOV bit, C Move carry to direct bit 2 3
JC rel Jump if carry is set 2 3
JNC rel Jump if no carry is set 2 3
JB bit, rel Jump if direct bit is set 3 5
JNB bit, rel Jump if direct bit is not set 3 5
JBC bit, rel Jump if direct bit is set and clear bit 3 5
Table 4-3. Data Transfer Instructions (continued)
Mnemonic Description Bytes Cycles
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Data Sheet
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4.3.1.5 Program Branching Instructions
The 8051 supports a set of conditional and unconditional jump instructions that help to modify the program execution flow. Table 4-5
shows the list of jump instructions.
4.4 DMA and PHUB
The PHUB and the DMA controller are responsible for data
transfer between the CPU and peripherals, and also data
transfers between peripherals. The PHUB and DMA also control
device configuration during boot. The PHUB consists of:
A central hub that includes the DMA controller, arbiter, and
router
Multiple spokes that radiate outward from the hub to most
peripherals
There are two PHUB masters: the CPU and the DMA controller.
Both masters may initiate transactions on the bus. The DMA
channels can handle peripheral communication without CPU
intervention. The arbiter in the central hub determines which
DMA channel is the highest priority if there are multiple requests.
4.4.1 PHUB Features
CPU and DMA controller are both bus masters to the PHUB
Eight multi-layer AHB bus parallel access paths (spokes) for
peripheral access
Simultaneous CPU and DMA access to peripherals located on
different spokes
Simultaneous DMA source and destination burst transactions
on different spokes
Supports 8-, 16-, 24-, and 32-bit addressing and data
Table 4-5. Jump Instructions
Mnemonic Description Bytes Cycles
ACALL addr11 Absolute subroutine call 2 4
LCALL addr16 Long subroutine call 3 4
RET Return from subroutine 1 4
RETI Return from interrupt 1 4
AJMP addr11 Absolute jump 2 3
LJMP addr16 Long jump 3 4
SJMP rel Short jump (relative address) 2 3
JMP @A + DPTR Jump indirect relative to DPTR 1 5
JZ rel Jump if accumulator is zero 2 4
JNZ rel Jump if accumulator is nonzero 2 4
CJNE A,Direct, rel Compare direct byte to accumulator and jump if not equal 3 5
CJNE A, #data, rel Compare immediate data to accumulator and jump if not equal 3 4
CJNE Rn, #data, rel Compare immediate data to register and jump if not equal 3 4
CJNE @Ri, #data, rel Compare immediate data to indirect RAM and jump if not equal 3 5
DJNZ Rn,rel Decrement register and jump if not zero 2 4
DJNZ Direct, rel Decrement direct byte and jump if not zero 3 5
NOP No operation 1 1
Table 4-6. PHUB Spokes and Peripherals
PHUB Spokes Peripherals
0SRAM
1IOs, PICU, EMIF
2 PHUB local configuration, Power manager,
Clocks, IC, SWV, EEPROM, Flash
programming interface
3Analog interface and trim, Decimator
4USB, CAN, I2C, Timers, Counters, and PWMs
5DFB
6UDBs group 1
7UDBs group 2
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4.4.2 DMA Features
24 DMA channels
Each channel has one or more transaction descriptors (TD) to
configure channel behavior. Up to 128 total TDs can be defined
TDs can be dynamically updated
Eight levels of priority per channel
Any digitally routable signal, the CPU, or another DMA channel,
can trigger a transaction
Each channel can generate up to two interrupts per transfer
Transactions can be stalled or canceled
Supports transaction size of infinite or 1 to 64 KB
TDs may be nested and/or chained for complex transactions
4.4.3 Priority Levels
The CPU always has higher priority than the DMA controller
when their accesses require the same bus resources. Due to the
system architecture, the CPU can never starve the DMA. DMA
channels of higher priority (lower priority number) may interrupt
current DMA transfers. In the case of an interrupt, the current
transfer is allowed to complete its current transaction. To ensure
latency limits when multiple DMA accesses are requested
simultaneously, a fairness algorithm guarantees an interleaved
minimum percentage of bus bandwidth for priority levels 2
through 7. Priority levels 0 and 1 do not take part in the fairness
algorithm and may use 100 percent of the bus bandwidth. If a tie
occurs on two DMA requests of the same priority level, a simple
round robin method is used to evenly share the allocated
bandwidth. The round robin allocation can be disabled for each
DMA channel, allowing it to always be at the head of the line.
Priority levels 2 to 7 are guaranteed the minimum bus bandwidth
shown in Tab le 4 - 7 after the CPU and DMA priority levels 0 and
1 have satisfied their requirements.
When the fairness algorithm is disabled, DMA access is granted
based solely on the priority level; no bus bandwidth guarantees
are made.
4.4.4 Transaction Modes Supported
The flexible configuration of each DMA channel and the ability to
chain multiple channels allow the creation of both simple and
complex use cases. General use cases include, but are not
limited to:
4.4.4.1 Simple DMA
In a simple DMA case, a single TD transfers data between a
source and sink (peripherals or memory location). The basic
timing diagrams of DMA read and write cycles are shown in
Figure 4-1. For more description on other transfer modes, refer
to the Technical Reference Manual.
Figure 4-1. DMA Timing Diagram
Table 4-7. Priority Levels
Priority Level % Bus Bandwidth
0 100.0
1 100.0
2 50.0
3 25.0
4 12.5
56.2
63.1
71.5
CLK
ADDR 16/32
WRITE
DATA
READY
Basic DMA Read Transfer without wait states
AB
DATA (A)
ADDRESS Phase DATA Phase
AB
ADDRESS Phase DATA Phase
CLK
WRITE
DATA
READY
DATA (A)
Basic DMA Write Transfer without wait states
ADDR 16/32
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PSoC® 3: CY8C38 Family
Data Sheet
Document Number: 001-11729 Rev. *S Page 17 of 130
4.4.4.2 Auto Repeat DMA
Auto repeat DMA is typically used when a static pattern is
repetitively read from system memory and written to a peripheral.
This is done with a single TD that chains to itself.
4.4.4.3 Ping Pong DMA
A ping pong DMA case uses double buffering to allow one buffer
to be filled by one client while another client is consuming the
data previously received in the other buffer. In its simplest form,
this is done by chaining two TDs together so that each TD calls
the opposite TD when complete.
4.4.4.4 Circular DMA
Circular DMA is similar to ping pong DMA except it contains more
than two buffers. In this case there are multiple TDs; after the last
TD is complete it chains back to the first TD.
4.4.4.5 Scatter Gather DMA
In the case of scatter gather DMA, there are multiple
noncontiguous sources or destinations that are required to
effectively carry out an overall DMA transaction. For example, a
packet may need to be transmitted off of the device and the
packet elements, including the header, payload, and trailer, exist
in various noncontiguous locations in memory. Scatter gather
DMA allows the segments to be concatenated together by using
multiple TDs in a chain. The chain gathers the data from the
multiple locations. A similar concept applies for the reception of
data onto the device. Certain parts of the received data may need
to be scattered to various locations in memory for software
processing convenience. Each TD in the chain specifies the
location for each discrete element in the chain.
4.4.4.6 Packet Queuing DMA
Packet queuing DMA is similar to scatter gather DMA but
specifically refers to packet protocols. With these protocols,
there may be separate configuration, data, and status phases
associated with sending or receiving a packet.
For instance, to transmit a packet, a memory mapped
configuration register can be written inside a peripheral,
specifying the overall length of the ensuing data phase. The CPU
can set up this configuration information anywhere in system
memory and copy it with a simple TD to the peripheral. After the
configuration phase, a data phase TD (or a series of data phase
TDs) can begin (potentially using scatter gather). When the data
phase TD(s) finish, a status phase TD can be invoked that reads
some memory mapped status information from the peripheral
and copies it to a location in system memory specified by the
CPU for later inspection. Multiple sets of configuration, data, and
status phase ‘subchains’ can be strung together to create larger
chains that transmit multiple packets in this way. A similar
concept exists in the opposite direction to receive the packets.
4.4.4.7 Nested DMA
One TD may modify another TD, as the TD configuration space
is memory mapped similar to any other peripheral. For example,
a first TD loads a second TD’s configuration and then calls the
second TD. The second TD moves data as required by the
application. When complete, the second TD calls the first TD,
which again updates the second TD’s configuration. This
process repeats as often as necessary.
4.5 Interrupt Controller
The interrupt controller provides a mechanism for hardware
resources to change program execution to a new address,
independent of the current task being executed by the main
code. The interrupt controller provides enhanced features not
found on original 8051 interrupt controllers:
Thirty-two interrupt vectors
Jumps directly to ISR anywhere in code space with dynamic
vector addresses
Multiple sources for each vector
Flexible interrupt to vector matching
Each interrupt vector is independently enabled or disabled
Each interrupt can be dynamically assigned one of eight
priorities
Eight level nestable interrupts
Multiple I/O interrupt vectors
Software can send interrupts
Software can clear pending interrupts
Figure 4-2 on page 18 represents typical flow of events when an
interrupt triggered. Figure 4-3 on page 19 shows the interrupt
structure and priority polling.
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Document Number: 001-11729 Rev. *S Page 18 of 130
PSoC® 3: CY8C38 Family
Data Sheet
Figure 4-2. Interrupt Processing Timing Diagram
Notes
1: Interrupt triggered asynchronous to the clock
2: The PEND bit is set on next active clock edge to indicate the interrupt arrival
3: POST bit is set following the PEND bit
4: Interrupt request and the interrupt number sent to CPU core after evaluation priority (Takes 3 clocks)
5: ISR address is posted to CPU core for branching
6: CPU acknowledges the interrupt request
7: ISR address is read by CPU for branching
8, 9: PEND and POST bits are cleared respectively after receiving the IRA from core
10: IRA bit is cleared after completing the current instruction and starting the instruction execution from ISR location (Takes 7 cycles)
11: IRC is set to indicate the completion of ISR, Active int. status is restored with previous status
The total interrupt latency (ISR execution)
= POST + PEND + IRQ + IRA + Completing current instruction and branching
= 1+1+1+2+7 cycles
= 12 cycles
The active interrupt ISR
address is posted to core
Interrupt generation and posting to CPU
The active interrupt
number is posted to core
Interrupt request sent to core for processing
Interrupt is posted to ascertain the priority
Pend bit is set on next system clock active edge
Arrival of new Interrupt
CLK
INT_INPUT
PEND
POST
IRQ
ACTIVE_INT_NUM
(#10)
INT_VECT_ADDR
IRA
IRC
S
S
S
S
S
S
S
S
S
S
S
0x0010NA
CPU Response
Int. State
Clear Completing current instruction and branching to vector address Complete ISR and return
NA
IRQ cleared after receiving IRA
POST and PEND bits cleared after IRQ is sleared
0x0000
NA
TIME
1 2 3 4 5 6 7 8 9 10 11
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Data Sheet
Document Number: 001-11729 Rev. *S Page 19 of 130
Figure 4-3. Interrupt Structure
When an interrupt is pending, the current instruction is
completed and the program counter is pushed onto the stack.
Code execution then jumps to the program address provided by
the vector. After the ISR is completed, a RETI instruction is
executed and returns execution to the instruction following the
previously interrupted instruction. To do this the RETI instruction
pops the program counter from the stack.
If the same priority level is assigned to two or more interrupts,
the interrupt with the lower vector number is executed first. Each
interrupt vector may choose from three interrupt sources: Fixed
Function, DMA, and UDB. The fixed function interrupts are direct
connections to the most common interrupt sources and provide
the lowest resource cost connection. The DMA interrupt sources
provide direct connections to the two DMA interrupt sources
provided per DMA channel. The third interrupt source for vectors
is from the UDB digital routing array. This allows any digital signal
available to the UDB array to be used as an interrupt source.
Fixed function interrupts and all interrupt sources may be routed
to any interrupt vector using the UDB interrupt source
connections.
Interrupts 0 to 30
from UDBs
Interrupt
routing logic
to select 31
sources
Interrupt 2 to 29
0
1
30
Individual
Enable Disable
bits
Global Enable
disable bit
Interrupt Enable/
Disable, PEND and
POST logic
Interrupts form Fixed
function blocks, DMA and
UDBs
8 Level
Priority
decoder
for all
interrupts
Polling sequence
Highest Priority
Lowest Priority
Interrupt Polling logic
IRC
IRA
IRQ
0 to 30
[15:0]
ACTIVE_INT_NUM
INT_VECT_ADDR
Interrupts 0 to 30
from Fixed
Function Blocks
Interrupts 0 to
30 from DMA
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