DS04-27204-5Ea
FUJITSU MICROELECTRONICS
DATA SHEET
Copyright©1994-2008 FUJITSU MICROELECTRONICS LIMITED All rights reserved
2006.5
ASSP
BIPOLAR
SWITCHING REGULATOR
CONTROLLER
MB3775
■LOW VOLTAGE DUAL PWM SWITCHING REGULATOR CONTROLLER
The MB3775 is a dual pulse-width-modulation control circuit. It contains the basic circuits required for two PWM
control circuits. Complete synchronization is obtained by using the same oscillator output waveform.
This IC can provide following types of output voltage: step down, step up, and in verter . P ower consumption is low ,
thus the MB3775 is ideal for use in high-efficiency portable equipment.
■FEATURES
• Wide supply voltage range: 3.6 V to 18 V
• Low current consum pti on: 1.3 mA typ ic al
• Wide oscillation frequency range: 1 kHz to 500 kHz
• On-chip timer latch short protection circuit
• On-chip under voltage lockout protection
• On-chip reference voltage: 1.28 V
• Variable dead time provides control over total operating range.
• Two types of packages (SOP-16pin : 1 type, SSOP-16pin : 1 type)
■APPLICATIONS
• LCD monitor/panel
• Surveillance camera etc.
MB3775
2
■PIN ASSIGNMENT
■BLO C K DIAGRAM
(TOP VIEW)
E/GND VCC
OUT2
VREF
D.T.C.2
FB2
-IN2
+IN2
SCP
1
9
+IN1
CT
RT
-IN1
FB1
OUT1
D.T.C.1
2
3
4
5
6
7
810
11
12
13
14
15
16
(FPT-16P-M06)
(FPT-16P-M05)
−
+
−
++
−
+
+
−
+
1.8 V
1.1 V
2.5 V
1.9 V
1.3 V
2.5 V
1 µA
OUT 1
OUT 2
PWM Comp.1
PWM Comp.2
U.V.L.O.
Latch
D.T.C.Comp.
Error Amp 2
Error Amp 1 S.C.P.Comp.
RSR
1.28 V
0.9 V 0.9 V
GND
V REF = 1.28 V
V CC
+
−
−
+
−
−
14
9
16
3
4
5
12
13
15
611
10
7
2
1
8
Reference
Voltage Triangular
Waveform
MB3775
3
■OPERATION DESCRIPTION
1. Reference voltage
The reference voltage circuit generates a stable, temperature-compensated 2.5 V reference from Vcc terminals
(pin 9) for use by internal circuits.
A reference voltage of tem perature compe nsated 1/2 V REF c an be obtained to exter na l circuit by V REF te r minal
(pin 16).
2. Oscillator
A tr iang ular waveform of any frequenc y is obtain ed by conne cting an externa l cap acitor a nd resis tor t o the CT
terminal (pin 1) and RT terminals (pin 2).
The amplitude of this wav eform is from 1.3 V to 1.9 V. The oscillator is internally connected to the non-inverting
inputs of the PWM comparators. The oscillator waveform is available at the CT terminal (pin 1).
3. Error amplifiers
The error amplifier detects the output voltage of the switching regulator.
The com mon-mod e input voltage rang e is −0.2 V to 1.45 V, so the inp ut reference voltage can be set the V REF
ter minal (pin 16) and GND terminal levels. Error amplifiers can be u sed as either inverting and non-inverting
amplifiers.
The voltage g ai n is fi xed. Phas e c omp ensati on i s poss ible by connect ing a c apa ci tor to the FB term ina ls (p ins
5 and 12) of the error amplifiers.
The error amplifier output are internally connected to the inverting inputs of the PWM comparators and also to
the short protection circuit.
4. Timer latch short protection circuit
The timer latch short protection circuit detects the output levels of the error amplifiers. If one or both error amplifier
outputs are 1.1 V or lower , the timer circuit begins charging the externally connected protection enable capacitor.
If the output level of the error amplifier does not drop below the normal voltage range before the capacitor voltage
reaches the transistor base-emitter voltage VBE ( 0.65 V), the latch circui t turns the outp ut dr ive transistor off
and sets the dead time to 100 %.
5. Under voltage lockout protection circuit
An ambi guous transition state at power-on or a momentar y fluctuati on in the suppl y line may result in lo ss of
control and may adversely affect or even destroy the system. The under voltage lockout protection circuit com-
pares the internal reference voltage level with the supply voltage lev el. If the supply voltage level f alls below the
reference lev el the latch circuit is reset the output drive transistor is turned off and the dead time is set to 100%.
The protection enable terminal (pin 15) is pulled “Low”.
6. PWM comparator
Each P WM c omparator has two inverting inp uts an d one non-i nver ti ng in put. T his voltage- to-puls e-wid th con -
verter controls the output pulse width according to the input voltage.
The PWM comparator turns the output drive transistor on when the oscillator triangular wav ef orm is higher than
the error amplifier output and the dead time control terminal voltage.
7. Output drive transistor
The open-collector output-drive transistors provide common-emitter output of 18 V dielectric capability. The
output drive transistors can source up to 50 mA of drive current to the switching power transistor.
MB3775
4
■ABSOLUTE MAXIMUM RATING
*: The packages are mounted on the epoxy board (4 cm x 4 cm x 1.5 mm).
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
■RECOMMENDED OPERATING CONDITIONS
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the
semiconductor device. All of the device’s electrical characteristics are warranted when the device is
operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges. Operation
outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on
the data sheet. Users considering application outside the listed conditions are advised to contact their
representatives beforehand.
Parameter Symbol Condition Rating Unit
Min Max
Power Supply Voltage VCC 20 V
Error Amp Input Voltage VI−0.3 +10 V
Collector Output Voltage V O20 V
Collector Output Current IO75 mA
Power Dissipation PDTa ≤ +25 °C(SOP) *620 mW
Ta ≤ +25 °C(SSOP) *430 mW
Operating Ambient Temperature Ta −30 +85 °C
Storage temperature Tstg −55 +125 °C
Parameter Symbol Value Unit
Min Typ Max
Power Supply Voltage VCC 3.6 6.0 18 V
Error Amp Input Voltage VI−0.2 +1.45 V
Collector Output Voltage V O18 V
Collector Output Current IO0.3 50 mA
Phase Compensation Capacitor CP0.1 µF
Timing Capacitor CT150 15000 pF
Timing Resistor RT5.1 100 kΩ
Oscillator Frequency fOSC 1500 kHz
Reference Voltage Output Current IREF −3−1mA
Operating Ambient Temperature Ta −30 +25 +85 °C
MB3775
5
■ELECTRICAL CHARACTERISTICS (Ta = +25 °C, VCC = 6 V)
(Continued)
Parameter Condition Symbol Value Unit
Min Typ Max
Reference
Section
Output Voltage IOR = −1 mA VREF 1.26 1.28 1.30 V
Output Temp. Stability Ta = −30 °C to +85 °CVRTC −2±0.2+2 %
Input Sta bil it y VCC = 3.6 V to 18 V Line 210mV
Load Sta bil it y IOR = −0.1 mA to −1 mA Load 17.5mV
Short Circuit Output Cur-
rent VREF = 0 V IOS –30 –10 mA
Under
Voltage
Lockout
Protection
Section
Threshol d Voltage IOR = −0.1 mA VtH 2.72 V
IOR = −0.1 mA VtL 2.60 V
Hysteresis Width IOR = −0.1 mA VHYS 80 120 mV
Reset Voltage (VCC)VR1.5 1.9 V
Protection
Circuit
Section
Input Thres hol d Volt age VtPC 0.60 0.65 0.7 V
Input Stand by Voltage No pull up VSTB 50 100 mV
Input Latch Voltage No pull up VI50 100 mV
Input Sour ce Cur rent Ibpc −1.4 −1.0 −0.6 µA
Comparator Threshold
Voltage Pin 5, Pin 12 VtC 1.1 V
Triangular
Waveform
Oscillator
Section
Oscillator Frequency CT = 330 pF, RT = 15 kΩfOSC 200 kHz
Frequency Deviation CT = 330 pF , RT = 15 kΩfdev 10 %
Frequency Stability (VCC)VCC = 3.6 V to 18 V fdV 1%
Frequency Stability (Ta)Ta = −30 °C to +85 °C fdT −4–+4%
Dead-Time
Control
Section
Input Thres hol d Volt age
(fOSC = 10 kHz) Duty Cycle = 0 % Vt0 1.0 VREF
−0.15 V
Duty Cycle = 100 % Vt100 0.2 0.4 V
Input Bias Current Ibdt −0.2 –1 µA
Latch Mode Sou rce Cur -
rent Vdt = 0.7 V Idt −150 −80 µA
Latch Input Voltage Idt = −40 µAVdt
VREF
−0.1 V
MB3775
6
(Continued) (Ta = +25 °C, VCC = 6 V)
Parameter Condition Symbol Value Unit
Min Typ Max
Error Amp
Section
Input Offse t Voltage VO = 1.6 V VIO −10 +10 mV
Input Offset Curren t VO = 1.6 V IIO −100 +100 nA
Input Bias Current VO = 1.6 V IB−500 −100 nA
Common Mode Input
Voltage Range VCC = 3.6 V to 18 V VICR −0.2 +1.45 V
Voltage Gain AV84 120 V/V
Frequency Band Width AV = −3 dB BW 3MHz
Common Mode
Rejection Rati o CMRR 60 80 dB
Max Output Voltage
Width VOM+ 2.2 2.4 V
VOM- –0.70.9V
Output Sink Current VO = 1.6 V IOM+ 24 50 µA
Output Source Current VO = 1.6 V IOM- −1.2 −0.7 mA
PWM Com-
parator
Section
Input Thres hol d Volt age
(fOSC=10 kHz) Duty Cycle = 0 % Vt0 1.9 2.1 V
Duty Cycle = 100 % Vt100 1.05 1.3 V
Input Sink Current Pin 5, Pin 12 = 1.6 V IIN+ 24 50 µA
Input Source Current Pin 5, Pin 12 = 1.6 V IIN- −1.2 −0.7 mA
Output
Section
Output Leak Current VO = 18 V Leak 10 µA
Output Saturation Volt-
age IO = 50 mA VSAT 1.1 1.4 V
Stand by Current Output “OFF” ICCS 1.3 1.8 mA
Average Supply Current RT = 15 kΩICCa 1.7 2.4 mA
MB3775
7
■TEST CIRCUIT
■TIMING CHART (Internal Waveform)
SW TEST INPUT
OUTPUT 1
OUTPUT 2
TEST INPUT
330 pF
0.1µF
12345678
16 15 14 13 12 11 10 9
MB3775
CPE
VCC=6 V
15 kΩ
4.7 kΩ
4.7 kΩ
1.9 V
1.5 V
1.3 V
1.1 V
“High”
“Low”
“High”
“Low”
0.6 V
0 V
“High”
“Low”
3.6 V
0 V
2.8 V (Typ Value)
tPE
DEAD TIME 100%
LOCK-OUT CANCEL
Protection Enable Time tPE := 0.6 x 106 x CPE (s )
LOCK-OUT
Error Amp output
Tr iangular waveform oscillator output
Dead Time PWM
input voltage
Short circuit protection
comparator Reference
PWM comparator
Output Transistor
collector w avefo rm
SCP Terminal
Short circuit protection
comparator output
Power supply voltage
(VCC : Min Value)
input
output
waveform
MB3775
8
■APPLICATION CIRCUIT
(Continued)
MB3775
116
215
314
413
5
6
7
8
12
11
10
9
820 pF
10 kΩ
2.3 kΩ
33 kΩ
0.1 µF
33 kΩ
1 µF
33 kΩ
1 µF
330 Ω
9.1 kΩ
330 Ω
33 kΩ
120 µH
220 µF220 µF
470 Ω
120 µH
5.6 kΩ
1.9 kΩ
0.1 µF
0.1 µF
220 µF
56 µH
VIN (10 V)
V0- (−5 V) GND V0+ (+5 V)
+−
+−
−+
−+
−+
470 Ω
+−
+−
−+
−+
−+
820 pF
10 kΩ
2.3 kΩ
33 kΩ
0.1 µF
33 kΩ
1 µF
33 kΩ
1 µF
330 Ω
9.1 kΩ
330 Ω
33 kΩ
120 µH
220 µF220 µF
100 Ω
120 µH
16 kΩ
1.9 kΩ
0.1 µF
0.1 µF
220 µF
56 µH
VIN (5 V)
V0- (−5 V) GND V0+ (+12 V)
3.9 kΩ
MB3775
116
215
314
413
5
6
7
8
12
11
10
9
Fig. 1 - Chopper Type Step Down/Inverting
Fig. 2 - Choppe r Ty pe Step Up/Inve r t ing
MB3775
9
(Continued)
+−
+−
−+
−+
−+
−
+
MB3775
116
215
314
413
5
6
7
8
12
11
10
9
820 pF
10 kΩ
2.3 kΩ
33 kΩ
0.1 µF
33 kΩ
1 µF
33 kΩ
1 µF
9.1 kΩ
33 k Ω
120 µH
220 µF220 µF
1.9 kΩ
0.1 µF
0.1 µF
220 µF
56 µH
VIN (5 V)
V0- (−5 V) GND V0+ (+12 V)
16 kΩ
150 Ω
120 µH
470 Ω
330 pF
33 kΩ
33 kΩ
220 Ω
470 Ω
470 Ω
470 Ω
1 µF
33 kΩ
1.9 kΩ
0.1 µF
0.1 µF
56 µH
VIN (10 V)
V02-
(−12 V)
−+
220 µF
V01-
(−5 V) GND V02+
(+5 V) V01+
(+12 V)
−+
220 µF
−+
220 µF
−+
220 µF
−+
220 µF
820 pF
10 kΩ
33 kΩ
220 Ω
1 nF
1.8 kΩ
0.1 µF
5.6 kΩ
MB3775
116
215
314
413
5
6
7
8
12
11
10
9
Fig. 3 - Chopper Type Step Up/Inverting (For High Speed)
Fig. 4 - Mult i Output Type (A pply Transfo r m e r )
MB3775
10
■HOW TO SET OUTPUT VOLTAGE
The output voltage is set using the connection shown in Fig. 5 and 6.
The err or amp lifiers are supp lied to the intern al reference voltage circuit a s are t he other in ter na l circ uits. The
common-mode input voltage range is from −0.2 V to +1.45 V.
When the amplifiers are operated non-inverting, tie the inverting terminal to VREF ( 1.28 V). When the amplifiers
are operated inverting, tie the non-inverting terminal to ground.
R2
R1
VREF
+
−
PIN 5 or PIN 12
V0+ [V0+ = VREF X (1 + R2/R1)]
Fig. 5 -Connect ion of Error Amp
Output Voltage V0 is plus
R2
R1
VREF
+
−PIN 5 or PIN 12
V0- [V0- = −VREF X (R2/R1)]
Fig. 6 -Connection of Error Amp
Output Voltage V0 is minus
MB3775
11
■HOW TO SET TIME CONSTANT FOR TIMER LATCH SHORT PROTECTION CIRCUIT
TIMING CHAR T shows the configuration of the protection latch circuit.
Error am plifi er outpu ts, are inter na lly co nnecte d to the non- inverting inputs of the short-circ uit prot ectio n com-
parator and are compared with the reference voltage (1.1 V) connected to the inverting input.
When the load condition of the switching regulator is stable, the error amplifier has no output fluctuation. Thus,
short-circuit protection control is also kept in balance, and the protection enable terminal (pin 15) voltage is kept
at about 50 mV.
If the load co ndit ion drasti call y cha nges d ue to a load s hort-circui t and if low-level signal s (1.1 V or lower) ar e
input to the non- inver ting i nputs of the shor t- circuit pr otection co mparator from the er ror amplif iers, the sho r t-
circuit protection comparator outputs a “Low” level to turn transistor Q1 off. The protection enable terminal voltage
is discharged, and then the short-circuit protection comparator charges the externally connected protection
enable capacitor CPE according to the following formula:
VPE = 50 mV + tPE x 10-6/CPE
0.65 = 50 mV + tPE x 10-6/CPE
CPE = tPE/0.6 (µF)
When th e protec tion enable ca pacitor ch arges to about 0.65 V, the protec tion latch is set to en able the under
voltage lockout protection circuit and to turn the output drive transistor off. The dead time is set to 100 %.
Once the under voltage lockout protection circuit is enabled, the protection enable is released; however, the
protection latch is not reset if the power is not turned off.
The non-inv erting inputs of the D.T.C. comparator are connected to the D.T.C. terminals (pins 6 and 11) through
the power supply (about 0.9 V) and are compared with a reference voltage (about 1.8 V) connected to the
inverting input.
To prevent malfunction of the short protection circuit in soft-start mode (using D.T.C. terminals), the D.T.C.
comparator outputs a “High” lev el to turn Q2 on until the D.T.C . terminals (pins 6 and 11) v oltage drops to about
0.9 V.
Error Amp1
Error Amp2
1.1 V
S.C.P.Comp. R1
Q1Q2Q3
CPE
15
11
6
SR
Latch U.V.L.O.
1 µA
2.5 V
D.T.C.1
D.T.C.2
D.T.C.Comp.
+
+
−
1.8 V 0.9 V 0.9 V
+
+
−
Fig. 7 - Prote c tion Latc h Cir c uit
SCP
MB3775
12
■SYNCHRONIZATION OF ICs
To synchronize MB3775 ICs, first, the specified capacitor and resistor are connected to the CT and RT terminals
(pins 1 and 2) of the master IC to start self oscillation. Next, 2 V is applied to the RT terminals (pin 2) of the slav e
ICs to disable the charge/discharge circuit for triangular wave oscillation. Finally, the CT terminals (pin 1) of the
master and slave ICs are connected.
Instead of applying VRT to the RT terminals (pin 2), these terminals can be pulled up by a resistor (see resistance
indicated by the dashed line in Fig. 8). Select the pull-up resistance Rpull from the formula given below.
VCC
0.5 x N ≤ Rpull Rpull: Pull up Resistor (kΩ)
VCC: Power Supply Voltage (V)
N: Number of Slave ICs
MB3775
MB3775
MB3775
2 V
VRT
Rpull CTRT
VCC
Fig. 8 - Connection of Master, Slave
(MASTER)
(SLAVE)
(SLAVE)
MB3775
13
■TYPICAL PERFORMANCE CHARACTERISTICS
(Continued)
2.0
1.5
1.0
0.5
05101520 05101520
2.0
1.5
1.0
0.5
2.0
1.5
1.0
0.5
05101520
1.29
1.28
1.26
−30 +0 +30 +60 +90
1.25
3.0
2.0
1.0
0100 1k 10k 100k 1M
3.5
3.0
2.5
2.0
1.5
1.0
0.5
050 100 150 350200 250 300
Fig. 9 - Reference voltage vs. Power supply voltage Fig. 10 - Average supply current vs. Power supply voltage
Fig. 12 - Reference voltage vs. Operating ambient temperature
Fig. 13 - Collectorsaturation saturation voltage vs. Sink current Fig. 14 - Error Amp Max output voltage vs. Frequency
Power supply voltage VCC (V) Power supply voltage VCC (V)
Power supply voltage VCC (V) Operating ambient temperature Ta ( °C)
Sink current lO (mA) Frequency f (Hz)
1.27
Fig. 11 - Stand by current vs. Power supply v oltage
Reference v olt age V REF(V)
Average supply current I (mA)
Stand by current ICCS (mA)
(V)
Error Amp Max output voltage VOM (V) Reference voltage VREF (V) CCa
Collectorsaturation voltage VSAT
MB3775
14
(Continued)
1M
100k
10k
1k
1001k 10k 100k 1M 10M 101102103104105
103
102
101
100
10-1
1011021031041051k 10k 100k 1M 10M
2.2
2.0
1.8
1.4
1.0
1.6
1.2
60
40
20
−20
−60
0
−40
180
90
−90
0
−180
90
60
40
20
−20
−60
0
−40
60
40
20
−20
−60
0
−40
100102103107
105
101104106
100102103107
105
101104106
180
90
−90
0
−180
180
90
−90
0
−180
CFB = 1 µF CFB = 0.1 µF
Fig. 15 - Oscillation Frequency vs. Timing resistor Fig. 16 - Triangular wavef orm cycle vs. Timing capacitor
Fig. 17 - Triangular waveform Max Amplitude voltage vs. Timing capacitor Fig. 18 - Gain/Phase vs. Frequency
Fig. 19 - Gain/Phase vs. Frequency (Actual Data) Fig. 20 - Gain/Phase vs. Frequency (Actual Data)
CT = 150 pF
CT = 1500 pF
CT = 15000 pF
Timing resistance=1 5 kΩ
VCC = 6 V
Timing resistance = 15 kΩ
VCC = 6 V
Gain AV
Timing resistor RT (Ω)Timing capacitor CT (pF)
Timing capacitor CT (pF) Frequency f (Hz)
Frequency f (Hz) Frequency f (Hz)
Phase φ
Gain AV
Phase φ
Gain AV
Phase φ
Tr iangular waveform Max Amplitude voltage (V)
Gain AV(dB)
Tr iangular waveform cycle (µs)
Phase φ (deg) Phase φ (deg)
Gain AV(dB)
Phase φ (deg)
Gain AV(dB)
Oscillation Frequency fOSC (Hz)
MB3775
15
(Continued)
V
60
40
20
−20
−60
0
−40
100102103107
105
101104106
180
90
−90
0
−180
Fig. 21 - Gain/Phase vs. Frequency (Actual Data)
Frequency f (Hz)
Gain AV
Phase φ
Gain A (dB)
Phase φ (deg)
CFB=0.01 µF
MB3775
16
■HOW TO SET THE ERROR AMPLIFIER FREQUENCY CHARACTERISTIC
Figure 22 shows the equivalent circuit of the error amplifier.
The frequency characteristic of the error amplifier is set by R1, R2, and CP. The high-frequency gain is set by the
ratio of resistors R1 and R2 in the IC (set value 0 dB).
When CP = 0.1 µF, the gai n at 20 kH z ≤ f ≤ 5 MHz is about 0 dB. The roll-off frequency is adjusted by changing
external phase compensating capacitor CP (see Fig. 24).
When high frequency gain is needed or the phase must be advanced at a low frequency, connect a resistor RP
between the FB terminals (pins 5 and 12) and CP as shown in Figure 23 (see Fig. 25).
Note:As shown above, the frequency characteristic of the error amplifier is set by the external phase compensating
capacitor CP.
When a ceramic chip capacitor must be used to meet the requirements of a small system, be careful of its
temperature characteristic. ( −30 °C 1/5 and +80 °C 1/3 for the frequency characteristic, so a sufficient
phase margin must be allowed for at room temperature.) Ceramic chip capacitors with a low temperature
characteristic (B characteristic) or film capacitors are recommended (see Fig. 26 to 28).
R1 38 kΩPWM COMP
[− IN]
[+ IN]
[FB]
CP
R2 470 Ω
−
+
x 120
Error Amp
Fig. 22 - Error Amp Equivalent Circuit
PWM COMP
[− IN]
[+ IN]
[FB]
CP
−
+
x 120
RP
Error Amp
Fig. 23 - Error Amp Equivalent Circuit (Insert RP)
R1 38 kΩ
R2 470 Ω
=
..=
..
MB3775
17
Gain AV(dB) Gain AV(dB)
60
20
−20
−40
−60
60
40
20
0
−20
−40
−60
10 100 1k 10k 100k 1M 10M 100M
100 1k 10k 100k 1M 10M 100M10
180
90
0
−90
−180
180
90
0
−90
−180
RP=0 Ω
RP=0 Ω
CP = 0.1 µF
CP = 0.1 µF
AV
AVCP = 0.1 µF
(Large)
(Large)
(Large)
(Large)
(Small)
(Small)
ϕ
ϕ
Frequency f (Hz)
0
40
Fig. 24 - Error Amp Frequency characteristics
Frequency f (Hz)
Fig. 25 - Error Amp Fr equency characteri stics
Phase φ (deg)
Phase φ (deg)
MB3775
18
Gain AV(dB) Gain AV(dB) Gain AV(dB)
20
10
0
−10
−20
20
10
0
−10
−20
20
10
0
−10
−20
1k 10k 100k 1M
1k 10k 100k
1k 10k 100k 1M
90
0
90
−90
90
0
−90
φ
φ
AV
AV
AV
−30°C
+80°C
+25°C
+80°C
+25°C
−30°C, +25°C, +80°C
−30°C,
+25°C
+80°C
1M
Frequency f (Hz)
Frequency f (Hz)
Frequency f (Hz)
−90
−30°C
+25°C
+80°C
0
−30°C
+25°C
Fig. 26 - Ceramic Chip Capacitor (0.1 µF)
Fig. 27 - Tantal Capacitor (0.33 µF)
Fig. 28 - Film Capacitor (0.1 µF)
−30°C :0.19
+25°C:1.0
+80°C :0.32
−30°C :0.95 to 1.05
+25°C:1.0
+80°C :0.95 to 1.05
−30°C :0.9 to 1.1
+25°C:1.0
+80°C :0.9 to 1.1
−30°C
Phase φ (deg)
Phase φ (deg)Phase φ (deg)
φ
+80°C
Temp. characteristic
Temp. : Ratio
Temp. characteristic
Temp. characteristic
Temp. : Ratio
MB3775
19
■EFFECT OF EQUIVALENT SERIES RESISTANCE OF SMOOTHING CAPACITOR
The equi valent ser ies resis tance (ESR) of the sm oothing cap acitor in the DC/DC conver t er gre atly affects the
loop phase characteristic.
A smoothing capacitor with a low ESR reduces system stability by increasing the phase shift in the high-frequency
region (see Fig. 30). Theref ore, a smoothing capacitor with a high ESR will improve system stability. Be careful
when using low ESR semiconductor electrolytic capacitors (OS-CONTM) and tantalum capacitors.
Note: OS-CON is the trademark of Sanyo Electric Co., Ltd.
Tr
VIN DRL
RC
C
L
Fig. 29 - Step Down DC/DC Converter Basic Circuit
20
0
−20
−40
−60
10 100 1k 10k 100k 10 100 1k 10k 100k
−90
0
−180
: RC = 0 Ω
: RC = 31 mΩ
Frequency f (Hz) Frequency f (Hz)
Fig. 30 - Gain vs. Frequency Fig. 31 - Phase vs. Frequency
(1)
(2)
(2)
(1)
(1)
(2)
: RC = 0 Ω
: RC = 31 mΩ
(1)
(2)
Gain AV (dB)
Phase φ (deg)
MB3775
20
Reference data
If an aluminum electrolytic smoothing capacitor (RC1.0 Ω) is replaced with a low ESR semiconductor electro-
lytic capacitor (OS-CONTM: RC 0.2 Ω), the phase shift is reduced by half (see Fig. 33 and 34).
R1
− IN
−
+~
R2
+ IN
VOUT V0+
VREF
VIN
FB
0.1 µF
Error Amp
Fig. 32 - DC/DC Converter AV vs. φ characteristic Test Circuit
AV vs. φ characteristic
Between this point.
V
60
20
0
−20
−40
60
20
0
−20
−40
10 100 1k 10k 100k
10 100 1k 10k
+
−
+
−
OS-CONTM
22 µF(16V)
RC0.2 Ω : fosc=1 kHz
AI Capacitor
220 µF(16 V)
RC1.0 Ω : fosc=1 kHz
GND
GND
V0+
V0+
AV
AV
φ
φ
100k
180
90
0
−90
−180
180
90
0
−90
−180
40
Frequency f (Hz)
Frequency f (Hz)
40
Fig. 33 - DC/DC Converter +5 V Gain/Phase vs. Frequency
Fig. 34 - DC/DC Converter +5 V Gain/Phase vs. Frequency
Gain A (dB)
Phase φ (deg)
Gain AV (dB)
Phase φ (deg)
VCC=10 V
RL=25 Ω
CP=0.1 µF
VCC=10 V
RL=25 Ω
CP=0.1 µF
+62°
+27°
MB3775
21
■MEASURES FOR ENSURING SYSTEM STABILITY WHEN A LO W ESR SMOOTHING CA-
PACITOR IS USED
When a l ow ESR smooth ing capacit or is used in the D C/DC conver ter, only the L and C a re app arent even in
the high- frequen cy r egion, and the ph ase is de layed by almost 18 0°. Conseq uen tly, the syste m phase ma rgin
and stab ility are re duced. On the oth er hand, a low ES R capacitor i s needed to redu ce the amount o f output
ripple. This is contrary to the system stability explained above.
To solve this problem, phase compensation can be used. This method increases the phase margin by advancing
the phase when the phase margin is reduced by a low ESR capacitor.
The three suggestions listed below are recommended f or DC/DC converters using the MB3775.
(1) As shown in Fig. 35, a capacito r is connect ed in paralle l with the out put feedback resi stor to advance the
phase. Use the formula below as a guideline for the capacitance.
C11
2πfR2
Unstable F requency (See Fig. 32)
R1
CP
R2
+ IN +
−
V0+
VREF
FB
− IN
C1
Fig. 35 - External circuit example1 to advance the phase
60
40
20
0
−20
−40
10 100 1k 10k 100k
180
90
0
−90
−180
+66°
φ
AV
VCC = 10 V
RL = 25 Ω
CP = 0.1 µF
Smoothing Capacitor
22 µF OS-CON
C1 = 4700 pF
R1 = 1.8 kΩ
R2 = 5.6 Ω
Frequency f (Hz)
Fig. 36 - DC/DC Converter +5 V Gain/Phase vs. Frequency
Gain AV (dB)
Phase φ (deg)
MB3775
22
(2) A s shown in Fi gure 3 7 , a resi s tor ( RP) is c on nected between the F B t ermi nal (pin s 5 and 12 ) a nd CP of the
error amplifier to advance the phase. The more RP is increased, the more the phase is advanced. However,
the gain in the high-frequency range is also increased, which causes instability . Therefore, select the optimum
resistance (see Fig. 38).
R1
CP
R2
+ IN +
−
V0+
VREF
FB
− IN
RP
Fig. 37 - External circuit example 2 to advance the phase
VCC = 10 V
RL = 25 Ω
CP = 0.1 µF
Smoothing Capacitor
22 µF OS-CON
RP = 470 Ω
R1 = 1.8 kΩ
R2 = 5.6 Ω
φ
60
40
20
0
−20
−40
10 100 1k 10k 100k
180
90
0
−90
−180
AV
Frequency f (Hz)
Fig. 38 - DC/DC Converter +5 V Gain/Phase vs. Frequency
Gain A V (dB)
Phase φ (deg)
+45°
MB3775
23
(3) As shown in Fig. 39, the phase is advanced by using both example 1 and 2 (Fig. 35 and 37).
■ERROR AMPLIFIER INPUT RIPPLE VOLTAGE
The boost circuit for charging the phase compensating capacitor CP is c onnect ed to th e error amplifie r as sh own
in Figure 40 to protect against output voltage overload at power-on.
A :=15 mV offset voltage is provided for the negative input side so that the boost circuit only operates at power-
on. When a capacitor is connected in parallel with the output feedback resistor , because the output ripple is too
large or for advanced ph ase c om pens at ion , th e boost cir cuit starts ope rating, whi ch may degrade regu lat ion if
the differential input voltage of the error amplifier exceeds :=15 mV. Be careful with the differential input voltage
of the error amplifier.
R1
R2
+ IN +
−
V0+
VREF
FB
− IN
C1
CP
RP
Fig. 39 - External circuit example 3 to advance the phase
R3
[+ IN]
+
−
VREF
[FB]
[− IN]
CP
+
−
× 120
15 mV
R4
VCC
V0 +
Fig. 40 - Error Amp /Boost Equivalent circuit
Advanced phase
compensation
capacitor
Boost circuit
Error Amp
R1 38 kΩ
R2 470 Ω
MB3775
24
■NOTES ON USE
• Take account of common impedance when designing the earth line on a printed wiring board.
• Take measures against static electricity.
- For semiconductors, use antistatic or conductive containers.
- When storing or carrying a printed circuit board after chip mounting, put it in a conductive bag or container.
- The work table, tools and measuring instruments must be grounded.
- The worker must put on a grounding device containing 250 kΩ to 1 MΩ resistors in series.
• Do not apply a negative voltage
- Applying a negative voltage of −0.3 V or less to an LSI may generate a parasitic transistor, resulting in
malfunction.
■ORDERING INFORMATION
■RoHS Compliance Information of Lead (Pb) Free version
The LS I products of Fujits u Microele ctronic s with “E1 ” are com pliant wit h RoHS Dir ective , and has o bser ved
the standard of lead, cadmium, mercury, Hexa valent chromium, polybrominated biphenyls (PBB) , and polybro-
minated diphenyl ethers (PBDE) .
The product that conforms to this standard is added “E1” at the end of the part number.
Part number Package Remarks
MB3775PF-❏❏❏ 16-pin pla st ic SOP
(FPT-16P-M06) Conventional ver sion
MB3775PFV-❏❏❏ 16-pin plastic SSOP
(FPT-16P-M05) Conventional ver sion
MB3775PF-❏❏❏E1 16-pin pla st ic SOP
(FPT-16P-M06) Lead Fre e versi on
MB3775PFV-❏❏❏E1 16-pin plastic SSOP
(FPT-16P-M05) Lead Fre e versi on
MB3775
25
■MARKING FORMAT (Lead Free version)
INDEX
MB3775
XXXX XXX
E1
INDEX
3775
E1XXXX
XXX
Lead Free version
Lead Free version
SOP-16
SSOP-16
MB3775
26
■LABELING SAMPLE (Lead free version)
2006/03/01
ASSEMBLED IN JAPAN
G
QC PASS
(3N) 1MB123456P-789-GE1
1000
(3N)2 1561190005 107210
1,000
PCS
0605 - Z01A
1000
1/1
1561190005
MB123456P - 789 - GE1
MB123456P - 789 - GE1
MB123456P - 789 - GE1
Pb
Lead Free version
lead-free mark
JEITA logo JEDEC logo
MB3775
27
■MB3775PF-❏❏❏E1, MB3775PFV-❏❏❏E1
RECOMMENDED CONDITIONS of MOISTURE SENSITIVITY LEVEL
[Temperature Profile for FJ Standard IR Reflow]
(1) IR (infrared reflow)
(2) Manual soldering (partial heating method )
Conditions : Temperature 400 °C Max
Times : 5 s max/pin
Item Condition
Mounting Method IR (infrared reflow) , Manual soldering (partial heating method)
Mounting tim es 2 times
Storage period
Before opening Please use it within two years after
Manufacture.
From opening to the 2nd
reflow Less than 8 days
When the storage period after
opening was exceeded Please processes within 8 days
after baking (125 °C, 24H)
Storage conditions 5 °C to 30 °C, 70%RH or less (the lowest possible humidity)
260 °C
(e)
(d')
(d)
255 °C
170 °C
190 °C
RT (b)
(a)
(c)
to
Note : Temperature : the top of the package body
(a) Te mperat ure Incr ease grad ient : Aver age 1 °C/s to 4 °C/s
(b) Preliminary heating : Temperature 170 °C to 190 °C, 60s to 180s
(c) Tem perat ure Increas e grad ient : Average 1 °C/s to 4 °C/s
(d) Actual heating : Temperature 260 °C Max; 255 °C or more, 10s or less
(d’) : Temperature 230 °C or more, 40s or less
or
Temperature 225 °C or more, 60s or less
or
Temperature 220 °C or more, 80s or less
(e) Cooling : Natural cooling or forced cooling
H rank : 260 °C Max
MB3775
28
■PACKAGE DIMENSION
(Continued)
16-pin plastic SOP Lead pitch 1.27 mm
Package width
×
package length
5.3 × 10.15 mm
Lead shape Gullwing
Sealing method Plastic mold
Mounting height 2.25 mm MAX
Weight 0.20 g
Code
(Reference) P-SOP16-5.3×10.15-1.27
16-pin plastic SOP
(FPT-16P-M06)
(FPT-16P-M06)
C
2002 FUJITSU LIMITED F16015S-c-4-7
0.13(.005) M
Details of "A" part
7.80±0.405.30±0.30
(.209±.012) (.307±.016)
–.008
+.010
–0.20
+0.25
10.15
INDEX
1.27(.050)
0.10(.004)
18
916
0.47±0.08
(.019±.003)
–0.04
+0.03
0.17
.007 +.001
–.002
"A" 0.25(.010)
(Stand off)
0~8˚
(Mounting height)
2.00 +0.25
–0.15
.079 +.010
–.006
0.50±0.20
(.020±.008)
0.60±0.15
(.024±.006)
0.10 +0.10
–0.05
–.002
+.004
.004
.400
*1
*2
0.10(.004)
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
Note 1) *1 : These dimensions include resin protrusion.
Note 2) *2 : These dimensions do not include resin protrusion.
Note 3) Pins width and pins thickness include plating thickness.
Note 4) Pins width do not include tie bar cutting remainder.
MB3775
29
(Continued)
16-pin plastic SSOP Lead pitch 0.65 mm
Package width
×
package length
4.40 × 5.00 mm
Lead shape Gullwing
Sealing method Plastic mold
Mounting height 1.45mm MAX
Weight 0.07g
Code
(Reference) P-SSOP16-4.4×5.0-0.65
16-pin plastic SSOP
(FPT-16P-M05)
(FPT-16P-M05)
C
2003 FUJITSU LIMITED F16013S-c-4-6
5.00±0.10(.197±.004)
4.40±0.10 6.40±0.20
(.252±.008)(.173±.004)
.049 –.004
+.008
–0.10
+0.20
1.25 (Mounting height)
0.10(.004)
0.65(.026) 0.24±0.08
(.009±.003)
18
16 9
"A"
0.10±0.10 (Stand off)
0.17±0.03
(.007±.001)
M
0.13(.005)
(.004±.004)
Details of "A" part
0~8˚
(.024±.006)
0.60±0.15
(.020±.008)
0.50±0.20
0.25(.010)
LEAD No.
INDEX
*1
*2
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
Note 1) *1 : Resin protrusion. (Each side : +0.15 (.006) Max).
Note 2) *2 : These dimensions do not include resin protrusion.
Note 3) Pins width and pins thickness include plating thickness.
Note 4) Pins width do not include tie bar cutting remainder.
MB3775
30
MEMO
MB3775
31
MEMO
FUJITSU MICROELECTRONICS LIMITED
Shinjuku Dai-Ichi Seimei Bldg. 7-1, Nishishinjuku 2-chome, Shinjuku-ku,
Tokyo 163-0722, Japan Tel: +81-3-5322-3347 Fax: +81-3-5322-3387
http://jp.fujitsu.com/fml/en/
For further information please contact:
North and South America
FUJITSU MICROELECTRONICS AMERICA, INC.
1250 E. Arques Avenue, M/S 333
Sunnyvale, CA 94085-5401, U.S.A.
Tel: +1-408-737-5600 Fax: +1-408-737-5999
http://www.fma.fujitsu.com/
Europe
FUJITSU MICROELECTRONICS EUROPE GmbH
Pittlerstrasse 47, 63225 Langen,
Germany
Tel: +49-6103-690-0 Fax: +49-6103-690-122
http://emea.fujitsu.com/microelectronics/
Korea
FUJITSU MICROELECTRONICS KOREA LTD.
206 KOSMO TOWER, 1002 Daechi-Dong,
Kangnam-Gu,Seoul 135-280
Korea
Tel: +82-2-3484-7100 Fax: +82-2-3484-7111
http://www.fmk.fujitsu.com/
Asia Pacific
FUJITSU MICROELECTRONICS ASIA PTE LTD.
151 Lorong Chuan, #05-08 New Tech Park,
Singapore 556741
Tel: +65-6281-0770 Fax: +65-6281-0220
http://www.fujitsu.com/sg/services/micro/semiconductor/
FUJITSU MICROELECTRONICS SHANGHAI CO., LTD.
Rm.3102, Bund Center, No.222 Yan An Road(E),
Shanghai 200002, China
Tel: +86-21-6335-1560 Fax: +86-21-6335-1605
http://cn.fujitsu.com/fmc/
FUJITSU MICROELECTRONICS PACIFIC ASIA LTD.
10/F., World Commerce Centre, 11 Canton Road
Tsimshatsui, Kowloon
Hong Kong
Tel: +852-2377-0226 Fax: +852-2376-3269
http://cn.fujitsu.com/fmc/tw
All Rights Reserved.
The contents of this document are subject to change without notice.
Customers are advised to consult with sales representatives before ordering.
The information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose
of reference to show examples of operations and uses of FUJITSU MICROELECTRONICS device; FUJITSU MICROELECTRONICS
does not warrant proper operation of the device with respect to use based on such information. When you develop equipment incorporat-
ing the device based on such information, you must assume any responsibility arising out of such use of the information.
FUJITSU MICROELECTRONICS assumes no liability for any damages whatsoever arising out of the use of the information.
Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use
or exercise of any intellectual property right, such as patent right or copyright, or any other right of FUJITSU MICROELECTRONICS
or any third party or does FUJITSU MICROELECTRONICS warrant non-infringement of any third-party's intellectual property right or
other right by using such information. FUJITSU MICROELECTRONICS assumes no liability for any infringement of the intellectual
property rights or other rights of third parties which would result from the use of information contained herein.
The products described in this document are designed, developed and manufactured as contemplated for general use, including without
limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured
as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect
to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in
nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in
weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite).
Please note that FUJITSU MICROELECTRONICS will not be liable against you and/or any third party for any claims or damages arising
in connection with above-mentioned uses of the products.
Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by
incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current
levels and other abnormal operating conditions.
Exportation/release of any products described in this document may require necessary procedures in accordance with the regulations of
the Foreign Exchange and Foreign Trade Control Law of Japan and/or US export control laws.
The company names and brand names herein are the trademarks or registered trademarks of their respective owners.
Edited Strategic Business Development Dept.
