MF943-03 CMOS 4-BIT SINGLE CHIP MICROCOMPUTER S1C60N01 Technical Manual S1C60N01 Technical Hardware/S1C60N01 Technical Software NOTICE No part of this material may be reproduced or duplicated in any form or by any means without the written permission of Seiko Epson. Seiko Epson reserves the right to make changes to this material without notice. Seiko Epson does not assume any liability of any kind arising out of any inaccuracies contained in this material or due to its application or use in any product or circuit and, further, there is no representation that this material is applicable to products requiring high level reliability, such as medical products. Moreover, no license to any intellectual property rights is granted by implication or otherwise, and there is no representation or warranty that anything made in accordance with this material will be free from any patent or copyright infringement of a third party. This material or portions thereof may contain technology or the subject relating to strategic products under the control of the Foreign Exchange and Foreign Trade Law of Japan and may require an export license from the Ministry of International Trade and Industry or other approval from another government agency. (c) SEIKO EPSON CORPORATION 2001 All rights reserved. PREFACE This part explains the function of the S1C60N01, the circuit configurations, and details the controlling method. II. S1C60N01 Technical Software This part explains the programming method of the S1C60N01. Software I. S1C60N01 Technical Hardware Hardware This manual is individualy described about the hardware and the software of the S1C60N01. The information of the product number change Starting April 1, 2001, the product number will be changed as listed below. To order from April 1, 2001 please use the new product number. For further information, please contact Epson sales representative. Configuration of product number Devices S1 C 60N01 F 0A01 00 Packing specification Specification Package (D: die form; F: QFP) Model number Model name (C: microcomputer, digital products) Product classification (S1: semiconductor) Development tools C 60R08 S5U1 D1 1 00 Packing specification Version (1: Version 1 2) Tool type (D1: Development Tool 1) Corresponding model number (60R08: for S1C60R08) Tool classification (C: microcomputer use) Product classification (S5U1: development tool for semiconductor products) 1: For details about tool types, see the tables below. (In some manuals, tool types are represented by one digit.) 2: Actual versions are not written in the manuals. Comparison table between new and previous number S1C60 Family processors Previous No. E0C6001 E0C6002 E0C6003 E0C6004 E0C6005 E0C6006 E0C6007 E0C6008 E0C6009 E0C6011 E0C6013 E0C6014 E0C60R08 New No. S1C60N01 S1C60N02 S1C60N03 S1C60N04 S1C60N05 S1C60N06 S1C60N07 S1C60N08 S1C60N09 S1C60N11 S1C60N13 S1C60140 S1C60R08 S1C62 Family processors Previous No. E0C621A E0C6215 E0C621C E0C6S27 E0C6S37 E0C623A E0C623E E0C6S32 E0C6233 E0C6235 E0C623B E0C6244 E0C624A E0C6S46 New No. S1C621A0 S1C62150 S1C621C0 S1C6S2N7 S1C6S3N7 S1C6N3A0 S1C6N3E0 S1C6S3N2 S1C62N33 S1C62N35 S1C6N3B0 S1C62440 S1C624A0 S1C6S460 Previous No. E0C6247 E0C6248 E0C6S48 E0C624C E0C6251 E0C6256 E0C6292 E0C6262 E0C6266 E0C6274 E0C6281 E0C6282 E0C62M2 E0C62T3 New No. S1C62470 S1C62480 S1C6S480 S1C624C0 S1C62N51 S1C62560 S1C62920 S1C62N62 S1C62660 S1C62740 S1C62N81 S1C62N82 S1C62M20 S1C62T30 Comparison table between new and previous number of development tools Development tools for the S1C60/62 Family Previous No. ASM62 DEV6001 DEV6002 DEV6003 DEV6004 DEV6005 DEV6006 DEV6007 DEV6008 DEV6009 DEV6011 DEV60R08 DEV621A DEV621C DEV623B DEV6244 DEV624A DEV624C DEV6248 DEV6247 New No. S5U1C62000A S5U1C60N01D S5U1C60N02D S5U1C60N03D S5U1C60N04D S5U1C60N05D S5U1C60N06D S5U1C60N07D S5U1C60N08D S5U1C60N09D S5U1C60N11D S5U1C60R08D S5U1C621A0D S5U1C621C0D S5U1C623B0D S5U1C62440D S5U1C624A0D S5U1C624C0D S5U1C62480D S5U1C62470D Previous No. DEV6262 DEV6266 DEV6274 DEV6292 DEV62M2 DEV6233 DEV6235 DEV6251 DEV6256 DEV6281 DEV6282 DEV6S27 DEV6S32 DEV6S37 EVA6008 EVA6011 EVA621AR EVA621C EVA6237 EVA623A New No. S5U1C62620D S5U1C62660D S5U1C62740D S5U1C62920D S5U1C62M20D S5U1C62N33D S5U1C62N35D S5U1C62N51D S5U1C62560D S5U1C62N81D S5U1C62N82D S5U1C6S2N7D S5U1C6S3N2D S5U1C6S3N7D S5U1C60N08E S5U1C60N11E S5U1C621A0E2 S5U1C621C0E S5U1C62N37E S5U1C623A0E Previous No. EVA623B EVA623E EVA6247 EVA6248 EVA6251R EVA6256 EVA6262 EVA6266 EVA6274 EVA6281 EVA6282 EVA62M1 EVA62T3 EVA6S27 EVA6S32R ICE62R KIT6003 KIT6004 KIT6007 New No. S5U1C623B0E S5U1C623E0E S5U1C62470E S5U1C62480E S5U1C62N51E1 S5U1C62N56E S5U1C62620E S5U1C62660E S5U1C62740E S5U1C62N81E S5U1C62N82E S5U1C62M10E S5U1C62T30E S5U1C6S2N7E S5U1C6S3N2E2 S5U1C62000H S5U1C60N03K S5U1C60N04K S5U1C60N07K I. S1C60N01 Technical Hardware CONTENTS CONTENTS CHAPTER 2 INTRODUCTION ............................................................... I-1 1.1 Configuration ................................................................... I-1 1.2 Features .......................................................................... I-2 1.3 Block Diagram ................................................................. I-3 1.4 Pin Layout Diagram ......................................................... I-4 1.5 Pin Description ................................................................ I-5 Hardware CHAPTER 1 POWER SUPPLY AND INITIAL RESET ................................ I-6 2.1 Power Supply .................................................................. I-6 2.2 Initial Reset ...................................................................... I-8 Oscillation detection circuit ...................................... I-9 Reset pin (RESET) .................................................... I-9 Simultaneous high input to input ports (K00-K03) ... I-9 Internal register following initialization .................... I-10 2.3 CHAPTER 3 Test Pin (TEST) .............................................................. I-10 CPU, ROM, RAM ............................................................ I-11 3.1 CPU ................................................................................ I-11 3.2 ROM ............................................................................... I-12 3.3 RAM ............................................................................... I-12 S1C60N01 TECHNICAL HARDWARE EPSON I-i CONTENTS CHAPTER 4 PERIPHERAL CIRCUITS AND OPERATION ...................... I-13 4.1 Memory Map .................................................................. I-13 4.2 Oscillation Circuit ............................................................ I-18 Crystal oscillation circuit ......................................... I-18 CR oscillation circuit ............................................... I-19 4.3 Input Ports (K00-K03) .................................................... I-20 Configuration of input port ...................................... Interrupt function ................................................... Mask option ............................................................ Control of input port ............................................... 4.4 I-20 I-20 I-22 I-23 Output Ports (R00, R01) ................................................. I-25 Configuration of output port .................................... I-25 Mask option ............................................................ I-26 Control of output port ............................................. I-28 4.5 I/O Ports (P00-P03) ....................................................... I-31 Configuration of I/O port ........................................ I/O control register and I/O mode ........................... Mask option ............................................................ Control of I/O port .................................................. 4.6 LCD Driver (COM0-COM3, SEG0-SEG19) .................. I-35 Configuration of LCD driver ..................................... Cadence adjustment of oscillation frequency ........... Mask option (segment allocation) ............................. Control of LCD driver .............................................. 4.7 I-31 I-32 I-32 I-33 I-35 I-41 I-42 I-44 Clock Timer .................................................................... I-45 Configuration of clock timer .................................... I-45 Interrupt function ................................................... I-46 Control of clock timer .............................................. I-47 4.8 Heavy Load Protection Function .................................... I-49 Operation of heavy load protection function ............ I-49 Control of heavy load protection function ................ I-50 I-ii EPSON S1C60N01 TECHNICAL HARDWARE CONTENTS Interrupt and HALT ......................................................... I-51 Interrupt factors ...................................................... Specific masks and factor flags for interrupt ............ Interrupt vectors ..................................................... Control of interrupt ................................................. I-53 I-54 I-54 I-55 CHAPTER 5 BASIC EXTERNAL WIRING DIAGRAM ............................. I-56 CHAPTER 6 ELECTRICAL CHARACTERISTICS .................................... I-58 CHAPTER 7 CHAPTER 8 6.1 Absolute Maximum Rating ............................................. I-58 6.2 Recommended Operating Conditions ............................ I-59 6.3 DC Characteristics ......................................................... I-60 6.4 Analog Circuit Characteristics and Power Current Consumption ................................... I-62 6.5 Oscillation Characteristics .............................................. I-66 PACKAGE ...................................................................... I-68 7.1 Plastic Package .............................................................. I-68 7.2 Ceramic Package for Test Samples ............................... I-69 PAD LAYOUT .................................................................. I-70 8.1 Diagram of Pad Layout ................................................... I-70 8.2 Pad Coordinates ............................................................. I-71 S1C60N01 TECHNICAL HARDWARE EPSON I-iii Hardware 4.9 CHAPTER 1: INTRODUCTION CHAPTER 1 INTRODUCTION Each member of the S1C60N01 Series of single chip microcomputers feature a 4-bit S1C6200B core CPU, 1,024 words of ROM (12 bits per word), 80 words of RAM (4 bits per word), an LCD driver, 4 bits for input ports (K00-K03), 2 bits for output ports (R00, R01), one 4-bit I/O port (P00- P03) and one timer (clock timer). Because of their low voltage operation and low power consumption, the S1C60N01 Series are ideal for a wide range of applications. 1.1 Configuration The S1C60N01 Series are configured as follows, depending on the supply voltage. Table 1.1.1 Configuration of the S1C60N01 Series S1C60N01 TECHNICAL HARDWARE Model Supply Voltage Supply Voltage Range Oscillation Circuits S1C60N01 3.0 V 1.8-3.6 V Crystal or CR S1C60L01 1.5 V 1.2-2.0 V Crystal or CR EPSON I-1 CHAPTER 1: INTRODUCTION 1.2 Features Core CPU S1C6200B Built-in oscillation circuit Crystal or CR oscillation circuit, 32.768 kHz (typ.) Instruction set 100 instructions ROM capacity 1,024 words x12 bits RAM capacity (data RAM) 80 words x 4 bits Input port 4 bits (Supplementary pull-down resistors may be used ) Output port 2 bits (Piezo buzzer and programmable frequency output can be driven directry by mask option) Input/output port 4 bits LCD driver 20 segments x 4, 3 or 2 common duty Timer 1 system: clock timer Interrupts: External interrupt Input port interrupt Internal interrupt Timer interrupt 1 system 1 system Supply voltage 1.5 V (1.2-2.0 V) 3.0 V (1.8-3.6 V) Current consumption (typ.) 1.0 A (Crystal oscillation CLK = 32.768 kHz, when halted) 2.5 A (Crystal oscillation CLK = 32.768 kHz, when executing) Supply form QFP12-48pin (plastic) or chip I-2 EPSON S1C60L01 S1C60N01 S1C60N01 TECHNICAL HARDWARE CHAPTER 1: INTRODUCTION ROM 1,024 x 12 RESET OSC1 OSC2 1.3 Block Diagram OSC System Reset Control Core CPU S1C6200B RAM 80 x 4 COM0 | COM3 SEG0 | SEG19 Interrupt Generator LCD Driver I Port Test Port K00~K03 Power Controller I/O Port P00~P03 O Port R00, R01 TEST VDD VL1 | VL3 CA CB VS1 VSS (FOUT/BUZZER) (BUZZER) FOUT & BUZZER Timer Fig. 1.3.1 Block diagram S1C60N01 TECHNICAL HARDWARE EPSON I-3 CHAPTER 1: INTRODUCTION 1.4 Pin Layout Diagram QFP12-48pin 36 25 37 24 INDEX 48 13 1 12 Pin No Pin Name Pin No Pin Name Pin No Pin Name Pin No Pin Name Fig. 1.4.1 Pin assignment I-4 1 OSC2 13 R01 25 TEST 37 COM0 2 VS1 14 R00 26 RESET 38 COM1 3 N.C. 15 SEG19 27 SEG9 39 COM2 4 P00 16 SEG18 28 SEG8 40 COM3 5 P01 17 SEG17 29 SEG7 41 VL3 6 P02 18 SEG16 30 SEG6 42 VL2 7 P03 19 SEG15 31 SEG5 43 VL1 8 K00 20 SEG14 32 SEG4 44 CA 9 K01 21 SEG13 33 SEG3 45 CB 10 K02 22 SEG12 34 SEG2 46 VSS 11 K03 23 SEG11 35 SEG1 47 VDD 12 N.C. 24 SEG10 36 SEG0 48 OSC1 N.C. = No Connection EPSON S1C60N01 TECHNICAL HARDWARE CHAPTER 1: INTRODUCTION 1.5 Pin Description Table 1.5.1 Pin description Terminal Name Pin No. Input/Output Function VDD 47 (I) Power source (+) terminal VSS 46 (I) Power source (-) terminal VS1 2 O Oscillation and internal logic system regulated voltage output terminal VL1 43 O VL2 42 O LCD system reducer output terminal (VL2 x 1/2) / LCD system reducer output terminal (VL3 x 1/3) LCD system booster output terminal (VL1 x 2) / LCD system reducer output terminal (VL3 x 2/3) VL3 LCD system booster output terminal (VL1 x 3) 41 O 44, 45 - Booster capacitor connecting terminal OSC1 48 I Crystal or CR oscillation input terminal OSC2 1 O Crystal or CR oscillation output terminal Input terminal / LCD system booster output terminal (VL2 x 3/2) CA, CB K00-K03 8-11 I P00-P03 4-7 I/O R00, R01 14, 13 O Output terminal SEG0-19 36-27 O LCD segment output terminal (convertible to DC output terminal by mask option) 24-15 COM0-3 I/O terminal 37-40 O LCD common output terminal RESET 26 I Initial setting input terminal TEST 25 I Test input terminal S1C60N01 TECHNICAL HARDWARE EPSON I-5 CHAPTER 2: POWER SUPPLY AND INITIAL RESET CHAPTER 2 POWER SUPPLY AND INITIAL RESET 2.1 Power Supply With a single external power supply (*1) supplied to VDD through VSS, the S1C60N01 Series generate the necessary internal voltages with the regulated voltage circuit (<VS1> for oscillators and internal circuit) and the voltage booster/ reducer (<VL2, VL3 or VL1, VL3> for LCDs). When the S1C60N01 LCD power is selected for 4.5 V LCD panel by mask option, the S1C60N01 short-circuits between <VL2> and <VSS> in internally, and the voltage booster/ reducer generates <VL1> and <VL3>. When 3.0 V LCD panel is selected, the S1C60N01 short-circuits between <VL3> and <VSS>, and the voltage reducer generates <VL1> and <VL2>. The S1C60L01 short-circuits between <VL1> and <VSS>, and the voltage booster generates <VL2> and <VL3>. The voltage <VS1> for the internal circuit that is generated by the regulated voltage circuit is -1.2 V (VDD standard). Figure 2.1.1 shows the power supply configuration of the S1C60N01 Series in each condition. *1 Supply voltage: Note - I-6 S1C60N01 .... 3.0 V S1C60L01 .... 1.5 V External loads cannot be driven by the output voltage of the regulated voltage circuit and the voltage booster/reducer. See Chapter 6, "ELECTRICAL CHARACTERISTICS", for voltage values. EPSON S1C60N01 TECHNICAL HARDWARE CHAPTER 2: POWER SUPPLY AND INITIAL RESET * S1C60N01 4.5 V LCD panel 1/4, 1/3, 1/2 duty, 1/3 bias VDD VS1 VL1 VL2 VL3 CA C5 C2 C4 C1 3V CB VSS Note: VL2 is shorted to VSS inside the IC. 3 V LCD panel 1/4, 1/3, 1/2 duty, 1/3 bias VDD VS1 VL1 VL2 VL3 CA 3 V LCD panel 1/4, 1/3, 1/2 duty, 1/2 bias VDD VS1 VL1 VL2 VL3 CA C5 C2 C3 C1 3V CB VSS C5 C2 C1 3V CB VSS Note: VL3 is shorted to VSS inside the IC. * S1C60L01 4.5 V LCD panel 1/4, 1/3, 1/2 duty, 1/3 bias VDD VS1 VL1 VL2 VL3 CA 3 V LCD panel 1/4, 1/3, 1/2 duty, 1/2 bias VDD VS1 VL1 VL2 VL3 CA C5 C3 C4 1.5 V C1 CB VSS C5 C4 C1 1.5 V CB VSS Note: VL1 is shorted to VSS inside the IC. Fig. 2.1.1 External element configuration of power system S1C60N01 TECHNICAL HARDWARE EPSON I-7 CHAPTER 2: POWER SUPPLY AND INITIAL RESET 2.2 Initial Reset To initialize the S1C60N01 Series circuits, an initial reset must be executed. There are three ways of doing this. (1) Initial reset by the oscillation detection circuit (Note) (2) External initial reset via the RESET pin (3) External initial reset by simultaneous high input to pins K00-K03 (depending on mask option) Figure 2.2.1 shows the configuration of the initial reset circuit. OSC1 OSC1 OSC2 Oscillation circuit Oscillation detection circuit K00 Vss Noise rejection circuit K01 Initial reset Noise rejection circuit K02 K03 Fig. 2.2.1 Configuration of initial reset circuit RESET Vss Note Be sure to use reset function (2) or (3) at power-on because the initial reset function by the oscillation detection circuit (1) may not operate normally depending on the power-on procedure. I-8 EPSON S1C60N01 TECHNICAL HARDWARE CHAPTER 2: POWER SUPPLY AND INITIAL RESET Oscillation detection The oscillation detection circuit outputs the initial reset signal at power-on until the crystal oscillation circuit starts circuit oscillating, or when the crystal oscillation circuit stops oscillating for some reason. However, use the following reset functions at power-on because the initial reset function by the oscillation detection circuit may not operate normally depending on the power-on procedure. Reset pin (RESET) An initial reset can be invoked externally by making the reset pin high. This high level must be maintained for at least 5 ms (when oscillating frequency, fosc = 32 kHz), because the initial reset circuit contains a noise rejection circuit. When the reset pin goes low the CPU begins to operate. Simultaneous high input to input ports (K00-K03) Another way of invoking an initial reset externally is to input a high signal simultaneously to the input ports (K00-K03) selected with the mask option. The specified input port pins must be kept high for at least 4 sec (when oscillating frequency fosc = 32 kHz), because of the noise rejection circuit. Table 2.2.1 shows the combinations of input ports (K00- K03) that can be selected with the mask option. Table 2.2.1 Input port combinations A B C D Not used K00*K01 K00*K01*K02 K00*K01*K02*K03 When, for instance, mask option D (K00*K01*K02*K03) is selected, an initial reset is executed when the signals input to the four ports K00-K03 are all high at the same time. If you use this function, make sure that the specified ports do not go high at the same time during normal operation. S1C60N01 TECHNICAL HARDWARE EPSON I-9 CHAPTER 2: POWER SUPPLY AND INITIAL RESET Internal register following initialization An initial reset initializes the CPU as shown in the table below. Table 2.2.2 Initial values CPU Core Name Program counter step Program counter page New page pointer Stack pointer Index register X Index register Y Register pointer General register A General register B Interrupt flag Decimal flag Zero flag Carry flag Signal Number of Bits Setting Value PCS PCP NPP SP X Y RP A B I D Z C 8 4 4 8 8 8 4 4 4 1 1 1 1 00H 1H 1H Undefined Undefined Undefined Undefined Undefined Undefined 0 0 Undefined Undefined Peripheral Circuits Name Number of Bits Setting Value 80 x 4 20 x 4 - Undefined Undefined *1 RAM Display memory Other peripheral circuit *1: See section 4.1, "Memory Map" 2.3 Test Pin (TEST) This pin is used when IC is inspected for shipment. During normal operation connect it to VSS. I-10 EPSON S1C60N01 TECHNICAL HARDWARE CHAPTER 3: CPU, ROM, RAM CHAPTER 3 CPU, ROM, RAM 3.1 CPU The S1C60N01 Series employs the S1C6200B core CPU, so that register configuration, instructions, and so forth are virtually identical to those in other processors in the family using the S1C6200B. Refer to the "S1C6200/6200A Core CPU Manual" for details of the S1C6200B. Note the following points with regard to the S1C60N01 Series: (1) The SLEEP operation is not provided, so the SLP instruction cannot be used. (2) Because the ROM capacity is 1,024 words, 12 bits per word, bank bits are unnecessary, and PCB and NBP are not used. (3) The RAM page is set to 0 only, so the page part (XP, YP) of the index register that specifies addresses is invalid. PUSH POP LD LD S1C60N01 TECHNICAL HARDWARE XP XP XP,r r,XP EPSON PUSH POP LD LD YP YP YP,r r,YP I-11 CHAPTER 3: CPU, ROM, RAM 3.2 ROM The built-in ROM, a mask ROM for the program, has a capacity of 1,024 x 12-bit steps. The program area is 4 pages (0-3), each consisting of 256 steps (00H-FFH). After an initial reset, the program start address is page 1, step 00H. The interrupt vector is allocated to page l, steps 01H- 07H. Bank 0 00H step 0 page Program start address 01H step 1 page 2 page Interrupt vector area 3 page 07H step 08H step Program area FFH step Fig. 3.2.1 12 bits ROM configuration 3.3 RAM The RAM, a data memory for storing a variety of data, has a capacity of 80 words, 4-bit words. When programming, keep the following points in mind: (1) Part of the data memory is used as stack area when saving subroutine return addresses and registers, so be careful not to overlap the data area and stack area. (2) Subroutine calls and interrupts take up three words on the stack. (3) Data memory 000H-00FH is the memory area pointed by the register pointer (RP). I-12 EPSON S1C60N01 TECHNICAL HARDWARE CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Memory Map) CHAPTER 4 PERIPHERAL CIRCUITS AND OPERATION Peripheral circuits (timer, I/O, and so on) of the S1C60N01 Series are memory mapped. Thus, all the peripheral circuits can be controlled by using memory operations to access the I/O memory. The following sections describe how the peripheral circuits operate. 4.1 Memory Map The data memory of the S1C60N01 Series has an address space of 113 words, of which 32 words are allocated to display memory and 13 words, to I/O memory. Figure 4.1.1 show the overall memory map for the S1C60N01 Series, and Tables 4.1.1(a)-(d), the memory maps for the peripheral circuits (I/O space). Address Low 0 Page 1 2 3 4 5 6 7 8 9 A B C D F E High 0 M0 M1 M2 M3 M4 M5 M6 M7 M8 M9 MA MB MC MD ME MF 1 2 RAM area (000H-04FH) 80 words x 4 bits (R/W) 3 4 5 6 0 7 8 Display memory area (090H-0AFH) 32 words x 4 bits (Write only) 9 A B C D Fig. 4.1.1 E F I/O memory area Memory map Tables 4.1.1(a)-(d) Unused area Note Memory is not mounted in unused area within the memory map and in memory area not indicated in this chapter. For this reason, normal operation cannot be assured for programs that have been prepared with access to these areas. S1C60N01 TECHNICAL HARDWARE EPSON I-13 CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Memory Map) Table 4.1.1(a) I/O memory map Address D3 Register D2 D1 D0 Name K03 K02 K00 K03 - K02 K01 R SR *1 Comment 1 0 *2 High Low - *2 High Low K01 - *2 High Low K00 - *2 High Low TM3 - High Low Timer data (clock timer 2 Hz) TM2 - High Low Timer data (clock timer 4 Hz) TM1 - High Low Timer data (clock timer 8 Hz) TM0 - High Low Timer data (clock timer 16 Hz) EIK03 0 Enable Mask Interrupt mask register (K03) EIK02 0 Enable Mask Interrupt mask register (K02) EIK01 0 Enable Mask Interrupt mask register (K01) EIK00 0 Enable Mask Interrupt mask register (K00) EIT2 0 Enable Mask Interrupt mask register (clock timer 2 Hz) EIT8 0 Enable Mask Interrupt mask register (clock timer 8 Hz) EIT32 0 Enable Mask Interrupt mask register (clock timer 32 Hz) 0E0H Input port (K00-K03) TM3 TM2 TM1 TM0 R 0E4H EIK03 EIK02 EIK01 EIK00 R/W 0E8H 0 R EIT2 EIT8 R/W EIT32 0 *5 0EBH *1 *2 *3 *4 *5 *6 I-14 Initial value following initial reset Not set in the circuit Undefined Reset (0) immediately after being read Constantly 0 when being read Refer to main manual EPSON S1C60N01 TECHNICAL HARDWARE CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Memory Map) Table 4.1.1(b) I/O memory map Address Register D2 D1 D3 0 0 0 D0 Name IK0 0 0 R 0EDH 0 IK0 0 IT2 IT8 IT32 R 0 IT2 0EFH IT8 IT32 0 0 R01 BUZZER R R00 FOUT R/W 0F3H P03 P02 P01 R/W P00 1 0 0 Yes No Interrupt factor flag (K00-K03) 0 Yes No Interrupt factor flag (clock timer 2 Hz) 0 Yes No Interrupt factor flag (clock timer 8 Hz) 0 Yes No Interrupt factor flag (clock timer 32 Hz) *5 *5 *5 *4 *5 *4 *4 *4 0 *5 0 *5 R01 0 High Low R01 output port data BUZZER 0 ON OFF Buzzer ON/OFF control register R00 0 High Low R00 output port data FOUT 0 ON OFF Frequency output ON/OFF control register P03 - *2 High Low P02 - *2 High Low P01 - *2 High Low P00 - *2 High Low 0F6H *1 *2 *3 *4 *5 *6 Comment SR *1 I/O port (P00-P03) Initial value following initial reset Not set in the circuit Undefined Reset (0) immediately after being read Constantly 0 when being read Refer to main manual S1C60N01 TECHNICAL HARDWARE EPSON I-15 CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Memory Map) Table 4.1.1(c) I/O memory map Address D3 Register D2 D1 0 TMRST R W 0 D0 Name 0 0 1 0 Reset Reset - 0 Heavy load Normal load Heavy load protection mode register 0 Static Dynamic LCD drive switch 0 Output Input *5 TMRST R Comment SR *1 Clock timer reset 0F9H HLMOD 0 R/W 0 0 R 0 *5 0 *5 HLMOD 0 0FAH 0 0 CSDC 0 R/W 0 0 R *5 *5 *5 CSDC 0 *5 0 *5 0 *5 0FBH 0 0 R 0 IOC 0 *5 R/W 0 *5 0FCH 0 *5 IOC *1 *2 *3 *4 *5 *6 I-16 I/O port P00-P03 Input/Output Initial value following initial reset Not set in the circuit Undefined Reset (0) immediately after being read Constantly 0 when being read Refer to main manual EPSON S1C60N01 TECHNICAL HARDWARE CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Memory Map) Table 4.1.1(d) I/O memory map Address D3 Register D2 D1 D0 Comment Name SR *1 1 0 0 2 kHz 4 kHz Buzzer frequency control 0 High Low FOUT frequency control: XBZR 0 XFOUT1 XFOUT0 XBZR R/W R R/W 0 *5 0FDH XFOUT1 XFOUT0 *1 *2 *3 *4 *5 *6 0 High Low XFOUT1(0), XFOUT0(0) -> F1 XFOUT1(0), XFOUT0(1) -> F2 XFOUT1(1), XFOUT0(0) -> F3 XFOUT1(1), XFOUT0(1) -> F4 Initial value following initial reset Not set in the circuit Undefined Reset (0) immediately after being read Constantly 0 when being read Refer to main manual S1C60N01 TECHNICAL HARDWARE EPSON I-17 CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Oscillation Circuit) 4.2 Oscillation Circuit Crystal oscillation circuit The S1C60N01 Series have a built-in crystal oscillation circuit. This circuit generates the operating clock for the CPU and peripheral circuit on connection to an external crystal oscillator (typ. 32.768 kHz) and trimmer capacitor (5-25 pF). Figure 4.2.1 is the block diagram of the crystal oscillation circuit. VDD CG OSC2 Fig. 4.2.1 Crystal oscillation circuit RD To CPU and peripheral circuits Rf X'tal OSC1 VDD CD The S1C60N01 Series As Figure 4.2.1 indicates, the crystal oscillation circuit can be configured simply by connecting the crystal oscillator (X'tal) between the OSC1 and OSC2 pins and the trimmer capacitor (CG) between the OSC1 and VDD pins. Note The OSC1 and OSC2 terminals on the board should be shielded with the VDD (+ side). I-18 EPSON S1C60N01 TECHNICAL HARDWARE CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Oscillation Circuit) CR oscillation circuit For the S1C60N01 Series, CR oscillation circuit (typ. 65 kHz) may also be selected by a mask option. Figure 4.2.2 is the block diagram of the CR oscillation circuit. OSC1 To CPU and peripheral circuits R OSC2 C Fig. 4.2.2 The S1C60N01 Series CR oscillation circuit As Figure 4.2.2 indicates, the CR oscillation circuit can be configured simply by connecting the register (R) between pins OSC1 and OSC2 since capacity (C) is built-in. See Chapter 6, "ELECTRICAL CHARACTERISTICS" for R value. S1C60N01 TECHNICAL HARDWARE EPSON I-19 CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Input Ports) 4.3 Input Ports (K00-K03) Configuration of input port The S1C60N01 Series have a 4-bit general-purpose input port. Each of the input port pins (K00-K03) has an internal pull-down resistance. The pull-down resistance can be selected for each bit with the mask option. Figure 4.3.1 shows the configuration of input port. Interrupt request Kxx Data bus VDD Address Fig. 4.3.1 VSS Configuration of input port Mask option Selecting "pull-down resistance enabled" with the mask option allows input from a push button, key matrix, and so forth. When "pull-down resistance disabled" is selected, the port can be used for slide switch input and interfacing with other LSIs. Interrupt function I-20 All four input port bits (K00-K03) provide the interrupt function. The conditions for issuing an interrupt can be set by the software for the four bits. Also, whether to mask the interrupt function can be selected individually for all four bits by the software. Figure 4.3.2 shows the configuration of K00-K03. EPSON S1C60N01 TECHNICAL HARDWARE CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Input Ports) Kxx Data bus One for each pin series Address Noise rejector Interrupt factor flag (IK) Interrupt request Address Fig. 4.3.2 Input interrupt circuit configuration (K00-K03) Mask option (K00-K03) Interrupt mask register (EIK) Address The interrupt mask registers (EIK00-EIK03) enable the interrupt mask to be selected individually for K00-K03. An interrupt occurs when the input value which are not masked change and the interrupt factor flag (IK0) is set to 1. Input interrupt programing related precautions Port K input Active status Mask register Fig. 4.3.3 Input interrupt timing Factor flag set Not set When the content of the mask register is rewritten, while the port K input is in the active status. The input interrupt factor flag is set at . When using an input interrupt, if you rewrite the content of the mask register, when the value of the input terminal which becomes the interrupt input is in the active status (input terminal = high status), the factor flag for input interrupt may be set. For example, a factor flag is set with the timing of shown in Figure 4.3.3. However, when clearing the content of the mask register with the input terminal kept in the high status and then setting it, the factor flag of the input interrupt is again set at the timing that has been set. S1C60N01 TECHNICAL HARDWARE EPSON I-21 CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Input Ports) Consequently, when the input terminal is in the active status (high status), do not rewrite the mask register (clearing, then setting the mask register), so that a factor flag will only set at the rising edge in this case. When clearing, then setting the mask register, set the mask register, when the input terminal is not in the active status (low status). Mask option The contents that can be selected with the input port mask option are as follows: (1) An internal pull-down resistance can be selected for each of the four bits of the input ports (K00-K03). Having selected "pull-down resistance disabled", take care that the input does not float. Select "pull-down resistance enabled" for input ports that are not being used. (2) The input interrupt circuit contains a noise rejection circuit to prevent interrupts form occurring through noise. The mask option enables selection of the noise rejection circuit for each separate pin series. When "use" is selected, a maximum delay of 0.5 ms (fosc = 32 kHz) occurs from the time an interrupt condition is established until the interrupt factor flag (IK) is set to 1. I-22 EPSON S1C60N01 TECHNICAL HARDWARE CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Input Ports) Control of input port Table 4.3.1 list the input port control bits and their addresses. Table 4.3.1 Input port control bits Address D3 Register D2 D1 D0 Name SR 1 0 K03 K02 K00 K03 - High Low K02 - High Low K01 - High Low K00 - High Low EIK03 0 Enable Mask Interrupt mask register (K03) EIK02 0 Enable Mask Interrupt mask register (K02) EIK01 0 Enable Mask Interrupt mask register (K01) EIK00 0 Enable Mask Interrupt mask register (K00) 0 Yes No K01 R Comment 0E0H Input port (K00-K03) EIK03 EIK02 EIK01 EIK00 R/W 0E8H 0 0 0 R IK0 0 0 0EDH 0 IK0 Interrupt factor flag (K00-K03) K00-K03 Input port data (0E0H) The input data of the input port pins can be read with these registers. When 1 is read: High level When 0 is read: Low level Writing: Invalid The value read is 1 when the pin voltage of the four bits of the input port (K00-K03) goes high (VDD), and 0 when the voltage goes low (VSS). These bits are reading, so writing cannot be done. S1C60N01 TECHNICAL HARDWARE EPSON I-23 CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Input Ports) EIK00-EIK03 Interrupt mask registers (0E8H) Masking the interrupt of the input port pins can be done with these registers. When 1 is written: Enable When 0 is written: Mask Reading: Valid With these registers, masking of the input port bits can be done for each of the four bits. After an initial reset, these registers are all set to 0. IK0 Interrupt factor flag (0EDH) This flag indicates the occurrence of an input interrupt. When 1 is read: When 0 is read: Writing: Interrupt has occurred Interrupt has not occurred Invalid The interrupt factor flag IK0 is associated with K00-K03. From the status of this flag, the software can decide whether an input interrupt has occurred. This flag is reset when the software has read it. Reading of interrupt factor flag is available at EI, but be careful in the following cases. If the interrupt mask register value corresponding to the interrupt factor flag to be read is set to 1, an interrupt request will be generated by the interrupt factor flag set timing, or an interrupt request will not be generated. After an initial reset, this flag is set to 0. I-24 EPSON S1C60N01 TECHNICAL HARDWARE CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Output Ports) 4.4 Output Ports (R00, R01) Configuration of output port The S1C60N01 Series have a 2-bit general output port (R00, R01). Output specification of the output port can be selected in a bit unit with the mask option. Two kinds of output specifications are available: complementary output and Pch open drain output. Also, the mask option enables the output ports R00 and R01 to be used as special output ports. Figure 4.4.1 shows the configuration of the output port. Data bus VDD Register Rxx Complementary Pch open drain Address VSS Fig. 4.4.1 Mask option Configuration of output port S1C60N01 TECHNICAL HARDWARE EPSON I-25 CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Output Ports) The mask option enables the following output port selection. Mask option (1) Output specification of output port The output specifications for the output port (R00, R01) may be either complementary output or Pch open drain output for each of the two bits. However, even when Pch open drain output is selected, a voltage exceeding the source voltage must not be applied to the output port. (2) Special output In addition to the regular DC output, special output can be selected for output ports R00 and R01, as shown in Table 4.4.1. Figure 4.4.2 shows the structure of output ports R00 and R01. Table 4.4.1 Pin Name When Special Output is Selected Special output R00 FOUT or BUZZER R01 BUZZER Data bus BUZZER R01 Register (R01) BUZZER Register (R00) Fig. 4.4.2 Structure of output ports R00, R01 I-26 R00 FOUT Address (0F3H) Mask option EPSON S1C60N01 TECHNICAL HARDWARE CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Output Ports) FOUT (R00) When output port R00 is set for FOUT output, this port will generate fosc (CPU operating clock frequency) or clock frequency divided into fosc. Clock frequency may be selected individually for F1-F4, from among 5 types by mask option; one among F1-F4 is selected by software and used. The types of frequency which may be selected are shown in Table 4.4.2. Table 4.4.2 FOUT clock frequency Mask Option Sets Clock Frequency (Hz) fosc = 32.768 kHz F1 F2 F3 F4 (D1,D0)=(0,0) (D1,D0)=(0,1) (D1,D0)=(1,0) (D1,D0)=(1,1) Set 1 256 (fosc/128) 512 (fosc/64) 1,024 (fosc/32) 2,048 (fosc/16) Set 2 512 (fosc/64) 1,024 (fosc/32) 2,048 (fosc/16) 4,096 (fosc/8) Set 3 1,024 (fosc/32) 2,048 (fosc/16) 4,096 (fosc/8) 8,192 (fosc/4) Set 4 2,048 (fosc/16) 4,096 (fosc/8) 8,192 (fosc/4) 16,384 (fosc/2) Set 5 4,096 (fosc/8) 8,192 (fosc/4) 16,384 (fosc/2) 32,768 (fosc/1) (D1, D0) = (XFOUT1, XFOUT0) Note A hazard may occur when the FOUT signal is turned on or off. BUZZER, BUZZER Output ports R01 and R00 may be set to BUZZER output (R01, R00) and BUZZER output (BUZZER reverse output), respectively, allowing for direct driving of the piezo-electric buzzer. BUZZER output (R00) may only be set if R01 is set to BUZZER output. In such case, whether ON/OFF of the BUZZER output is done through R00 register or is controlled through R01 simultaneously with BUZZER output is also selected by mask option. The frequency of buzzer output may be selected by software to be either 2 kHz or 4 kHz. S1C60N01 TECHNICAL HARDWARE EPSON I-27 CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Output Ports) Table 4.4.3 lists the output port control bits and their addresses. Control of output port Table 4.4.3 Control bits of output port Address Register D2 D1 R01 0 BUZZER D3 0 R D0 R00 FOUT R/W 0F3H Name SR 1 Comment 0 0 0 R01 0 High Low R01 output port data BUZZER 0 ON OFF Buzzer ON/OFF control register R00 0 High Low R00 output port data FOUT 0 ON OFF Frequency output ON/OFF control register 0 2 kHz 4 kHz Buzzer frequency control XFOUT1 0 High Low FOUT frequency control: XFOUT0 0 High Low XBZR 0 XFOUT1 XFOUT0 XBZR R/W R R/W 0 0FDH XFOUT1(0), XFOUT0(0) -> F1 XFOUT1(0), XFOUT0(1) -> F2 XFOUT1(1), XFOUT0(0) -> F3 XFOUT1(1), XFOUT0(1) -> F4 R00, R01 Output port data (0F3H D0, 0F3H D1) Sets the output data for the output ports. When 1 is written: High output When 0 is written: Low output Reading: Valid The output port pins output the data written to the corresponding registers (R00, R01) without changing it. When 1 is written to the register, the output port pin goes high (VDD), and when 0 is written, the output port pin goes low (VSS). After an initial reset, all the registers are set to 0. I-28 EPSON S1C60N01 TECHNICAL HARDWARE CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Output Ports) R00 (when FOUT is Special output port data (0F3H D0) selected) Controls the FOUT (clock) output. When 1 is written: Clock output When 0 is written: Low level (DC) output Reading: Valid FOUT output can be controlled by writing data to R00. After an initial reset, this register is set to 0. Figure 4.4.3 shows the output waveform for FOUT output. R00 register Fig. 4.4.3 FOUT output waveform 0 1 FOUT output waveform XFOUT0, XFOUT1 FOUT frequency control (0FDH D0, 0FDH D1) Selects the output frequency when R00 port is set for FOUT output. Table 4.4.4 FOUT frequency selection XFOUT1 XFOUT0 Frequency Selection 0 0 F1 0 1 F2 1 0 F3 1 1 F4 After an initial reset, these registers are set to 0. S1C60N01 TECHNICAL HARDWARE EPSON I-29 CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Output Ports) R00, R01 (when BUZZER Special output port data (0F3H D0, 0F3H D1) and BUZZER is Controls the buzzer output. selected) When 1 is written: Buzzer output When 0 is written: Low level (DC) output Reading: Valid BUZZER and BUZZER output can be controlled by writing data to R00 and R01. When BUZZER output by R01 register control is selected by mask option, BUZZER output and BUZZER output can be controlled simultaneously by writing data to R01 register. After an initial reset, these registers are set to 0. Figure 4.4.4 shows the output waveform for buzzer output. R01 (R00) register 0 1 BUZZER output waveform Fig. 4.4.4 Buzzer output waveform BUZZER output waveform XBZR Buzzer frequency control (0FDH D3) Selects the frequency of the buzzer signal. When 1 is written: 2 kHz When 0 is written: 4 kHz Reading: Valid When R00 and R01 port is set to buzzer output, the frequency of the buzzer signal can be selected by this register. When 1 is written to this register, the frequency is set in 2 kHz, and in 4 kHz when 0 is written. After an initial reset, this register is set to 0. I-30 EPSON S1C60N01 TECHNICAL HARDWARE CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (I/O Ports) 4.5 I/O Ports (P00-P03) The S1C60N01 Series have a 4-bit general-purpose I/O port. Figure 4.5.1 shows the configuration of the I/O port. The four bits of the I/O port P00-P03 can be set to either input mode or output mode. The mode can be set by writing data to the I/O control register (IOC). Data bus Configuration of I/O port Input control Register Pxx Address Fig. 4.5.1 Configuration of I/O port S1C60N01 TECHNICAL HARDWARE Address I/O control register (IOC) EPSON Vss I-31 CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (I/O Ports) I/O control register and I/O mode Input or output mode can be set for the four bits of I/O port P00-P03 by writing data into I/O control register IOC. To set the input mode, 0 is written to the I/O control register. When an I/O port is set to input mode, its impedance becomes high and it works as an input port. However, the input line is pulled down when input data is read. The output mode is set when 1 is written to the I/O control register (IOC). When an I/O port set to output mode works as an output port, it outputs a high signal (VDD) when the port output data is 1, and a low signal (VSS) when the port output data is 0. After an initial reset, the I/O control register is set to 0, and the I/O port enters the input mode. Mask option I-32 The output specification during output mode (IOC = 1) of the I/O port can be set with the mask option for either complementary output or Pch open drain output. This setting can be performed for each bit of the I/O port. However, when Pch open drain output has been selected, voltage in excess of the supply voltage must not be applied to the port. EPSON S1C60N01 TECHNICAL HARDWARE CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (I/O Ports) Table 4.5.1 lists the I/O port control bits and their addresses. Control of I/O port Table 4.5.1 I/O port control bits Address D3 Register D2 D1 D0 Name SR 1 0 P03 P02 P00 P03 - High Low P02 - High Low P01 - High Low P00 - High Low 0 Output Input P01 R/W 0F6H Comment I/O port (P00-P03) 0 0 R 0 IOC 0 R/W 0 0FCH 0 IOC I/O port P00-P03 Input/Output P00-P03 I/O port data (0F6H) I/O port data can be read and output data can be written through the port. * When writing data When 1 is written: High level When 0 is written: Low level When an I/O port is set to the output mode, the written data is output from the I/O port pin unchanged. When 1 is written as the port data, the port pin goes high (VDD), and when 0 is written, the level goes low (VSS). Port data can also be written in the input mode. * When reading data When 1 is read: When 0 is read: S1C60N01 TECHNICAL HARDWARE EPSON High level Low level I-33 CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (I/O Ports) The pin voltage level of the I/O port is read. When the I/ O port is in the input mode the voltage level being input to the port pin can be read; in the output mode the output voltage level can be read. When the pin voltage is high (VDD) the port data read is 1, and when the pin voltage is low (VSS) the data is 0. Also, the built-in pulldown resistance functions during reading, so the I/O port pin is pulled down. Note - - When the I/O port is set to the output mode and a low-impedance load is connected to the port pin, the data written to the register may differ from the data read. When the I/O port is set to the input mode and a low-level voltage (Vss) is input by the built-in pull-down resistance, an erroneous input results if the time constant of the capacitive load of the input line and the built- in pull-down resistance load is greater than the read-out time. When the input data is being read, the time that the input line is pulled down is equivalent to 0.5 cycles of the CPU system clock. Hence, the electric potential of the pins must settle within 0.5 cycles. If this condition cannot be met, some measure must be devised, such as arranging a pull-down resistance externally, or performing multiple read-outs. IOC I/O control register (0FCH D0) The input or output I/O port mode can be set with this register. When 1 is written: Output mode When 0 is written: Input mode Reading: Valid The input or output mode of the I/O port is set in units of four bits. For instance, IOC sets the mode for P00-P03. Writing 1 to the I/O control register makes the I/O port enter the output mode, and writing 0, the input mode. After an initial reset, the IOC register is set to 0, so the I/O port is in the input mode. I-34 EPSON S1C60N01 TECHNICAL HARDWARE CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (LCD Driver) 4.6 LCD Driver (COM0-COM3, SEG0-SEG19) Configuration of LCD The S1C60N01 Series have four common pins and 20 (SEG0-SEG19) segment pins, so that an LCD with a maxidriver mum of 80 (20 x 4) segments can be driven. The power for driving the LCD is generated by the CPU internal circuit, so there is no need to supply power externally. The driving method is 1/4 duty (or 1/3, 1/2 duty by mask option) dynamic drive, adopting the four types of potential (1/3 bias), VDD, VL1, VL2 and VL3. Moreover, the 1/2 bias dynamic drive that uses three types of potential, VDD, VL1 = VL2 and VL3, can be selected by setting the mask option (drive duty can also be selected from 1/4, 1/3 or 1/2). 1/2 bias drive is effective when the LCD system regulated voltage circuit is not used. The VL1 terminal and the VL2 terminal should be connected outside of the IC. The frame frequency is 32 Hz for 1/4 duty and 1/2 duty, and 42.7 Hz for 1/3 duty (in the case of fosc = 32.768 kHz). Figure 4.6.1 shows the drive waveform for 1/4 duty (1/3 bias), Figure 4.6.2 shows the drive waveform for 1/3 duty (1/3 bias), Figure 4.6.3 shows the drive waveform for 1/2 duty (1/3 bias), Figure 4.6.4 shows the drive waveform for 1/4 duty (1/2 bias), Figure 4.6.5 shows the drive waveform for 1/3 duty (1/2 bias) and Figure 4.6.6 shows the drive waveform for 1/2 duty (1/2 bias). Note fosc indicates the oscillation frequency of the oscillation circuit. S1C60N01 TECHNICAL HARDWARE EPSON I-35 CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (LCD Driver) COM0 -VDD -VL1 -VL2 -VL3 COM1 LCD lighting status COM0 COM1 COM2 COM3 SEG0-19 COM2 Not lit Lit COM3 -VDD -VL1 -VL2 -VL3 SEG 0-19 Fig. 4.6.1 Drive waveform for Frame frequency 1/4 duty (1/3 bias) I-36 EPSON S1C60N01 TECHNICAL HARDWARE CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (LCD Driver) COM0 -VDD -VL1 -VL2 -VL3 LCD lighting status COM0 COM1 COM2 COM1 SEG0-19 COM2 Not lit Lit COM3 -VDD -VL1 -VL2 -VL3 SEG 0-19 Fig. 4.6.2 Drive waveform for Frame frequency 1/3 duty (1/3 bias) S1C60N01 TECHNICAL HARDWARE EPSON I-37 CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (LCD Driver) -VDD -VL1 -VL2 -VL3 COM0 LCD lighting status COM0 COM1 SEG0-19 COM1 Not lit COM2 Lit COM3 -VDD -VL1 -VL2 -VL3 SEG 0-19 Fig. 4.6.3 Frame frequency Drive waveform for 1/2 duty (1/3 bias) I-38 EPSON S1C60N01 TECHNICAL HARDWARE CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (LCD Driver) -VDD -VL1, L2 -VL3 COM0 COM1 LCD lighting status COM0 COM1 COM2 COM3 SEG0-19 COM2 Not lit COM3 Lit -VDD -VL1, L2 -VL3 SEG 0-19 Fig. 4.6.4 Drive waveform for Frame frequency 1/4 duty (1/2 bias) S1C60N01 TECHNICAL HARDWARE EPSON I-39 CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (LCD Driver) -VDD -VL1, L2 -VL3 COM0 COM1 LCD lighting status COM0 COM1 COM2 SEG0-19 COM2 Not lit COM3 Lit -VDD -VL1, L2 -VL3 SEG 0-19 Fig. 4.6.5 Drive waveform for Frame frequency 1/3 duty (1/2 bias) -VDD -VL1, L2 -VL3 COM0 COM1 LCD lighting status COM0 COM1 SEG0-19 COM2 Not lit COM3 Lit -VDD -VL1, L2 -VL3 SEG 0-19 Fig. 4.6.6 Drive waveform for 1/2 duty (1/2 bias) I-40 Frame frequency EPSON S1C60N01 TECHNICAL HARDWARE CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (LCD Driver) Cadence adjustment of oscillation frequency In the S1C60N01 Series, the LCD drive duty can be set to 1/1 duty by software. This function enables easy adjustment (cadence adjustment) of the oscillation frequency of the OSC circuit. The procedure to set to 1/1 duty drive is as follows: Write 1 to the CSDC register at address 0FBH D3. Write the same value to all registers corresponding to COMs 0 through 3 of the display memory. The frame frequency is 32 Hz (fOSC1/1,024, when fOSC1 = 32.768 kHz). Note - - Even when l/3 or 1/2 duty is selected by the mask option, the display data corresponding to all COM are valid during 1/1 duty driving. Hence, for 1/1 duty drive, set the same value for all display memory corresponding to COMs 0 through 3. For cadence adjustment, set the display data corresponding to COMs 0 through 3, so that all the LCD segments go on. Figure 4.6.7 shows the 1/1 duty drive waveform (1/3 bias). Figure 4.6.8 shows the 1/1 duty drive waveform (1/2 bias). LCD lighting status -VDD -VL1 -VL2 -VL3 COM 0-3 Frame frequency COM0 COM1 COM2 COM3 SEG0-19 Not lit Lit -VDD -VL1 -VL2 -VL3 SEG 0-19 Fig. 4.6.7 1/1 duty drive waveform -VDD -VL1 -VL2 -VL3 (1/3 bias) LCD lighting status -VDD -VL1, VL2 -VL3 COM 0-3 SEG0-19 Not lit Lit Frame frequency -VDD -VL1, VL2 -VL3 SEG 0-19 -VDD -VL1, VL2 -VL3 Fig. 4.6.8 1/1 duty drive waveform (1/2 bias) S1C60N01 TECHNICAL HARDWARE COM0 COM1 COM2 COM3 EPSON I-41 CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (LCD Driver) (1) Segment allocation Mask option (segment allocation) As shown in Figure 4.l.1, the S1C60N01 Series display data is decided by the display data written to the display memory (write-only) at address 090H-0AFH. The address and bits of the display memory can be made to correspond to the segment pins (SEG0-SEG19) in any combination through mask option. This simplifies design by increasing the degree of freedom with which the liquid crystal panel can be designed. Figure 4.6.9 shows an example of the relationship between the LCD segments (on the panel) and the display memory in the case of 1/3 duty. Address Common 0 Common 1 Common 2 9A, D0 9B, D1 9B, D0 (a) (f) (e) SEG11 9A, D1 9B, D2 9A, D3 (b) (g) (d) SEG12 9D, D1 9A, D2 9B, D3 (f') (c) (p) Data D3 D2 D1 D0 09AH d c b a 09BH p g f e 09CH d' c' b' a' 09DH p' g' f' e' SEG10 Display data memory allocation Pin address allocation a a' b f g' g e c c' e' p d SEG10 b' f' SEG11 p' d' SEG12 Common 0 Common 1 Fig. 4.6.9 Segment allocation I-42 Common 2 EPSON S1C60N01 TECHNICAL HARDWARE CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (LCD Driver) (2) Drive duty According to the mask option, either 1/4, 1/3 or 1/2 duty can be selected as the LCD drive duty. Table 4.6.1 shows the differences in the number of segments according to the selected duty. Table 4.6.1 Differences according to selected duty Duty Pins Used in Common Maximum Number of Segments Frame Frequency (when fosc = 32 kHz) 1/4 1/3 1/2 COM0-3 COM0-2 COM0-1 80 (20 x 4) 60 (20 x 3) 40 (20 x 2) 32 Hz 42.7 Hz 32 Hz (3) Output specification The segment pins (SEG0-SEG19) are selected by mask option in pairs for either segment signal output or DC output (VDD and VSS binary output). When DC output is selected, the data corresponding to COM0 of each segment pin is output. When DC output is selected, either complementary output or Pch open drain output can be selected for each pin by mask option. Note The pin pairs are the combination of SEG (2*n) and SEG (2*n + 1) (where n is an integer from 0 to 12). (4) Drive bias For the drive bias of the S1C60N01 or the S1C60L01, either 1/3 bias or 1/2 bias can be selected by the mask option. S1C60N01 TECHNICAL HARDWARE EPSON I-43 CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (LCD Driver) Table 4.6.2 shows the control bits of the LCD driver and their addresses. Figure 4.6.10 shows the display memory map. Control of LCD driver Table 4.6.2 Control bits of LCD driver Address Register D2 D1 D3 CSDC 0 Name SR 1 0 0 CSDC 0 Static Dynamic 0 R R/W Comment D0 LCD drive switch 0 0FBH 0 0 Address Fig. 4.6.10 Display 090 memory map 0A0 0 1 2 3 4 5 6 7 8 9 A B C D E F Display memory (Write only) 32 words x 4 bits CSDC LCD drive switch (0FBH D3) The LCD drive format can be selected with this switch. When 1 is written: Static drive When 0 is written: Dynamic drive Reading: Valid After an initial reset, dynamic drive (CSDC = 0) is selected. Display memory (090H-0AFH) The LCD segments are turned on or off according to this data. When 1 is written: On When 0 is written: Off Reading: Invalid By writing data into the display memory allocated to the LCD segment (on the panel), the segment can be turned on or off. After an initial reset, the contents of the display memory are undefined. I-44 EPSON S1C60N01 TECHNICAL HARDWARE CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Clock Timer) 4.7 Clock Timer Configuration of clock timer The S1C60N01 Series have a built-in clock timer driven by the source oscillator. The clock timer is configured as a seven-bit binary counter that serves as a frequency divider taking a 256 Hz source clock from the dividing circuit. The four high-order bits (16 Hz-2 Hz) can be read by the software. Figure 4.7.1 is the block diagram of the clock timer. Data bus OSC (oscillation circuit) and dividing circuit 256 Hz 16 Hz-2 Hz 32 Hz, 8 Hz, 2 Hz Fig. 4.7.1 Block diagram of clock timer 128 Hz-32 Hz Clock timer reset signal Interrupt control Interrupt request Normally, this clock timer is used for all kinds of timing purpose, such as clocks. S1C60N01 TECHNICAL HARDWARE EPSON I-45 CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Clock Timer) Interrupt function Address 0E4H The clock timer can interrupt on the falling edge of the 32 Hz, 8 Hz, and 2 Hz signals. The software can mask any of these interrupt signals. Figure 4.7.2 is the timing chart of the clock timer. Register Frequency bits D0 16 Hz D1 8 Hz D2 4 Hz D3 2 Hz Clock timer timing chart Occurrence of 32 Hz interrupt request Occurrence of 8 Hz interrupt request Occurrence of 2 Hz interrupt request Fig. 4.7.2 Timing chart of the clock timer As shown in Figure 4.7.2, an interrupt is generated on the falling edge of the 32 Hz, 8 Hz, and 2 Hz frequencies. When this happens, the corresponding interrupt event flag (IT32, IT8, IT2) is set to 1. Masking the separate interrupts can be done with the interrupt mask register (EIT32, EIT8, EIT2). However, regardless of the interrupt mask register setting, the interrupt event flags will be set to 1 on the falling edge of their corresponding signal (e.g. the falling edge of the 2 Hz signal sets the 2 Hz interrupt factor flag to 1). Note Write to the interrupt mask register (EIT32, EIT8, EIT2) and read the interrupt factor flags (IT32, IT8, IT2) only in the DI status (interrupt flag = 0). Otherwise, it causes malfunction. I-46 EPSON S1C60N01 TECHNICAL HARDWARE CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Clock Timer) Table 4.7.1 shows the clock timer control bits and their addresses. Control of clock timer Table 4.7.1 Control bits of clock timer Address D3 Register D2 D1 TM3 TM2 TM1 Comment D0 Name SR 1 0 TM0 TM3 - High Low Timer data (clock timer 2 Hz) TM2 - High Low Timer data (clock timer 4 Hz) TM1 - High Low Timer data (clock timer 8 Hz) TM0 - High Low Timer data (clock timer 16 Hz) EIT2 0 Enable Mask Interrupt mask register (clock timer 2 Hz) EIT8 0 Enable Mask Interrupt mask register (clock timer 8 Hz) EIT32 0 Enable Mask Interrupt mask register (clock timer 32 Hz) IT2 0 Yes No Interrupt factor flag (clock timer 2 Hz) IT8 0 Yes No Interrupt factor flag (clock timer 8 Hz) IT32 0 Yes No Interrupt factor flag (clock timer 32 Hz) Reset Reset - Clock timer reset R 0E4H 0 EIT2 EIT8 R EIT32 R/W 0 0EBH 0 IT2 IT8 IT32 R 0 0EFH 0 TMRST R W 0 0 R 0 TMRST 0F9H 0 0 TM0-TM3 Timer data (0E4H) The l6 Hz to 2 Hz timer data of the clock timer can be read from this register. These four bits are read-only, and write operations are invalid. After an initial reset, the timer data is initialized to 0H. S1C60N01 TECHNICAL HARDWARE EPSON I-47 CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Clock Timer) EIT32, EIT8, EIT2 Interrupt mask registers (0EBH D0-D2) These registers are used to mask the clock timer interrupt. When 1 is written: Enabled When 0 is written: Masked Reading: Valid The interrupt mask register bits (EIT32, EIT8, EIT2) mask the corresponding interrupt frequencies (32 Hz, 8 Hz, 2 Hz). After an initial reset, these registers are all set to 0. IT32, IT8, IT2 Interrupt factor flags (0EFH D0-D2) These flags indicate the status of the clock timer interrupt. When 1 is read: When 0 is read: Writing: Interrupt has occurred Interrupt has not occurred Invalid The interrupt factor flags (IT32, IT8, IT2) correspond to the clock timer interrupts (32 Hz, 8 Hz, 2 Hz). The software can determine from these flags whether there is a clock timer interrupt. However, even if the interrupt is masked, the flags are set to 1 on the falling edge of the signal. These flags can be reset when the register is read by the software. Reading of interrupt factor flags is available at EI, but be careful in the following cases. If the interrupt mask register value corresponding to the interrupt factor flags to be read is set to 1, an interrupt request will be generated by the interrupt factor flags set timing, or an interrupt request will not be generated. Be very careful when interrupt factor flags are in the same address. After an initial reset, these flags are set to 0. TMRST Clock timer reset (0F9H D2) This bit resets the clock timer. When 1 is written: Clock timer reset When 0 is written: No operation Reading: Always 0 The clock timer is reset by writing 1 to TMRST. The clock timer starts immediately after this. No operation results when 0 is written to TMRST. This bit is write-only, and so is always 0 when read. I-48 EPSON S1C60N01 TECHNICAL HARDWARE CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Heavy Load Protection Function) 4.8 Heavy Load Protection Function Operation of heavy load protection function The S1C60N01 Series have a heavy load protection function for when the battery load becomes heavy and the supply voltage drops, such as when an external buzzer sounds or an external lamp lights. This function works in the heavy load protection mode. The normal mode changes to the heavy load protection mode in the following case: * When the software changes the mode to the heavy load protection mode (HLMOD = 1) In the heavy load protection mode, the internally regulated voltage is switched to the high-stability mode from the low current consumption mode. Consequently, more current is consumed in the heavy load protection mode than in the normal mode. Unless necessary, do not select the heavy load protection mode with the software. S1C60N01 TECHNICAL HARDWARE EPSON I-49 CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Heavy Load Protection Function) Table 4.8.1 shows the control bits and their addresses for the heavy load protection function. Control of heavy load protection function Table 4.8.1 Control bits for heavy load protection function Address D3 HLMOD R/W Register D2 D1 0 0 R D0 Name SR 1 0 0 HLMOD 0 Heavy load Normal load Comment Heavy load protection mode register 0 0FAH 0 0 HLMOD Heavy load protection mode on/off (0FAH D3) When 1 is written: Heavy load protection mode on When 0 is written: Heavy load protection mode off Reading: Valid When HLMOD is set to 1, the IC enters the heavy load protection mode. In the heavy load protection mode, the consumed current becomes larger. Unless necessary, do not select the heavy load protection mode with the software. I-50 EPSON S1C60N01 TECHNICAL HARDWARE CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Interrupt and HALT) 4.9 Interrupt and HALT The S1C60N01 Series provide the following interrupt settings, each of which is maskable. External interrupt: Input interrupt (one) Internal interrupt: Timer interrupt (one) To enable interrupts, the interrupt flag must be set to 1 (EI) and the necessary related interrupt mask registers must be set to 1 (enable). When an interrupt occurs, the interrupt flag is automatically reset to 0 (DI) and interrupts after that are inhibited. When a HALT instruction is input, the CPU operating clock stops and the CPU enters the halt state. The CPU is reactivated from the halt state when an interrupt request occurs. Figure 4.9.1 shows the configuration of the interrupt circuit. S1C60N01 TECHNICAL HARDWARE EPSON I-51 CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Interrupt and HALT) Interrupt vector (MSB) : Program counter of CPU (three low-order bits) : (LSB) K00 EIK00 INT (Interrupt request) K01 EIK01 IK0 Interrupt flag K02 EIK02 K03 EIK03 IT2 Interrupt factor flag EIT2 Interrupt mask register IT8 EIT8 IT32 EIT32 Fig. 4.9.1 Configuration of interrupt circuit I-52 EPSON S1C60N01 TECHNICAL HARDWARE CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Interrupt and HALT) Table 4.9.1 shows the factors that generate interrupt requests. Interrupt factors The interrupt factor flags are set to 1 depending on the corresponding interrupt factors. The CPU is interrupted when the following two conditions occur and an interrupt factor flag is set to 1. * The corresponding mask register is 1 (enabled) * The interrupt flag is 1 (EI) The interrupt factor flag is a read-only register, but can be reset to 0 when the register data is read. After an initial reset, the interrupt factor flags are reset to 0. Note Reading of interrupt factor flags is available at EI, but be careful in the following cases. If the interrupt mask register value corresponding to the interrupt factor flags to be read is set to 1, an interrupt request will be generated by the interrupt factor flags set timing, or an interrupt request will not be generated. Be very careful when interrupt factor flags are in the same address. Table 4.9.1 Interrupt factors S1C60N01 TECHNICAL HARDWARE Interrupt Factor Interrupt Factor Flag Colck timer 2 Hz falling edge IT2 (0EFH D2) Colck timer 8 Hz falling edge IT8 (0EFH D1) Colck timer 32 Hz falling edge IT32 (0EFH D0) Input data (K00-K03) rising edge IK0 (0EDH D0) EPSON I-53 CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Interrupt and HALT) Specific masks and factor flags for interrupt Table 4.9.2 Interrupt mask registers and interrupt factor flags The interrupt factor flags can be masked by the corresponding interrupt mask registers. The interrupt mask registers are read/write registers. They are enabled (interrupt enabled) when 1 is written to them, and masked (interrupt disabled) when 0 is written to them. After an initial reset, the interrupt mask register is set to 0. Table 4.9.2 shows the correspondence between interrupt mask registers and interrupt factor flags. Interrupt Mask Register Interrupt Factor Flag EIT2 (0EBH D2) IT2 (0EFH D2) EIT8 (0EBH D1) IT8 (0EFH D1) EIT32 (0EBH D0) IT32 (0EFH D0) EIK03* (0E8H D3) EIK02* (0E8H D2) EIK01* (0E8H D1) IK0 (0EDH D0) EIK00* (0E8H D0) * There is an interrupt mask register for each input port pin. Interrupt vectors When an interrupt request is input to the CPU, the CPU begins interrupt processing. After the program being executed is suspended, interrupt processing is executed in the following order: The address data (value of the program counter) of the program step to be executed next is saved on the stack (RAM). The interrupt request causes the value of the interrupt vector (page 1, 01H-07H) to be loaded into the program counter. The program at the specified address is executed (execution of interrupt processing routine). Note The processing in steps 1 and 2, above, takes 12 cycles of the CPU system clock. I-54 EPSON S1C60N01 TECHNICAL HARDWARE CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Interrupt and HALT) Tables 4.9.3 shows the interrupt control bits and their addresses. Control of interrupt Table 4.9.3 Interrupt control bits Address D3 EIK03 Register D2 D1 EIK02 EIK01 Comment D0 Name SR 1 0 EIK00 EIK03 0 Enable Mask Interrupt mask register (K03) EIK02 0 Enable Mask Interrupt mask register (K02) EIK01 0 Enable Mask Interrupt mask register (K01) EIK00 0 Enable Mask Interrupt mask register (K00) EIT2 0 Enable Mask Interrupt mask register (clock timer 2 Hz) EIT8 0 Enable Mask Interrupt mask register (clock timer 8 Hz) EIT32 0 Enable Mask Interrupt mask register (clock timer 32 Hz) 0 Yes No IT2 0 Enable Mask Interrupt factor flag (clock timer 2 Hz) IT8 0 Enable Mask Interrupt factor flag (clock timer 8 Hz) IT32 0 Enable Mask Interrupt factor flag (clock timer 32 Hz) R/W 0E8H 0 EIT2 EIT8 R EIT32 R/W 0 0EBH 0 0 0 IK0 0 0 R 0EDH 0 IK0 0 IT2 IT8 R IT32 Interrupt factor flag (K00-K03) 0 0EFH EIT32, EIT8, EIT2 Interrupt mask registers (0EBH D0-D2) IT32, IT8, IT2 Interrupt factor flags (0EFH D0-D2) See 4.7, "Clock Timer". EIK00-EIK03 Interrupt mask registers (0E8H) IK0 Interrupt factor flag (0EDH D0) See 4.3, "Input Ports". S1C60N01 TECHNICAL HARDWARE EPSON I-55 CHAPTER 5: BASIC EXTERNAL WIRING DIAGRAM CHAPTER 5 BASIC EXTERNAL WIRING DIAGRAM (1) Piezo Buzzer Single Terminal Driving COM3 I COM0 K00 SEG19 SEG0 LCD PANEL CA CB VL1 K03 VL2 VL3 P00 I/O C1 Capacitors (C2-C4) are connected. Connection depending on power supply and LCD panel specification. Please refer to page I-7. VDD CG OSC1 P03 X'tal OSC2 VS1 C5 RESET TEST Cp R00 VSS R01 O 1.5 V or 3.0 V Piezo Buzzer Coil I-56 X'tal Crystal oscillator 32.768 kHz CI(MAX) = 35 k CG Trimmer capacitor 5-25 pF C1-C5 Capacitor 0.1 F Cp Capacitor 3.3 F EPSON S1C60N01 TECHNICAL HARDWARE CHAPTER 5: BASIC EXTERNAL WIRING DIAGRAM (2) Piezo Buzzer Direct Driving COM3 COM0 I SEG0 K00 SEG19 LCD PANEL CA CB VL1 K03 VL2 VL3 P00 I/O C1 Capacitors (C2-C4) are connected. Connection depending on power supply and LCD panel specification. Please refer to page I-7. VDD CG OSC1 P03 X'tal OSC2 VS1 C5 RESET TEST 1.5 V or 3.0 V Cp R00 R01 VSS Piezo Buzzer X'tal Crystal oscillator 32.768 kHz CI(MAX) = 35 k CG Trimmer capacitor 5-25 pF C1-C5 Capacitor 0.1 F Cp Capacitor 3.3 F S1C60N01 TECHNICAL HARDWARE EPSON I-57 CHAPTER 6: ELECTRICAL CHARACTERISTICS CHAPTER 6 ELECTRICAL CHARACTERISTICS 6.1 Absolute Maximum Rating (VDD=0V) Item Power voltage Input voltage (1) Input voltage (2) Permissible total output current *1 Operating temperature Storage temperature Soldering temperature / Time Allowable dissipation *2 Symbol VSS VI VIOSC IVSS Topr Tstg Tsol PD Rated Value -5.0 to 0.5 Vss-0.3 to 0.5 Vss-0.3 to 0.5 10 -20 to 70 -65 to 150 260C, 10sec (lead section) 250 Unit V V V mA C C - mW 1 The permissible total output current is the sum total of the current (average current) that simultaneously flows from the output pins (or is draw in). 2 In case of QFP12-48pin plastic package I-58 EPSON S1C60N01 TECHNICAL HARDWARE CHAPTER 6: ELECTRICAL CHARACTERISTICS 6.2 Recommended Operating Conditions S1C60N01 Item Power voltage Oscillation frequency Booster capacitor Capacitor between VDD and VL1 or VSS and VL1 Capacitor between VSS and VL2 Capacitor between VDD and VL3 Capacitor between VDD and VS1 Symbol Condition VSS VDD=0V fOSC1 Crystal oscillation fOSC2 CR oscillation, R=470k C1 C2 Min -3.6 50 0.1 0.1 Typ -3.0 32.768 65 F F F 0.1 0.1 0.1 C3 C4 C5 S1C60L01 Item Power voltage Oscillation frequency Booster capacitor Capacitor between VDD and VL1 Capacitor between VDD and VL2 Capacitor between VDD and VL3 Capacitor between VDD and VS1 S1C60N01 TECHNICAL HARDWARE Symbol Condition VSS VDD=0V fOSC1 Crystal oscillation fOSC2 CR oscillation, R=470k C1 C2 C3 C4 C5 EPSON Min -2.0 50 0.1 0.1 0.1 0.1 0.1 (Ta=-20 to 70C) Max Unit -1.8 V kHz 80 kHz F F Typ -1.5 32.768 65 (Ta=-20 to 70C) Max Unit -1.2 V kHz 80 kHz F F F F F I-59 CHAPTER 6: ELECTRICAL CHARACTERISTICS 6.3 DC Characteristics S1C60N01 Unless otherwise specified VDD=0 V, VSS=-3.0 V, fosc=32.768 kHz, Ta=25C, VS1, VL1, VL2 and VL3 are internal voltages, and C1=C2=C3=C4=C5=0.1 F Item Symbol Condition High level input voltage (1) VIH1 K00-K03, P00-P03 High level input voltage (2) VIH2 RESET Low level input voltage (1) K00-K03, P00-P03 VIL1 Low level input voltage (2) RESET VIL2 High level input current (1) K00-K03, P00-P03 IIH1 VIH1=0V Without pull down resistor High level input current (2) K00-K03 IIH2 VIH2=0V With pull down resistor High level input current (3) P00-P03, RESET IIH3 VIH3=0V With pull down resistor VIL=VSS Low level input current K00-K03, P00-P03, IIL RESET, TEST P00-P03 High level output current (1) IOH1 VOH1=0.1*VSS R00, R01 High level output current (2) IOH2 VOH2=0.1*VSS (built-in protection resistance) P00-P03 Low level output current (1) IOL1 VOL1=0.9*VSS R00, R01 Low level output current (2) IOL2 VOL2=0.9*VSS (built-in protection resistance) COM0-COM3 IOH3 VOH3=-0.05V Common output current IOL3 VOL3=VL3+0.05V SEG0-SEG19 IOH4 VOH4=-0.05V Segment output current IOL4 VOL4=VL3+0.05V (during LCD output) Segment output current SEG0-SEG19 IOH5 VOH5=0.1*VSS (during DC output) IOL5 VOL5=0.9*VSS I-60 EPSON Max Min Typ Unit 0 0.2*Vss V 0 0.15*Vss V 0.8*Vss Vss V 0.85*Vss V Vss 0.5 0 A 10 40 A 30 100 A -0.5 0 A -1.0 -1.0 mA mA 3.0 3.0 mA mA -3 3 -3 3 -300 300 A A A A A A S1C60N01 TECHNICAL HARDWARE CHAPTER 6: ELECTRICAL CHARACTERISTICS S1C60L01 Unless otherwise specified VDD=0 V, VSS=-1.5 V, fosc=32.768 kHz, Ta=25C, VS1, VL1, VL2 and VL3 are internal voltages, and C1=C2=C3=C4=C5=0.1 F Item Symbol Condition High level input voltage (1) VIH1 K00-K03, P00-P03 High level input voltage (2) VIH2 RESET Low level input voltage (1) K00-K03, P00-P03 VIL1 Low level input voltage (2) RESET VIL2 High level input current (1) K00-K03, P00-P03 IIH1 VIH1=0V Without pull down resistor High level input current (2) K00-K03 IIH2 VIH2=0V With pull down resistor High level input current (3) P00-P03, RESET IIH3 VIH3=0V With pull down resistor VIL=VSS Low level input current K00-K03, P00-P03, IIL RESET, TEST P00-P03 High level output current (1) IOH1 VOH1=0.1*VSS R00, R01 High level output current (2) IOH2 VOH2=0.1*VSS (built-in protection resistance) P00-P03 Low level output current (1) IOL1 VOL1=0.9*VSS R00, R01 Low level output current (2) IOL2 VOL2=0.9*VSS (built-in protection resistance) COM0-COM3 IOH3 VOH3=-0.05V Common output current IOL3 VOL3=VL3+0.05V SEG0-SEG19 IOH4 VOH4=-0.05V Segment output current IOL4 VOL4=VL3+0.05V (during LCD output) Segment output current SEG0-SEG19 IOH5 VOH5=0.1*VSS (during DC output) IOL5 VOL5=0.9*VSS S1C60N01 TECHNICAL HARDWARE EPSON Max Min Typ Unit 0 0.2*Vss V 0 0.15*Vss V 0.8*Vss Vss V 0.85*Vss V Vss 0.5 0 A 5.0 20 A 9.0 100 A -0.5 0 A -200 -200 A A A A 700 700 -3 3 -3 3 -100 130 A A A A A A I-61 CHAPTER 6: ELECTRICAL CHARACTERISTICS 6.4 Analog Circuit Characteristics and Power Current Consumption S1C60N01 (Normal Operating Mode) Unless otherwise specified VDD=0 V, VSS=-3.0 V, fosc=32.768 kHz (crystal oscillation), Ta=25C, CG=25 pF, VS1, VL1, VL2 and VL3 are internal voltages, and C1=C2=C3=C4=C5=0.1 F Item Internal voltage Symbol VL1 VL2 VL3 Power current consumption IOP Condition Connect 1M load resistor between VDD and VL1 (without panel load) Connect 1M load resistor between VDD and VL2 (without panel load) Connect 1M load resistor between VDD and VL3 (without panel load) During HALT Without panel load During execution Min 1/2*VL2 -0.1 Typ Max 1/2*VL2 x 0.9 V VSS 3/2*VL2 -0.1 1.0 2.5 Unit V 3/2*VL2 x 0.9 2.5 5.0 V A A S1C60N01 (Heavy Load Protection Mode) Unless otherwise specified VDD=0 V, VSS=-3.0 V, fosc=32.768 kHz (crystal oscillation), Ta=25C, CG=25 pF, VS1, VL1, VL2 and VL3 are internal voltages, and C1=C2=C3=C4=C5=0.1 F Item Internal voltage Symbol VL1 VL2 VL3 Power current consumption I-62 IOP Condition Connect 1M load resistor between VDD and VL1 (without panel load) Connect 1M load resistor between VDD and VL2 (without panel load) Connect 1M load resistor between VDD and VL3 (without panel load) During HALT Without panel load During execution EPSON Min 1/2*VL2 -0.1 Typ Max 1/2*VL2 x 0.85 V VSS 3/2*VL2 -0.1 2.0 5.5 Unit V 3/2*VL2 x 0.85 5.5 10.0 V A A S1C60N01 TECHNICAL HARDWARE CHAPTER 6: ELECTRICAL CHARACTERISTICS S1C60L01 (Normal Operating Mode) Unless otherwise specified VDD=0 V, VSS=-1.5 V, fosc=32.768 kHz (crystal oscillation), Ta=25C, CG=25 pF, VS1, VL1, VL2 and VL3 are internal voltages, and C1=C2=C3=C4=C5=0.1 F Item Internal voltage Symbol VL1 VL2 VL3 Power current consumption IOP Condition Connect 1M load resistor between VDD and VL1 (without panel load) Connect 1M load resistor between VDD and VL2 (without panel load) Connect 1M load resistor between VDD and VL3 (without panel load) During HALT Without panel load During execution Min Typ VSS 2*VL1 -0.1 3*VL1 -0.1 1.0 2.5 Max Unit V 2*VL1 x 0.9 3*VL1 x 0.9 2.5 5.0 V V A A S1C60L01 (Heavy Load Protection Mode) Unless otherwise specified VDD=0 V, VSS=-1.5 V, fosc=32.768 kHz (crystal oscillation), Ta=25C, CG=25 pF, VS1, VL1, VL2 and VL3 are internal voltages, and C1=C2=C3=C4=C5=0.1 F Item Internal voltage Symbol VL1 VL2 VL3 Power current consumption IOP Condition Connect 1M load resistor between VDD and VL1 (without panel load) Connect 1M load resistor between VDD and VL2 (without panel load) Connect 1M load resistor between VDD and VL3 (without panel load) During HALT Without panel load During execution S1C60N01 TECHNICAL HARDWARE EPSON Min Typ VSS 2*VL1 -0.1 3*VL1 -0.1 Max Unit V 2*VL1 V x 0.85 3*VL1 V x 0.85 2.0 5.5 5.5 10.0 A A I-63 CHAPTER 6: ELECTRICAL CHARACTERISTICS S1C60N01 (CR, Normal Operating Mode) Unless otherwise specified VDD=0 V, VSS=-3.0 V, fosc=65 kHz, Ta=25C, CG=25 pF, VS1, VL1, VL2 and VL3 are internal voltages, and C1=C2=C3=C4=C5=0.1 F, Recommended external resistance for CR oscillation=470 k Item Internal voltage Symbol VL1 VL2 VL3 Power current consumption IOP Condition Connect 1M load resistor between VDD and VL1 (without panel load) Connect 1M load resistor between VDD and VL2 (without panel load) Connect 1M load resistor between VDD and VL3 (without panel load) During HALT Without panel load During execution Min 1/2*VL2 -0.1 Typ Max 1/2*VL2 x 0.9 V VSS 3/2*VL2 -0.1 8.0 15.0 Unit V 3/2*VL2 x 0.9 15.0 20.0 V A A S1C60N01 (CR, Heavy Load Protection Mode) Unless otherwise specified VDD=0 V, VSS=-3.0 V, fosc=65 kHz, Ta=25C, CG=25 pF, VS1, VL1, VL2 and VL3 are internal voltages, and C1=C2=C3=C4=C5=0.1 F, Recommended external resistance for CR oscillation=470 k Item Internal voltage Symbol VL1 VL2 VL3 Power current consumption I-64 IOP Condition Connect 1M load resistor between VDD and VL1 (without panel load) Connect 1M load resistor between VDD and VL2 (without panel load) Connect 1M load resistor between VDD and VL3 (without panel load) During HALT Without panel load During execution EPSON Min 1/2*VL2 -0.1 Typ Max 1/2*VL2 x 0.85 V VSS 3/2*VL1 -0.1 16.0 30.0 Unit V 3/2*VL1 x 0.85 30.0 40.0 V A A S1C60N01 TECHNICAL HARDWARE CHAPTER 6: ELECTRICAL CHARACTERISTICS S1C60L01 (CR, Normal Operating Mode) Unless otherwise specified VDD=0 V, VSS=-1.5 V, fosc=65 kHz, Ta=25C, CG=25 pF, VS1, VL1, VL2 and VL3 are internal voltages, and C1=C2=C3=C4=C5=0.1 F, Recommended external resistance for CR oscillation=470 k Item Internal voltage Symbol VL1 VL2 VL3 Power current consumption IOP Condition Connect 1M load resistor between VDD and VL1 (without panel load) Connect 1M load resistor between VDD and VL2 (without panel load) Connect 1M load resistor between VDD and VL3 (without panel load) During HALT Without panel load During execution Min Typ VSS 2*VL1 -0.1 3*VL1 -0.1 8.0 15.0 Max Unit V 2*VL1 x 0.9 3*VL1 x 0.9 15.0 20.0 V V A A S1C60L01 (CR, Heavy Load Protection Mode) Unless otherwise specified VDD=0 V, VSS=-1.5 V, fosc=65 kHz, Ta=25C, CG=25 pF, VS1, VL1, VL2 and VL3 are internal voltages, and C1=C2=C3=C4=C5=0.1 F, Recommended external resistance for CR oscillation=470 k Item Internal voltage Symbol VL1 VL2 VL3 Power current consumption IOP Condition Connect 1M load resistor between VDD and VL1 (without panel load) Connect 1M load resistor between VDD and VL2 (without panel load) Connect 1M load resistor between VDD and VL3 (without panel load) During HALT Without panel load During execution S1C60N01 TECHNICAL HARDWARE EPSON Min Typ VSS 2*VL1 -0.1 3*VL1 -0.1 Max Unit V 2*VL1 V x 0.85 3*VL1 V x 0.85 16.0 30.0 30.0 40.0 A A I-65 CHAPTER 6: ELECTRICAL CHARACTERISTICS 6.5 Oscillation Characteristics Oscillation characteristics will vary according to different conditions. Use the following characteristics are as reference values. S1C60N01 Unless otherwise specified VDD=0 V, VSS=-3.0 V, Crystal : Q13MC146, CG=25 pF, CD=built-in, Ta=25C Item Symbol Condition Oscillation start Vsta tsta5sec voltage (Vss) Oscillation stop Vstp tstp10sec voltage (Vss) Built-in capacity (drain) CD Including the parasitic capacity inside the IC Frequency voltage deviation f/V Vss=-1.8 to -3.6V Frequency IC deviation f/IC Frequency adjustment range f/CG CG=5-25pF Higher harmonic oscillation Vhho CG=5pF start voltage (Vss) Allowable leak resistance Rleak Between OSC1 and VDD Min -1.8 Typ Max Unit V V -1.8 20 5 10 -10 40 -3.6 pF ppm ppm ppm V M 200 S1C60L01 Unless otherwise specified VDD=0 V, VSS=-1.5 V, Crystal : Q13MC146, CG=25 pF, CD=built-in, Ta=25C Item Symbol Condition Oscillation start Vsta tsta5sec voltage (Vss) Oscillation stop Vstp tstp10sec voltage (Vss) Built-in capacity (drain) CD Including the parasitic capacity inside the IC Frequency voltage deviation f/V Vss=-1.2 to -2.0V Frequency IC deviation f/IC Frequency adjustment range f/CG CG=5-25pF Higher harmonic oscillation Vhho CG=5pF start voltage (Vss) Allowable leak resistance Rleak Between OSC1 and VDD I-66 EPSON Min -1.2 Typ Max V -1.2 20 -10 40 5 10 -2.0 200 Unit V pF ppm ppm ppm V M S1C60N01 TECHNICAL HARDWARE CHAPTER 6: ELECTRICAL CHARACTERISTICS S1C60N01 (CR) Unless otherwise specified VDD=0 V, VSS=-3.0 V, RCR=470 k, Ta=25C Symbol Condition Min Item fosc -20 Oscillation frequency dispersion Vsta -1.8 Oscillation start voltage Oscillation start time tsta Vss=-1.8 to -3.6V Oscillation stop voltage Vstp -1.8 Typ 65kHz Max 20 Unit % V ms V Max 20 Unit % V ms V 3 S1C60L01 (CR) Unless otherwise specified VDD=0 V, VSS=-1.5 V, RCR=470 k, Ta=25C Symbol Item Condition Min fosc -20 Oscillation frequency dispersion Vsta Oscillation start voltage -1.2 Oscillation start time tsta Vss=-1.2 to -2.0V Oscillation stop voltage Vstp -1.2 S1C60N01 TECHNICAL HARDWARE EPSON Typ 65kHz 3 I-67 CHAPTER 7: PACKAGE CHAPTER 7 PACKAGE 7.1 Plastic Package Plastic QFP12-48pin 90.4 70.1 36 25 70.1 90.4 24 37 INDEX 13 48 1 12 +0.1 0.18 -0.05 0.1 1.40.1 1.7max 0.5 0.1250.05 0 10 0.50.2 1 I-68 EPSON S1C60N01 TECHNICAL HARDWARE CHAPTER 7: PACKAGE 7.2 Ceramic Package for Test Samples DIP-64pin 81.3 34 33 22.8 23.1 64 63 Pin No. 1 2 31 32 Index Mark 2.54 78.7 (Unit: mm) Pin No. Pin Name Pin No. Pin Name Pin No. 1 N.C. 17 VL1 33 2 SEG5 18 CA 34 3 SEG4 19 CB 35 4 SEG3 20 VSS 36 5 SEG2 21 VDD 37 6 SEG1 22 OSC1 38 7 SEG0 23 OSC2 39 8 N.C. 24 N.C. 40 9 N.C. 25 N.C. 41 10 N.C. 26 VS1 42 11 COM0 27 N.C. 43 12 COM1 28 N.C. 44 13 COM2 29 N.C. 45 14 COM3 30 P00 46 15 VL3 31 P01 47 16 32 P02 48 VL2 S1C60N01 TECHNICAL HARDWARE EPSON Pin Name Pin No. Pin Name P03 49 SEG15 K00 50 SEG14 K01 K02 K03 N.C. N.C. N.C. N.C. N.C. R01 R00 SEG19 SEG18 SEG17 SEG16 51 SEG13 52 SEG12 53 SEG11 54 SEG10 55 N.C. 56 N.C. 57 N.C. 58 TEST 59 RESET 60 SEG9 61 SEG8 62 SEG7 63 SEG6 64 N.C. N.C. = No Connection I-69 CHAPTER 8: PAD LAYOUT CHAPTER 8 PAD LAYOUT 8.1 Diagram of Pad Layout 10 5 1 45 15 Y 40 25 (0, 0) Die No. 20 X 30 35 Chip size: 2,640 m (X) x 2,180 m (Y) I-70 EPSON S1C60N01 TECHNICAL HARDWARE CHAPTER 8: PAD LAYOUT 8.2 Pad Coordinates Pad No Pad Name X Y X Y R01 759 923 24 SEG0 -1,151 -644 2 R00 629 923 3 SEG19 401 923 25 COM0 -1,126 -923 26 COM1 -988 -923 4 SEG18 271 923 27 COM2 -858 -923 5 SEG17 141 923 28 COM3 -727 -923 6 7 SEG16 11 923 29 VL3 -597 -923 SEG15 -119 923 30 VL2 -466 -923 8 SEG14 -249 923 31 VL1 -336 -923 9 SEG13 -379 923 32 CA -206 -923 10 SEG12 -509 923 33 CB -76 -923 11 SEG11 -639 923 34 VSS 570 -923 12 SEG10 -769 923 35 VDD 700 -923 13 TEST -1,151 789 36 OSC1 835 -923 14 RESET -1,151 657 37 OSC2 987 -923 15 SEG9 -1,151 526 38 VS1 1,140 -923 16 SEG8 -1,151 396 39 P00 1,151 -11 17 SEG7 -1,151 266 40 P01 1,151 119 18 SEG6 -1,151 136 41 P02 1,151 249 19 SEG5 -1,151 6 42 P03 1,151 379 20 SEG4 -1,151 -124 43 K00 1,151 518 21 SEG3 -1,151 -254 44 K01 1,151 648 22 SEG2 -1,151 -384 45 K02 1,151 778 23 SEG1 -1,151 -514 46 K03 1,151 908 1 Pad No Pad Name (Unit: m) S1C60N01 TECHNICAL HARDWARE EPSON I-71 II. S1C60N01 Technical Software CONTENTS CONTENTS CHAPTER 2 CHAPTER 3 CONFIGURATION ........................................................... II-1 1.1 S1C60N01 Block Diagram ............................................. II-1 1.2 ROM Map ....................................................................... II-2 1.3 Interrupt Vectors ............................................................. II-3 1.4 Data Memory Map .......................................................... II-4 INITIAL RESET ................................................................... II-9 2.1 Internal Register Status on Initial Reset ......................... II-9 2.2 Initialize Program Example ............................................ II-11 PERIPHERAL CIRCUITS .................................................... II-13 3.1 Input Ports ..................................................................... II-13 Input port memory map .......................................... II-13 Control of the input port ......................................... II-14 Examples of input port control program .................. II-14 3.2 Output Ports .................................................................. II-16 Output port memory map ........................................ II-16 Control of the output port ....................................... II-16 Examples of output port control program ................ II-17 3.3 Special Use Output Ports .............................................. II-19 Special use output port memory map ...................... II-19 Control of the special use output port ..................... II-20 Examples of special use output port control program ...................................................... II-21 S1C60N01 TECHNICAL SOFTWARE EPSON II-i Software CHAPTER 1 CONTENTS 3.4 I/O Ports ........................................................................ II-23 I/O port memory map ............................................. II-23 Control of the I/O port ............................................ II-24 Examples of I/O port control program ..................... II-25 3.5 LCD Driver ..................................................................... II-28 LCD driver memory map ......................................... II-28 Control of the LCD driver ........................................ II-29 Examples of LCD driver control program ................. II-31 3.6 Timer ............................................................................. II-33 Timer memory map ................................................. II-33 Control of the timer ................................................. II-34 Examples of timer control program .......................... II-35 3.7 Heavy Load Protection Function ................................... II-37 Heavy load protection function memory map ........... II-37 Heavy load protection function ................................ II-37 Examples of heavy load protection function control program ......................................... II-38 3.8 Interrupt and Halt ........................................................... II-39 Interrupt memory map ............................................ II-39 Control of interrupts and halt ................................. II-40 Examples of interrupt and halt control program ...... II-48 II-ii CHAPTER 4 SUMMARY OF PROGRAMMING POINTS....................... II-50 APPENDIX A Table of Instructions ...................................................... II-54 B The S1C60N01 I/O Memory Map .................................. II-59 C Table of the ICE Commands ......................................... II-60 D Cross-assembler Pseudo-instruction List ...................... II-62 EPSON S1C60N01 TECHNICAL SOFTWARE CHAPTER 1: CONFIGURATION CHAPTER 1 CONFIGURATION ROM 1,024 x 12 RESET OSC1 OSC2 1.1 S1C60N01 Block Diagram OSC System Reset Control Core CPU S1C6200B RAM 80 x 4 COM0 | COM3 SEG0 | SEG19 Interrupt Generator LCD Driver I Port Test Port K00~K03 Power Controller I/O Port P00~P03 O Port R00, R01 TEST VDD VL1 | VL3 CA CB VS1 VSS (FOUT/BUZZER) (BUZZER) FOUT & BUZZER Timer Fig. 1.1.1 S1C60N01 block diagram S1C60N01 TECHNICAL SOFTWARE EPSON II-1 CHAPTER 1: CONFIGURATION 1.2 ROM Map The S1C60N01 has a built-in mask ROM with a capacity of 1,024 steps x 12 bits for program storage. The configuration of the ROM is shown in Figure 1.2.1. Bank 0 00H step 0 page Program start address 01H step 1 page 2 page Interrupt vector area 3 page 07H step 08H step Program area FFH step Fig. 1.2.1 Configuration of built-in ROM II-2 12 bits EPSON S1C60N01 TECHNICAL SOFTWARE CHAPTER 1: CONFIGURATION 1.3 Interrupt Vectors When an interrupt request is received by the CPU, the CPU initiates the following interrupt processing after completing the instruction being executed. (1) The address of the next instruction to be executed (the value of the program counter) is saved on the stack (RAM). (2) The interrupt vector address corresponding to the interrupt request is loaded into the program counter. (3) The branch instruction written in the vector is executed to branch to the software interrupt processing routine. Note Steps 1 and 2 require 12 cycles of the CPU system clock. The interrupt vectors are shown in Table 1.3.1. Table 1.3.1 Interrupt requests and vectors Page 1 Step Interrupt Vector 00H Initial reset 01H Clock timer interrupt 04H Input (K00-K03) interrupt 05H Input interrupt and clock timer interrupt Addesses (start address of interrupt processing routines) to jump to are written into the addresses available for interrupt vector allocation. S1C60N01 TECHNICAL SOFTWARE EPSON II-3 CHAPTER 1: CONFIGURATION 1.4 Data Memory Map The S1C60N01 built-in RAM has 80 words of data memory, 32 words of display memory for the LCD, and I/O memory for controlling the peripheral circuit. When writing programs, note the following: (1) Since the stack area is in the data memory area, take care not to overwrite the stack with data. Subroutine calls or interrupts use 3 words on the stack. (2) Data memory addresses 000H-00FH are memory register areas that are addressed with register pointer RP. Address Low 0 Page 1 2 3 4 5 6 7 8 9 A B C D E F High 0 M0 M1 M2 M3 M4 M5 M6 M7 M8 M9 MA MB MC MD ME MF 1 2 RAM (80 words x 4 bits) R/W 3 4 5 6 0 Unused area 7 8 9 Display memory A B Unused area C D Fig. 1.4.1 Data memory map E I/O memory F Note Memory is not mounted in unused area within the memory map and in memory area not indicated in this chapter. For this reason, normal operation cannot be assured for programs that have been prepared with access to these areas. II-4 EPSON S1C60N01 TECHNICAL SOFTWARE CHAPTER 1: CONFIGURATION Table 1.4.1(a) I/O memory map 1 Address D3 Register D2 D1 D0 Name K03 K02 K00 K03 - K02 K01 R SR *1 Comment 1 0 *2 High Low - *2 High Low K01 - *2 High Low K00 - *2 High Low TM3 - High Low Timer data (clock timer 2 Hz) TM2 - High Low Timer data (clock timer 4 Hz) TM1 - High Low Timer data (clock timer 8 Hz) TM0 - High Low Timer data (clock timer 16 Hz) EIK03 0 Enable Mask Interrupt mask register (K03) EIK02 0 Enable Mask Interrupt mask register (K02) EIK01 0 Enable Mask Interrupt mask register (K01) EIK00 0 Enable Mask Interrupt mask register (K00) EIT2 0 Enable Mask Interrupt mask register (clock timer 2 Hz) EIT8 0 Enable Mask Interrupt mask register (clock timer 8 Hz) EIT32 0 Enable Mask Interrupt mask register (clock timer 32 Hz) 0E0H Input port (K00-K03) TM3 TM2 TM1 TM0 R 0E4H EIK03 EIK02 EIK01 EIK00 R/W 0E8H 0 EIT2 R EIT8 R/W EIT32 0 *5 0EBH *1 *2 *3 *4 *5 *6 Initial value following initial reset Not set in the circuit Undefined Reset (0) immediately after being read Always 0 when being read Refer to main manual S1C60N01 TECHNICAL SOFTWARE EPSON II-5 CHAPTER 1: CONFIGURATION Table 1.4.1(b) I/O memory map 2 Address Register D2 D1 D3 0 0 D0 0 IK0 Name 0 0 R 0EDH 0 IK0 0 IT2 IT8 IT32 R 0 IT2 0EFH IT8 IT32 0 0 R01 BUZZER R R00 FOUT R/W 0F3H P03 P02 P01 R/W P00 1 0 0 Yes No Interrupt factor flag (K00-K03) 0 Yes No Interrupt factor flag (clock timer 2 Hz) 0 Yes No Interrupt factor flag (clock timer 8 Hz) 0 Yes No Interrupt factor flag (clock timer 32 Hz) *5 *5 *4 *5 *4 *4 *4 0 *5 0 *5 R01 0 High Low R01 output port data BUZZER 0 ON OFF Buzzer ON/OFF control register R00 0 High Low R00 output port data FOUT Frequency output ON/OFF control register 0 ON OFF P03 - *2 High Low P02 - *2 High Low P01 - *2 High Low P00 - *2 High Low 0F6H *1 *2 *3 *4 *5 *6 II-6 Comment SR *1 *5 I/O port (P00-P03) Initial value following initial reset Not set in the circuit Undefined Reset (0) immediately after being read Always 0 when being read Refer to main manual EPSON S1C60N01 TECHNICAL SOFTWARE CHAPTER 1: CONFIGURATION Table 1.4.1(c) I/O memory map 3 Address D3 Register D2 D1 0 TMRST R W 0 D0 Name 0 0 1 0 Reset Reset - 0 Heavy load Normal load Heavy load protection mode register 0 Static Dynamic LCD drive switch 0 Output Input *5 TMRST R Comment SR *1 Clock timer reset 0F9H HLMOD 0 R/W 0 0 R 0 *5 0 *5 HLMOD 0 0FAH 0 0 CSDC 0 R/W 0 0 R *5 *5 *5 CSDC 0 *5 0 *5 0 *5 0FBH 0 0 R 0 IOC 0 *5 R/W 0 *5 0FCH 0 *5 IOC *1 *2 *3 *4 *5 *6 I/O port P00-P03 Input/Output Initial value following initial reset Not set in the circuit Undefined Reset (0) immediately after being read Always 0 when being read Refer to main manual S1C60N01 TECHNICAL SOFTWARE EPSON II-7 CHAPTER 1: CONFIGURATION Table 1.4.1(d) I/O memory map 4 Address D3 XBZR R/W Register D2 D1 0 R D0 XFOUT1 XFOUT0 R/W Comment Name SR *1 1 0 XBZR 0 2 kHz 4 kHz Buzzer frequency control 0 High Low FOUT frequency control: 0 High Low 0 *5 0FDH XFOUT1 XFOUT0 *1 *2 *3 *4 *5 *6 II-8 XFOUT1(0), XFOUT0(0) -> F1 XFOUT1(0), XFOUT0(1) -> F2 XFOUT1(1), XFOUT0(0) -> F3 XFOUT1(1), XFOUT0(1) -> F4 Initial value following initial reset Not set in the circuit Undefined Reset (0) immediately after being read Always 0 when being read Refer to main manual EPSON S1C60N01 TECHNICAL SOFTWARE CHAPTER 2: INITIAL RESET CHAPTER 2 INITIAL RESET 2.1 Internal Register Status on Initial Reset Following an initial reset, the internal registers and internal data memory area are initialized to the values shown in Tables 2.1.1 and 2.1.2. Table 2.1.1 Initial values of internal registers Table 2.1.2 Initial values of internal data memory area S1C60N01 TECHNICAL SOFTWARE Internal Register Program counter step Program counter page New page pointer Stack pointer Index register Index register Register pointer General register General register Interrupt flag Decimal flag Zero flag Carry flag Internal Data Memory Area PCS PCP NPP SP X Y RP A B I D Z C Bit Length RAM data Display memory Internal I/O register EPSON Bit Length Initial Value Following Reset 8 4 4 8 8 8 4 4 4 1 1 1 1 00H 1H 1H Undefined Undefined Undefined Undefined Undefined Undefined 0 0 Undefined Undefined Initial Value Following Reset 4 x 80 Undefined 4 x 20 Undefined See Tables 1.4.1(a)-1.4.1(d) Address 000H-05FH 090H-0AFH 0E0H-0FDH II-9 CHAPTER 2: INITIAL RESET After an initial reset, the program counter page (PCP) is initialized to 1H, and the program counter step (PCS), to 00H. This is why the program is executed from step 00H of the first page. The initial values of some internal registers and internal data memory area locations are undefined after a reset. Set them as necessary to the proper initial values in the program. The peripheral I/O functions (memory-mapped I/O) are assigned to internal data memory area addresses 0E0H to 0FDH. Each address represents a 4-bit internal I/O register, allowing access to the peripheral functions in 1-word (4-bit) read/write units. II-10 EPSON S1C60N01 TECHNICAL SOFTWARE CHAPTER 2: INITIAL RESET 2.2 Initialize Program Example The following is a program that clears the RAM and LCD, resets the flags, registers and timer, and sets the stack pointer immediately after resetting the system. Label Mnemonic/operand Comment ORG JP 100H INIT ;Jump to "INIT" ORG RST 110H F,0011B ; INIT ;Interrupt mask, decimal ;adjustment off ; LD RAMCLR LDPX CP JP LD LCDCLR LDPX CP JP ; LD LD LD LD ; LD OR ; LD OR ; LD OR ; LD LD LD LD RST EI S1C60N01 TECHNICAL SOFTWARE X,0 MX,0 XH,5H NZ,RAMCLR X,90H MX,0 XH,0BH NZ,LCDCLR ; ; ; ; ; ; ; ; A,0 B,4 SPL,A SPH,B ; ; ; ; Set stack pointer to 40H X,0F9H MX,0100B ; ; Reset timer X,0EBH MX,0111B ; ; Enable timer interrupt X,0E8H MX,1111B ; ; X,0 Y,0 A,0 B,0 F,0 ; ; ; Reset register flags ; ; ;Enable interrupt EPSON Clear RAM (00H-4FH) Clear LCD (90H-AFH) Enable input interrupt (K03-K00) II-11 CHAPTER 2: INITIAL RESET The above program is a basic initialization program for the S1C60N01. The setting data are all initialized as shown in Table 2.1.1 by executing this program. When using this program, add setting items necessary for each specific application. (Figure 2.2.1 is the flow chart for this program.) Initialization Reset I (Interrupt flag) D (Decimal adjustment flag) Clear RAM Set SP I : Interrupt flag D : Decimal adjustment flag Clear data RAM (00H to 04FH) Clear segment RAM (90H to 0AFH) Set stack pointer to 40H Reset timer Enable timer interrupt Enable timer interrupt 2 Hz, 8 Hz, 32 Hz Enable input interrupt Enable K03-K00 input port interrupt Reset registers (X, Y, A, B) flags (I, Z, D, C) EI (enable interrupt) Fig. 2.2.1 Flow chart of the initialization To next process program II-12 EPSON S1C60N01 TECHNICAL SOFTWARE CHAPTER 3: PERIPHERAL CIRCUITS (Input Ports) CHAPTER 3 PERIPHERAL CIRCUITS Details on how to control the S1C60N01 peripheral circuit is given in this chapter. 3.1 Input Ports Input port memory map Table 3.1.1 I/O memory map Address D3 Register D2 D1 D0 Name K03 K02 K00 K03 - K02 K01 R SR *1 Comment 1 0 *2 High Low - *2 High Low K01 - *2 High Low K00 - *2 High Low EIK03 0 Enable Mask Interrupt mask register (K03) EIK02 0 Enable Mask Interrupt mask register (K02) EIK01 0 Enable Mask Interrupt mask register (K01) EIK00 0 Enable Mask Interrupt mask register (K00) 0 Yes No 0E0H Input port (K00-K03) EIK03 EIK02 EIK01 EIK00 R/W 0E8H 0 0 0 R IK0 0 *5 0 *5 0EDH 0 *5 IK0 *4 *1 *2 *3 *4 *5 *6 Interrupt factor flag (K00-K03) Initial value following initial reset Not set in the circuit Undefined Reset (0) immediately after being read Always 0 when being read Refer to main manual S1C60N01 TECHNICAL SOFTWARE EPSON II-13 CHAPTER 3: PERIPHERAL CIRCUITS (Input Ports) The S1C60N01 has one 4-bit input port (K00-K03). Input port data can be read as a 4-bit unit (K00-K03). Control of the input port The state of the input ports can be obtained by reading the data (bits D3, D2, D1, D0) of address 0E0H. The input ports can be used to send an interrupt request to the CPU via the input interrupt condition flag. See Section 3.8 "Interrupt and Halt", for details. Examples of input port control program * Loading K00-K03 into the A register Label Mnemonic/operand Comment LD LD ;Set address of port ;A register K00-K03 Y,0E0H A,MY As shown in Figure 3.1.1, the two instruction steps above load the data of the input port into the A register. A register Fig. 3.1.1 D3 D2 D1 D0 K03 K02 K01 K00 Loading the A register The data of the input port can be loaded into the B register or MX instead of the A register. II-14 EPSON S1C60N01 TECHNICAL SOFTWARE CHAPTER 3: PERIPHERAL CIRCUITS (Input Ports) * Bit-unit checking of input ports Label Mnemonic/operand DI LD INPUT1: FAN JP INPUT2: FAN JP Y,0E0H MY,0010B NZ,INPUT1 MY,0010B Z,INPUT2 Comment ;Disable interrupt ;Set address of port ; ;Loop until K01 becomes "0" ; ;Loop until K01 becomes "1" This program loopes until a rising edge is input to input port K01. The input port can be addressed using the X register instead of the Y register. Note When the input port is changed from high level to low level with a pull-down resistor, the signal falls following a certain delay caused by the time constants of the pull-down resistance and the input gate capacitance. It is therefore necessary to observe a proper wait time before the input port data is read. S1C60N01 TECHNICAL SOFTWARE EPSON II-15 CHAPTER 3: PERIPHERAL CIRCUITS (Output Ports) 3.2 Output Ports Output port memory map Table 3.2.1 I/O memory map Address Register D2 D1 R01 0 BUZZER D3 0 R 0F3H *1 *2 *3 *4 *5 *6 Name SR *1 1 0 Comment 0 *5 0 *5 R01 0 High Low R01 output port data BUZZER 0 ON OFF Buzzer ON/OFF control register R00 0 High Low R00 output port data FOUT 0 ON OFF Frequency output ON/OFF control register Initial value following initial reset Not set in the circuit Undefined Reset (0) immediately after being read Always 0 when being read Refer to main manual Control of the output port II-16 R/W D0 R00 FOUT The S1C60N01 Series have 2 bits for general output ports (R00, R01). R00 and R01 although can be use for special use output port as shown in later of this section. The output port is a read/write register, output pins provide the contents of the register. The states of the output ports (R00, R01) are decided by the data of address 0F3H. Output ports can also be read, and output control is possible using the operation instructions (AND, OR, etc.). The output ports are all initialized to low level (0) after an initial reset. EPSON S1C60N01 TECHNICAL SOFTWARE CHAPTER 3: PERIPHERAL CIRCUITS (Output Ports) Examples of output port control program * Loading B register data into R00, R01 Label Mnemonic/operand Comment LD LD ;Set address of port ;R00, R01 B register Y,0F3H MY,B As shown in Figure 3.2.1, the two instruction steps above load the data of the B register into the output ports. B register D3 D2 D1 D0 Data register R00 Data register R01 "0" when being read Fig. 3.2.1 "0" when being read Control of the output port The output data can be taken from the A register, MX, or immediate data instead of the B register. S1C60N01 TECHNICAL SOFTWARE EPSON II-17 CHAPTER 3: PERIPHERAL CIRCUITS (Output Ports) * Bit-unit operation of output ports Label Mnemonic/operand Comment LD OR AND ;Set address of port ;Set R01 to 1 ;Set R00 to 0 Y,0F3H MY,0010B MY,1110B The three instruction steps above cause the output port to be set, as shown in Figure 3.2.2. Address 0F3H D3 0 D2 0 D1 R01 D0 R00 Sets "0" Sets "1" Unused Unused Fig. 3.2.2 Setting of the output port II-18 EPSON S1C60N01 TECHNICAL SOFTWARE CHAPTER 3: PERIPHERAL CIRCUITS (Special Use Output Ports) 3.3 Special Use Output Ports Special use output port memory map Table 3.3.1 I/O memory map Address Register D2 D1 R01 0 BUZZER D3 0 R D0 R00 FOUT R/W 0F3H XBZR 0 XFOUT1 XFOUT0 R/W R R/W Name SR *1 1 0 Comment 0 *5 0 *5 R01 0 High Low R01 output port data BUZZER 0 ON OFF Buzzer ON/OFF control register R00 0 High Low R00 output port data FOUT 0 ON OFF Frequency output ON/OFF control register XBZR 0 2 kHz 4 kHz Buzzer frequency control 0 High Low FOUT frequency control: 0 *5 0FDH XFOUT1 XFOUT0 *1 *2 *3 *4 *5 *6 0 High Low XFOUT1(0), XFOUT0(0) -> F1 XFOUT1(0), XFOUT0(1) -> F2 XFOUT1(1), XFOUT0(0) -> F3 XFOUT1(1), XFOUT0(1) -> F4 Initial value following initial reset Not set in the circuit Undefined Reset (0) immediately after being read Always 0 when being read Refer to main manual S1C60N01 TECHNICAL SOFTWARE EPSON II-19 CHAPTER 3: PERIPHERAL CIRCUITS (Special Use Output Ports) In addition to the regular DC, special output can be selected for output ports R00 and R01, as shown in Table 3.3.2. Figure 3.3.1 shows the structure of output ports R00 and R01. Control of the special use output port Table 3.3.2 Special output Pin Name When Special Output is Selected R00 FOUT or BUZZER R01 BUZZER BUZZER R01 Data bus Register (R01) BUZZER Register (R00) R00 FOUT Address (0F3H) Mask option Fig. 3.3.1 Structure of output ports R00, R01 II-20 EPSON S1C60N01 TECHNICAL SOFTWARE CHAPTER 3: PERIPHERAL CIRCUITS (Special Use Output Ports) Examples of special use output port control program * Buzzer driver output (BUZZER) When output port R01 is set for BUZZER and R00 is set for BUZZER, it performs 2,048 Hz or 4,096 Hz selected by register XBZR (0FDH D3). Label S1C60N01 TECHNICAL SOFTWARE Mnemonic/operand Comment LD Y,0FDH LD LD OR : AND MY,1000B Y,0F3H MY,0010B : MY,1101B ;Set address of BUZZER ;frequency control register ;Select 2,048 Hz ;Set address of output port ;Turn on BUZZER EPSON ;Turn off BUZZER II-21 CHAPTER 3: PERIPHERAL CIRCUITS (Special Use Output Ports) * Internal divided frequency output (FOUT) When output port R00 is set to FOUT output, fosc or clock frequency divided into fosc is generated. Clock frequency may be selected individually for F1-F4, from among 5 types by mask option; a clock frequency is then selected from 4 types (i.e., F1-F4) through XFOUT0 and XFOUT1 (0FDH D0 and D1) registers and is generated. The clock frequency types are shown in Table 3.3.3. Table 3.3.3 Mask option and register selection Mask Option Sets Clock Frequency (Hz) fosc = 32.768 kHz F1 F2 F3 F4 (D1,D0)=(0,0) (D1,D0)=(0,1) (D1,D0)=(1,0) (D1,D0)=(1,1) Set 1 256 (fosc/128) 512 (fosc/64) 1,024 (fosc/32) 2,048 (fosc/16) Set 2 512 (fosc/64) 1,024 (fosc/32) 2,048 (fosc/16) 4,096 (fosc/8) Set 3 1,024 (fosc/32) 2,048 (fosc/16) 4,096 (fosc/8) 8,192 (fosc/4) Set 4 2,048 (fosc/16) 4,096 (fosc/8) 8,192 (fosc/4) 16,384 (fosc/2) Set 5 4,096 (fosc/8) 8,192 (fosc/4) 16,384 (fosc/2) 32,768 (fosc/1) For example mask option is set to Set 4: Label II-22 Mnemonic/operand Comment LD Y,0FDH LD LD OR : AND MY,0011B Y,0F3H MY,0001B : MY,1110B ;Set address of FOUT ;frequency control register ;Select 16,384 Hz ;Set address of output port ;Turn on FOUT EPSON ;Turn off FOUT S1C60N01 TECHNICAL SOFTWARE CHAPTER 3: PERIPHERAL CIRCUITS (I/O Ports) 3.4 I/O Ports I/O port memory map Table 3.4.1 I/O memory map Address D3 Register D2 D1 D0 Name P03 P02 P00 P03 P01 R/W SR *1 1 0 - *2 High Low P02 - *2 High Low P01 - *2 High Low P00 - *2 High Low Output Input 0F6H Comment I/O port (P00-P03) 0 0 R 0 IOC 0 *5 R/W 0 *5 0FCH 0 *5 IOC *1 *2 *3 *4 *5 *6 0 I/O port P00-P03 Input/Output Initial value following initial reset Not set in the circuit Undefined Reset (0) immediately after being read Always 0 when being read Refer to main manual S1C60N01 TECHNICAL SOFTWARE EPSON II-23 CHAPTER 3: PERIPHERAL CIRCUITS (I/O Ports) Control of the I/O port The S1C60N01 contains a 4-bit general I/O port (4 bits x 1). This port can be used as an input port or an output port, according to I/O port control register IOC. When IOC is "0", the port is set for input, when it is "1", the port is set for output. * How to set an input port Set "0" in the I/O port control register (D0 of address 0FCH), and the I/O port is set as an input port. The state of the I/O port (P00-P03) is decided by the data of address 0F6H. (In the input mode, the port level is read directly.) * How to set an output port Set "1" in the I/O port control register, and the I/O port is set as an output port. The state of the I/O port is decided by the data of address 0F6H. This data is held by the register, and can be set regardless of the contents of the I/O control register. (The data can be set whether P00 to P03 ports are input ports or output ports.) The I/O control registers are cleared to "0" (input/output ports are set as input ports), and the data registers are also cleared to "0" after an initial reset. II-24 EPSON S1C60N01 TECHNICAL SOFTWARE CHAPTER 3: PERIPHERAL CIRCUITS (I/O Ports) Examples of I/O port * Loading P00-P03 input data into A register control program Label Mnemonic/operand Comment LD AND LD LD ;Set address of I/O control port ;Set port as input port ;Set address of port ;A register P00-P03 Y,0FCH MY,1110B Y,0F6H A,MY As shown in Figure 3.4.1, the four instruction steps above load the data of the I/O ports into the A register. Fig. 3.4.1 Loading into the A register S1C60N01 TECHNICAL SOFTWARE A register EPSON D3 D2 D1 D0 P03 P02 P01 P00 II-25 CHAPTER 3: PERIPHERAL CIRCUITS (I/O Ports) * Loading P00-P03 output data into A register Label Mnemonic/operand Comment LD Y,0FCH OR LD LD MY,0001B Y,0F6H A,MY ;Set the address of input/output ;port control register ;Set as output port ;Set the address of port ;A register P00-P03 As shown in Figure 3.4.2, the four instruction steps above load the data of the I/O ports into the A register. A register D3 D2 D1 D0 P03 P02 P01 P00 Fig. 3.4.2 Control of I/O port (input) Data register P00 Data register P01 Data register P02 Data register P03 Data can be loaded from the I/O port into the B register or MX instead of the A register. II-26 EPSON S1C60N01 TECHNICAL SOFTWARE CHAPTER 3: PERIPHERAL CIRCUITS (I/O Ports) * Loading contents of B register into P00-P03 Label Mnemonic/operand Comment LD Y,0FCH OR LD LD MY,0001B Y,0F6H MY,B ;Set the address of input/output ;port control register ;Set port as output port ;Set the address of port ;P00-P03 B register As shown in Figure 3.4.3, the four instruction steps above load the data of the B register into the I/O ports. B register D3 D2 Fig. 3.4.3 Control of the I/O port (output) D1 D0 Data register P00 Data register P01 Data register P02 Data register P03 The output data can be taken from the A register, MX, or immediate data instead of the B register. Bit-unit operation for the I/O port is identical to that for the input ports (K00-K03) or output ports (R00, R01). S1C60N01 TECHNICAL SOFTWARE EPSON II-27 CHAPTER 3: PERIPHERAL CIRCUITS (LCD Driver) 3.5 LCD Driver LCD driver memory map Table 3.5.1 I/O memory map Address Register D2 D1 D3 CSDC 0 0 Name SR *1 1 0 0 CSDC 0 Static Dynamic R R/W Comment D0 0 *5 0 *5 0 *5 LCD drive switch 0FBH *1 *2 *3 *4 *5 *6 Initial value following initial reset Not set in the circuit Undefined Reset (0) immediately after being read Always 0 when being read Refer to main manual Address 0 090 0A0 1 2 3 4 5 6 7 8 9 A B C D E F Display memory (write only) 32 words x 4 bits Fig. 3.5.1 Display memory map II-28 EPSON S1C60N01 TECHNICAL SOFTWARE CHAPTER 3: PERIPHERAL CIRCUITS (LCD Driver) Control of the LCD driver The S1C60N01 contains 128 bits of display memory in addresses 090H to 0AFH of the data memory. Each display memory can be assigned to any 80 bits of the 128 bits for the LCD driver (20 SEG x 4 COM), 60 bits of the 128 bits (20 SEG x 3 COM) or 40 bits of the 128 bits (20 SEG x 2 COM) by using a mask option. The remaining 48 bits, 68 bits or 88 bits of display memory are not connected to the LCD driver, and are not output even when data is written. An LCD segment is on with "1" set in the display memory, and off with "0" set in the display memory. Note that the display memory is a write-only. * LCD drive control register (CSDC) The LCD drive control register (CSDC: address 0FBH, D3) can set the 1/1 duty drive. Set "0" in CSDC for 1/4 duty, 1/3 duty or 1/1 duty drive. Set "1" in CSDC and the same value in the registers corresponding to COMs 0 through 3 for 1/1 duty drive. Figure 3.5.2 shows the 1/1 duty drive waveform (1/3 bias) and Figure 3.5.3 shows an example of the 7-segment LCD assignment. See page I-41 for the 1/1 duty drive waveform (1/2 bias). S1C60N01 TECHNICAL SOFTWARE EPSON II-29 CHAPTER 3: PERIPHERAL CIRCUITS (LCD Driver) LCD lighting status -VDD -VL1 -VL2 -VL3 COM 0-3 COM0 COM1 COM2 COM3 Frame frequency SEG0-19 -VDD -VL1 -VL2 -VL3 Not lit Lit SEG 0-19 -VDD -VL1 -VL2 -VL3 Fig. 3.5.2 1/1 duty drive control (1/3 bias) a f b g Address 090H e Fig. 3.5.3 7-segment LCD assignment c 091H Register D3 D2 D1 D0 d c g b f a e d In the assignment shown in Figure 3.5.3, the 7-segment display pattern is controlled by writing data to display memory addresses 090H and 091H. II-30 EPSON S1C60N01 TECHNICAL SOFTWARE CHAPTER 3: PERIPHERAL CIRCUITS (LCD Driver) Examples of LCD driver control program * Displaying 7-segment The LCD display routine using the assignment of Figure 3.5.3 can be programmed as follows. Label Mnemonic/operand Comment ORG RETD RETD RETD RETD RETD RETD RETD RETD RETD RETD 000H 3FH 06H 5BH 4FH 66H 6DH 7DH 27H 7FH 6FH ;0 is displayed ;1 is displayed ;2 is displayed ;3 is displayed ;4 is displayed ;5 is displayed ;6 is displayed ;7 is displayed ;8 is displayed ;9 is displayed B,0 X,090H ;Set the address of jump ;Set address of display memory SEVENS: LD LD JPBA When the above routine is called (by the CALL or CALZ instruction) with any number from "0" to "9" set in the A register for the assignment of Figure 3.5.4, seven segments are displayed according to the contents of the A register. Fig. 3.5.4 Data set in A register and displayed patterns A resister Display A resister Display A resister Display A resister Display A resister 0 2 4 6 8 1 3 5 7 9 Display The RETD instruction can be used to write data to the display memory only if it is addressed using the X register. (Addressing using the Y register is invalid.) Note that the stack pointer must be set to a proper value before the CALL (CALZ) instruction is executed. S1C60N01 TECHNICAL SOFTWARE EPSON II-31 CHAPTER 3: PERIPHERAL CIRCUITS (LCD Driver) * Bit-unit operation of the display memory Address Fig. 3.5.5 Example of segment assignment Data D3 D2 090H Label D1 D0 : SEG-A : SEG-B Mnemonic/operand Comment LD X,SEGBUF LD LD LD AND LD AND LD Y,090H MX,3 MY,MX MX,1110B MY,MX MX,1101B MY,MX ;Set address display ;memory buffer ;Set address display memory ;Set buffer data ;SEG-A, B ON ( , ) ;Change buffer data ;SEG-A OFF (, ) ;Change buffer data ;SEG-B OFF (, ) For manipulation of the display memory in bit-units for the assignment of Figure 3.5.5, a buffer must be provided in RAM to hold data. Note that, since the display memory is write-only, data cannot be changed directly using an ALU instruction (for example, AND or OR). After manipulating the data in the buffer, write it into the corresponding display memory using the transfer command. II-32 EPSON S1C60N01 TECHNICAL SOFTWARE CHAPTER 3: PERIPHERAL CIRCUITS (Timer) 3.6 Timer Timer memory map Table 3.6.1 I/O memory map Address D3 Register D2 D1 TM3 TM2 TM1 D0 Name TM0 TM3 R Comment 1 0 - High Low Timer data (clock timer 2 Hz) TM2 - High Low Timer data (clock timer 4 Hz) TM1 - High Low Timer data (clock timer 8 Hz) TM0 - High Low Timer data (clock timer 16 Hz) EIT2 0 Enable Mask Interrupt mask register (clock timer 2 Hz) EIT8 0 Enable Mask Interrupt mask register (clock timer 8 Hz) EIT32 0 Enable Mask Interrupt mask register (clock timer 32 Hz) 0 Yes No Interrupt factor flag (clock timer 2 Hz) 0 Yes No Interrupt factor flag (clock timer 8 Hz) 0 Yes No Interrupt factor flag (clock timer 32 Hz) Reset Reset - Clock timer reset SR *1 0E4H 0 EIT2 EIT8 R EIT32 R/W 0 *5 0EBH 0 IT2 IT8 IT32 R 0 IT2 0EFH IT8 IT32 0 TMRST R W 0 0 R 0 *4 *4 *4 *5 TMRST 0F9H 0 0 *1 *2 *3 *4 *5 *6 *5 *5 *5 Initial value following initial reset Not set in the circuit Undefined Reset (0) immediately after being read Always 0 when being read Refer to main manual S1C60N01 TECHNICAL SOFTWARE EPSON II-33 CHAPTER 3: PERIPHERAL CIRCUITS (Timer) Control of the timer Address 0E4H Register bit Frequency D0 16 Hz D1 8 Hz D2 4 Hz D3 2 Hz The S1C60N01 contains a timer with a basic oscillation of 32.768 kHz (typical). This timer is a 4-bit binary counter, and the counter data can be read as necessary. The counter data of the 16 Hz clock can be read by reading TM3 to TM0 (address 0E4H, D3 to D0). ("1" to "0" are set in TM3 to TM0, corresponding to the high-low levels of the 2 Hz, 4 Hz, 8 Hz, and 16 Hz 50 % duty waveform. See Figure 3.6.1.) The timer can also interrupt the CPU on the falling edges of the 32 Hz, 8 Hz, and 2 Hz signals. For details, see Section 3.8, "Interrupt and Halt". Clock timer timing chart Occurrence of 32 Hz interrupt request Occurrence of 8 Hz interrupt request Occurrence of 2 Hz interrupt request Fig. 3.6.1 Output waveform of timer and interrupt timing The timer is reset by setting "1" in TMRST (address 0F9H, D2). Note The 128 Hz to 2 Hz of the internal divider is initialized by resetting the timer. II-34 EPSON S1C60N01 TECHNICAL SOFTWARE CHAPTER 3: PERIPHERAL CIRCUITS (Timer) Examples of timer control program * Initializing the timer Label Mnemonic/operand Comment LD Y,0F9H OR MY,0100B ;Set address of the timer ;reset register ;Reset the timer The two instruction steps above are used to reset (clear TM0-TM3 to 0) and restart the timer. The TMRST register is cleared to "0" by hardware 1 clock after it is set to "1". * Loading the timer Label Mnemonic/operand Comment LD Y,0E4H LD A,MY ;Set address of ;the timer data (TM0 to TM3) ;Load the data of ;TM0 to TM3 into A register As shown in Table 3.6.2, the two instruction steps load the data of TM0 to TM3 into the A register. Table 3.6.2 Loading the timer data S1C60N01 TECHNICAL SOFTWARE A register D3 D2 TM3 (2 Hz) TM2 (4 Hz) EPSON D1 D0 TM1 (8 Hz) TM0 (16 Hz) II-35 CHAPTER 3: PERIPHERAL CIRCUITS (Timer) * Checking timer edge Label Mnemonic/operand Comment LD CP X,TMSTAT MX,0 JP LD LD Z,RETURN Y,0E4H A,MY LD XOR Y,TMDTBF MY,A FAN LD MX,0100B MY,A JP ADD Z,RETURN MX,0FH ;Set address of the timer edge counter ;Check whether the timer edge ;counter is "0" ;Jump if "0" (Z-flag is "1") ;Set address of the timer ;Read the data of TM0 to TM3 ;into A register ;Set address of the timer data buffer ;Did the count on the timer ;change? ;Check bit D2 of the timer data buffer ;Set the data of A register into ;the timer data buffer ;Jump, if the Z-flag is "1" ;Decrement the timer edge counter ; RETURN: RET ;Return This program takes a subroutine form. It is called at short intervals, and decrements the data at address TMSTAT every 125 ms until the data reaches "0". The timing chart is shown in Figure 3.6.2. The timer can be addressed using the X register instead of the Y register. Note TMSTAT and TMDTBF may be any address in RAM and not involve a hardware function. TM2 125 ms Fig. 3.6.2 Timing of the timer edge counter II-36 Timer edge counter (TMSTAT) decrementing timing EPSON S1C60N01 TECHNICAL SOFTWARE CHAPTER 3: PERIPHERAL CIRCUITS (Heavy Load Protection Function) 3.7 Heavy Load Protection Function Heavy load protection function memory map Table 3.7.1 I/O memory map Address D3 HLMOD Register D2 D1 0 R/W 0 R D0 Name 0 HLMOD 0 0FAH 0 0 *1 *2 *3 *4 *5 *6 SR *1 0 1 0 Heavy load Normal load Comment Heavy load protection mode register *5 *5 *5 Initial value following initial reset Not set in the circuit Undefined Reset (0) immediately after being read Always 0 when being read Refer to main manual Heavy load protection function The S1C60N01 has the heavy load protection function for when the battery load becomes heavy and the source voltage changes, such as when an external buzzer sounds or an external lamp lights. The state where the heavy load protection function is in effect is called the heavy load protection mode. Compared with the normal operation mode, this mode can reduce the output voltage variation of the internal regulated voltage and spend more power consumption. The normal mode changes to the heavy load protection mode in the following case: * When the software changes the mode to the heavy load protection mode (HLMOD = "1") S1C60N01 TECHNICAL SOFTWARE EPSON II-37 CHAPTER 3: PERIPHERAL CIRCUITS (Heavy Load Protection Function) Examples of heavy load protection function control program * Operation through the HLMOD register This is a sample program when lamp is driven with the R00 terminal during performance of heavy load protection. Label Mnemonic/operand Comment LD OR LD OR X,0FAH MX,1000B Y,0F3H MY,0001B ;Sets the address of HLMOD ;Sets to the heavy protection mode ;Sets the address of R0n port ;Turns lamp ON Y,0F3H MY,1110B WT1S MX,0111B ;Sets the R0n port address ;Turns the lamp OFF ;1 second waiting time (software timer) ;Cancels the heavy load protection mode : : LD AND CALL AND In the above program, the heavy load protection mode is canceled after 1 sec waiting time provided as the time for the battery voltage to stabilize after the lamp is turned off; however, since this time varies according to the nature of the battery, time setting must be done in accordance with the actual application. II-38 EPSON S1C60N01 TECHNICAL SOFTWARE CHAPTER 3: PERIPHERAL CIRCUITS (Interrupt and Halt) 3.8 Interrupt and Halt Interrupt memory map Table 3.8.1 I/O memory map Address D3 EIK03 Register D2 D1 EIK02 EIK01 D0 Name EIK00 EIK03 R/W Comment 1 0 0 Enable Mask Interrupt mask register (K03) EIK02 0 Enable Mask Interrupt mask register (K02) EIK01 0 Enable Mask Interrupt mask register (K01) EIK00 0 Enable Mask Interrupt mask register (K00) EIT2 0 Enable Mask Interrupt mask register (clock timer 2 Hz) EIT8 0 Enable Mask Interrupt mask register (clock timer 8 Hz) EIT32 0 Enable Mask Interrupt mask register (clock timer 32 Hz) 0 Yes No 0 Enable Mask Interrupt factor flag (clock timer 2 Hz) 0 Enable Mask Interrupt factor flag (clock timer 8 Hz) 0 Enable Mask Interrupt factor flag (clock timer 32 Hz) SR *1 0E8H 0 EIT2 EIT8 R EIT32 R/W 0 *5 0EBH 0 0 0 IK0 0 *5 0 *5 R 0EDH 0 *5 IK0 *4 0 IT2 IT8 R IT32 0 IT2 Interrupt factor flag (K00-K03) *5 *4 0EFH IT8 IT32 *1 *2 *3 *4 *5 *6 *4 *4 Initial value following initial reset Not set in the circuit Undefined Reset (0) immediately after being read Always 0 when being read Refer to main manual S1C60N01 TECHNICAL SOFTWARE EPSON II-39 CHAPTER 3: PERIPHERAL CIRCUITS (Interrupt and Halt) Control of interrupts and halt The S1C60N01 supports two types of a total of 7 interrupts. There are three timer interrupts (2 Hz, 8 Hz, 32 Hz) and four input interrupts (K00-K03). The 7 interrupts are individually enabled or masked (disabled) by interrupt mask registers. The EI and DI instructions can be used to set or reset the interrupt flag (I), which enables or disables all the interrupts at the same time. When an interrupt is accepted, the interrupt flag (I) is reset, and cannot accepts any other interrupts (DI state). Restart from the halt state created by the HALT instruction, is done by interrupt. II-40 EPSON S1C60N01 TECHNICAL SOFTWARE CHAPTER 3: PERIPHERAL CIRCUITS (Interrupt and Halt) * Interrupt factor flags IK0 This flag is set when any of the K00 to K03 input interrupts occurs. The interrupt factor flag (IK0) is set to "1" when the contents of the input (K00-K03) become "1" and the data of the corresponding interrupt mask register (EIK00-EIK03) is "1". The contents of the IK0 flag can be loaded by software to determine whether the K00-K03 input interrupts have occured. The flag is reset when loaded by software. (See Figure 3.8.1.) Data bus K00 K01 K02 K03 Address 0E0H Input interrupt factor flag register (IK0) INT (Interrupt request) Data bus FF Interrupt flag (I) D0 D1 D2 D3 Input interrupt mask register (EIK00-EIK03) Address 0E8H Fig. 3.8.1 K00-K03 Input interrupt circuit S1C60N01 TECHNICAL SOFTWARE EPSON II-41 CHAPTER 3: PERIPHERAL CIRCUITS (Interrupt and Halt) IT32 This flag is set to "1" when a falling edge is detected in the timer TM1 (32 Hz) signal. The contents of the IT32 flag can be loaded by software to determine whether a 32 Hz timer interrupt has occured. The flag is reset, when it is loaded by software. (See Figure 3.8.2.) IT8 This flag is set to "1" when a falling edge is detected in the timer TM1 (8 Hz) signal. The contents of the IT8 flag can be loaded by software to determine whether an 8 Hz timer interrupt has occured. The flag is reset, when it is loaded by software. (See Figure 3.8.2.) IT2 This flag is set to "1" when a falling edge is detected in the timer TM1 (2 Hz) signal. The contents of the IT2 flag can be loaded by software to determine whether a 2 Hz timer interrupt has occured. The flag is reset, when it is loaded by software. (See Figure 3.8.2.) Timer interrupt factor flag (IT) D0 Data bus Basic clock counter 32 Hz 8 Hz D1 2 Hz D2 Address 0EFH Timer interrupt mask register (EIT) Data bus D0 INT (Interrupt request) D1 D2 Address 0EBH Interrupt flag (I) Fig. 3.8.2 Timer interrupt circuit II-42 EPSON S1C60N01 TECHNICAL SOFTWARE CHAPTER 3: PERIPHERAL CIRCUITS (Interrupt and Halt) * Interrupt mask registers The interrupt mask registers are registers that individually specify whether to enable or mask the timer interrupt (2 Hz, 8 Hz, 32 Hz) or input interrupt (K00-K03). The following are descriptions of the interrupt mask registers. EIK00 to EIK03 This register enables or masks the K00-K03 input interrupt. The interrupt condition flag (IK0) is set to "1" when the contents of the input (K00-K03) become "1" and the data of the corresponding interrupt mask register (EIK00-EIK03) is "1". The CPU is interrupted if it is in the EI state (interrupt flag [I] = "1"). (See Figure 3.8.1.) <Input interrupt programing related precautions> Port K input Active status Mask register Fig. 3.8.3 Input interrupt timing Factor flag set Not set When the content of the mask register is rewritten, while the port K input is in the active status. The input interrupt factor flag is set at . When using an input interrupt, if you rewrite the content of the mask register, when the value of the input terminal which becomes the interrupt input is in the active status (input terminal = high status), the factor flag for input interrupt may be set. For example, a factor flag is set with the timing of shown in Figure 3.8.3. However, when clearing the content of the mask register with the input terminal kept in the high status and then setting it, the factor flag of the input interrupt is again set at the timing that has been set. Consequently, when the input terminal is in the active status (high status), do not rewrite the mask register (clearing, then setting the mask register), so that a factor flag will only set at the rising edge in this case. When clearing, then setting the mask register, set the mask register, when the input terminal is not in the active status (low status). S1C60N01 TECHNICAL SOFTWARE EPSON II-43 CHAPTER 3: PERIPHERAL CIRCUITS (Interrupt and Halt) EIT32 This register enables or masks the 32 Hz timer interrupt. The CPU is interrupted if it is in the EI state when the interrupt mask register (EIT32) is set to "1" and the interrupt condition flag (IT32) is "1". (See Figure 3.8.2.) EIT8 This register enables or masks the 8 Hz timer interrupt. The CPU is interrupted if it is in the EI state when the interrupt mask register (EIT8) is set to "1" and the interrupt condition flag (IT8) is "1". (See Figure 3.8.2.) EIT2 This register enables or masks the 2 Hz timer interrupt. The CPU is intterrupted if it is in the EI state when the interrupt mask register (EIT2) is set to "1" and the interrupt condition flag (IT2) is "1". (See Figure 3.8.2.) II-44 EPSON S1C60N01 TECHNICAL SOFTWARE CHAPTER 3: PERIPHERAL CIRCUITS (Interrupt and Halt) * Interrupt vector address The S1C60N01 interrupt vector address is made up of the low-order 2 bits of the program counter (12 bits), each of which is assigned a specific function as shown in Figure 3.8.4. PCP3 PCP2 PCP1 PCP0 PCS7 PCS6 PCS5 PCS4 PCS3 PCS2 PCS1 PCS0 Fig. 3.8.4 Assignment of the 0 interrupt vector address 0 0 1 0 0 0 0 0 x 0 x Input (K00-K03) interrupt Clock timer interrupt Note that all of the three timer interrupts have the same vector address, and software must be used to judge whether or not a given timer interrupt has occurred. For instance, when the 32 Hz timer interrupt and the 8 Hz timer interrupt are enabled at the same time, the accepted timer interrupt must be identified by software. (Similarly, the K00-K03 input interrupts must be identified by software.) When an interrupt is generated, the hardware resets the interrupt flag (I) to enter the DI state. Execute the EI instruction as necessary to recover the EI state after interrupt processing. Set the EI state at the start of the interrupt processing routine to allow nesting of the interrupts. The interrupt factor flags must always be reset before setting the EI status in the corresponding interrupt processing routine. (The flag is reset when the interrupt condition flag is read by software.) S1C60N01 TECHNICAL SOFTWARE EPSON II-45 CHAPTER 3: PERIPHERAL CIRCUITS (Interrupt and Halt) If the EI instruction is executed without resetting the interrupt factor flag after generating the timer interrupt, and if the corresponding interrupt mask register is still "1", the same interrupt is generated once more. (See Figure 3.8.5.) If the EI state is set without resetting the interrupt factor flag after generating the input interrupt (K00-K03), the same interrupt is generated once more. (See Figure 3.8.5.) The interrupt factor flag must always be read (reset) in the DI state (interrupt flag [I] = "0"). There may be an operation error if read in the EI state. The timer interrupt factor flags (IT32, IT8, IT2) and the stopwatch interrupt factor flags (ISW1, ISW0) are set whether the corresponding interrupt mask register is set or not. The input interrupt factor flag (IK0) is allowed to be set in the condition when the corresponding interrupt mask register (EIK00-EIK03) is set to "1" (interrupt is enabled). (See Figure 3.8.5.) Table 3.8.2 shows the interrupt vector map. Table 3.8.2 Page Interrupt vector map 1 Step Interrupt Vector 00H Initial reset 01H Clock timer interrupt 04H Input (K00-K03) interrupt 05H Input interrupt and clock timer interrupt Addesses (start address of interrupt processing routines) to jump to are written into the addresses available for interrupt vector allocation. II-46 EPSON S1C60N01 TECHNICAL SOFTWARE CHAPTER 3: PERIPHERAL CIRCUITS (Interrupt and Halt) Interrupt vector (MSB) : Program counter of CPU (three low-order bits) : (LSB) K00 EIK00 INT (Interrupt request) K01 EIK01 IK0 Interrupt flag K02 EIK02 K03 EIK03 IT2 Interrupt factor flag EIT2 Interrupt mask register IT8 EIT8 IT32 EIT32 Fig. 3.8.5 Internal interrupt circuit S1C60N01 TECHNICAL SOFTWARE EPSON II-47 CHAPTER 3: PERIPHERAL CIRCUITS (Interrupt and Halt) Examples of interrupt * Restart from halt state by interrupt and halt control Main routine program Label Mnemonic/operand Comment LD X,0E8H OR MX,1111B ;Set address of K00 to K03 ;interrupt mask register ;Enable K00 to K03 ;input interrupt LD X,0EBH OR MX,0111B EI HALT JP MAIN ; MAIN: ;Set address of timer interrupt ;mask register ;Enable timer interrupt ;(32 Hz, 8 Hz, 2 Hz) ;Set interrupt flag (EI state is set) ;Halt mode ;Jump to MAIN Interruption vector routine Label Mnemonic/operand ORG JP JP JP JP JP JP 100H INIT INTR INTR INTR INTR INTR Comment ;Timer interrupt is generated ;K00 to K03 interrupt is generated ;Timer interrupt, K00 to K03 interrupt ;are generated ; INTR: LD LD LD FAN JP CALL X,0EFH Y,TMFSK MY,MX MY,0100B Z,TI8RQ TINT2 ;Address of timer interrupt factor flag ;Address of timer interrupt factor flag buffer LD FAN JP CALL Y,TMFSK MY,0010B Z,TI32RQ TINT8 ;Address of timer factor flag buffer ;Check 8 Hz timer interrupt ;Jump if not 8 Hz timer interrupt ;Call 8 Hz timer interrupt service routine ;Check 2 Hz timer interrupt ;Jump if not 2 Hz timer interrupt ;Call 2 Hz timer interrupt service routine TI8RQ: II-48 EPSON S1C60N01 TECHNICAL SOFTWARE CHAPTER 3: PERIPHERAL CIRCUITS (Interrupt and Halt) TI32RQ: LD FAN JP CALL Y,TMFSK MY,0001B Z,IK0RQ TINT32 ;Address of timer factor flag buffer ;Check 8 Hz timer interrupt ;Jump if not 32 Hz timer interrupt ;Call 32 Hz timer interrupt service routine LD FAN JP CALL X,0EDH MX,0001B Z,INTEND IK0INT ;Address of K00 to K03 input interrupt flag ;Check K00 to K03 input interrupt ;Jump if not K00 to K03 input interrupt ;Call K00 to K03 input interrupt service ;routine IK0RQ: INTEND: EI RET The above program is normally used to restart the CPU when in the halt state by interrupt and to return it to the halt state again after the interrupt processing is completed. The processing proceeds by repeating the halt interrupt halt interrupt cycle. The interrupt factor flag is reset when load by the software. Thus, when using interrupts which interrupt factor flags are in the same address at the same time, flag check must be done after storing the data. For example, store the 1 word including the factor flag in the RAM. (If check is directly done by the FAN instruction, the factor flags of the same address are all reset.) Reading of interrupt factor flags is available at EI, but be careful in the following cases. If the interrupt mask register value corresponding to the interrupt factor flags to be read is set to "1", an interrupt request will be generated by the interrupt factor flags set timing, or an interrupt request will not be generated. S1C60N01 TECHNICAL SOFTWARE EPSON II-49 CHAPTER 4: SUMMARY OF PROGRAMMING POINTS CHAPTER 4 SUMMARY OF PROGRAMMING POINTS * Core CPU After the system reset, only the program counter (PC), new page pointer (NPP) and interrupt flag (I) are initialized by the hardware. The other internal circuits whose settings are undefined must be initialized with the program. * Power Supply External load driving through the output voltage of constant voltage circuit or voltage booster/reducer is not permitted. * Data Memory - Since some portions of the RAM are also used as stack area during sub-routine call or register saving, see to it that the data area and the stack area do not overlap. - The stack area consumes 3 words during a sub-routine call or interrupt. - Address 00H-0FH in the RAM is the memory register area addressed by the register pointer RP. - Memory is not mounted in unused area within the memory map and in memory area not indicated in this manual. For this reason, normal operation cannot be assured for programs that have been prepared with access to these areas. * Initial Reset - Maintain the initial reset circuit at high level for at least 4 seconds (in case of oscillation frequency fosc = 32 kHz) because noise rejector is built-in. - When utilizing the simultaneous high input reset function of the input ports (K00-K03), take care not to make the ports specified during normal operation to go high simultaneously. II-50 EPSON S1C60N01 TECHNICAL SOFTWARE CHAPTER 4: SUMMARY OF PROGRAMMING POINTS * Input Port - When modifying the input port from high level to low level with pull-down resistance, a delay will occur at the rise of the waveform due to time constant of the pull-down resistance and input gate capacities. Provide appropriate waiting time in the program when performing input port reading. - Input interrupt programing related precautions Port K input Active status Mask register Fig. 4.1 Input interrupt timing Factor flag set Not set When the content of the mask register is rewritten, while the port K input is in the active status. The input interrupt factor flag is set at . When using an input interrupt, if you rewrite the content of the mask register, when the value of the input terminal which becomes the interrupt input is in the active status (input terminal = high status), the factor flag for input interrupt may be set. For example, a factor flag is set with the timing of shown in Figure 4.1. However, when clearing the content of the mask register with the input terminal kept in the high status and then setting it, the factor flag of the input interrupt is again set at the timing that has been set. Consequently, when the input terminal is in the active status (high status), do not rewrite the mask register (clearing, then setting the mask register), so that a factor flag will only set at the rising edge in this case. When clearing, then setting the mask register, set the mask register, when the input terminal is not in the active status (low status). * Output Port S1C60N01 TECHNICAL SOFTWARE The FOUT and BUZZER output signal may produce hazards when the output ports R00 and R01 are turned on or off. EPSON II-51 CHAPTER 4: SUMMARY OF PROGRAMMING POINTS * I/O Port - When the I/O port is set to the output mode and a lowimpedance load is connected to the port pin, the data written to the register may differ from the data read. - When the I/O port is set to the input mode and a lowlevel voltage (VSS) is input by the built-in pull-down resistance, an erroneous input results if the time constant of the capacitive load of the input line and the builtin pull-down resistance load is greater than the read-out time. When the input data is being read, the time that the input line is pulled down is equivalent to 0.5 cycles of the CPU system clock. Hence, the electric potential of the pins must settle within 0.5 cycles. If this condition cannot be met, some measure must be devised, such as arranging a pull-down resistance externally, or performing multiple read-outs. * LCD Driver - Because the display memory is for writing only, re-writing the contents with computing instructions (e.g., AND, OR, etc.) which come with read-out operations is not possible. To perform bit operations, a buffer to hold the display data is required on the RAM. - Even when 1/2 duty is selected, the display data corresponding to COM0, COM3 are valid for static drive. Hence, for static drive set the same value to all display memory corresponding COM0-COM3. - Even when 1/3 duty is selected, the display data corresponding to COM3 is valid for static drive. Hence, for static drive set the same value to all display memory corresponding COM0-COM3. - For cadence adjustment, set the display data including display data corresponding to COM3. - fosc indicates the oscillation frequency of the oscillation circuit. * II-52 Heavy Load Protection Function In the heavy load protection function (heavy load protection mode flag = "1"), the internal regulated voltage is more stabler but spend more power current consumption. EPSON S1C60N01 TECHNICAL SOFTWARE CHAPTER 4: SUMMARY OF PROGRAMMING POINTS * Interrupt - Re-start from the HALT state is performed by the interrupt. The return address after completion of the interrupt processing in this case will be the address following the HALT instruction. - When interrupt occurs, the interrupt flag will be reset by the hardware and it will become DI state. After completion of the interrupt processing, set to the EI state through the software as needed. Moreover, the nesting level may be set to be programmable by setting to the EI state at the beginning of the interrupt processing routine. - Be sure to reset the interrupt factor flag before setting to the EI state on the interrupt processing routine. The interrupt factor flag is reset by reading through the software. Not resetting the interrupt factor flag and interrupt mask register being "1", will cause the same interrupt to occur again. - The interrupt factor flag will be reset by reading through the software. Because of this, when multiple interrupt factor flags are to be assigned to the same address, perform the flag check after the contents of the address has been stored in the RAM. Direct checking with the FAN instruction will cause all the interrupt factor flag to be reset. - Reading of interrupt factor flags is available at EI, but be careful in the following cases. If the interrupt mask register value corresponding to the interrupt factor flags to be read is set to "1", an interrupt request will be generated by the interrupt factor flags set timing, or an interrupt request will not be generated. * Vacant Register and Read/Write S1C60N01 TECHNICAL SOFTWARE Writing data into the addresses where read/write bits and read only bits are mixed in 1 word (4 bits) does not affect the read only bits. EPSON II-53 APPENDIX A: TABLE OF INSTRUCTIONS APPENDIX A Table of Instructions Operation Code Classification Mnemonic Branch PSET p Operand Flag B A 9 8 7 6 5 4 3 2 1 0 I D Z C Clock Operation 1 1 1 0 0 1 0 p4 p3 p2 p1 p0 5 NBP p4, NPP p3~p0 s 0 0 0 0 s7 s6 s5 s4 s3 s2 s1 s0 5 PCB NBP, PCP NPP, PCS s7~s0 C, s 0 0 1 0 s7 s6 s5 s4 s3 s2 s1 s0 5 PCB NBP, PCP NPP, PCS s7~s0 if C=1 NC, s 0 0 1 1 s7 s6 s5 s4 s3 s2 s1 s0 5 PCB NBP, PCP NPP, PCS s7~s0 if C=0 Z, s 0 1 1 0 s7 s6 s5 s4 s3 s2 s1 s0 5 PCB NBP, PCP NPP, PCS s7~s0 if Z=1 NZ, s 0 1 1 1 s7 s6 s5 s4 s3 s2 s1 s0 5 PCB NBP, PCP NPP, PCS s7~s0 if Z=0 JPBA 1 1 1 1 1 1 1 0 1 0 0 0 5 PCB NBP, PCP NPP, PCSH B, PCSL A CALL s 0 1 0 0 s7 s6 s5 s4 s3 s2 s1 s0 7 M(SP-1) PCP, M(SP-2) PCSH, M(SP-3) PCSL+1 CALZ s 0 1 0 1 s7 s6 s5 s4 s3 s2 s1 s0 7 instructions JP SP SP-3, PCP NPP, PCS s7~s0 M(SP-1) PCP, M(SP-2) PCSH, M(SP-3) PCSL+1 SP SP-3, PCP 0, PCS s7~s0 PCSL M(SP), PCSH M(SP+1), PCP M(SP+2) RET 1 1 1 1 1 1 0 1 1 1 1 1 7 RETS 1 1 1 1 1 1 0 1 1 1 1 0 12 RETD l 0 0 0 1 l7 l6 l5 l4 l3 l2 l1 l0 12 System NOP5 1 1 1 1 1 1 1 1 1 0 1 1 5 No operation (5 clock cycles) control NOP7 1 1 1 1 1 1 1 1 1 1 1 1 7 No operation (7 clock cycles) SP SP+3 PCSL M(SP), PCSH M(SP+1), PCP M(SP+2) SP SP+3, PC PC+1 PCSL M(SP), PCSH M(SP+1), PCP M(SP+2) SP SP+3, M(X) i3~i0, M(X+1) l7~l4, X X+2 instructions HALT 1 1 1 1 1 1 1 1 1 0 0 0 5 Halt (stop clock) X 1 1 1 0 1 1 1 0 0 0 0 0 5 X X+1 operation Y 1 1 1 0 1 1 1 1 0 0 0 0 5 Y Y+1 instructions LD X, x 1 0 1 1 x7 x6 x5 x4 x3 x2 x1 x0 5 XH x7~x4, XL x3~x0 Y, y 1 0 0 0 y7 y6 y5 y4 y3 y2 y1 y0 5 YH y7~y4, YL y3~y0 XH, r 1 1 1 0 1 0 0 0 0 1 r1 r0 5 XH r XL, r 1 1 1 0 1 0 0 0 1 0 r1 r0 5 XL r YH, r 1 1 1 0 1 0 0 1 0 1 r1 r0 5 YH r YL, r Index INC ADC II-54 1 1 1 0 1 0 0 1 1 0 r1 r0 5 YL r r, XH 1 1 1 0 1 0 1 0 0 1 r1 r0 5 r XH r, XL 1 1 1 0 1 0 1 0 1 0 r1 r0 5 r XL r, YH 1 1 1 0 1 0 1 1 0 1 r1 r0 5 r YH r, YL 1 1 1 0 1 0 1 1 1 0 r1 r0 5 r YL XH, i 1 0 1 0 0 0 0 0 i3 i2 i1 i0 7 XH XH+i3~i0+C XL, i 1 0 1 0 0 0 0 1 i3 i2 i1 i0 7 XL XL+i3~i0+C YH, i 1 0 1 0 0 0 1 0 i3 i2 i1 i0 7 YH YH+i3~i0+C YL, i 7 YL YL+i3~i0+C 1 0 1 0 0 0 1 1 i3 i2 i1 i0 EPSON S1C60N01 TECHNICAL SOFTWARE APPENDIX A: TABLE OF INSTRUCTIONS Operation Code Flag Classification Mnemonic Operand Index CP XH, i 1 0 1 0 0 1 0 0 i3 i2 i1 i0 7 XH-i3~i0 operation XL, i 1 0 1 0 0 1 0 1 i3 i2 i1 i0 7 XL-i3~i0 instructions YH, i 1 0 1 0 0 1 1 0 i3 i2 i1 i0 7 YH-i3~i0 YL, i 1 0 1 0 0 1 1 1 i3 i2 i1 i0 7 YL-i3~i0 r, i 1 1 1 0 0 0 r1 r0 i3 i2 i1 i0 5 r i3~i0 transfer r, q 1 1 1 0 1 1 0 0 r1 r0 q1 q0 5 r q instructions A, Mn 1 1 1 1 1 0 1 0 n3 n2 n1 n0 5 A M(n3~n0) B, Mn 1 1 1 1 1 0 1 1 n3 n2 n1 n0 5 B M(n3~n0) Mn, A 1 1 1 1 1 0 0 0 n3 n2 n1 n0 5 M(n3~n0) A Mn, B 1 1 1 1 1 0 0 1 n3 n2 n1 n0 5 M(n3~n0) B LDPX MX, i 1 1 1 0 0 1 1 0 i3 i2 i1 i0 5 M(X) i3~i0, X X+1 1 1 1 0 1 1 1 0 r1 r0 q1 q0 5 r q, X X+1 LDPY MY, i 1 1 1 0 0 1 1 1 i3 i2 i1 i0 Data LD r, q B A 9 8 7 6 5 4 3 2 1 0 I D Z C Clock Operation 5 M(Y) i3~i0, Y Y+1 1 1 1 0 1 1 1 1 r1 r0 q1 q0 5 r q, Y Y+1 LBPX MX, l 1 0 0 1 l7 l6 l5 l4 l3 l2 l1 l0 5 M(X) l3~l0, M(X+1) l7~l4, X X+2 r, q Flag SET F, i 1 1 1 1 0 1 0 0 i3 i2 i1 i0 7 F F i3~i0 operation RST F, i 1 1 1 1 0 1 0 1 i3 i2 i1 i0 7 F F i3~i0 instructions SCF 1 1 1 1 0 1 0 0 0 0 0 1 7 C 1 RCF 1 1 1 1 0 1 0 1 1 1 1 0 7 C 0 SZF 1 1 1 1 0 1 0 0 0 0 1 0 7 Z 1 RZF 1 1 1 1 0 1 0 1 1 1 0 1 7 Z 0 SDF 1 1 1 1 0 1 0 0 0 1 0 0 7 D 1 (Decimal Adjuster ON) RDF 1 1 1 1 0 1 0 1 1 0 1 1 7 D 0 (Decimal Adjuster OFF) EI 1 1 1 1 0 1 0 0 1 0 0 0 7 I 1 (Enables Interrupt) DI 1 1 1 1 0 1 0 1 0 1 1 1 7 I 0 (Disables Interrupt) Stack INC SP 1 1 1 1 1 1 0 1 1 0 1 1 5 SP SP+1 operation DEC SP 1 1 1 1 1 1 0 0 1 0 1 1 5 SP SP-1 1 1 1 1 1 1 0 0 0 0 r1 r0 5 SP SP-1, M(SP) r XH 1 1 1 1 1 1 0 0 0 1 0 1 5 SP SP-1, M(SP) XH XL 1 1 1 1 1 1 0 0 0 1 1 0 5 SP SP-1, M(SP) XL YH 1 1 1 1 1 1 0 0 1 0 0 0 5 SP SP-1, M(SP) YH YL 1 1 1 1 1 1 0 0 1 0 0 1 5 SP SP-1, M(SP) YL F 1 1 1 1 1 1 0 0 1 0 1 0 5 SP SP-1, M(SP) F r 1 1 1 1 1 1 0 1 0 0 r1 r0 5 r M(SP), SP SP+1 XH 1 1 1 1 1 1 0 1 0 1 0 1 5 XH M(SP), SP SP+1 XL 1 1 1 1 1 1 0 1 0 1 1 0 5 XL M(SP), SP SP+1 instructions PUSH r POP S1C60N01 TECHNICAL SOFTWARE EPSON II-55 APPENDIX A: TABLE OF INSTRUCTIONS Operation Code Flag Classification Mnemonic Operand Stack POP YH 1 1 1 1 1 1 0 1 1 0 0 0 5 YH M(SP), SP SP+1 operation YL 1 1 1 1 1 1 0 1 1 0 0 1 5 YL M(SP), SP SP+1 instructions F 1 1 1 1 1 1 0 1 1 0 1 0 5 LD B A 9 8 7 6 5 4 3 2 1 0 I D Z C ADD instructions ADC F M(SP), SP SP+1 5 SPH r SPL, r 1 1 1 1 1 1 1 1 0 0 r1 r0 5 SPL r r, SPH 1 1 1 1 1 1 1 0 0 1 r1 r0 5 r SPH 5 r SPL r, i 1 1 0 0 0 0 r1 r0 i3 i2 i1 i0 7 r r+i3~i0 r, q 1 0 1 0 1 0 0 0 r1 r0 q1 q0 7 r r+q r, i 1 1 0 0 0 1 r1 r0 i3 i2 i1 i0 7 r r+i3~i0+C r, q 1 0 1 0 1 0 0 1 r1 r0 q1 q0 7 r r+q+C r r-q SUB r, q 1 0 1 0 1 0 1 0 r1 r0 q1 q0 7 SBC r, i 1 1 0 1 0 1 r1 r0 i3 i2 i1 i0 7 r r-i3~i0-C r, q 1 0 1 0 1 0 1 1 r1 r0 q1 q0 7 r r-q-C r, i 1 1 0 0 1 0 r1 r0 i3 i2 i1 i0 7 r r i3~i0 r, q 1 0 1 0 1 1 0 0 r1 r0 q1 q0 7 r r q r, i 1 1 0 0 1 1 r1 r0 i3 i2 i1 i0 7 r r i3~i0 r, q 1 0 1 0 1 1 0 1 r1 r0 q1 q0 7 r r q r, i 1 1 0 1 0 0 r1 r0 i3 i2 i1 i0 7 r r i3~i0 r, q 1 0 1 0 1 1 1 0 r1 r0 q1 q0 7 r r q r, i 1 1 0 1 1 1 r1 r0 i3 i2 i1 i0 7 r-i3~i0 r, q 1 1 1 1 0 0 0 0 r1 r0 q1 q0 7 r-q r, i 1 1 0 1 1 0 r1 r0 i3 i2 i1 i0 7 r i3~i0 r, q 1 1 1 1 0 0 0 1 r1 r0 q1 q0 7 r q RLC r 1 0 1 0 1 1 1 1 r1 r0 r1 r0 7 d3 d2, d2 d1, d1 d0, d0 C, C d3 RRC r 1 1 1 0 1 0 0 0 1 1 r1 r0 5 d3 C, d2 d3, d1 d2, d0 d1, C d0 INC Mn 1 1 1 1 0 1 1 0 n3 n2 n1 n0 7 M(n3~n0) M(n3~n0)+1 DEC Mn AND OR XOR CP FAN M(n3~n0) M(n3~n0)-1 1 1 1 1 0 1 1 1 n3 n2 n1 n0 7 ACPX MX, r 1 1 1 1 0 0 1 0 1 0 r1 r0 7 M(X) M(X)+r+C, X X+1 ACPY MY, r 1 1 1 1 0 0 1 0 1 1 r1 r0 7 M(Y) M(Y)+r+C, Y Y+1 SCPX MX, r 1 1 1 1 0 0 1 1 1 0 r1 r0 7 M(X) M(X)-r-C, X X+1 SCPY MY, r 1 1 1 1 0 0 1 1 1 1 r1 r0 7 M(Y) M(Y)-r-C, Y Y+1 NOT II-56 Operation SPH, r 1 1 1 1 1 1 1 0 0 0 r1 r0 r, SPL 1 1 1 1 1 1 1 1 0 1 r1 r0 Arithmetic Clock r 1 1 0 1 0 0 r1 r0 1 1 1 1 EPSON 7 r r S1C60N01 TECHNICAL SOFTWARE APPENDIX A: TABLE OF INSTRUCTIONS Abbreviations used in the explanations have the following meanings. Symbols associated with A .............. A register registers and memory B .............. B register X .............. XHL register (low order eight bits of index register IX) Y .............. YHL register (low order eight bits of index register IY) XH ........... XH register (high order four bits of XHL register) XL ............ XL register (low order four bits of XHL register) YH ............ YH register (high order four bits of YHL register) YL ............ YL register (low order four bits of YHL register) XP ............ XP register (high order four bits of index register IX) YP ............ YP register (high order four bits of index register IY) SP ............ Stack pointer SP SPH .......... High-order four bits of stack pointer SP SPL .......... Low-order four bits of stack pointer SP MX, M(X) .. Data memory whose address is specified with index register IX MY, M(Y) ... Data memory whose address is specified with index register IY Mn, M(n) .. Data memory address 000H-00FH (address specified with immediate data n of 00H-0FH) M(SP) ....... Data memory whose address is specified with stack pointer SP r, q ........... Two-bit register code r, q is two-bit immediate data; according to the contents of these bits, they indicate registers A, B, and MX and MY (data memory whose addresses are specified with index registers IX and IY) r S1C60N01 TECHNICAL SOFTWARE q r1 r0 q1 q0 0 0 1 1 0 1 0 1 0 0 1 1 0 1 0 1 EPSON Registers specified A B MX MY II-57 APPENDIX A: TABLE OF INSTRUCTIONS Symbols associated with NBP ..... program counter NPP ..... PCB ..... PCP ..... PCS ..... PCSH .. PCSL ... New bank pointer New page pointer Program counter bank Program counter page Program counter step Four high order bits of PCS Four low order bits of PCS Symbols associated with F ......... Flag register (I, D, Z, C) flags C ......... Carry flag Z ......... Zero flag D ......... Decimal flag I .......... Interrupt flag ............. Flag reset ............. Flag set ......... Flag set or reset Associated with p ......... immediate data s .......... l .......... i .......... Five-bit immediate data or label 00H-1FH Eight-bit immediate data or label 00H-0FFH Eight-bit immediate data 00H-0FFH Four-bit immediate data 00H-0FH Associated with + ......... Add arithmetic and other - .......... Subtract operations ............. Logical AND ............. Logical OR ............ Exclusive-OR ......... Add-subtract instruction for decimal operation when the D flag is set II-58 EPSON S1C60N01 TECHNICAL SOFTWARE APPENDIX B: THE S1C60N01 I/O MEMORY MAP APPENDIX ADDRESS E0 E4 E8 EB ED EF F3 F6 F9 FA FB FC B The S1C60N01 I/O Memory Map DATA D3 K03 R D2 K02 R D1 K01 R D0 K00 R TM3 R TM2 R TM1 R TM0 R EIK03 R/W EIK02 R/W EIK01 R/W EIK00 R/W 0 R EIT2 R/W EIT8 R/W EIT32 R/W 0 R 0 R 0 R IK0 R 0 R IT2 R IT8 R IT32 R 0 0 R R R01 BUZZER R/W R00 FOUT R/W P03 R/W P02 R/W P01 R/W P00 R/W 0 R TMRST W 0 R 0 R HLMOD R/W 0 R 0 R 0 R CSDC R/W 0 R 0 R 0 R 0 R 0 R 0 R IOC R/W XBZR R/W 0 R XFOUT1 R/W XFOUT0 R/W FD S1C60N01 TECHNICAL SOFTWARE NAME K03 K02 K01 K00 TM3 TM2 TM1 TM0 EIK03 EIK02 EIK01 EIK00 0 EIT2 EIT8 EIT32 0 0 0 IK0 0 IT2 IT8 IT32 0 0 R01 BUZZER R00 FOUT P03 P02 P01 P00 0 TMRST 0 0 HLMOD 0 0 0 CSDC 0 0 0 0 0 0 IOC XBZR 0 XFOUT1 XFOUT0 SR - - - - - - - - 0 0 0 0 - 0 0 0 - - - 0 - 0 0 0 - - 0 0 0 0 - - - - - RESET - - 0 - - - 0 - - - - - - 0 0 - 0 0 1 HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH ENABLE ENABLE ENABLE ENABLE - ENABLE ENABLE ENABLE - - - YES - YES YES YES - - HIGH ON HIGH ON HIGH HIGH HIGH HIGH - RESET - - HEAVY - - - STATIC - - - - - - OUT 2 kHz - HIGH HIGH EPSON 0 LOW LOW LOW LOW LOW LOW LOW LOW MASK MASK MASK MASK - MASK MASK MASK - - - NO - NO NO NO - - LOW OFF LOW OFF LOW LOW LOW LOW - - - - NORMAL - - - DYNAMIC - - - - - - IN 4 kHz - LOW LOW COMMENT INPORT DATA K03 INPORT DATA K02 INPORT DATA K01 INPORT DATA K00 CLOCK TIMER DATA 2 Hz CLOCK TIMER DATA 4 Hz CLOCK TIMER DATA 8 Hz CLOCK TIMER DATA 16 Hz K03 INTERRUPT MASK REGISTER K02 INTERRUPT MASK REGISTER K01 INTERRUPT MASK REGISTER K00 INTERRUPT MASK REGISTER TIMER INTERRUPT MASK REGISTER 2 Hz TIMER INTERRUPT MASK REGISTER 8 Hz TIMER INTERRUPT MASK REGISTER 32 Hz K00-K03 INTERRUPT FACTOR FLAG TIMER INTERRUPT FACTOR FLAG 2 Hz TIMER INTERRUPT FACTOR FLAG 8 Hz TIMER INTERRUPT FACTOR FLAG 32 Hz R01 OUTPUT PORT DATA BUZZER ON/OFF CONTROL REGISTER R00 OUTPUT PORT DATA FREQUENCY OUTPUT ON/OFF CONTROL REGISTER P03 I/O PORT DATA P02 I/O PORT DATA P01 I/O PORT DATA P00 I/O PORT DATA TIMER RESET HEAVY LOAD PROTECTION MODE LCD DRIVER CONTROL REG. I/O IN-OUT CONTROL REG. BUZZER FREQUENCY CONTROL FOUT FREQUENCY CONTROL: XFOUT1(0), XFOUT0(0) -> F1 XFOUT1(0), XFOUT0(1) -> F2 XFOUT1(1), XFOUT0(0) -> F3 XFOUT1(1), XFOUT0(1) -> F4 II-59 APPENDIX C: TABLE OF THE ICE COMMANDS APPENDIX Item No. Function 1 2 3 Assemble Disassemble Dump 4 Fill 5 Set Run Mode 6 Trace 7 Break C Table of the ICE Commands Command Format #A,a #L,a1,a2 #DP,a1,a2 #DD,a1,a2 #FP,a1,a2,d #FD,a1,a2,d #G,a #TIM #OTF #T,a,n #U,a,n #BA,a #BAR,a #BD #BDR #BR #BRR #BM #BMR 8 Move #BRES #BC #BE #BSYN #BT #BRKSEL,REM #MP,a1,a2,a3 #MD,a1,a2,a3 9 Data Set 10 Change CPU Internal Registers II-60 #SP,a #SD,a #DR #SR #I #DXY #SXY Outline of Operation Assemble command mnemonic code and store at address "a" Contents of addresses a1 to a2 are disassembled and displayed Contents of program area a1 to a2 are displayed Content of data area a1 to a2 are displayed Data d is set in addresses a1 to a2 (program area) Data d is set in addresses a1 to a2 (data area) Program is executed from the "a" address Execution time and step counter selection On-the-fly display selection Executes program while displaying results of step instruction from "a" address Displays only the final step of #T,a,n Sets Break at program address "a" Breakpoint is canceled Break condition is set for data RAM Breakpoint is canceled Break condition is set for Evaluation Board CPU internal registers Breakpoint is canceled Combined break conditions set for program data RAM address and registers Cancel combined break conditions for program data ROM address and registers All break conditions canceled Break condition displayed Enter break enable mode Enter break disable mode Set break stop/trace modes Set BA condition clear/remain modes Contents of program area addresses a1 to a2 are moved to addresses a3 and after Contents of data area addresses a1 to a2 are moved to addresses a3 and after Data from program area address "a" are written to memory Data from data area address "a" are written to memory Display Evaluation Board CPU internal registers Set Evaluation Board CPU internal registers Reset Evaluation Board CPU Display X, Y, MX and MY Set data for X and Y display and MX, MY EPSON S1C60N01 TECHNICAL SOFTWARE APPENDIX C: TABLE OF THE ICE COMMANDS Item No. 11 Function History Command Format #HSW,a #HSR,a #RF,file #RFD,file #VF,file #VFD,file #WF,file #WFD,file #CL,file #CS,file #CVD #CVR #RP #VP #ROM #Q Display history data for pointer 1 and pointer 2 Display upstream history data Display 21 line history data Display history pointer Set history pointer Sets up the history information acquisition before (S), before/after (C) and after (E) Sets up the history information acquisition from program area a1 to a2 Sets up the prohibition of the history information acquisition from program area a1 to a2 Indicates history acquisition program area Retrieves and indicates the history information which executed a program address "a" Retrieves and indicates the history information which wrote or read the data area address "a" Move program file to memory Move data file to memory Compare program file and contents of memory Compare data file and contents of memory Save contents of memory to program file Save contents of memory to data file Load ICE set condition from file Save ICE set condition to file Indicates coverage information Clears coverage information Move contents of ROM to program memory Compare contents of ROM with contents of program memory Set ROM type Terminate ICE and return to operating system control #HELP Display ICE instruction #CHK Report results of ICE self diagnostic test #H,p1,p2 #HB #HG #HP #HPS,a #HC,S/C/E #HA,a1,a2 #HAR,a1,a2 #HAD #HS,a 12 File 13 Coverage 14 ROM Access 15 Terminate ICE Command Display Self Diagnosis 16 17 Outline of Operation means press the RETURN key. S1C60N01 TECHNICAL SOFTWARE EPSON II-61 APPENDIX D: CROSS-ASSEMBLER PSEUDO-INSTRUCTION LIST APPENDIX D Item No. Pseudo-instruction 1 EQU Cross-assembler Pseudo-instruction List Meaning Example of Use To allocate data to label (Equation) 2 ORG ABC EQU 9 BCD EQU ABC+1 ORG 100H ORG 256 To define location counter (Origin) 3 4 SET To allocate data to label ABC SET 0001H (Set) (data can be changed) ABC SET 0002H DW To define ROM data ABC DW 'AB' BCD DW 0FFBH PAGE 1H PAGE 3 (Define Word) 5 PAGE To define boundary of page (Page) 6 SECTION To define boundary of section SECTION To terminate assembly END (Section) 7 END (End) 8 MACRO To define macro (Macro) 9 10 CHECK MACRO DATA LOCAL To make local specification of label LOCAL LOOP (Local) during macro definition LOOP CP MX,DATA JP NZ,LOOP ENDM To end macro definition ENDM (End Macro) CHECK II-62 EPSON 1 S1C60N01 TECHNICAL SOFTWARE International Sales Operations AMERICA ASIA EPSON ELECTRONICS AMERICA, INC. EPSON (CHINA) CO., LTD. - HEADQUARTERS - 28F, Beijing Silver Tower 2# North RD DongSanHuan ChaoYang District, Beijing, CHINA Phone: 64106655 Fax: 64107319 1960 E. Grand Avenue EI Segundo, CA 90245, U.S.A. Phone: +1-310-955-5300 Fax: +1-310-955-5400 SHANGHAI BRANCH 4F, Bldg., 27, No. 69, Gui Jing Road Caohejing, Shanghai, CHINA Phone: 21-6485-5552 Fax: 21-6485-0775 - SALES OFFICES West 150 River Oaks Parkway San Jose, CA 95134, U.S.A. Phone: +1-408-922-0200 Fax: +1-408-922-0238 Central 101 Virginia Street, Suite 290 Crystal Lake, IL 60014, U.S.A. Phone: +1-815-455-7630 Fax: +1-815-455-7633 Northeast 301 Edgewater Place, Suite 120 Wakefield, MA 01880, U.S.A. Phone: +1-781-246-3600 Fax: +1-781-246-5443 EPSON HONG KONG LTD. 20/F., Harbour Centre, 25 Harbour Road Wanchai, Hong Kong Phone: +852-2585-4600 Fax: +852-2827-4346 Telex: 65542 EPSCO HX EPSON TAIWAN TECHNOLOGY & TRADING LTD. 10F, No. 287, Nanking East Road, Sec. 3 Taipei Phone: 02-2717-7360 Fax: 02-2712-9164 Telex: 24444 EPSONTB HSINCHU OFFICE Southeast 3010 Royal Blvd. South, Suite 170 Alpharetta, GA 30005, U.S.A. Phone: +1-877-EEA-0020 Fax: +1-770-777-2637 13F-3, No. 295, Kuang-Fu Road, Sec. 2 HsinChu 300 Phone: 03-573-9900 Fax: 03-573-9169 EPSON SINGAPORE PTE., LTD. No. 1 Temasek Avenue, #36-00 Millenia Tower, SINGAPORE 039192 Phone: +65-337-7911 Fax: +65-334-2716 EUROPE EPSON EUROPE ELECTRONICS GmbH SEIKO EPSON CORPORATION KOREA OFFICE - HEADQUARTERS Riesstrasse 15 80992 Munich, GERMANY Phone: +49-(0)89-14005-0 Fax: +49-(0)89-14005-110 SALES OFFICE Altstadtstrasse 176 51379 Leverkusen, GERMANY Phone: +49-(0)2171-5045-0 Fax: +49-(0)2171-5045-10 UK BRANCH OFFICE Unit 2.4, Doncastle House, Doncastle Road Bracknell, Berkshire RG12 8PE, ENGLAND Phone: +44-(0)1344-381700 Fax: +44-(0)1344-381701 50F, KLI 63 Bldg., 60 Yoido-dong Youngdeungpo-Ku, Seoul, 150-763, KOREA Phone: 02-784-6027 Fax: 02-767-3677 SEIKO EPSON CORPORATION ELECTRONIC DEVICES MARKETING DIVISION Electronic Device Marketing Department IC Marketing & Engineering Group 421-8, Hino, Hino-shi, Tokyo 191-8501, JAPAN Phone: +81-(0)42-587-5816 Fax: +81-(0)42-587-5624 ED International Marketing Department Europe & U.S.A. FRENCH BRANCH OFFICE 1 Avenue de l' Atlantique, LP 915 Les Conquerants Z.A. de Courtaboeuf 2, F-91976 Les Ulis Cedex, FRANCE Phone: +33-(0)1-64862350 Fax: +33-(0)1-64862355 BARCELONA BRANCH OFFICE Barcelona Design Center Edificio Prima Sant Cugat Avda. Alcalde Barrils num. 64-68 E-08190 Sant Cugat del Valles, SPAIN Phone: +34-93-544-2490 Fax: +34-93-544-2491 421-8, Hino, Hino-shi, Tokyo 191-8501, JAPAN Phone: +81-(0)42-587-5812 Fax: +81-(0)42-587-5564 ED International Marketing Department Asia 421-8, Hino, Hino-shi, Tokyo 191-8501, JAPAN Phone: +81-(0)42-587-5814 Fax: +81-(0)42-587-5110 In pursuit of "Saving" Technology, Epson electronic devices. Our lineup of semiconductors, liquid crystal displays and quartz devices assists in creating the products of our customers' dreams. Epson IS energy savings. S1C60N01 Technical Manual ELECTRONIC DEVICES MARKETING DIVISION EPSON Electronic Devices Website http://www.epson.co.jp/device/ First issue February, 1997 Printed March, 2001 in Japan M A