ADL5335 Data Sheet
Rev. 0 | Page 8 of 16
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
12
11
10
1
3
49
2
6
5
7
8
16
15
14
13
VPOS1
RFIN–
RFIN+
VPOS2
FA
VPOS3
SDIO
SCLK
CS
ENBL
RFOUT
GND5
GND1
GND2
GND3
GND4
ADL5335
TOP VIEW
(Not to Scale)
NOTES
1. EXPOSED PAD. CONNECT THE EXPOSED PAD TO
A GROUND PLANE WITH A LOW THERMAL AND
ELECTRICAL IMPEDANCE.
16304-003
Figure 3. Pin Configuration
Table 5. Pin Function Descriptions
Pin No. Mnemonic Description
1, 4, 13 VPOS1, VPOS2,
VPOS3
Power Supplies. Separately decouple each power supply pin using 100 pF and 0.1μF capacitors.
2, 3 RFIN−, RFIN+ RF Negative and Positive Inputs. These pins have a 50 Ω differential input pair and are internally ac-
coupled.
5 to 9 GND1, GND2, GND3,
GND4, GND5
Ground. Connect these ground pins to a low impedance ground plane.
10 RFOUT RF Output. This pin has a 50 Ω single-ended output and is internally ac-coupled.
11 ENBL Enable. A logic high on this pin (1.8 V logic) enables operation and a logic low on this pin puts the
device in a low power sleep mode.
12 FA Fast Attack. A logic high on this pin (1.8 V logic) decreases the programmed gain by an additional 2 dB,
4 dB, 8 dB, or 16 dB. The fast attack attenuation step is defined by the last two bits of an 8-bit
programming byte that is written to the device via the SPI. When FA returns to a logic low, the gain
returns to its normal programmed level. When not using the fast attack function, tie the FA pin to
ground.
14 SDIO Serial Data Input/Output (SDIO), 1.8 V Logic. The gain and fast attack attenuation levels are programmed
using eight bits (Register Address 0x100). The 24-bit write consists of an R/W bit, a 15-bit register
address, and the eight bits of data. The first six bits of data set the gain and the last two bits set the fast
attack attenuation (−2 dB, −4 dB, −8 dB, or −16 dB).
15 SCLK Serial Clock (SCLK), 1.8 V Logic. The gain and fast attack attenuation levels are programmed using eight
bits (Register Address 0x100). The 24-bit write consists of an R/W bit, a 15-bit register address, and the
eight bits of data. The first six bits of data set the gain and the last two bits set the fast attack
attenuation (−2 dB, −4 dB, −8 dB, or −16 dB).
16 CS Chip Select Bar (CS), 1.8 V Logic. The gain and fast attack attenuation levels are programmed using
eight bits (Register Address 0x100). The 24-bit write consists of an R/W bit, a 15-bit register address,
and the eight bits of data. The first six bits of data set the gain and the last two bits set the fast attack
attenuation (−2 dB, −4 dB, −8 dB, or −16 dB).
EP Exposed Pad. Connect the exposed pad to a ground plane with a low thermal and electrical
impedance.