1
REV 0.0 (Prelimin ary)
08/2002 © NANYA TECHNOLOGY CORP.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
NT5DU4M32EF
4Mx32 Double Data Rate SDRAM
128Mbit DDR SDRAM
1M x 32Bit x 4 Banks
Double Data Rate Synchronous RAM
With Bi-directional Data Strobe and DLL
(144-Ball FBGA)
Nanya Technology Corp.
Nanya Technology Corp.
NTC reserves the right to change products or specification without notice.
2
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NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
NT5DU4M32EF
4Mx32 Double Data Rate SDRAM
TABLE OF CONTENTS
Timing - 32
Basic Timing(@BL=2, CL=3) - 32
Multi Bank Interleaving Read(@BL=4,CL=3) - 33
Multi Bank Interleaving Write(@BL= 4,CL=3) - 34
Auto Precharge after Read Burst(@BL=8) - 35
Auto Precharge after Write Burst(@BL=4) - 36
Normal Write Burst(@BL=4) - 37
Write Interrupt by Precharge & DM(@BL=8) - 38
Read Interrupt by Precharge(@BL=8) - 39
Read Interrupt by Burst Stop & Write(@BL=8,CL=3) - 40
Read Interrupt by Read(@BL=8,CL=3) - 41
DM Function only for Write(@BL=8) - 42
Power up Sequence & Auto Refresh(CBR) - 43
Mode Register Set - 44
I/V Characteristics for Input and Output Buffer - 45
Reduced Output Driver Characteristics - 45
Impedance Match Output Driver Characteristics - 47
Package Dimension(FBGA) - 48
Table of Contents - 2
Memory Part Numbering - 3
General Description & Device Features - 4
Pin Configuration & Pin Description - 5
Input/Output Functional Description - 6
Functional Block Diagram - 7
Simplified State Diagram - 8
Functional Description - 9
Power up Sequence - 9
Mode Register Set(MRS) - 10
Extended Mode Register Set - 11
Burst Mode Operation - 12
Burst Length & Sequence - 12
Bank Activation Command - 12
Burst Read Operation - 13
Burst Write Operation - 13
Burst Interruption - 14
Read Interrupt by Read - 14
Read Interrupt by Burst Stop & Write - 14
Read Interrupt by Precharge - 15
Write Interrupt by Write - 15
Write Interrupt by Read & DM - 16
Write Interrupt by Precharge & DM - 17
Burst Stop Command - 18
DM Function - 18
Auto Precharge Operation - 19
Read with Auto Precharge - 19
Write with Auto Precharge - 20
Precharge Command - 20
Auto Refresh - 21
Self Refresh - 21
Power Down Mode - 22
Absolute Maximum Ratings - 23
Power & DC Operating Conditions - 23
DC Characteristics - 24
AC Input Operating Conditions - 24
AC Operating Test Conditions - 25
Capacitance - 25
Decoupling Capacitance Guide Line - 25
AC Characteristics(I) - 26
AC Characteristics(II) - 27
Simplified Truth Table - 28
Functional Truth Table - 29
Functional Truth Table for CKE - 31
3
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08/2002 © NANYA TECHNOLOGY CORP.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
NT5DU4M32EF
4Mx32 Double Data Rate SDRAM
1M x32Bit x4Banks Double Data Rate Synchronous RAM with Bi-directional Data Strobe and DLL
GENERAL DESCRIPTION
For 1M x 32Bit x 4 Bank DDR SDRAM
The NT5DU4M32EF is 134,217,728 bits of double data rate synchronous dynamic RAM organized as 4 x 1,048,576 bits by 32 I/Os.
Synchronous features with Data Strobe allow extremely high performance up to 2.4GB/s/chip. I/O transactions are possible on both
edges of the clock. Range of operating frequencies, programmable burst length and programmable latencies allow the device to be
useful for a variet y of hig h p erf ormanc e memory system ap plicatio ns.
FEATURES
• VDD = 1.8V±5% , VDDQ = 1.8V±5%
• SSTL_18 compatible inputs/outputs
• 4 banks operation
• MRS cycle with address key programs
-. Read latency 3, 4 (clock)
-. Burst length (2, 4, 8 and Full page)
-. Burst type (sequential & interleave)
• Full page burst length for sequential burst type only
• Start address of the full page burst should be even
• All inputs except data & DM are sampled at the rising
edge of the system clock
• Differential clock input(CK & /CK)
• Data I/O transaction on both edges of Data strobe
• 4 DQS (1 DQS/Byte)
• DLL aligns DQ and DQS transaction with Clock
transaction
• Edge aligned data & data strobe output
• Center aligned data & data strobe input
• DM for write masking only
• Auto & self refresh
• 32ms refresh period (4K cycle)
• 144-Ball FBGA package
• Maximum clock frequency up to 300MHz
• Maximum data rate up to 600Mbps/pin
ORDERING INFORMATION
Part NO.
NT5DU4M32EF-33
NT5DU4M32EF-4
NT5DU4M32EF-5
Max Freq.
300MHz
250MHz
200MHz
Max Data Rate
600Mbps/pin
500Mbps/pin
400Mbps/pin
Interface Package
SSTL_18 144-Ball FBGA
NT5DU4M32EF-6 166MHz 332Mbps/pin
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NT5DU4M32EF
4Mx32 Double Data Rate SDRAM
PIN CONFIGURATION (Top View)
DQS0 DM0 VSSQ DQ3 DQ2 DQ0 DQ31 DQ29 DQ28 VSSQ DM3 DQS3
VSS
Thermal
VSS
Thermal VSS
Thermal VSS
Thermal
VSS
Thermal
VSS
Thermal VSS
Thermal VSS
Thermal
VSS
Thermal
VSS
Thermal VSS
Thermal VSS
Thermal
VSS
Thermal
VSS
Thermal VSS
Thermal VSS
Thermal
DQ4 VDDQ NC VDDQ DQ1 VDDQ VDDQ DQ30 VDDQ NC VDDQ DQ27
DQ6 DQ5 VSSQ VSSQ VSSQ VDD VDD VSSQ VSSQ VSSQ DQ26 DQ25
DQ7 VDDQ VDD VSS VSSQ VSS VSS VSSQ VSS VDD VDDQ DQ24
DQ17 DQ16 VDDQ VSSQ
DQ19 DQ18 VDDQ VSSQ
DQS2 DM2 NC VSSQ
DQ21 DQ20 VDDQ VSSQ
VSSQ VDDQ DQ15 DQ14
VSSQ VDDQ DQ13 DQ12
VSSQ NC DM1 DQS1
VSSQ VDDQ DQ11 DQ10
DQ22 DQ23 VDDQ VSSQ VSS VSS VSS VSS VSSQ VDDQ DQ9 DQ8
/CAS /WE VDD VSS A10 VDD VDD RFU1 VSS VDD NC NC
/RAS NC NC BA1 A2 A11 A9 A5 RFU2 CK /CK MCL
/CS NC BA0 A0 A1 A3 A4 A6 A7 A8/AP CKE VREF
1 2 3 4 5 6 7 8 9 10 11 12
A
B
C
D
E
F
G
H
J
K
L
M
NOTE :
1. RFU1 is reserved for A12
2. RFU2 is reserved for BA2
3. VSS Thermal balls are optional
PIN Description
Bank Select Address
Address Inp ut
Data Input/Output
Power
Ground
Power for DQ’s
Ground for DQ’s
Must Connect Low
BA0, BA1
A0 ~ A11
DQ0 ~ DQ31
VDD
VSS
VDDQ
VSSQ
MCL
Differential Clock Input
Clock Enable
Chip Select
Row Address Strobe
Column Address Stro b e
Write Enable
Data Strobe
Data Mask
Reserved for Future Use
CK, /CK
CKE
/CS
/RAS
/CAS
/WE
DQS
DM
RFU
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NT5DU4M32EF
4Mx32 Double Data Rate SDRAM
INPUT/OUTPUT FUNCTIONAL DESCRIPTION
This pin is recommended to be left “No Connection” on the device
No Connec tion/
Reserved for future use
NC/RFU
Must Connect LowMust Connect Low
MCL
Reference voltage for inputs, used for SSTL interface.Power SupplyVREF
Isolated power supply and ground for the output buffers to provide improved
noise immunity.
Power SupplyVDDQ,VSSQ
Power and ground for the input buffers and core logic.Power SupplyVDD,VSS
Row,Column addresses are multiplexed on the same pin. Row address : RA0~ RA11,
Column address : CA0~ CA7. Column address CA8 is used for auto precharge.
InputA0~ A11
Select which bank is to be active.InputBA0, BA1
Data inputs and outputs are multiplexed on the same pins.Input,OutputDQ0~ DQ31
Data-In mask. Data-In is masked by DM Latency=0 when DM is high in burst write. DM0for DQ0~ DQ7,
DM1for DQ8~ DQ15, DM2for DQ16 ~DQ23, DM3for DQ24 ~ DQ31.
InputDM0~ DM3
Data inputs and outputs are synchronized with both edge of DQS.
DQS0for DQ0~DQ7, DQS1for DQ8~DQ15, DQS2for DQ16~DQ23, DQS3for DQ24~DQ31
Input,OutputDQS0~DQS3
Enables write operation and row precharge.
Latches data in starting from /CAS, /WE active.
Input
/WE
Latches Column addresses on the positive going edge of the CK with /CAS
low. Enables column access.
Input
/CAS
Latches row addresses on the positive going edge of the CK with /RAS low.
Enables row access & precharge.
Input
/RAS
/CS enables(registered Low) and disables(registered High) the command decoder. When /CS is
registered High,new commands are ignored but previous operations are continued.
Input
/CS
CKE high activates and CKE low deactivates the internal clock,input buffers and output drivers. By
deactivating the clock, CK E low indicates the Power down mode or Self refresh mode.
The differential system clock inputs.
All of the input are sampled on the rising edge of the clock except DQ’s and
DM’s that are sampled on both edges of the DQS.
Function
Input
Input
Type
CKE
CK, /CK#
Symbol
#: The timing reference point for the differential clocking is the cross point of CK and /CK.
For any applications using the single ended clocking, apply VREF to /CK pin.
6
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NT5DU4M32EF
4Mx32 Double Data Rate SDRAM
FUNCTIONAL BLOCK DIAGRAM (1Mbit x 32 I/O x 4 B an k)
Sense AMP
Column Decoder
Latency & Burst Length
2-bit prefetch
Output Buffer
Row Decoder Column Buffer
Refresh Counter
Row Buffer
Address Registe r
64
LRAS
LCBR
LCKE
LRAS LCBR LWE LCAS
•
64 32
I/O Control
CK,/CK
ADDR
DQi
32
Input Buffer
LWE
CK, /CK Data Input Register
Serial to parallel LDMi
Bank Select
1M x 32
1M x 32 x32
1M x 32
1M x 32
St
Gen.
robe
Data Strobe
(DQS0~DQS3)
Programming Register DLL
LDMi
LWCBR CK,/CK
Timing Register
CK,/CK CKE /CS /RAS /CAS /WE DMi
7
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NT5DU4M32EF
4Mx32 Double Data Rate SDRAM
SIMPLIFIED STATE DIAGRAM
SELF
REFRESH
AUTO
REFRESH
CKEL
CKEH
REFA
REFS
REFSX
IDLE
ROW
ACTIVE
POWER
DOWN
READ AWRITE A
PRE
PRE
BST
PRE
PRE
WRITE
WRITEA READA
READ
WRITEA READA
READA
READ
WRITE
WRITEA
MODE
REGISTER
SET
MRS
ACT
POWER
DOWN
CKEL
CKEH
WRITE READ
PRE-
CHARGE
POWER
ON
POWER
APPLIED
Automatic Sequence
Command Sequence
WRITEA : Write with Autoprecharge
READA : Read with Autoprecharge
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NT5DU4M32EF
4Mx32 Double Data Rate SDRAM
FUNCTIONAL DESCRIPTION
Power-Up Sequence
DDR SDRAMs must be powered up and initialized in a predefined manner to prevent undefined operations.
1. Apply power and keep CKE at low state (All other inputs may be undefined)
- Apply VDD before or at the same time as VDDQ.
- Apply VDDQ before or at the same time as VREF & VTT
2. Start clock and maintain stable condition for minimum 200µs
3. The minimum of 200µs after stable power and clock (CK,/CK), apply NOP and CKE to be high.
4. Issue precharge command for all banks of the device.
5. Issue a EMRS command to enable DLL
*1 6. Issue a MRS command to reset DLL. The additional 200 clock cycles are required to lock the DLL.
*1,2 7. Issue precharge command for all banks of the device.
8. Issue at least 2 or more auto-refresh commands.
9. Issue a mode register set command with A8 to low to initialize the mode register.
*1 Every “DLL Enable” command resets DLL. Therefore sequence 6 can be skipped during power-up.
Instead of it, the additional 200cycles of clock input is required to lock the DLL after enabling DLL.
*2 Sequence of 6 & 7 is regardless of the order.
Power-Up & Initialization Sequence
/CK
CK
tRP 2Clock
min. 2Clock
min. tRP tRFC tRFC 2Clock
min.
Precharge
ALL Banks EMRS MRS
DLL Reset Precharge
ALL Banks 1st Auto
Refresh 2nd Auto
Refresh Mode
Register Set Any
Command
200 Clock min.
Command
Input must be
stable for 200us
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NT5DU4M32EF
4Mx32 Double Data Rate SDRAM
Mode Register Set (MRS)
The mode re gister stores the data for controlling the vario us operating modes o f DDR SDRAM. It programs /CAS late ncy, address
mode, burst length, test mode, DLL reset and various vendor specific option to make DDR SDRAM useful for variety of different
applications. The default value of the mode register is not defined, therefore the mode register must be written after EMRS setting for
proper operation. The mode register is written by asserting low on /CS, /RAS, /CAS and WE (The DDR SDRAM should be in active
mode with CKE already high prior to writing into the mode register). The state of address pins A0~ A11 and BA0,BA1in the same cycle
as /CS, /RAS, /CAS and /WE going low is written in the mode register. Minimum two clock cycles are requested to complete the write
operation in the mode register. The mode register contents can be changed using the same command and clock cycle requirements
during operation as long as all banks are in the idle state. The mode register is divided into various fields depending on functionality.
The burst length uses A0~A2, address mode uses A3, /CAS latency(read latency from column address) uses A4 ~ A6. A7is used for test
mode. A8is used for DLL for DLL reset. A7, A8, BA0, and BA1must be set to low for normal MRS operation. Refer to the table for
specific codes for various burst length, address modes and /CAS latencies.
BA1BA0A11 A10 A9A8A7A6A5A4A3A2A1A0Address Bus
RFU 0DLL TM BTRFU /CAS Latency Burst Length Mode
Register
DLL ResetA8ModeA7
TypeA3
Burst Type
Test ModeDLL
No0Normal0
Yes1Test1
Sequential0
Interleave1
ModeBA0
MRS0
EMRS1
LatencyA4
Reserved0
Reserved1
A5
0
0
A6
0
0
20
31
1
1
0
0
40
Reserved1
0
0
1
1
Reserved0
Reserved1
1
1
1
1
Interleave
Reserve
2
4
8
Reserve
Reserve
Reserve
Reserve
Sequential
Reserve
2
4
8
Reserve
Reserve
Reserve
Full page
0
1
0
0
0
0
0
1
1
1
0
0
0
1
0
0
1
1
0
1
1
1
1
1
Burst Type
A0A1A2
Burst Length
/CAS Latency
* RFU(Reserved for future use)
should stay “0” during MRS cycle.
012345678
NOP Precharge
All Banks NOP NOP MRS * 1NOP Any
Command NOP NOP
tRP *2tMRD =2 tCK
MRS Cycle
/CK
CK
Command
* 1 : MRS can be issued only at all banks precharge state.
* 2 : Minimum tRP is required to issue MRS command.
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NT5DU4M32EF
4Mx32 Double Data Rate SDRAM
Extended Mode Register Set (EMRS)
The extended mode register stores the data for enabling or disabling DLL and selecting output driver strength. The default valueof
the extended mode register is not defined, therefore the extended mode register must be written after power up for enabling or
disabling DLL. The extended mode register is written by asserting low on /CS, /RAS, /CAS, /WE and high on BA0 (The DDR SDRAM
should be in all bank precharge with CKE already high prior to writing into the extended mode register). The state of address pins
A0,A2~A5, A7~A11 and BA1 in the same cycle as /CS,/RAS,/CAS and /WE going low are written in the extended mode register. A1and
A6are used for setting driver strength to weak or matched impedance. Two clock cycles are required to complete the write operation
in the extended mode register. The mode register contents can be changed using the same command and clock cycle requirements
during operation as long as all banks are in the idle state A0is used for DLL enable or disable.“High”on BA0is used for EMRS. All the
other address pins except A0,A1, A6and BA0must be set to low for proper EMRS operation. Refer to the table for specific codes.
Address Bus
BA1BA0A11 A10 A9A8A7A6A5A4A3A2A1A0
RFU 1RFU Extended
Mode Register
ModeBA0
MRS0
EMRS1
• RFU(Reserved for Future Use) should stay “0” during MRS cycle.
DIC RFU DIC DLL
Output Driver Imp e dance ControlA6
60% of full drive strength
A1A0DLL Enable
0
30% of full drive strength1
Enable0
Disable1
1Weak
1Matched impedance
DLL DISABLE MODE
/CK
CK
tRP 2Clock
min. 2Clock
min.
Precharge
ALL Banks EMRS MRS*1 CMD MRS Active Read*2
200 Clock min.
Command
Enter DLL
Disable
Mode
2Clock
min.
EMRS
2Clock
min.
DLL Disable
Mode tRP
Precharge
ALL Banks
Exit DLL
Disable
Mode
MRS
DLL RESET
2Clock
min.
CL=2 Only,
BL=FREE
Notes:
- DLL disable mode is operating mode for low operating frequency between 66MHz and 100MHz without DLL.
- This DLL disable mode is useful for power saving.
- All banks precharge or a bank precharge command can omit before entering and exiting DLL disable mode.
*1 : CL=2 only and BL can set any burst length at DLL disable mode.
*2 :A write command can be applied as far as tRCD is satisfied after any bank active command.
And it needs an additional 200 clock cycles for read operation after exiting DLL disable mode.
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NT5DU4M32EF
4Mx32 Double Data Rate SDRAM
Burst Mode Operation
Burst mode operation is used to provide a constant flow of data to memory location (write cycle), or from memory location (read
cycle). There are two parameters that define how the burst mode operates. These parameters including burst sequence and burst
length are programmable and determined by address A0~ A3 during the Mode Register Set command. The burst type is used to
define the sequence in which the burst data will be delivered or stored to the DDR SDRAM. Two types of burst sequences are
supported, sequential and interleaved. See the below table. The burst length controls the number of bits that will be output after a
read command, or the number of bits to be input after a write command. The burst length can be programmed to have values of 2,4,8
or full page. For the full page operation, the starting address must be an even number and the burst stop at the end of burst.
Burst Length and Sequence
Burst Length
xx0
Starting Address(A2,A1,A0)Sequential Mode Interleave Mode
xx1
x00
x01
x10
x11
000
001
010
011
100
101
110
111
0-1
1-0
0-1-2-3
1-2-3-0
2-3-0-1
3-0-1-2
0-1-2-3-4-5-6-7
3-4-5-6-7-0-1-2
4-5-6-7-0-1-2-3
5-6-7-0-1-2-3-4
6-7-0-1-2-3-4-5
7-0-1-2-3-4-5-6
0-1
1-0
0-1-2-3
1-0-3-2
2-3-0-1
3-2-1-0
0-1-2-3-4-5-6-7
1-0-3-2-5-4-7-6
2-3-0-1-6-7-4-5
3-2-1-0-7-6-5-4
4-5-6-7-0-1-2-3
5-4-7-6-1-0-3-2
6-7-4-5-2-3-0-1
7-6-5-4-3-2-1-0
2
4
8
1-2-3-4-5-6-7-0
2-3-4-5-6-7-0-1
n = A0-A7, A0= 0 Cn, Cn+1, Cn+2, …, Cn-1 Not supportedFull Page (256)
Bank Activation Command
The Bank Activation command is issued by holding /CAS and /WE high with /CS and /RAS low at the rising edge of the clock. The
DDR SDRAM has four independent Banks, so two Bank Select Addresses(BA0, BA1) are supported. The Bank Activation command
must be applied before any Read or Write operation is executed.The delay from the Bank Activation command to the first read or write
command must meet or exceed the minimum of /RAS to /CAS delay time(tRCDR/tRCDWmin). Once a bank has been activated, it
must be precharged before another Bank Activation command can be applied to the same bank. The minimum time interval between
interleaved Bank Activation commands(Bank A to B and vice versa) is the Bank to Bank delay time (tRRD min).
Bank Activation Command Cycle ( /CAS Latency = 3 )
012 nn+1n+2
Bank A
Row Addr. Bank A
Col. Addr. Bank A
Row Addr. Bank B
Row Addr.
Bank A
Activate NOP NOP READ A
with Auto Bank A
Activate NOP Ba nk B
Activate
/RAS-/CAS delay time(tRCDR f o r READ) /RAS-/RAS delay time(tRRD)
Precharge
Row cycle Time (tRC): Don’t care
/CK
CK
Address
Command
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NT5DU4M32EF
4Mx32 Double Data Rate SDRAM
Burst Read Operation
Burst Read operation in DDR SDRAM is in the same manner as the current SDRAM such that the burst read command is issued
by asserting /CS and /CAS low while holding /RAS and /WE high at the rising edge of the clock after tRCD from the bank activation.
The address inputs (A0~A7) determine the starting address for the Burst. The Mode Register sets type of burst (Sequential or
interleave) and burst length(2,4,8, Full page). The first output data is available after the /CAS Latency from the READ command,
and the consecutive data are presented on the falling and rising edge of Data Strobe adopted by DDR SDRAM until the burst length
is completed.
< Burst Length = 4, /CAS Latency = 3,4 >
012
NOP
/CK
CK
Command
345678
NOP NOP NOP NOP NOP NOP NOPREAD
tRPRE tRPST
DQS
Dout 0 Dout 1 Dout 2 Dout 3
DQ’s
tRPRE tRPST
Dout 0 Dout 1 Dout 2 Dout 3
DQS
DQ’s
/CAS Latency = 3
/CAS Latency = 4
Burst Write Operation
The Burst Write command is issued by having /CS, /CAS and /WE low while holding /RAS high at the rising edge of the clock. The
address inputs determine the starting column address. There is no real write latency required for burst write cycle. The first data for
burst write cycle must be applied at the first rising edge of the data strobe enabled after tDQSS from the rising edge of the clock that
the write command is issued.The remaining data inputs must be supplied on each subsequent falling and rising edge of Data Strobe
until the burst length is completed. When the burst has been finished, any additional data supplied to the DQ pins will be ignored.
< Burst Length = 4 >
012
WRITEA
/CK
CK
Command
345678
NOP WRITEB NOP NOP NOP NOP NOPNOP
tDQSSmax tWPST
DQS
Din a2 Din a3 Din b0 Din b1
DQ’s Din b2 Din b3Din a0 Din a1
tWPREH
tWPRES
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NT5DU4M32EF
4Mx32 Double Data Rate SDRAM
Burst Interruption
Read Interrupted by Read
Burst Read can be interrupted before completion of the burst by new Read command of any bank. When the previous burst is
interrupted, the remaining address are overridden by the new address with the full burst length. The data from the previous Read
command continues to appear on the outputs until the /CAS latency from the interrupting Read command is satisfied. Read to
Read interval is minimum 1 tCK.
< Burst Length = 4, /CAS Latency = 3 >
012
READ B
/CK
CK
Command
345678
NOP NOP NOP NOP NOP NOP NOPREAD A
DQS
Douta0 Douta1 Doutb0 Doutb1
DQ’s Doutb2 Doutb3
/CAS Latency = 3
Read Interrupted by Burst stop & Write
To interrupt Burst Read with a write command, Burst stop command must be asserted to avoid data contention on the I/O bus
by placing the DQ’s(Output drivers) in a high impedance state at least one clock cycle before the Write Command is initiated.
Once the burst stop command has been issued, the minimum delay to a write command is CL(RU). [CL is /CAS Latency and RU
means round up to the nearest integer.]
< Burst Length = 4, /CAS Latency = 3 >
012
Burst
stop
/CK
CK
Command
345678
NOP NOP NOP WRITE NOP NOPREAD
DQS
Dout0 Dout1 Din 0 Din 1
DQ’s Din 2 Din 3
/CAS Latency = 3
tRPRE
Preamble
tWPREH
tDQSS
tWPRES
14
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NT5DU4M32EF
4Mx32 Double Data Rate SDRAM
Read Interrupted by Precharge
Burst Read can be interrupted by precharge of the same bank. The minimum 1 clock cycle is required for the read precharge
interval. Precharge command to output disable latency is equivalent to the /CAS latency.
< Burst Length = 8, /CAS Latency = 3 >
012
Precharge
/CK
CK
Command
345678
NOP NOP NOP NOP NOP NOPREAD
DQS
DQ’s Dout 0 Dout 1 Dout 2 Dout 3 Dout 4 Dout 5
/CAS Latency = 3
1tCK
Dout 6 Dout 7
Interrupted by prechagre
tRPRE tRPST
NOP
Write Interrupted by Write
Burst Write can be interrupted by the new Write Command before completion of the previous burst write, with the onlyrestriction
being that the interval that separates the commands must be at least one clock cycle. When the previous burst is interrupted, the
remaining addresses are overridden by the new addresses and data will be written into the device until the programmed burst
length is satisfied.
< Burst Length = 4 >
012
WRITEA
/CK
CK
Command
345678
WRITEB NOP NOP NOP NOP NOP NOPNOP
DQS
DQ’s Din a0 Din a1 Din b0 Din b1 Din b2 Din b3
/CAS Latency = 3
1tCK
tWPREH
tWPRES
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NT5DU4M32EF
4Mx32 Double Data Rate SDRAM
Write Interrupted by Read & DM
A burst write can be interrupted by a read command of any bank. The DQ’s must be in the high impedance state at least one
clock cycle before the interrupting read data appear on the outputs to avoid data contention. When the read command is
registered, any residual data from the burst write cycle must be masked by DM. The delay from the last data to read command
(tWTR) is required to avoid the data contention DRAM inside. Data that are presented on the DQ pins before the read command is
initiated will actually be written to the memory. Read command interrupting write can not be issued at the next clock edge of the
write command.
< Burst Length = 8 >
WRITE
/CK
CK
Command NOP NOP NOP NOP READ NOP NOP
012345678
DQS
DQ’s Din 0 Din 1 Din 2 Din 3 Din 4 Din 5
/CAS
Latency=3
tDQSSmax
tWPRES
tWTR
Din 6 Din 7
DQS
DQ’s Din 0 Din 1 Din 2 Din 4 Din 5 Din 6 Din 7
DM
Din 3
/CAS
Latency=3
Dout0 Dout1
tDQSSmin
tWPRES
DM tWTR
Dout0 Dout1
NOP
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NT5DU4M32EF
4Mx32 Double Data Rate SDRAM
Write Interrupted by Precharge & DM
A burst Write can be interrupted by a precharge of the same bank before completion of the previous burst. A write recovery
time(tWR) is required from the last data to precharge command. When Precharge command is asserted, any residual data from the
burst write cycle must be masked by DM.
< Burst Length = 8 >
012
WRITE A
/CK
CK
Command
345678
NOP NOP NOP NOP Precharge WRITE B NOPNOP
DQS
DQ’s Din a0 Din a1 Din a2 Din a3 Din a4 Din a5
Max tDQSS
tDQSSmax
tWPREH
tWPRES
tWPREH
tDQSSmax
tWPRES
tWR
Din a6 Din a7 Din a0 Din a1
DM
DQS
DQ’s Din a0 Din a1 Din a2 Din a4 Din a5
Min tDQSS
tDQSSmin
tWPREH
tWPRES
tWPREH
tDQSSmin
tWPRES
Din a6 Din a7 Din b0 Din b1
DM
tWR
Din b2Din a3
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NT5DU4M32EF
4Mx32 Double Data Rate SDRAM
BURST STOP COMMAND
The Burst stop command is initiated by having /RAS and /CAS high with /CS and /WE low at the rising edge of the clock only. The
Burst Stop command has the fewest restrictions making it the easiest method to use when terminating a burst operation beforeit
has been completed. When the Burst Stop command is issued during a burst read cycle, both the data and DQS(Data Strobe) go to a
high impedance state after a delay which is equal to the /CAS Latency set in the Mode Register. The Burst Stop command, however,
is not supported during a write burst operation.
< Burst Length = 4, /CAS Latency = 3,4 >
012
Burst
Stop
/CK
CK
Command
345678
NOP NOP NOP NOP NOP NOP NOPREAD
DQS
DQ’s Dout 0 Dout 1
/CAS Latency = 3
1tCK
The burst ends after a delay equal to the /CAS Latency
Dout 0 Dout 1
DQS
DQ’s
/CAS Latency = 4 The burst ends after a delay equal to the /CAS Latency
DM FUNCTION
The DDR SDRAM has a Data mask function that can be used in conjunction with data Write cycle only, not Read cycle. When the
Data Mask is activated (DM high) during write operation, the write data is masked immediately (DM to Data-mask Latency is Zero).
DM must be issued at the rising edge or the falling edge of Data Strobe instead of a clock edge.
< Burst Length = 8 >
012
NOP
/CK
CK
Command
345678
NOP NOP NOP NOP NOP NOP NOPWRITE
DQS
DQ’s Din 0
tDQSS
tWPREH
tWPRES Din 1 Din 2 Din 3 Din 4 Din 5 Din 6 Din 7
Masked by DM=H
DM
DM
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NT5DU4M32EF
4Mx32 Double Data Rate SDRAM
AUTO-PRECHARGE OPERATION
The Auto precharge command can be issued by having column address A8High when a Read or a Write command is asserted into
the DDR SDRA M. If A8 is low when Read or Write command is issued, normal Read or Write burst operation is asserted and the bank
remains active after the completion of the burst sequence. When the Auto precharge command is activated, the active bank
automatically begins to precharge at the earliest possible moment during read or write cycle after tRAS(min) is satisfied.
Read with Auto Precharge
If a Read with Auto-precharge command is initiated, the DDR SDRAM automatically starts the precharge operation on 2 clock
previous to the end of burst from a Read with Auto-Precharge command when tRAS(min) is satisfied. If not, the start point of
precharge operation will be delayed until tRAS(min) is satisfied. The bank started the Precharge operation once cannot be
reactivated and the new command can not be asserted until the Precharge time(tRP) is satisfied.
< Burst Length = 4, /CAS Latency = 3 >
012
NOP
/CK
CK
Command
345678
NOP READ A
Auto Precharge NOP NOP NOP NOP NOP
BANK A
ACTIVE
DQS
DQ’s Douta0 Douta1
/CAS Latency = 3
* Bank can be reactivated at
completion of tRP
tRCDR(min)
tRAS(min) tRP
Douta2 Douta3
Auto-Pre charge start point
tRC(min)
When the Read with Auto precharge command is issued, new command can be asserted at T5,T6 and T7 respectively as follows.
*1 : AP = Auto Precharge
For same Bank For Different Bank
567567
Asserted
command
READ
READ+AP
Active
Precharge
READ +
No AP*1
READ +
AP
Illegal
Legal
READ +
No AP
READ +
AP
Illegal
Legal
Illegal
Illegal
Illegal
Illegal
Legal
Legal
Legal
Legal
Legal
Legal
Legal
Legal
Legal
Legal
Legal
Legal
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NT5DU4M32EF
4Mx32 Double Data Rate SDRAM
Write with Auto Precharge
If A8is high when Write command is issued, the write with Auto-Precharge function is performed. Any new command to the same
bank should not be issued until the internal precharge is completed. The internal precharge begins after keeping tWR(min).
< Burst Length = 4, /CAS Latency = 3 >
012
WRITE A
Auto Precharge
/CK
CK
Command
345678
NOP NOP NOP NOP NOP NOP NOP
BANK A
ACTIVE
DQS
DQ’s Din a0 Din a1
/CAS Latency = 3 * Bank can be reactivated at
completion of tRP
tWPREH
tWR
Din a2 Din a3
Internal precharge starts
tWPRES
tRP
LegalLegalLegalLegalLegalIllegalIllegalIllegalIllegalIllegalIllegalPrecharge
LegalLegalLegalLegalLegalIllegalIllegalIllegalIllegalIllegalIllegalActive
LegalLegalIllegalIllegalIllegalIllegal
READ +
AP
READ +
AP
READ + AP
+ DM
READ + AP
+ DM
IllegalREAD + AP
LegalLegalIllegalIllegalIllegalIllegal
READ +
No AP
READ +
No AP
READ + No
AP + DM
READ + No
AP + DM *2
IllegalREAD
LegalLegalLegalLegalLegalIllegalIllegalIllegalWRITE+APWRITE + APWRITE + APWRITE + AP
LegalLegalLegalLegalLegalIllegalIllegalIllegal
WRITE + No
AP
WRITE + No
AP
WRITE + No
AP *1
WRITE
65
432765432
For Different BankFor same Bank
Asserted
command
*1 AP = Auto Precharge
*2 DM : Refer to “Write Interrupted by Rean & DM” in page 16.
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NT5DU4M32EF
4Mx32 Double Data Rate SDRAM
PRECHARGE COMMAND
The precharge command is issued when /CS, /RAS, and /WE are low and /CAS is high at the rising edge of the clock, CK. The
precharge command can be used to precharge each bank respectively or all banks simultaneously. The Bank select addresses(BA0,
BA1) are used to define which bank is precharged when the command is initiated. For write cycle, tWR(min.) must be satisfied from
the start of the last burst write cycle until the precharge command can be issued. After tRP from the precharge, an active command to
the same bank can be initiated.
< Bank Selection for Precharge by Bank address bits >
Bank A Only
000
All Banks
XX1
Bank D Only
110
Bank C Only
010
Bank B Only
100
PrechargeBA0BA1A8/AP
AUTO REFRESH
An Auto Refresh command is issued by having /CS, /RAS and /CAS held low with CKE and /WE high at the rising edge of the clock,
CK. All banks must be precharged and idle for a tRP(min) before the Auto Refresh command is applied. The refresh addressing is
generated by the internal refresh address counter. This makes the address bits “Don’t care” during an Auto Refresh command. When
the refresh cycle has completed, all banks will be in the idle state. A delay between the Auto Refresh command and the next Activate
Command or subsequent Auto Refresh Command must be greater than or equal to the tRFC(min).
012
/CK
CK
Command
345678
PRE
tRFC
tRP
91011
Auto
Refresh CMD
CKE=High
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NT5DU4M32EF
4Mx32 Double Data Rate SDRAM
SELF REFRESH
A self refresh command is defined by having /CS, /RAS, /CAS and CKE low with /WE high at the rising edge of the clock (CK). Once
the self refresh command is initiated, CKE must be held low to keep the device in self refresh mode. During the self refresh operation,
all inputs except CKE are ignored. The clock is internally disabled during self refresh operation to reduce power consumption. The
self refresh is exited by supplying stable clock input before returning CKE high, asserting deselect or NOP command and then
asserting CKE high for longer than tXSR for locking of DLL.
/CK
CK
Command Self
Refresh
tXSA *1
tXSR *2
CKE
Active Read
tIS
*1 Exit self refresh to bank active command, a write command can be applied as far as tRCD is satisfied after any bank active command.
*2 Exit self refresh to read command.
POWER DOWN MODE
The power down is entered when CKE Low, and exited when CKE High. Once the power down mode is initiated, all of the receiver
circuits except CK and CKE are gated off to reduce power consumption. The all banks should be in idle state prior to entering the
precharge power down mode and CKE should be set high at least 1tCK+tIS prior to Row active command. During power down mode,
refresh operations can’t be performed, therefore the device cannot remain in power down mode longer than the refresh period(tREF) of
the device.
/CK
CK
Command
01234567891011
CKE
12 13
Precharge
Precharge
power
down
Entry
Precharge
power
down
Exit
Active
power
down
Entry
Active
Active
power
down
Exit Read
NOP NOP
tIS tIS tIS tIS
tPDEX
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NT5DU4M32EF
4Mx32 Double Data Rate SDRAM
ABSOLUTE MAXIMUM RATINGS
Parameter
Voltage on any pin relative to Vss
Voltage on VDD supply relative to Vss
Storage Temperature
Power dissipation
Short circuit current
Symbol
VIN, VOUT
VDD
TSTG
PD
IOS
Value
-0.5 ~ 2.7
-0.5 ~ 2.7
-55 ~ +150
2.0
50
Unit
V
V
°C
W
mA
Voltage on VDDQ supply relative to Vss VDDQ -0.5 ~ 2.7 V
Note :
Permanent device damage may occur if ABSOLUTE MAXIMUM RATING are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
POWER & DC OPERATING CONDITIONS (SSTL_18 In/Out)
Recommended operating conditions (Voltage referenced to Vss=0V, TA=0 to 70°C)
Parameter
Device supply Voltage
Output supply Voltage
Reference Voltage
Termination Voltage
Input logic high Voltage
Symbol
VDD
VDDQ
VREF
Vtt
VIH
Min
1.70
1.70
0.49* VDDQ
VREF -0.04
VREF +0.12
Unit
V
V
V
V
V
Input logic low Voltage VIL -0.30 V
Output logic high Voltage VOH Vtt+0.60 V
Output logic low Voltage VOL - V
Input leakage current IIL -5 uA
Output leakage current IOL -5 uA
Typ
1.80
1.80
-
VREF
-
-
-
-
-
-
Max
1.90
1.90
0.51* VDDQ
VREF +0.04
VDDQ +0.30
VREF -0.12
-
Vtt-0.60
5
5
Note
1
1
2
3
4
5
IOH = -13.4mA
IOL = +13.4mA
6
6
Note :
1. For -33/-36/-40/-45/-50/-55/-60, VDD / VDDQ = 1.8V ±5% / 1.8V ±5%
2. VREF is expected to equal 0.50* VDDQ of the transmitting device and to track variations in the DC level of the same. Peak to peak noise on the VREF
may not exceed ±2% of the DC value. Thus, from 0.50* VDDQ, VREF is allowed ±18mV for DC error and an additional ±18mV for AC noise.
3. Vtt of the transmitting device must track VREF of the receiving device.
4. VIH(max.) = VDDQ +1.5V for a pulse and it which can not be greater than 1/3 of the cycle rate.
5. VIL(mim.) =-1.5V for a pulse width and it can not be greater than 1/3 of the cycle rate.
6. For any pin under test input of 0V ≤VIN ≤VDD is acceptable. For all other pins that are not under test VIN =0V.
23
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NT5DU4M32EF
4Mx32 Double Data Rate SDRAM
DC CHARACTERISTICS
Recommended operating conditions (Voltage referenced to Vss=0V, VDD/VDDQ=1.8V±5%/ 1.8V±5%,, TA=0 to 70°C)
Parameter
Operating current
(One Bank Active)
Symbol
Icc1
Test Condition
Burst Length=2, tRC ≥tRC(min)
IOL=0mA, tCK=tCK(min)
Unit
mA
Precharge Standby Current
in Power-down mode Icc2P CKE ≤VIL(max), tCK=tCK(min) mA
Precharge Standby Current
in Non Power-down mode Icc2N CKE ≥VIH(min), /CS ≥VIH(min),
tCK=tCK(min). mA
Active Standby Current
in Power-down mode Icc3P CKE ≤VIL(max), tCK=tCK(min) mA
Active Standby Current
in Non Power-down mode Icc3N CKE ≥VIH(min), /CS ≥VIH(min),
tCK=tCK(min). mA
Operating Current
(Burst mode) Icc4 IOL=0mA, tCK=tCK(min), Page Burst,
All Banks activated. mA
Refresh current Icc5 tRC ≥tRFC(min) mA
Self Refresh current Icc6 CKE ≤0.2V mA
Note
1
2
TBD TBD TBD TBD TBD
TBD TBD TBD TBD TBD
TBD TBD TBD TBD TBD
TBD
-40 -45 -50 -55 -60
Version
TBD TBD
TBD TBD
TBD TBD
-33 -36
Operating Current
(4Bank Interleaving) Icc7 Burst Length=4, tRC ≥tRC(min)
IOL=0mA, tCK=tCK(min) mATBD TBD TBD TBD TBDTBD TBD
TBD TBD TBD TBD TBDTBD TBD
TBD TBD TBD TBD TBDTBD TBD
TBD TBD TBD TBD TBDTBD TBD
TBD TBD TBD TBD TBDTBD TBD
Notes :
1. Measured with outputs open.
2. Refresh period is 32ms.
AC INPUT OPERATING CONDITIONS
Recommended operating conditions (Voltage referenced to Vss=0V, VDD/VDDQ=1.8V±5%/ 1.8V±5%,, TA=0 to 70°C)
Parameter
Input High (Logic1) Voltage : DQ
Input Low (Logic0) Voltage : DQ
Clock input Differential Voltage ; CK and /CK
Clock input Crossing point Voltage ; CK and /CK
Symbol
VIH
VIL
VID
VIX
Min
VREF+0.31
-
0.7
0.5* VDDQ -0.175
Unit
V
V
V
V
Typ
-
-
-
-
Max
-
VREF -0.31
VDDQ+0.6
0.5* VDDQ +0.175
Note
1
2
Note :
1. VID is the magnitude of the difference between the input level on CK and the input level on /CK
2. The value of VIX is expected to equal 0.5* VDDQ of the transmitting device and must track variation in the DC level of the same
24
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NT5DU4M32EF
4Mx32 Double Data Rate SDRAM
AC OPERATING TEST CONDITIONS
(VDD=1.8V±0.10V, TA=0 to 70°C)
Parameter
Input reference voltage for CK (for signal ended)
Value
0.50* VDDQ
Unit
V
CK and /CK signal maximum peak swing 1.5 V
CK signal minimum slew rate 1.0 V/ns
Input levels (VIH/VIL) VREF+0.31 / VREF-0.31 V
Input timing measurement refrence level VREF V
Output timing measurement refrence level Vtt V
Output load condition See Fig.1
Note
On
O
Output Z0=50Ω
CLOAD=20pF
VREF
=0.5*VDDQ
RT=50Ω
Vtt=0.5*VDDQ
Fig.1) Output Load Circuit
CAPACITANCE (VDD=1.8V, TA=25°C, f=1MHz)
Parameter
Input capacitance (A0~A11, BA0~BA1)
Input capacitance (CKE, /CS, /RAS, /CAS, /WE)
Data & DQS input/output capacitance (DQ0~DQ31)
Input capacitance (DM0 ~ DM3)
Symbol
CIN2
CIN3
COUT
CIN4
Min
2.0
2.0
4.0
4.0
Unit
pF
pF
pF
pF
Max
3.0
3.0
5.0
5.0
Input capacitance(CK, /CK,) CIN1 2.0 pF3.0
DECOUPLING CAPACIT ANCE GUIDE LINE
Recommended decoupling capacitance added to power line at board.
Parameter
Decoupling Capacitance between VDD and VSS
Decoupling Capacitance between VDDQ and VSSQ
Symbol
CDC1
CDC2
Value
0.1+0.01
0.1+0.01
Unit
uF
uF
Note :
1. VDD and VDDQ pins are separated each other.
All VDD pins are connected in chip. All VDDQ pins are connected in chip.
2. VSS and VSSQ pins are separated each other.
All VSS pins are connected in chip. All VSSQ pins are connected in chip.
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NT5DU4M32EF
4Mx32 Double Data Rate SDRAM
AC CHARACTERISTICS (I)
Parameter Symbol -40 Unit Note
Min Max
-45
Min Max
-50
Min Max
-55
Min Max
-60
Min Max
tCK
CK cycle time
4.0
4.0
-
4.5
---ns
ns
CK high level width 0.45 0.45 0.45 0.45 0.45 tCK0.55 0.55 0.55 0.55 0.55tCH
CK low level width 0.45 0.45 0.45 0.45 0.45 tCK0.55 0.55 0.55 0.55 0.55tCL
DQS out access time from CK -0.6 -0.7 -0.7 -0.75 -0.75 ns+0.6 +0.7 +0.7 +0.75 +0.75
tDQSCK
Output access time from CK tAC
Data strobe edge to Dout edge -----ns 1+0.40 +0.45 +0.45 +0.5 +0.5
tDQSQ
Read preamble 0.9 0.9 0.9 0.9 0.9 tCK1.1 1.1 1.1 1.1 1.1
tRPRE
Read postamble 0.4 0.4 0.4 0.4 0.4 tCK0.6 0.6 0.6 0.6 0.6
tRPST
CK to valid DQS-in 0.8 0.8 0.75 0.75 tCK1..2 1..2 1.25 1.25
tDQSS
DQS-in setup time 00000ns-----
tWPRES
DQS-in hold time 0.35 0.30 0.30 0.25 0.25 tCK-----
tWPREH
DQS write postamble tWPST
DQS-in high level width tDQSH
DQS-in low level width tDQSL
Address and Control input setup 0.9 1.0 1.0 1.1 1.1 ns-----
tIS
Address and Control input hold tIH
DQ and DM setup time to DQS 0.40 0.45 0.45 0.5 0.5 ns-----
tDS
DQ and DM hold time to DQS tDH
Clock half period tCLmin
or
tCHmin ns 1-----
tHP
CL=3
CL=4
0.4 0.4 0.4 0.4 0.4 tCK0.6 0.6 0.6 0.6 0.6
0.4 0.4 0.4 0.4 0.4 tCK0.6 0.6 0.6 0.6 0.6
0.4 0.4 0.4 0.4 0.4 tCK0.6 0.6 0.6 0.6 0.6
0.9 1.0 1.0 1.1 1.1 ns-----
0.40 0.45 0.45 0.5 0.5 ns-----
Data output hold time from DQS tHP
-0.40 ns 1-----
tQH
tCLmin
or
tCHmin
tCLmin
or
tCHmin
tCLmin
or
tCHmin
tCLmin
or
tCHmin
tHP
-0.45 tHP
-0.45 tHP
-0.5 tHP
-0.5
-0.6 -0.7 -0.7 -0.75 -0.75 ns+0.6 +0.7 +0.7 +0.75 +0.75
-33
Min Max
-36
Min Max
3.3
-
3.6
0.45 0.450.55 0.55
0.45 0.450.55 0.55
-0.6 -0.6+0.6 +0.6
- -+0.35 +0.40
0.9 0.91.1 1.1
0.4 0.40.6 0.6
0 0- -
0.35 035- -
0.9 0.9- -
0.35 0.40- -
- -
0.4 0.40.6 0.6
0.4 0.40.6 0.6
0.4 0.40.6 0.6
0.9 0.9- -
0.35 0.40- -
- -
tCLmin
or
tCHmin
tCLmin
or
tCHmin
tHP
-0.35 tHP
-0.40
-0.7 -0.7+0.7 +0.7
CL=2 -ns
-
---
5.0
5.0
5.5
5.5
6.0
6.0
0.85 1.15 0.85 1.15 0.85 1.15
4 4
-
-
-
- -
5
5 -
5
-
-
5.5
10
-
6
10
-
7
10
Note 1:
-. The JEDEC DDR specification currently defines the output data valid window(tDV) as the period when the data strobe and all data associated with that
data strobe are coincidentally valid.
-. The previously used definition of tDV(=0.35tDK) artificially penalizes system timing budgets by assuming the worst case output valid window even then
the clock duty cycle applied to the device is better than 45/55%
-. A new AC timing term,tQH which stands for data output hold time from DQS is defined to account for clock duty cycle variation and r eplaces
tDV - tQHmin = tHP-X
where . tHP=Minimum half clock period for any given cycle and is defined by clock high or clock low time(tCH,tCL)
. X=A frequency dependent timing allowance account for tDQSQmax
26
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NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
NT5DU4M32EF
4Mx32 Double Data Rate SDRAM
AC CHARACTERISTICS (II)
Parameter Symbol
tRC
Refresh cycle time
15
17
13
15
12
14
12
14
10
12
tCK
tCK
Row active time 10 9887tCK100KtRAS
54443tCK----tRCDR
tRCDW
Row precharge time 54443tCKtRP
Row active to Row active 32222tCKtRRD
Last data in to Row precharge(@Normal) tWR
tWTR
Col. address to Col. address tCCD
Mode register set cycle time tMRD
Auto precharge write recovery
+ Precharge tDAL
tCKtXSR
Power down exit time tPDEX
Refresh interval time ustREF
Row cycle time
32222tCK
76665tCK
ns
tRFC
-
-
-
-
-
-
-
-
-
-
/RAS to /CAS delay for Write
/RAS to /CAS delay for Read
Internal Write in to Read command
Exit self refresh to read command
100K 100K 100K 100K
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
33222tCK 1-----
22222tCK 1-----
1 1 1 1 tCK-----
22222tCK-----
1
200 -----
1tCK +
tIS -----
7.8 -----
200
1tCK +
tIS
7.8
200
1tCK +
tIS
7.8
200
1tCK +
tIS
7.8
200
1tCK +
tIS
7.8
-40 Unit Note
Min Max
-45
Min Max
-50
Min Max
-55
Min Max
-60
Min Max
-33
Min Max
-36
Min Max
17
19
16
18
12 11
6 5- -
5 5
3 3
4 3
7 7
-
-
-
-
100K 100K
-
-
-
-
-
-
-
-
3 3- -
2 2- -
1- -
2 2- -
1
- -
- -
- -
200
1tCK +
tIS
7.8
200
1tCK +
tIS
7.8
Last data in to Row precharge(@Auto) tWR_A 33333tCK 1- - - - -3 3- -
ns 2tXSAExit self refresh to active command 75 -----75 75 75 75- -75 75
Note 1. For normal write operation, even numbers of Din are to be written inside DRAM
2. A write command can be applied with tRCD satisfied after this command.
-. AC parameters for DLL Disable Mode(66MHz ~ 100MHz, CL2 only) : Same as “-60” AC parameters except tCK.
27
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NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
NT5DU4M32EF
4Mx32 Double Data Rate SDRAM
SIMPLIFIED TRUTH TABLE
COMMAND CKEn-1 CKEn /CS /RAS /CAS /WE DM BA0,1 A8/AP A11~A9,A7~A0Note
Extended Mode Register
Mode Register Set
Register H X L L L L X
H X L L L L X
OP CODE
OP CODE 1,2
Auto Refresh
Entry
Exit
Self
Refresh
Refresh
H
L
H
L
H
L L L H X
L H H H
HXXXX
X
X
3
3
3
3
Bank Active & Row A d dress H X L L H H X V Row Address
Auto Precharge Disable
Auto Precharge Enable
Read &
Column Addr. H X L H L H X V L
HColumn
Address 4
4
Auto Precharge Disable
Auto Precharge Enable
Write &
Column Addr. H X L H L L X V L
HColumn
Address 4
4,6
Burst Stop H X L H H L X X 7
Bank Selection
All Banks
Precharge H X L L H L X V L
HX5X
H X X X
L V V V
XXXX
H X X X
L H H H
H X X X
L H H H
H X X X
L H H H
H L
L H
H L
L H
H X
H X
Entry
Exit
Entry
Exit
DM
Active Po wer Down
Precharge Power Down
Mode
No Operation Command
X
X
X
X
X
V
X
X
X
X
8
( V=Valid, X=Don’t care, H=Logic High, L=Logic Low )
Note : 1. OP CODE : Operand Code.
A0~ A11 & BA0~ BA1: Program Keys. (@EMRS/MRS)
2. EMRS/MRS can be issued only at all banks precharge state
A new command can be issued after 2 clock cycle of EMRS/MRS
3. Auto refresh function are as same as CBR refresh of DRAM.
The automatic precharge without row precharge command is meant by “Auto”.
Auto/Self refresh can be issued only at all banks precharge state.
4. BA0~ BA1: Bank select addresses.
If both BA0and BA1are “Low” at read, write, row active and precharge, bank A is selected.
If BA0is “High” and BA1is “Low” at read, write, row active and precharge, bank B is selected.
If BA0is “Low” and BA1is “High” at read, write, row active and precharge, bank C is selected.
If both BA0and BA1are “High” at read, write, row active and precharge, bank D is selected.
5. If A8/AP is “high” at row precharge ,BA0and BA1are ignored and all banks are selected.
6. During burst write with auto precharge, new read/write command cannot be issued.
Another bank read/write command can be issued after the end of burst.
New row active of the associated bank can be issued at tRP after the end of burst.
7. Burst stop command is valid at every burst length.
8. DM sampled at the rising and falling edges of the DQS and Data-in are masked at the both edges(Write DM latency is 0).
28
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NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
NT5DU4M32EF
4Mx32 Double Data Rate SDRAM
FUNCTION TRUTH TABLE
Current State /CS /RAS /CAS /WE Address Command Action
H X X X X DESEL NOP
L H H H X NOP NOP
L H H L X TERM NOP
L H L X BA0, CA, A8READ/WRITE ILLEGAL*2
L L H H BA, RA ACT Bank Active, Latch RA
L L H L BA, A8PRE/PREA NOP*4
L L L H X REFA AUTO-Refresh*5
LLLLOp-Code, Mode-Add MRS Mode Register Set*5
IDLE
H X X X X DESEL NOP
L H H H X NOP NOP
L H H L X TERM NOP
L H L H BA, CA, A8READ/READA Begin Read, Latcch CA,
Determine Auto-Precharge
L H L L BA, CA, A8WRITE/WRITEA Begin Write, Latch CA,
Determine Auto-Precharge
L L H H BA, RA ACT ILLEGAL*2
L L H L BA, A8PRE/PREA Precharge/Precharge All
L L L H X REFA ILLEGAL
LLLLOp-Code, Mode-Add MRS ILLEGAL
ROW ACTIVE
H X X X X DESEL NOP(Continue Burst to END)
L H H H X NOP NOP(Continue Burst to END)
L H H L X TERM Terminate Burst
L H L H BA, CA, A8READ/READA Terminate Burst, Latch CA,
Begin New Read, Det ermine
Auto-Precharge*3
L H L L BA, CA, A8WRITE/WRITEA ILLEGAL
L L H H BA, RA ACT ILLEGAL*2
L L H L BA, A8PRE/PREA Terminate Burst, Precharge
L L L H X REFA ILLEGAL
LLLLOp-Code, Mode-Add MRS ILLEGAL
READ
H X X X X DESEL NOP(Continue Burst to END)
L H H H X NOP NOP(Continue Burst to END)
L H H L X TERM ILLEGAL
L H L H BA, CA, A8READ/READA ILLEGAL
L H L L BA, CA, A8WRITE/WRITEA Terminate Burst, Latch CA,
Begin new Wri te, Determine
Precharge*3
L L H H BA, RA ACT ILLEGAL*2
L L H L BA, A8PRE/PREA Terminate Burst with DM=high
precharge
L L L H X REFA ILLEGAL
LLLLOp-Code, Mode-Add MRS ILLEGAL
WRITE
H X X X X DESEL NOP(Continue Burst to END)
L H H H X NOP NOP(Continue Burst to END)
L H H L X TERM ILLEGAL
L H L X BA, CA, A8READ/WRITE ILLEGAL*2
L L H H BA, RA ACT ILLEGAL*2
L L H L BA, A8PRE/PREA ILLEGAL*2
L L L H X REFA ILLEGAL
LLLLOp-Code, Mode-Add MRS ILLEGAL
READ with AUTO
PRECHARGE
29
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NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
NT5DU4M32EF
4Mx32 Double Data Rate SDRAM
FUNCTION TRUTH TABLE (continued)
Current State /CS /RAS /CAS /WE Address Command Action
H X X X X DESEL NOP(Continue Burst to END)
L H H H X NOP NOP(Continue Burst to END)
L H H L X TERM ILLEGAL
L H L X BA, CA, A8READ/WRITE ILLEGAL*2
L L H H BA, RA ACT ILLEGAL*2
L L H L BA, A8PRE/PREA ILLEGAL*2
L L L H X REFA ILLEGAL
LLLLOp-Code, Mode-Add MRS ILLEGAL
WRITE with AUTO
PRECHARGE
H X X X X DESEL NOP(Idle after tRP)
L H H H X NOP NOP(Idle after tRP)
L H H L X TERM NOP
L H L X BA, CA, A8READ/WRITE ILLEGAL*2
L L H H BA, RA ACT ILLEGAL*2
L L H L BA, A8PRE/PREA NOP*4(Idle after tRP)
L L L H X REFA ILLEGAL
LLLLOp-Code, Mode-Add MRS ILLEGAL
PRECHARGING
H X X X X DESEL NOP(ROW Active after tRCD)
L H H H X NOP NOP(ROW Active after tRCD)
L H H L X TERM NOP
L H L X BA, CA, A8READ/WRITE ILLEGAL*2
L L H H BA, RA ACT ILLEGAL*2
L L H L BA, A8PRE/PREA ILLEGAL*2
L L L H X REFA ILLEGAL
LLLLOp-Code, Mode-Add MRS ILLEGAL
ROW
ACTIVATING
WRITE
RECOVERING
RE-
FRESHING
H
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
X
H
H
H
H
L
L
L
L
H
L
L
L
L
X
H
H
L
L
H
L
L
L
L
H
H
L
L
X
H
L
H
L
H
H
L
L
X
H
L
H
L
HHH
XXX
H H L
X
X
X
BA, CA, A8
BA, CA, A8
BA, RA
BA, A8
X
Op-Code, Mode-Add
BA, CA, A8
BA, RA
BA, A8
X
Op-Code, Mode-Add
X
X
X
DESEL
NOP
TERM
READ
WRITE/WRITEA
ACT
PRE/PREA
REFA
MRS
READ/WRITE
ACT
PRE/PREA
REFA
MRS
NOP
DESEL
TERM
NOP
NOP
NOP
ILLEGAL*2
New Write, Determine AP.
ILLEGAL*2
ILLEGAL*2
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
NOP(Idle after tRP)
NOP(Idle after tRP)
NOP
ABBREVIATIONS :
H=High Level, L=Low Level, V=Valid, X=Don’t care
BA=Bank Address, RA=Row Address, CA=Column Address, NOP=No Operation
Note :
1. All entries assume that CKE was High during the preceding clock cycle and the current clock cycle.
2. ILLEGAL to bank in specified state ; function may be legal in the bank indicated by BA, depending on the state of that bank.
3. Must satisfy bus contention, bus turn around, write recovery requirements.
4. NOP to bank precharging or in idle state, May precharge bank indicated by B A.
5. ILLEGAL if any bank is not idle.
6. Same bank’s previous Auto precharge will not be performed. But if Bank is different, previous Auto precharge will be performed.
ILLEGAL = Device operation and/or data-integrity are not guaranteed.
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NT5DU4M32EF
4Mx32 Double Data Rate SDRAM
FUNCTION TRUTH TABLE for CKE
Current State
SELF-
REFRESHING
Both Bank
Precharge
POWER
DOWN
/CS /RAS /CAS /WE Add Action
INVALID
Exit Self-Refresh*1
Exit Self-Refresh*1
ILLEGAL
ILLEGAL
ILLEGAL
NOP(Maintain Self-Refresh)
INVALID
Exit Power Down*2
ILLEGAL
NOP(Maintain Power Down)
Refer to Function True Table
Enter Power Down*3
Enter Power Down*3
ILLEGAL
Exit Power Down*2
ILLEGAL
CKE
n-1
H
L
L
L
L
L
L
H
L
L
L
L
L
L
CKE
n
X
H
H
H
H
H
L
H
H
H
L
H
X
H
H
H
H
H
H
H
H
L
L
L
L
L
H
L
H
L
L
X
H
H
H
L
L
L
H
L
Any State
other than
listed above
ALL BANKS
IDLE
X
H
L
L
L
L
X
X
H
L
L
L
L
X
X
H
L
L
L
L
X
X
X
H
H
H
L
X
X
X
H
H
H
L
X
X
X
H
H
L
X
X
X
X
H
H
L
X
X
X
X
H
L
X
X
X
X
X
H
L
X
X
X
L
L
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
H
H
H
L
X
L
L
X
X
H
H
L
X
H
L
L
X
X
H
L
X
X
H
H
L
RA
X
OP Code
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
ILLEGAL
ILLEGAL
Row(& Bank) Active
Enter Self-Refresh *3
Begin Clock Suspend next cycle *4
Exit Clock Suspend next cycle *4
Maintain Clock Suspend
Refer to Current State=Power Down
Mode Register Access
Refer to Function True Table
ABBREVIATIONS :
H=High Level, L=Low Level, V=Valid, X=Don’t care
Note :
1. After CKE’s low to high transition to exist self refresh mode. And a time of tRC(min) has to be elapse after CKE’s low to high
transition to issue a new command.
2. CKE low to high transition is asynchronous as if restarts internal clock.
A minimum setup time “tIS + one clock” must be satisfied before any command other than exit.
3. Power-down and self-refresh can be entered only from the all banks idle state.
4. Must be a legal command.
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NT5DU4M32EF
4Mx32 Double Data Rate SDRAM
Timing
Basic Timing (Setup, Hold and Access Time @BL=2, CL=3)
012345678
/CK
CK
CKE
/CS
DQS
DQ
High
DM
COMMAND READA WRITEC
tRPRE
tCH tCL
tCK
tIStIH
/RAS
/CAS
A8/AP
BA[1:0]
ADDR
/WE
tRPST
tDQSQ
tDQSS
tWPREH
tWPRES
tDQSH tDQSL tWPST
tDS tDH tDS tDH
WRITEB
(A0~A7,A9~A11)
BAa
Ca
BAb
Cb
BAc
Cc
Qa1Qa0 Hi-Z
Hi-Z
Db0 Db1 Dc0 Dc1
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NT5DU4M32EF
4Mx32 Double Data Rate SDRAM
Multi Bank Interleaving READ (@BL=4, CL=3)
012345678 10
9
/CK
CK
CKE
/RAS
A8/AP
ADDR
/WE
DQS
DQ
High
BA[1:0]
/CAS
DM
COMMAND ACTIVEA ACTIVEB READA READB
(A0~A7,A9~A11)
BAa BAb
Ra Rb
Ra Rb
BAa
Ca
BAa
Ca
/CS
tRRD
Qa0 Qa1 Qa2 Qa3 Qb0
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NT5DU4M32EF
4Mx32 Double Data Rate SDRAM
Multi Bank Interl eaving WRITE (@BL=4, CL=3)
CKE
/CS
A8/AP
DQS
DQ
HIGH
BA[1:0]
COMMAND
/RAS
012345678
ADDR tRRD tRCDW
(A0~A7,A9~A11)
/CAS
/WE
tRCDW
WRITEA ACTIVEB WRITEB
BAa BAa BAb BAb
Ra Rb
Ra Ca Rb Cb
Da0 Da1 Da2 Da3 Db0 Db1 Db2 Db3
DM
ACTIVEA
/CK
CK
tDQSSmin
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NT5DU4M32EF
4Mx32 Double Data Rate SDRAM
Auto Precharge after READ Burst (@BL=8 )
*1 The row active command of the precharged bank can be issued after tRP from this point.
CKE High
DM
COMMAND
012345678
ACTIVEA
tRAS(min) tRP
Auto precharge start *1
/RAS
/CAS
BA[1:0] BAa
A8/AP
ADDR Ca
/WE
BAa
Ra
Ra
(A0~A7,A9~A11)
Qa0 Qa1 Qa2 Qa3 Qa4 Qa5 Qa6 Qa7
/CS
READA
/CK
CK
DQS(CL=3)
DQ(CL=3)
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NT5DU4M32EF
4Mx32 Double Data Rate SDRAM
Auto Precharge after WRITE Burst (@BL=4)
*1 The row active command of the precharged bank can be issued after tRP from this point.
CKE
/CAS
/WE
DQS
tWPRES
tWPREH tWR tRP
Auto precharge start *1
DQ
COMMAND WRITEA ACTIVEA
High
/RAS
BA[1:0] BAa
A8/AP
BAa
012345678
/CK
CK
ADDR BAa
Ra
Ra
(A0~A7,A9~A11)
/CS
Da0 Da1 Da2 Da3
DM
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NT5DU4M32EF
4Mx32 Double Data Rate SDRAM
Normal WRITE Burst (@BL=4)
CKE
/CS
COMMAND WRITEA PRE-
CHARGE
High
DQS
DQ
012345678
/CK
CK
BAa
/RAS
/CAS
BA[1:0]
A8/AP
Ca
ADDR
/WE
BAa
(A0~A7,A9~A11)
tWPRES
tWPREH tWR
Da0 Da1 Da2 Da3
DM
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NT5DU4M32EF
4Mx32 Double Data Rate SDRAM
Write Interrupted by Precharge & DM (@BL=8)
Dc3
CKE High
DQS
tWPRES
tWPREH
DQ
COMMAND WRITEA
tWR
PRE-
CHARGE WRITEB WRITEC
tCCD
012345678
/CAS
/WE
/RAS
BA[1:0] BAa
ADDR Ca
(A0~A7,A9~A11)
/CS
A8/AP
BAa BAb BAc
Cc
Cc
Db1 Dc0 Dc1 Dc2Db0
Da4 Da5 Da6 Da7Da3Da1 Da2Da0
DM
/CK
CK
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NT5DU4M32EF
4Mx32 Double Data Rate SDRAM
Read Interrupted by Precharge (@BL=8)
CKE High
COMMAND READA
DQS(CL=3)
DQ(CL=3)
DM
PRE
CHARGE
012345678
/CK
CK
/RAS
/CAS
BA[1:0] BAa
ADDR Ca
/WE
/CS
(A0~A7,A9~A11)
A8/AP
BAa
Qa2 Qa3 Qa4 Qa5
Qa0 Qa1
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NT5DU4M32EF
4Mx32 Double Data Rate SDRAM
Read Interrupted by Burst stop & W rite (@BL=8, CL= 3)
High
COMMAND READA
DQS
DQ
WRITEB
Burst
Stop
012345678
/CK
CK
CKE
/CAS
/WE
/RAS
BA[1:0]
ADDR
(A0~A7,A9~A11)
/CS
A8/AP
BAa
Ca
BAa
Cb
Qa5
Qa0 Qa1
DM
Db2 Db3 Db4
Db0 Db1
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NT5DU4M32EF
4Mx32 Double Data Rate SDRAM
Read Interrupted by Read (@BL= 8, CL= 3)
CKE High
COMMAND
DQS
DQ
012345678
/CK
CK
/CAS
/WE
/RAS
BA[1:0]
ADDR
(A0~A7,A9~A11)
/CS
A8/AP
BAa
Ca
BAb
BAb
DM
Qb3
Qb0 Qb1 Qb2
Qa0 Qa1 Qb7
Qb4 Qb5 Qb6
READA READB
tCCD
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NT5DU4M32EF
4Mx32 Double Data Rate SDRAM
DM Function (@BL=8) only for write
CKE High
COMMAND
DQS
DQ
WRITEA
012345678
/CK
CK
/RAS
/CAS
BA[1:0] BAa
ADDR Ca
/WE
/CS
(A0~A7,A9~A11)
A8/AP
tWPRES
tWPREH
Da3
Da0 Da1 Da2 Da7
Da4 Da5 Da6
DM tDH
tDStDS tDH
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NT5DU4M32EF
4Mx32 Double Data Rate SDRAM
Power up Sequence & Auto Refresh ( CBR )
DQS
DQ
DM
High - Z
High - Z
High
Inputs must be
stable for 200us Precharge
Command
All Bank
EMRS
Command Precharge
Command
All Bank
MRS
DLL Reset
Command
1st Auto
Refresh
Command
2nd Auto
Refresh
Command
Mode Register
Set Command Any
Command
tRP tMRD tMRD
tRFC
tRFC
tRPtMRD
Minimum of 2 Refresh Cycles are required
CKE
/CAS
ADDR
/WE
/CS
(A0~A7,A9~A11)
A8/AP
012345678
/CK
CK
/RAS
BA[1:0]
BA[1:0]
High
43
REV 0.0 (Prelimin ary)
08/2002 © NANYA TECHNOLOGY CORP.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
NT5DU4M32EF
4Mx32 Double Data Rate SDRAM
Mode Register Set
CKE High
DQS
DQ
DM
High - Z
High - Z
High
Precharge
All Bank
Command
Mode Register
Set Command Any
Command
tRP tMRD
/CAS
ADDR
/WE
/CS
(A0~A7,A9~A11)
A8/AP
012345678
/RAS
BA[1:0]
/CK
CK
44
REV 0.0 (Prelimin ary)
08/2002 © NANYA TECHNOLOGY CORP.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
NT5DU4M32EF
4Mx32 Double Data Rate SDRAM
IBIS : I/V CHARACTERISTICS F OR INPUT AND OUTPUT BUFFERS
Reduced Output Driver Characteristics.
1. The nominal pulldown V-I curve for DDR SDRAM devices will be within the inner bounding lines of the V-I curve of below figure.
2. The full variation in driver pulldown current from minimum to maximum process, temperature and voltage will lie within the outer
bounding lines of the V-I curve of below figure
Maximum
Typical High
Typical Low
Minimum
0.0
10.0
20.0
30.0
40.0
50.0
60.0
70.0
80.0
0.1 0.6 1.1 1.6 2.1
Iout(mA)
Vout(V)
3. The nominal pullup V-I curve for DDR SDRAM devices will be within the inner bounding lines of the V-I curve of below figure.
4. The full variation in driver pullup current from minimum to maximum process, temperature and voltage will lie within the outer
bounding lines of the V-I curve of below figure
Maximum
Typical High
Typical Low
Minimum
-110.0
-100.0
-90.0
-80.0
-70.0
-60.0
-50.0
-40.0
-30.0
-20.0
-10.0
0.0
0.10.61.11.62.1
Iout(mA)
Vout(V)
5. The full variation in the ratio of the maximum to minimum pullup and pulldown current will not exceed 1.7, for device drain to
source voltage from 0 to VDDQ/2
6. The full variation in the ratio of the nominal pullup to pulldown current should be unity ±0%, for device drain to source voltages
from 0 to VDDQ/2
45
REV 0.0 (Prelimin ary)
08/2002 © NANYA TECHNOLOGY CORP.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
NT5DU4M32EF
4Mx32 Double Data Rate SDRAM
Pulldo wn Current(mA) Pullup Current(mA)
Typical
Low Ty pical
High Minimum Maximum Ty pical
Low Ty pical
High Minimum Maximum
0.1 3.3 3.7 2.5 4.8 -3.3 -4.1 -2.5 -4.9
0.2 6.6 7.3 5.0 9.4 -6.6 -7.8 -5.0 -9.7
0.3 9.8 10.9 7.4 14.0 -9.8 -11.4 -7.4 -14.5
0.4 13.0 14.4 10.0 18.3 -12.9 -14.9 -10.0 -19.2
0.5 16.1 17.8 12.4 22.6 -16.1 -18.4 -12.4 -23.9
0.6 18.7 21.1 14.9 26.7 -18.5 -21.9 -14.9 -28.4
0.7 21.3 23.9 17.4 30.7 -20.5 -25.3 -17.4 -32.9
0.8 23.6 26.9 19.9 34.1 -22.2 -28.7 -19.5 -37.3
0.9 25.6 29.8 21.4 37.7 -23.6 -32.1 -20.6 -41.7
1.0 27.7 32.6 23.0 41.2 -24.8 -35.4 -20.9 -46.0
1.1 29.2 35.2 24.2 44.5 -25.8 -38.6 -21.1 -50.7
1.2 30.3 37.7 25.0 47.7 -26.6 -41.9 -21.2 -54.3
1.3 31.3 40.1 25.4 50.7 -27.0 -45.2 -21.3 -58.4
1.4 32.0 42.4 25.6 53.5 -27.2 -48.4 -21.4 -62.4
1.5 32.5 44.4 25.8 56.0 -27.4 -51.6 -21.5 -66.4
1.6 32.7 46.4 25.9 58.6 -27.5 -54.7 -21.6 -70.4
1.7 32.9 48.1 26.2 60.6 -27.6 -57.8 -21.7 -73.8
1.8 33.2 49.8 26.4 62.6 -27.7 -60.7 -21.8 -77.8
1.9 33.5 51.5 26.5 64.6 -27.8 -64.1 -21.8 -81.3
2.0 33.8 52.5 26.7 66.6 -27.9 -67.0 -21.9 -84.7
2.1 33.9 53.5 26.8 68.3 -28.0 -69.8 -21.9 -88.1
2.2 34.2 54.5 26.9 69.9 -28.1 -72.7 -22.0 -91.6
2.3 34.5 55.0 27.0 71.5 -28.2 -75.6 -22.0 -95.0
2.4 34.6 55.5 27.0 72.9 -28.2 -78.4 -22.1 -97.0
2.5 34.9 56.0 27.1 74.1 -28.3 -81.3 -22.2 -101.3
Voltage
(V)
Temperature (Ambient)
Typical 25°C
Minimum 70°C
Maximum 0°C
Vdd/Vddq
Typical 1.80V / 1.80V
Minimum 1.70V / 1.70V
Maximum 1.90V / 1.90V
The above characteristics are specified under best, worst and normal process variation/conditions
46
REV 0.0 (Prelimin ary)
08/2002 © NANYA TECHNOLOGY CORP.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
NT5DU4M32EF
4Mx32 Double Data Rate SDRAM
Impedance Match Output Driver Characteristics.
IN JEDEC
47
REV 0.0 (Prelimin ary)
08/2002 © NANYA TECHNOLOGY CORP.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
NT5DU4M32EF
4Mx32 Double Data Rate SDRAM
PACKAGE DIMENSIONS (144-Balla FBGA)
A1 INDEX MARK
12.0
12.0
<Top Vie w>
A
B
C
D
E
F
G
H
J
K
L
M12 11 10 9 8 7 6 5 4 3 2 1
0.40
0.80
0.40
0.80
< Bottom Vie w >
0.80x11=8.8
0.80x11=8.8
0.45 ±0.05
0.35 ±0.05
1.40 Max
0.10 MAX
