N-Channel JFET Switch
J108 – J110 / SST108 – SST110
FEATURES
••Low Cost
••Automa ted Inse rtion Package
••Low I nsertion Lo ss
••No Offset or Error V oltages Generated by Cl osed Switch
Purely Resistive
High I sol at ion Resi st an ce f rom Dri ve r
••Fast Switching
••Low Noise
APPLICATIONS
••An a lo g Sw it ch e s
••Choppers
••Commutators
••Lo w-Noise Audi o Am plifie rs
ABSOLUTE M AXIM UM R A T INGS
(TA = 25oC unless o th erw ise specified)
Gate- Dr ain or Gate -So urce Voltage . . . . . . . . . . . . . . . . -2 5V
Gate Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50mA
Stor age Temper at ure R a nge. . . . . . . . . . . . . -55oC t o +150oC
Oper at ing Temper atur e Ra nge . . . . . . . . . . . -55oC to +135oC
Lead Tem peratu re (So ld er ing, 10se c). . . . . . . . . . . . . +300oC
Power Dissipat ion . . . . . . . . . . . . . . . . . . . . . . . . . . . . 360mW
Derate above 25oC . . . . . . . . . . . . . . . . . . . . . . . 3.3mW/oC
NOTE: Stresses above those listed under "Absolute Maxi mum
Ratings " may cause permanent damage to the device. These are
stress ratings only and functional operation of the device at these or
any other conditions above those indicated in the operational sections
of the specifications is not implied. Exposure to absolute maximum
rating con ditions for extended per i ods may affect device reliability.
ORDERING INFORMATION
Part Package Temperat ure Range
J108- 11 0 Plastic TO-92 -55oC to +135oC
XJ108- 110 Sort ed Chips in Carrier s -55oC to +135oC
SST109- 110 Plastic SO T-23 -55oC to +135oC
LLC
PIN CONFIGUR ATI O N
TO-92
SG
D
5018
ELECTRICA L CHARACTERI STIC S (TA = 2 5oC unle ss otherwise sp ecif ie d)
SYMBOL PARAMETER 108 109 110 UNITS TEST CONDITIONS
MIN TYP MAX MIN TYP MAX MIN TYP MAX
IGSS Gate Reverse Current (Note 1) -3 -3 -3 nA VDS = 0V, VGS = -15V
VGS(off) Gate-Sourc e Cutoff Voltage -3 -10 -2 -6 -0.5 -4 VVDS = 5V, ID = 1µA
BVGSS Gate-Source Breakdown Voltage -25 -25 -25 VDS = 0V, IG = -1µA
IDSS Drain Saturation Current (Note 2) 80 40 10 mA VDS = 15V, VGS = 0V
ID(off) Drain Cutoff Curren t (Note 1) 3 3 3 nA VDS = 5V, VGS = -10V
rDS(on) Drain-Source ON Resistance 8 12 18 ΩVDS ≤0. 1V, VGS = 0V
Cdg(off) Drain-Gate OFF Capacitance 15 15 15
pF
VDS = 0,
VGS = -10V
(Note 3) f = 1 MHz
Csg(off) Source-Gate OFF Capacitance 15 15 15
Cdg(on)
+ Csg(on) Drain-Gate Plus Source-Gate
ON Capacitance 85 85 85 VDS = VGS = 0
(Note 3)
td(on) Turn On Delay Time 4 4 4
ns
Switchin g Time Test
Conditions (Note 3)
J107 J109 J110
VDD 1.5V1.5V1.5V
VGS(off)-12V -7V -5V
RL150Ω150Ω150Ω
trRise T ime 1 1 1
td(off) T urn OFF Delay Time 6 6 6
tfF all Time 30 30 30
NOTES: 1. A pproxi mately doubles for every 10oC increas e i n T A.
2. Pulse test duration = 300µs; duty cycle ≤3%.
3. For design reference only, not 100% tested.
PRODUCT MARKIN G (SOT-23 )
SST108 I08
SST109 I09
SST110 I10
SOT-23
G
S
D
CALOGIC LLC, 237 WHITNEY PLACE, FREMONT, CA 94539, 510-656-2900 PHONE, 510-651-1076 FAX DS038 REV A
