1
FEATURES
DESCRIPTION
R
DY
Z
A
B
R
DY
Z
A
B
DE
RE
2
3
2
5
4
3
5
6
8
7
9
10
12
11
2D
1D 1Y
1Z
2Y
2Z
DE 9
15
12
14
13
10
11
2R
1R 1A
1B
2A
2B
RE 5
3
4
2
1
6
7
1R
1D 1Y
1Z
1A
1B
1DE 3
15
4
14
13
2
1
2R
2D 2Y
2Z
2A
2B
2DE 5
9
12
10
11
6
7
1
2
3
4
8
7
6
5
VCC
R
D
GND
A
B
Z
Y
SN65LVDS179D (Marked as DL179 or LVD179)
SN65LVDS179DGK (Marked as S79)
(TOP VIEW)
1
2
3
4
5
6
7
14
13
12
11
10
9
8
NC
R
RE
DE
D
GND
GND
VCC
VCC
A
B
Z
Y
NC
SN65LVDS180D (Marked as LVDS180)
SN65LVDS180PW (Marked as LVDS180)
(TOP VIEW)
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
1B
1A
1R
RE
2R
2A
2B
GND
VCC
1D
1Y
1Z
DE
2Z
2Y
2D
SN65LVDS050D (Marked as LVDS050)
SN65LVDS050PW (Marked as LVDS050)
(TOP VIEW)
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
1B
1A
1R
1DE
2R
2A
2B
GND
VCC
1D
1Y
1Z
2DE
2Z
2Y
2D
SN65LVDS051D (Marked as LVDS051)
SN65LVDS051PW (Marked as LVDS051)
(TOP VIEW)
SN65LVDS179 , , SN65LVDS180SN65LVDS050 , SN65LVDS051
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............................................................................................................................................................ SLLS301P – APRIL 1998 – REVISED APRIL 2009
HIGH-SPEED DIFFERENTIAL LINE DRIVERS AND RECEIVERS
•Meets or Exceeds the Requirements of ANSITIA/EIA-644-1995 Standard•Full-Duplex Signaling Rates up to 100 Mbps(See Table 1 )•Bus-Terminal ESD Exceeds 12 kV•Operates From a Single 3.3-V Supply•Low-Voltage Differential Signaling With TypicalOutput Voltages of 350 mV and a 100- ΩLoad•Propagation Delay Times– Driver: 1.7 ns Typ– Receiver: 3.7 ns Typ•Power Dissipation at 200 MHz– Driver: 25 mW Typical– Receiver: 60 mW Typical•LVTTL Input Levels Are 5-V Tolerant•Receiver Maintains High Input Impedance WithV
CC
< 1.5 V•Receiver Has Open-Circuit Fail Safe
The SN65LVDS179, SN65LVDS180, SN65LVDS050,and SN65LVDS051 are differential line drivers andreceivers that use low-voltage differential signaling(LVDS) to achieve signaling rates as high as 400Mbps (see the Application Information section). TheTIA/EIA-644 standard compliant electrical interfaceprovides a minimum differential output voltagemagnitude of 247 mV into a 100- Ωload and receiptof 50-mV signals with up to 1 V of ground potentialdifference between a transmitter and receiver.
The intended application of this device and signalingtechnique is for point-to-point baseband datatransmission over controlled impedance media ofapproximately 100- Ωcharacteristic impedance. Thetransmission media may be printed-circuit boardtraces, backplanes, or cables. (Note: The ultimaterate and distance of data transfer depends on theattenuation characteristics of the media, the noisecoupling to the environment, and other applicationspecific characteristics).
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright © 1998 – 2009, Texas Instruments IncorporatedProducts conform to specifications per the terms of the TexasInstruments standard warranty. Production processing does notnecessarily include testing of all parameters.
DESCRIPTION (CONTINUED)
FUNCTION TABLES
SN65LVDS179 , , SN65LVDS180SN65LVDS050 , SN65LVDS051
SLLS301P – APRIL 1998 – REVISED APRIL 2009 ............................................................................................................................................................
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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foamduring storage or handling to prevent electrostatic damage to the MOS gates.
These devices offer various driver, receiver, and enabling combinations in industry-standard footprints. Becausethese devices are intended for use in simplex or distributed simplex bus structures, the driver enable functiondoes not put the differential outputs into a high-impedance state but rather disconnects the input and reduces thequiescent power used by the device. (For these functions with a high-impedance driver output, see theSN65LVDM series of devices.) All devices are characterized for operation from -40 ° C to 85 ° C.
Table 1. Maximum Recommended Operating Speeds
Part Number All Buffers Active Rx Buffer Only Tx Buffer Only
SN65LVDS179 150 Mbps 150 Mbps 400 MbpsSN65LVDS180 150 Mbps 150 Mbps 400 MbpsSN65LVDS050 100 Mbps 100 Mbps 400 MbpsSN65LVDS051 100 Mbps 100 Mbps 400 Mbps
AVAILABLE OPTIONS
(1)
PACKAGE
SMALL OUTLINE SMALL OUTLINE SMALL OUTLINE(D) (DGK) (PW)
SN65LVDS050D — SN65LVDS050PWSN65LVDS051D — SN65LVDS051PWSN65LVDS179D SN65LVDS179DGK —SN65LVDS180D — SN65LVDS180PW
(1) For the most current package and ordering information, see the Package Option Addendum at the endof this document, or see the TI website at www.ti.com .
SN65LVDS179 RECEIVER
INPUTS OUTPUT
(1)
V
ID
= V
A
- V
B
R
V
ID
≥50 mV H50 mV < V
ID
< 50 mV ?V
ID
≤-50 mV LOpen H
(1) H = high level, L = low level, ? = indeterminate
SN65LVDS179 DRIVER
(1)
INPUT OUTPUTS
D Y Z
L L HH H LOpen L H
(1) H = high level, L = low level
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EQUIVALENT INPUT AND OUTPUT SCHEMATIC DIAGRAMS
300 kΩ
50 Ω
VCC
7 V
D or
RE
Input
300 kΩ
50 Ω
VCC
7 V
DE
Input
5 Ω
10 kΩ
7 V
Y or Z
Output
VCC
7 V
VCC
7 V
R Output
VCC
5 Ω
B InputA Input
300 kΩ300 kΩ
7 V
SN65LVDS179 , , SN65LVDS180SN65LVDS050 , SN65LVDS051
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............................................................................................................................................................ SLLS301P – APRIL 1998 – REVISED APRIL 2009
SN65LVDS180, SN65LVDS050, andSN65LVDS051 RECEIVER
(1)
INPUTS OUTPUT
V
ID
= V
A
- V
B
RE R
V
ID
≥50 mV L H50 mV < V
ID
< 50 mV L ?V
ID
≤-50 mV L LOpen L HX H Z
(1) H = high level, L = low level, Z = high impedance, X = don ' t care,? = indeterminate
SN65LVDS180, SN65LVDS050, andSN65LVDS051 DRIVER
(1)
INPUTS OUTPUTS
D DE Y Z
L H L HH H H LOpen H L HX L Off Off
(1) H = high level, L = low level, Z = high impedance, X = don ' t care, Off= no output
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ABSOLUTE MAXIMUM RATINGS
(1)
DISSIPATION RATING TABLE
RECOMMENDED OPERATING CONDITIONS
2.4*
ŤVIDŤ
2
ŤVIDŤ
2
SN65LVDS179 , , SN65LVDS180SN65LVDS050 , SN65LVDS051
SLLS301P – APRIL 1998 – REVISED APRIL 2009 ............................................................................................................................................................
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over operating free-air temperature range (unless otherwise noted)
UNIT
V
CC
(see
(2)
) Supply voltage range – 0.5 V to 4 VD, R, DE, RE – 0.5 V to 6 VVoltage range:
Y, Z, A, and B – 0.5 V to 4 V|V
OD
| Differential output voltage: 1 VElectrostatic discharge: Y, Z, A, B , and GND (see
(3)
) CLass 3, A:12 kV, B:600 VAll Class 3, A:7 kV, B:500 VContinuous power dissipation See Dissipation Rating TableStorage temperature range – 65 ° C to 150 ° CLead temperature 1,6 mm (1/16 inch) from case for 10 seconds 250 ° C
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratingsonly, and functional operation of the device at these or any other conditions beyond those indicated under recommended operatingconditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.(2) All voltage values, except differential I/O bus voltages are with respect to network ground terminal.(3) Tested in accordance with MIL-STD-883C Method 3015.7.
T
A
≤25 ° C DERATING FACTOR T
A
= 85 ° CPACKAGE
POWER RATING ABOVE T
A
= 25 ° C
(1)
POWER RATING
PW(14) 736 mW 5.9 mW/ ° C 383 mWPW(16) 839 mW 6.7 mW/ ° C 437 mWD(8) 635 mW 5.1 mW/ ° C 330 mW/ ° CD(14) 987 mW 7.9 mW/ ° C 513 mW/ ° CD(16) 1110 mW 8.9 mW/ ° C 577 mW/ ° CDGK 424 mW 3.4 mW/ ° C 220 mW
(1) This is the inverse of the junction-to-ambient thermal resistance when board-mounted and with no airflow.
MIN NOM MAX UNIT
V
CC
Supply voltage 3 3.3 3.6 VV
IH
High-level input voltage 2 VV
IL
Low-level input voltage 0.8 V|V
ID
| Magnitude of differential input voltage 0.1 0.6 V|V
OD
(dis)| Magnitude of differential output voltage with disabled driver 520 mVV
OY
or V
OZ
Driver output voltage 0 2.4 V
V
IC
Common-mode input voltage (see Figure 5 ) V
V
CC
-0.8T
A
Operating free-air temperature – 40 85 ° C
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DEVICE ELECTRICAL CHARACTERISTICS
DRIVER ELECTRICAL CHARACTERISTICS
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............................................................................................................................................................ SLLS301P – APRIL 1998 – REVISED APRIL 2009
over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP
(1)
MAX UNIT
SN65LVDS179 No receiver load, driver R
L
= 100 Ω9 12 mADriver and receiver enabled, no receiver load, driver R
L
= 100 Ω9 12Driver enabled, receiver disabled, R
L
= 100 Ω5 7SN65LVDS180 mADriver disabled, receiver enabled, no load 1.5 2Disabled 0.5 1SupplyI
CC
Drivers and receivers enabled, no receiver loads, driver R
L
= 100 Ω12 20current
Drivers enabled, receivers disabled, R
L
= 100 Ω10 16SN65LVDS050 mADrivers disabled, receivers enabled, no loads 3 6Disabled 0.5 1Drivers enabled, No receiver loads, driver R
L
= 100 Ω12 20SN65LVDS051 mADrivers disabled, no loads 3 6
(1) All typical values are at 25 ° C and with a 3.3-V supply.
over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
|V
OD
| Differential output voltage magnitude 247 340 454R
L
= 100 Ω, See
mVChange in differential output voltage magnitude between logic
Figure 3 and Figure 2Δ|V
OD
| -50 50statesV
OC(SS)
Steady-state common-mode output voltage 1.125 1.2 1.375 VChange in steady-state common-mode output voltage betweenΔV
OC(SS)
See Figure 3 – 50 50 mVlogic statesV
OC(PP)
Peak-to-peak common-mode output voltage 50 150 mVDE – 0.5 – 20I
IH
High-level input current V
IH
= 5 V µAD 2 20DE – 0.5 – 10I
IL
Low-level input current V
IL
= 0.8 V µAD 2 10V
OY
or V
OZ
= 0 V 3 10I
OS
Short-circuit output current mAV
OD
= 0 V 3 10DE = OVV
OY
= V
OZ
= OVI
O(OFF)
Off-state output current – 1 1 µADE = V
CCV
OY
= V
OZ
= OV,V
CC
< 1.5 VC
IN
Input capacitance 3 pF
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RECEIVER ELECTRICAL CHARACTERISTICS
DRIVER SWITCHING CHARACTERISTICS
RECEIVER SWITCHING CHARACTERISTICS
SN65LVDS179 , , SN65LVDS180SN65LVDS050 , SN65LVDS051
SLLS301P – APRIL 1998 – REVISED APRIL 2009 ............................................................................................................................................................
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over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP
(1)
MAX UNIT
V
IT+
Positive-going differential input voltage threshold 50See Figure 5 and Table 2 mVV
IT-
Negative-going differential input voltage threshold – 50I
OH
= -8 mA 2.4V
OH
High-level output voltage VI
OH
= -4 mA 2.8V
OL
Low-level output voltage I
OL
= 8 mA 0.4 VV
I
= 0 – 2 – 11 – 20I
I
Input current (A or B inputs) µAV
I
= 2.4 V – 1.2 – 3I
I(OFF)
Power-off input current (A or B inputs) V
CC
= 0 ± 20 µAI
IH
High-level input current (enables) V
IH
= 5 V ± 10 µAI
IL
Low-level input current (enables) V
IL
= 0.8 V ± 10 µAI
OZ
High-impedance output current V
O
= 0 or 5 V ± 10 µAC
I
Input capacitance 5 pF
(1) All typical values are at 25 ° C and with a 3.3-V supply.
over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP
(1)
MAX UNIT
t
PLH
Propagation delay time, low-to-high-level output 1.7 2.7 nst
PHL
Propagation delay time, high-to-low-level output 1.7 2.7 nsR
L
= 100 Ω,t
r
Differential output signal rise time 0.8 1 nsC
L
= 10 pF,t
f
Differential output signal fall time 0.8 1 nsSee Figure 2t
sk(p)
Pulse skew (|t
pHL
- t
pLH
|)
(2)
300 pst
sk(o)
Channel-to-channel output skew
(3)
150 pst
en
Enable time 4.3 10 nsSee Figure 4t
dis
Disable time 3.1 10 ns
(1) All typical values are at 25 ° C and with a 3.3-V supply.(2) t
sk(p)
is the magnitude of the time difference between the high-to-low and low-to-high propagation delay times at an output.(3) t
sk(o)
is the magnitude of the time difference between the outputs of a single device with all of their inputs connected together.
over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP
(1)
MAX UNIT
t
PLH
Propagation delay time, low-to-high-level output 3.7 4.5 nst
PHL
Propagation delay time, high-to-low-level output 3.7 4.5 nsC
L
= 10 pF,t
sk(p)
Pulse skew (|t
pHL
- t
pLH
|)
(2)
0.3 nsSee Figure 6t
r
Output signal rise time 0.7 1.5 nst
f
Output signal fall time 0.9 1.5 nst
PZH
Propagation delay time, high-impedance-to-high-level output 2.5 nst
PZL
Propagation delay time, high-impedance-to-low-level output 2.5 nsSee Figure 7t
PHZ
Propagation delay time, high-level-to-high-impedance output 7 nst
PLZ
Propagation delay time, low-level-to-high-impedance output 4 ns
(1) All typical values are at 25 ° C and with a 3.3-V supply.(2) t
sk(p)
is the magnitude of the time difference between the high-to-low and low-to-high propagation delay times at an output.
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PARAMETER MEASUREMENT INFORMATION
DRIVER
VOD
VOZ
VOY
VOC
VI
IOY
IOZ
IIA
Z
Y
VOY )VOZ
2
Driver Enable
2 V
1.4 V
0.8 V
100%
80%
20%
0%
0 V
VOD(H)
VOD(L)
Output
Input
VOD
Z
Y
Input 100 Ω
±1%
CL = 10 pF
(2 Places)
tPHL
tPLH
tftr
Driver Enable
SN65LVDS179 , , SN65LVDS180SN65LVDS050 , SN65LVDS051
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............................................................................................................................................................ SLLS301P – APRIL 1998 – REVISED APRIL 2009
Figure 1. Driver Voltage and Current Definitions
A. All input pulses are supplied by a generator having the following characteristics: t
r
or t
f
≤1 ns, pulse repetition rate(PRR) = 50 Mpps, pulse width = 10 ± 0.2 ns. C
L
includes instrumentation and fixture capacitance within 0,06 mm ofthe D.U.T.
Figure 2. Test Circuit, Timing, and Voltage Definitions for the Differential Output Signal
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VOC
Z
Y
Input
CL = 10 pF
(2 Places)
3 V
0 V
VOC(PP) VOC(SS)
VOC
49.9 Ω, ±1% (2 Places)
Driver Enable
1.2 V
Z
Y
0.8 V or 2 V
49.9 Ω, ±1% (2 Places)
CL = 10 pF
(2 Places)
DE VOY VOZ
2 V
0.8 V
tdis
ten
tdis
ten
1.4 V
~1.4 V
1.2 V
1.25 V
1.2 V
~1 V
1.15 V
DE
VOY or VOZ
VOZ or VOY
D at 2 V and input to DE
D at 0.8 V and input to DE
SN65LVDS179 , , SN65LVDS180SN65LVDS050 , SN65LVDS051
SLLS301P – APRIL 1998 – REVISED APRIL 2009 ............................................................................................................................................................
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PARAMETER MEASUREMENT INFORMATION (continued)
A. All input pulses are supplied by a generator having the following characteristics: t
r
or t
f
≤1 ns, pulse repetition rate(PRR) = 50 Mpps, pulse width = 10 ± 0.2 ns. C
L
includes instrumentation and fixture capacitance within 0,06 mm ofthe D.U.T. The measurement of V
OC(PP)
is made on test equipment with a – 3-dB bandwidth of at least 300 MHz.
Figure 3. Test Circuit and Definitions for the Driver Common-Mode Output Voltage
A. All input pulses are supplied by a generator having the following characteristics: t
r
or t
f
≤1 ns, pulse repetition rate(PRR) = 0.5 Mpps, pulse width = 500 ± 10 ns. C
L
includes instrumentation and fixture capacitance within 0,06 mm ofthe D.U.T.
Figure 4. Enable and Disable Time Circuit and Definitions
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RECEIVER
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............................................................................................................................................................ SLLS301P – APRIL 1998 – REVISED APRIL 2009
PARAMETER MEASUREMENT INFORMATION (continued)
Figure 5. Receiver Voltage Definitions
Table 2. Receiver Minimum and Maximum Input Threshold Test Voltages
APPLIED VOLTAGES RESULTING DIFFERENTIAL RESULTING COMMON-(V) INPUT VOLTAGE (mV) MODE INPUT VOLTAGE (V)
V
IA
V
IB
V
ID
V
IC
1.25 1.15 100 1.21.15 1.25 – 100 1.22.4 2.3 100 2.352.3 2.4 – 100 2.350.1 0 100 0.050 0.1 – 100 0.051.5 0.9 600 1.20.9 1.5 – 600 1.22.4 1.8 600 2.11.8 2.4 – 600 2.10.6 0 600 0.30 0.6 – 600 0.3
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VIB
VID
VIA VO
CL
10 pF
VOH
VOL
1.4 V
VO
VIA
VIB
VID
1.4 V
1 V
0.4 V
0 V
–0.4 V
tPHL tPLH
tr
tf
0.4 V
2.4 V
SN65LVDS179 , , SN65LVDS180SN65LVDS050 , SN65LVDS051
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A. All input pulses are supplied by a generator having the following characteristics: t
r
or t
f
≤1 ns, pulse repetition rate(PRR) = 50 Mpps, pulse width = 10 ± 0.2 ns. C
L
includes instrumentation and fixture capacitance within 0,06 m of theD.U.T.
Figure 6. Timing Test Circuit and Waveforms
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VO
CL
10 pF +
–
500 Ω
1.2 V B
A
RE
Inputs VTEST
tPZL
VTEST
A
tPZL tPLZ
2.5 V
1.4 V
VOL +0.5 V VOL
2 V
1.4 V
0.8 V
2.5 V
1 V
RE
R
tPZH
VTEST
A
tPZH tPHZ
VOH
1.4 V
VOH –0.5 V
0 V
2 V
1.4 V
0.8 V
0 V
1.4 V
RE
R
SN65LVDS179 , , SN65LVDS180SN65LVDS050 , SN65LVDS051
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............................................................................................................................................................ SLLS301P – APRIL 1998 – REVISED APRIL 2009
A. All input pulses are supplied by a generator having the following characteristics: t
r
or t
f
≤1 ns, pulse repetition rate(PRR) = 0.5 Mpps, pulse width = 500 ± 10 ns. C
L
includes instrumentation and fixture capacitance within 0,06 m ofthe D.U.T.
Figure 7. Enable/Disable Time Test Circuit and Waveforms
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TYPICAL CHARACTERISTICS
−30
−20
−10
0
10
20
30
40
0 0.5 1 1.5 2 2.5 3
Other output at 0 V
VCC = 3.3 V
TA = 25°C
DE = 0 V
Other output at 1.2 V
VOZ = VOY
Other output at 2.4 V
Disabled Driver Output Current − mA
− Output Voltage − V
VO
−4 IOH − High-Level Output Current − mA
3.5
2.5
0−2 0
1.5
−3
0.5
VOH− High-Level Output Voltage − V
−1
3
2
1
VCC = 3.3 V
TA = 25°C
0IOL − Low-Level Output Current − mA
4
3
04 6
2
2
VCC = 3.3 V
TA = 25°C
1
VOL − Low-Level Output Voltage − V
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DISABLED DRIVER OUTPUT CURRENTvsOUTPUT VOLTAGE
Figure 8.
DRIVER DRIVERLOW-LEVEL OUTPUT VOLTAGE HIGH-LEVEL OUTPUT VOLTAGEvs vsLOW-LEVEL OUTPUT CURRENT HIGH-LEVEL OUTPUT CURRENT
Figure 9. Figure 10.
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0IOL − Low-Level Output Current − mA
5
060
2
10
VOL
20 30
3
1
− Low-Level Output Votlage − V
40 50
4
VCC = 3.3 V
TA = 25°C
−80 IOH − High-Level Output Current − mA
4
00
2
−60
VOH
−40 −20
3
1
− High-Level Output Voltage − V
VCC = 3.3 V
TA = 25°C
−50 TA − Free-Air Temperature − °C
2.5
1.5 50 90
2
−10
tPHL − High-To-Low Propagation Delay Time − ns
−30 30 70
10
VCC = 3.6 V
VCC = 3.3 V
VCC = 3 V
−50 TA − Free-Air Temperature − °C
2.5
1.5 50 90
2
−10
tPLH − Low-To-High Propagation Delay Time − ns
−30 30 70
10
VCC = 3.6 V
VCC = 3.3 V
VCC = 3 V
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............................................................................................................................................................ SLLS301P – APRIL 1998 – REVISED APRIL 2009
TYPICAL CHARACTERISTICS (continued)
RECEIVER RECEIVERLOW-LEVEL OUTPUT VOLTAGE HIGH-LEVEL OUTPUT VOLTAGEvs vsLOW-LEVEL OUTPUT CURRENT HIGH-LEVEL OUTPUT CURRENT
Figure 11. Figure 12.
DRIVER DRIVERHIGH-TO-LOW LEVEL PROPAGATION DELAY TIME LOW-TO-HIGH LEVEL PROPAGATION DELAY TIMEvs vsFREE-AIR TEMPERATURE FREE-AIR TEMPERATURE
Figure 13. Figure 14.
Copyright © 1998 – 2009, Texas Instruments Incorporated Submit Documentation Feedback 13
Product Folder Link(s): SN65LVDS179 SN65LVDS180 SN65LVDS050 SN65LVDS051
−50 TA − Free−Air Temperature − °C
4.5
2.5 50 90
3.5
−10
tPLH
−30 30 70
10
VCC = 3.6 V
VCC = 3 V
4
3
VCC = 3.3 V
− High-To-Low Level Propagation Delay Time − ms
−50 TA − Free-Air Temperature − °C
4.5
2.5 50 90
3.5
−10
tPLH − Low-To-High Level Propagation Delay Time − ns
−30 30 70
10
VCC = 3.6 V
VCC = 3 V
4
3
VCC = 3.3 V
SN65LVDS179 , , SN65LVDS180SN65LVDS050 , SN65LVDS051
SLLS301P – APRIL 1998 – REVISED APRIL 2009 ............................................................................................................................................................
www.ti.com
TYPICAL CHARACTERISTICS (continued)RECEIVERHIGH-TO-LOW LEVEL PROPAGATION DELAY TIMEvsFREE-AIR TEMPERATURE
Figure 15.
RECEIVERLOW-TO-HIGH LEVEL PROPAGATION DELAY TIMEvsFREE-AIR TEMPERATURE
Figure 16.
14 Submit Documentation Feedback Copyright © 1998 – 2009, Texas Instruments Incorporated
Product Folder Link(s): SN65LVDS179 SN65LVDS180 SN65LVDS050 SN65LVDS051
APPLICATION INFORMATION
Equipment
HewlettPackardHP6624A
DCPowerSupply
BenchTestBoard
AgilentParBERT
(E4832A)
TektronixTDS7404
RealTimeScope
(c)(a) (b)
SN65LVDS179 , , SN65LVDS180SN65LVDS050 , SN65LVDS051
www.ti.com
............................................................................................................................................................ SLLS301P – APRIL 1998 – REVISED APRIL 2009
•Hewlett Packard HP6624A DC power supply•Tektronix TDS7404 Real Time Scope•Agilent ParBERT E4832A
Figure 17. Equipment Setup
a. Tx + Rx running at 150 Mbps; Channel 1: R, Channel 2: Y-Zb. Rx only running at 150 Mbps; Channel 1: Rc. Tx only running at 400 Mbps; Channel 1: Y-Z
Figure 18. Typical Eye Patterns SN65LVDS179: (T = 25 ° C; V
CC
= 3.6 V; PRBS = 2
23-1
)
Copyright © 1998 – 2009, Texas Instruments Incorporated Submit Documentation Feedback 15
Product Folder Link(s): SN65LVDS179 SN65LVDS180 SN65LVDS050 SN65LVDS051
(c)(a) (b)
(c)(a) (b)
(c)(a) (b)
SN65LVDS179 , , SN65LVDS180SN65LVDS050 , SN65LVDS051
SLLS301P – APRIL 1998 – REVISED APRIL 2009 ............................................................................................................................................................
www.ti.com
a. Tx + Rx running at 150 Mbps; Channel 1: R, Channel 2: Y-Zb. Rx only running at 150 Mbps; Channel 1: Rc. Tx only running at 400 Mbps; Channel 1: Y-Z
Figure 19. Typical Eye Patterns SN65LVDS180: (T = 25 ° C; V
CC
= 3.6 V; PRBS = 2
23-1
)
a. All buffers running at 100 Mbps; Channel 1: R, Channel 2: 2R, Channel 3: 1Y-1Z, Channel 4: 2Y-2Z,b. Rx buffers only running at 100 Mbps; Channel 1: R, Channel 2: 2Rc. Tx buffers only running at 400 Mbps; Channel 3: 1Y-1Z, Channel 4: 2Y-2Z,
Figure 20. Typical Eye Patterns SN65LVDS050: (T = 25 ° C; V
CC
= 3.6 V; PRBS = 2
23-1
)
a. All buffers running at 100 Mbps; Channel 1: R, Channel 2: 2R, Channel 3: 1Y-1Z, Channel 4: 2Y-2Z,b. Rx buffers only running at 100 Mbps; Channel 1: R, Channel 2: 2Rc. Tx buffers only running at 400 Mbps; Channel 3: 1Y-1Z, Channel 4: 2Y-2Z,
Figure 21. Typical Eye Patterns SN65LVDS051: (T = 25 ° C; V
CC
= 3.6 V; PRBS = 2
23-1
)
16 Submit Documentation Feedback Copyright © 1998 – 2009, Texas Instruments Incorporated
Product Folder Link(s): SN65LVDS179 SN65LVDS180 SN65LVDS050 SN65LVDS051
10
0.1 1M Data Rate – Hz
1
100k 10M 100M
100
Transmission Distance – m
1000
5% Jitter
30% Jitter
24 AWG UTP 96 Ω (PVC Dielectric)
FAIL SAFE
Rt
100 Ω Typ
300 kΩ300 kΩ
VCC
VIT ≈ 2.3 V
A
BY
SN65LVDS179 , , SN65LVDS180SN65LVDS050 , SN65LVDS051
www.ti.com
............................................................................................................................................................ SLLS301P – APRIL 1998 – REVISED APRIL 2009
The devices are generally used as building blocks for high-speed point-to-point data transmission. Grounddifferences are less than 1 V with a low common-mode output and balanced interface for low noise emissions.Devices can interoperate with RS-422, PECL, and IEEE-P1596. Drivers/receivers maintain ECL speeds withoutthe power and dual supply requirements.
Figure 22. Data Transmission Distance Versus Rate
One of the most common problems with differential signaling applications is how the system responds when nodifferential voltage is present on the signal pair. The LVDS receiver is like most differential line receivers, in thatits output logic state can be indeterminate when the differential input voltage is between -100 mV and 100 mVand within its recommended input common-mode voltage range. TI's LVDS receiver is different in how it handlesthe open-input circuit situation, however.
Open-circuit means that there is little or no input current to the receiver from the data line itself. This could bewhen the driver is in a high-impedance state or the cable is disconnected. When this occurs, the LVDS receiverpulls each line of the signal pair to near V
CC
through 300-k Ωresistors as shown in Figure 11 . The fail-safefeature uses an AND gate with input voltage thresholds at about 2.3 V to V
CC
- 0.4 V to detect this condition andforce the output to a high-level regardless of the differential input voltage.
Figure 23. Open-Circuit Fail Safe of the LVDS Receiver
It is only under these conditions that the output of the receiver will be valid with less than a 100-mV differentialinput voltage magnitude. The presence of the termination resistor, Rt, does not affect the fail-safe function aslong as it is connected as shown in the figure. Other termination circuits may allow a dc current to ground thatcould defeat the pullup currents from the receiver and the fail-safe feature.
Copyright © 1998 – 2009, Texas Instruments Incorporated Submit Documentation Feedback 17
Product Folder Link(s): SN65LVDS179 SN65LVDS180 SN65LVDS050 SN65LVDS051
PACKAGE OPTION ADDENDUM
www.ti.com 16-Aug-2012
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
SN65LVDS050D ACTIVE SOIC D 16 40 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65LVDS050DG4 ACTIVE SOIC D 16 40 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65LVDS050DR ACTIVE SOIC D 16 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65LVDS050DRG4 ACTIVE SOIC D 16 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65LVDS050PW ACTIVE TSSOP PW 16 90 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65LVDS050PWG4 ACTIVE TSSOP PW 16 90 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65LVDS050PWR ACTIVE TSSOP PW 16 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65LVDS050PWRG4 ACTIVE TSSOP PW 16 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65LVDS051D ACTIVE SOIC D 16 40 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65LVDS051DG4 ACTIVE SOIC D 16 40 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65LVDS051DR ACTIVE SOIC D 16 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65LVDS051DRG4 ACTIVE SOIC D 16 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65LVDS051PW ACTIVE TSSOP PW 16 90 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65LVDS051PWG4 ACTIVE TSSOP PW 16 90 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65LVDS051PWR ACTIVE TSSOP PW 16 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65LVDS051PWRG4 ACTIVE TSSOP PW 16 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65LVDS179D ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
PACKAGE OPTION ADDENDUM
www.ti.com 16-Aug-2012
Addendum-Page 2
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
SN65LVDS179DG4 ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65LVDS179DGK ACTIVE VSSOP DGK 8 80 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65LVDS179DGKG4 ACTIVE VSSOP DGK 8 80 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65LVDS179DGKR ACTIVE VSSOP DGK 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65LVDS179DGKRG4 ACTIVE VSSOP DGK 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65LVDS179DR ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65LVDS179DRG4 ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65LVDS180D ACTIVE SOIC D 14 50 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65LVDS180DG4 ACTIVE SOIC D 14 50 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65LVDS180DR ACTIVE SOIC D 14 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65LVDS180DRG4 ACTIVE SOIC D 14 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65LVDS180PW ACTIVE TSSOP PW 14 90 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65LVDS180PWG4 ACTIVE TSSOP PW 14 90 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65LVDS180PWR ACTIVE TSSOP PW 14 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65LVDS180PWRG4 ACTIVE TSSOP PW 14 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
PACKAGE OPTION ADDENDUM
www.ti.com 16-Aug-2012
Addendum-Page 3
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF SN65LVDS050, SN65LVDS051, SN65LVDS179, SN65LVDS180 :
•Automotive: SN65LVDS050-Q1, SN65LVDS051-Q1, SN65LVDS180-Q1
•Enhanced Product: SN65LVDS179-EP
NOTE: Qualified Version Definitions:
•Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
•Enhanced Product - Supports Defense, Aerospace and Medical Applications
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
SN65LVDS050DR SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1
SN65LVDS050PWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
SN65LVDS051DR SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1
SN65LVDS051PWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
SN65LVDS179DGKR VSSOP DGK 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
SN65LVDS179DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
SN65LVDS180DR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
SN65LVDS180PWR TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 16-Aug-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
SN65LVDS050DR SOIC D 16 2500 367.0 367.0 38.0
SN65LVDS050PWR TSSOP PW 16 2000 367.0 367.0 35.0
SN65LVDS051DR SOIC D 16 2500 367.0 367.0 38.0
SN65LVDS051PWR TSSOP PW 16 2000 367.0 367.0 35.0
SN65LVDS179DGKR VSSOP DGK 8 2500 358.0 335.0 35.0
SN65LVDS179DR SOIC D 8 2500 340.5 338.1 20.6
SN65LVDS180DR SOIC D 14 2500 367.0 367.0 38.0
SN65LVDS180PWR TSSOP PW 14 2000 367.0 367.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 16-Aug-2012
Pack Materials-Page 2
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