SN65LVDS179,, SN65LVDS180 SN65LVDS050, SN65LVDS051 www.ti.com ............................................................................................................................................................ SLLS301P - APRIL 1998 - REVISED APRIL 2009 HIGH-SPEED DIFFERENTIAL LINE DRIVERS AND RECEIVERS FEATURES 1 * * * * * * * * * * Meets or Exceeds the Requirements of ANSI TIA/EIA-644-1995 Standard Full-Duplex Signaling Rates up to 100 Mbps (See Table 1) Bus-Terminal ESD Exceeds 12 kV Operates From a Single 3.3-V Supply Low-Voltage Differential Signaling With Typical Output Voltages of 350 mV and a 100- Load Propagation Delay Times - Driver: 1.7 ns Typ - Receiver: 3.7 ns Typ Power Dissipation at 200 MHz - Driver: 25 mW Typical - Receiver: 60 mW Typical LVTTL Input Levels Are 5-V Tolerant Receiver Maintains High Input Impedance With VCC < 1.5 V Receiver Has Open-Circuit Fail Safe DESCRIPTION The SN65LVDS179, SN65LVDS180, SN65LVDS050, and SN65LVDS051 are differential line drivers and receivers that use low-voltage differential signaling (LVDS) to achieve signaling rates as high as 400 Mbps (see the Application Information section). The TIA/EIA-644 standard compliant electrical interface provides a minimum differential output voltage magnitude of 247 mV into a 100- load and receipt of 50-mV signals with up to 1 V of ground potential difference between a transmitter and receiver. The intended application of this device and signaling technique is for point-to-point baseband data transmission over controlled impedance media of approximately 100- characteristic impedance. The transmission media may be printed-circuit board traces, backplanes, or cables. (Note: The ultimate rate and distance of data transfer depends on the attenuation characteristics of the media, the noise coupling to the environment, and other application specific characteristics). SN65LVDS179D (Marked as DL179 or LVD179) SN65LVDS179DGK (Marked as S79) (TOP VIEW) 3 VCC R D GND 1 8 2 7 3 6 4 5 A B Z Y 5 6 D 8 2 R 7 Y Z A B SN65LVDS180D (Marked as LVDS180) SN65LVDS180PW (Marked as LVDS180) (TOP VIEW) NC R RE DE D GND GND 1 14 2 13 3 12 4 11 5 10 6 9 7 8 VCC VCC A B Z Y NC 5 4 DE 1 16 2 15 3 14 4 13 5 12 6 11 7 10 8 9 VCC 1D 1Y 1Z DE 2Z 2Y 2D RE 12 2 R 4 13 5 12 6 11 7 10 8 9 1Z 2DE 2Z 2Y 2D 11 14 13 12 DE 10 9 2D 3 11 2 1 1R 4 RE 6 5 2R SN65LVDS051D (Marked as LVDS051) SN65LVDS051PW (Marked as LVDS051) (TOP VIEW) 15 1D 1B 1 16 VCC 4 1DE 1A 2 15 1D 3 1R 3 14 1Y 1R 1DE 2R 2A 2B GND 9 7 14 13 2 1 10 11 2D 12 2DE 6 5 2R Y Z 3 SN65LVDS050D (Marked as LVDS050) SN65LVDS050PW (Marked as LVDS050) 15 (TOP VIEW) 1D 1B 1A 1R RE 2R 2A 2B GND 9 10 D 7 A B 1Y 1Z 2Y 2Z 1A 1B 2A 2B 1Y 1Z 1A 1B 2Y 2Z 2A 2B 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright (c) 1998-2009, Texas Instruments Incorporated SN65LVDS179,, SN65LVDS180 SN65LVDS050, SN65LVDS051 SLLS301P - APRIL 1998 - REVISED APRIL 2009 ............................................................................................................................................................ www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. DESCRIPTION (CONTINUED) These devices offer various driver, receiver, and enabling combinations in industry-standard footprints. Because these devices are intended for use in simplex or distributed simplex bus structures, the driver enable function does not put the differential outputs into a high-impedance state but rather disconnects the input and reduces the quiescent power used by the device. (For these functions with a high-impedance driver output, see the SN65LVDM series of devices.) All devices are characterized for operation from -40C to 85C. Table 1. Maximum Recommended Operating Speeds Part Number All Buffers Active Rx Buffer Only Tx Buffer Only SN65LVDS179 150 Mbps 150 Mbps 400 Mbps SN65LVDS180 150 Mbps 150 Mbps 400 Mbps SN65LVDS050 100 Mbps 100 Mbps 400 Mbps SN65LVDS051 100 Mbps 100 Mbps 400 Mbps AVAILABLE OPTIONS (1) PACKAGE (1) SMALL OUTLINE (D) SMALL OUTLINE (DGK) SMALL OUTLINE (PW) SN65LVDS050D -- SN65LVDS050PW SN65LVDS051D -- SN65LVDS051PW SN65LVDS179D SN65LVDS179DGK -- SN65LVDS180D -- SN65LVDS180PW For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website at www.ti.com. FUNCTION TABLES SN65LVDS179 RECEIVER (1) INPUTS OUTPUT (1) VID = VA - VB R VID 50 mV H 50 mV < VID < 50 mV ? VID -50 mV L Open H H = high level, L = low level, ? = indeterminate SN65LVDS179 DRIVER (1) INPUT (1) 2 OUTPUTS D Y Z L L H H H L Open L H H = high level, L = low level Submit Documentation Feedback Copyright (c) 1998-2009, Texas Instruments Incorporated Product Folder Link(s): SN65LVDS179 SN65LVDS180 SN65LVDS050 SN65LVDS051 SN65LVDS179,, SN65LVDS180 SN65LVDS050, SN65LVDS051 www.ti.com ............................................................................................................................................................ SLLS301P - APRIL 1998 - REVISED APRIL 2009 SN65LVDS180, SN65LVDS050, and SN65LVDS051 RECEIVER (1) INPUTS (1) OUTPUT VID = VA - VB RE R VID 50 mV L H 50 mV < VID < 50 mV L ? VID -50 mV L L Open L H X H Z H = high level, L = low level, Z = high impedance, X = don't care, ? = indeterminate SN65LVDS180, SN65LVDS050, and SN65LVDS051 DRIVER (1) INPUTS (1) OUTPUTS D DE Y Z L H L H H H H L Open H L H X L Off Off H = high level, L = low level, Z = high impedance, X = don't care, Off = no output EQUIVALENT INPUT AND OUTPUT SCHEMATIC DIAGRAMS VCC VCC VCC 300 k 50 5 10 k D or RE Input Y or Z Output 50 DE Input 7V 300 k 7V 7V VCC VCC 300 k 300 k 5 A Input R Output B Input 7V Copyright (c) 1998-2009, Texas Instruments Incorporated 7V 7V Submit Documentation Feedback Product Folder Link(s): SN65LVDS179 SN65LVDS180 SN65LVDS050 SN65LVDS051 3 SN65LVDS179,, SN65LVDS180 SN65LVDS050, SN65LVDS051 SLLS301P - APRIL 1998 - REVISED APRIL 2009 ............................................................................................................................................................ www.ti.com ABSOLUTE MAXIMUM RATINGS (1) over operating free-air temperature range (unless otherwise noted) UNIT (2) VCC (see ) Supply voltage range Voltage range: |VOD| -0.5 V to 4 V D, R, DE, RE -0.5 V to 6 V Y, Z, A, and B -0.5 V to 4 V Differential output voltage: Electrostatic discharge: 1V Y, Z, A, B , and GND (see (3) ) CLass 3, A:12 kV, B:600 V All Class 3, A:7 kV, B:500 V Continuous power dissipation See Dissipation Rating Table Storage temperature range -65C to 150C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds (1) (2) (3) 250C Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values, except differential I/O bus voltages are with respect to network ground terminal. Tested in accordance with MIL-STD-883C Method 3015.7. DISSIPATION RATING TABLE (1) PACKAGE TA 25C POWER RATING DERATING FACTOR ABOVE TA = 25C (1) TA = 85C POWER RATING PW(14) 736 mW 5.9 mW/C 383 mW PW(16) 839 mW 6.7 mW/C 437 mW D(8) 635 mW 5.1 mW/C 330 mW/C D(14) 987 mW 7.9 mW/C 513 mW/C D(16) 1110 mW 8.9 mW/C 577 mW/C DGK 424 mW 3.4 mW/C 220 mW This is the inverse of the junction-to-ambient thermal resistance when board-mounted and with no airflow. RECOMMENDED OPERATING CONDITIONS MIN NOM MAX VCC Supply voltage 3 3.3 3.6 VIH High-level input voltage 2 VIL Low-level input voltage |VID| Magnitude of differential input voltage |VOD(dis)| Magnitude of differential output voltage with disabled driver VOY or VOZ Driver output voltage VIC Common-mode input voltage (see Figure 5) TA Operating free-air temperature 0 0.8 V 0.6 V 520 mV 2.4 V V ID 2 V V 0.1 V UNIT 2.4 * ID 2 V VCC-0.8 4 Submit Documentation Feedback -40 85 C Copyright (c) 1998-2009, Texas Instruments Incorporated Product Folder Link(s): SN65LVDS179 SN65LVDS180 SN65LVDS050 SN65LVDS051 SN65LVDS179,, SN65LVDS180 SN65LVDS050, SN65LVDS051 www.ti.com ............................................................................................................................................................ SLLS301P - APRIL 1998 - REVISED APRIL 2009 DEVICE ELECTRICAL CHARACTERISTICS over recommended operating conditions (unless otherwise noted) MIN TYP (1) MAX No receiver load, driver RL = 100 9 12 Driver and receiver enabled, no receiver load, driver RL = 100 9 12 PARAMETER TEST CONDITIONS SN65LVDS179 SN65LVDS180 Supply current ICC SN65LVDS050 SN65LVDS051 (1) Driver enabled, receiver disabled, RL = 100 5 7 Driver disabled, receiver enabled, no load 1.5 2 Disabled 0.5 1 Drivers and receivers enabled, no receiver loads, driver RL = 100 12 20 Drivers enabled, receivers disabled, RL = 100 10 16 3 6 Drivers disabled, receivers enabled, no loads Disabled 0.5 1 Drivers enabled, No receiver loads, driver RL = 100 12 20 3 6 MIN TYP MAX 247 340 454 Drivers disabled, no loads UNIT mA mA mA mA All typical values are at 25C and with a 3.3-V supply. DRIVER ELECTRICAL CHARACTERISTICS over recommended operating conditions (unless otherwise noted) PARAMETER |VOD| Differential output voltage magnitude |VOD| Change in differential output voltage magnitude between logic states VOC(SS) Steady-state common-mode output voltage VOC(SS) Change in steady-state common-mode output voltage between logic states VOC(PP) Peak-to-peak common-mode output voltage IIH High-level input current IIL Low-level input current IOS Short-circuit output current DE D DE D TEST CONDITIONS RL = 100 , See Figure 3 and Figure 2 -50 1.125 See Figure 3 50 1.2 -50 1.375 UNIT mV V 50 mV 50 150 mV -0.5 -20 2 20 -0.5 -10 2 10 VOY or VOZ = 0 V 3 10 VOD = 0 V 3 10 VIH = 5 V VIL = 0.8 V A A mA DE = OV VOY = VOZ = OV IO(OFF) Off-state output current CIN Input capacitance Copyright (c) 1998-2009, Texas Instruments Incorporated DE = VCC VOY = VOZ = OV, VCC < 1.5 V -1 1 3 Submit Documentation Feedback Product Folder Link(s): SN65LVDS179 SN65LVDS180 SN65LVDS050 SN65LVDS051 A pF 5 SN65LVDS179,, SN65LVDS180 SN65LVDS050, SN65LVDS051 SLLS301P - APRIL 1998 - REVISED APRIL 2009 ............................................................................................................................................................ www.ti.com RECEIVER ELECTRICAL CHARACTERISTICS over recommended operating conditions (unless otherwise noted) PARAMETER VIT+ Positive-going differential input voltage threshold VIT- Negative-going differential input voltage threshold VOH High-level output voltage VOL Low-level output voltage II Input current (A or B inputs) II(OFF) Power-off input current (A or B inputs) IIH IIL IOZ High-impedance output current CI Input capacitance (1) TEST CONDITIONS See Figure 5 and Table 2 MIN TYP (1) MAX 50 -50 IOH = -8 mA 2.4 IOH = -4 mA 2.8 VI = 0 mV V IOL = 8 mA VI = 2.4 V UNIT 0.4 -2 -11 -1.2 -3 -20 V A VCC = 0 20 A High-level input current (enables) VIH = 5 V 10 A Low-level input current (enables) VIL = 0.8 V 10 A VO = 0 or 5 V 10 A 5 pF All typical values are at 25C and with a 3.3-V supply. DRIVER SWITCHING CHARACTERISTICS over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP (1) MAX UNIT tPLH Propagation delay time, low-to-high-level output 1.7 2.7 ns tPHL Propagation delay time, high-to-low-level output 1.7 2.7 ns tr Differential output signal rise time 0.8 1 ns tf Differential output signal fall time 0.8 1 ns tsk(p) Pulse skew (|tpHL - tpLH|) (2) 300 ps tsk(o) Channel-to-channel output skew (3) 150 ps ten Enable time tdis Disable time (1) (2) (3) RL = 100 , CL = 10 pF, See Figure 2 See Figure 4 4.3 10 ns 3.1 10 ns All typical values are at 25C and with a 3.3-V supply. tsk(p) is the magnitude of the time difference between the high-to-low and low-to-high propagation delay times at an output. tsk(o) is the magnitude of the time difference between the outputs of a single device with all of their inputs connected together. RECEIVER SWITCHING CHARACTERISTICS over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP (1) MAX 3.7 4.5 ns 3.7 4.5 ns UNIT tPLH Propagation delay time, low-to-high-level output tPHL Propagation delay time, high-to-low-level output tsk(p) Pulse skew (|tpHL - tpLH|) (2) tr Output signal rise time 0.7 1.5 ns tf Output signal fall time 0.9 1.5 ns tPZH Propagation delay time, high-impedance-to-high-level output 2.5 ns tPZL Propagation delay time, high-impedance-to-low-level output 2.5 ns tPHZ Propagation delay time, high-level-to-high-impedance output 7 ns tPLZ Propagation delay time, low-level-to-high-impedance output 4 ns (1) (2) 6 CL = 10 pF, See Figure 6 0.3 See Figure 7 ns All typical values are at 25C and with a 3.3-V supply. tsk(p) is the magnitude of the time difference between the high-to-low and low-to-high propagation delay times at an output. Submit Documentation Feedback Copyright (c) 1998-2009, Texas Instruments Incorporated Product Folder Link(s): SN65LVDS179 SN65LVDS180 SN65LVDS050 SN65LVDS051 SN65LVDS179,, SN65LVDS180 SN65LVDS050, SN65LVDS051 www.ti.com ............................................................................................................................................................ SLLS301P - APRIL 1998 - REVISED APRIL 2009 PARAMETER MEASUREMENT INFORMATION DRIVER IOY Driver Enable Y II A IOZ VOD V VOY Z VI OY )V OZ 2 VOC VOZ Figure 1. Driver Voltage and Current Definitions Driver Enable Y 100 1% VOD Input Z CL = 10 pF (2 Places) 2V 1.4 V 0.8 V Input tPHL tPLH 100% 80% VOD(H) Output 0V VOD(L) 20% 0% tf A. tr All input pulses are supplied by a generator having the following characteristics: tr or tf 1 ns, pulse repetition rate (PRR) = 50 Mpps, pulse width = 10 0.2 ns. CL includes instrumentation and fixture capacitance within 0,06 mm of the D.U.T. Figure 2. Test Circuit, Timing, and Voltage Definitions for the Differential Output Signal Copyright (c) 1998-2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): SN65LVDS179 SN65LVDS180 SN65LVDS050 SN65LVDS051 7 SN65LVDS179,, SN65LVDS180 SN65LVDS050, SN65LVDS051 SLLS301P - APRIL 1998 - REVISED APRIL 2009 ............................................................................................................................................................ www.ti.com PARAMETER MEASUREMENT INFORMATION (continued) 49.9 , 1% (2 Places) Driver Enable 3V Y Input 0V Z VOC VOC(PP) CL = 10 pF (2 Places) VOC(SS) VOC A. All input pulses are supplied by a generator having the following characteristics: tr or tf 1 ns, pulse repetition rate (PRR) = 50 Mpps, pulse width = 10 0.2 ns. CL includes instrumentation and fixture capacitance within 0,06 mm of the D.U.T. The measurement of VOC(PP) is made on test equipment with a -3-dB bandwidth of at least 300 MHz. Figure 3. Test Circuit and Definitions for the Driver Common-Mode Output Voltage 49.9 , 1% (2 Places) Y 0.8 V or 2 V Z DE 1.2 V CL = 10 pF (2 Places) VOY 2V 1.4 V 0.8 V DE VOY or VOZ ten ten ~1.4 V 1.25 V 1.2 V D at 2 V and input to DE 1.2 V 1.15 V ~1 V D at 0.8 V and input to DE tdis VOZ or VOY A. VOZ tdis All input pulses are supplied by a generator having the following characteristics: tr or tf 1 ns, pulse repetition rate (PRR) = 0.5 Mpps, pulse width = 500 10 ns. CL includes instrumentation and fixture capacitance within 0,06 mm of the D.U.T. Figure 4. Enable and Disable Time Circuit and Definitions 8 Submit Documentation Feedback Copyright (c) 1998-2009, Texas Instruments Incorporated Product Folder Link(s): SN65LVDS179 SN65LVDS180 SN65LVDS050 SN65LVDS051 SN65LVDS179,, SN65LVDS180 SN65LVDS050, SN65LVDS051 www.ti.com ............................................................................................................................................................ SLLS301P - APRIL 1998 - REVISED APRIL 2009 PARAMETER MEASUREMENT INFORMATION (continued) RECEIVER A V IA )V IB VID 2 R VIA B VIC VO VIB Figure 5. Receiver Voltage Definitions Table 2. Receiver Minimum and Maximum Input Threshold Test Voltages APPLIED VOLTAGES (V) RESULTING DIFFERENTIAL INPUT VOLTAGE (mV) RESULTING COMMONMODE INPUT VOLTAGE (V) VIA VIB VID VIC 1.25 1.15 100 1.2 1.15 1.25 -100 1.2 2.4 2.3 100 2.35 2.3 2.4 -100 2.35 0.1 0 100 0.05 0 0.1 -100 0.05 1.5 0.9 600 1.2 0.9 1.5 -600 1.2 2.4 1.8 600 2.1 1.8 2.4 -600 2.1 0.6 0 600 0.3 0 0.6 -600 0.3 Copyright (c) 1998-2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): SN65LVDS179 SN65LVDS180 SN65LVDS050 SN65LVDS051 9 SN65LVDS179,, SN65LVDS180 SN65LVDS050, SN65LVDS051 SLLS301P - APRIL 1998 - REVISED APRIL 2009 ............................................................................................................................................................ www.ti.com VID VIA VIB CL 10 pF VO VIA 1.4 V VIB 1V VID 0.4 V 0V -0.4 V tPHL VO tPLH VOH 2.4 V 1.4 V 0.4 V VOL tf A. tr All input pulses are supplied by a generator having the following characteristics: tr or tf 1 ns, pulse repetition rate (PRR) = 50 Mpps, pulse width = 10 0.2 ns. CL includes instrumentation and fixture capacitance within 0,06 m of the D.U.T. Figure 6. Timing Test Circuit and Waveforms 10 Submit Documentation Feedback Copyright (c) 1998-2009, Texas Instruments Incorporated Product Folder Link(s): SN65LVDS179 SN65LVDS180 SN65LVDS050 SN65LVDS051 SN65LVDS179,, SN65LVDS180 SN65LVDS050, SN65LVDS051 www.ti.com ............................................................................................................................................................ SLLS301P - APRIL 1998 - REVISED APRIL 2009 B 1.2 V 500 A Inputs A. CL 10 pF RE + - VO VTEST All input pulses are supplied by a generator having the following characteristics: tr or tf 1 ns, pulse repetition rate (PRR) = 0.5 Mpps, pulse width = 500 10 ns. CL includes instrumentation and fixture capacitance within 0,06 m of the D.U.T. 2.5 V VTEST A 1V 2V RE 1.4 V 0.8 V tPZL tPZL tPLZ 2.5 V 1.4 V R VOL +0.5 V VOL 0V VTEST A 1.4 V 2V RE 1.4 V 0.8 V tPZH R tPZH VOH -0.5 V tPHZ VOH 1.4 V 0V Figure 7. Enable/Disable Time Test Circuit and Waveforms Copyright (c) 1998-2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): SN65LVDS179 SN65LVDS180 SN65LVDS050 SN65LVDS051 11 SN65LVDS179,, SN65LVDS180 SN65LVDS050, SN65LVDS051 SLLS301P - APRIL 1998 - REVISED APRIL 2009 ............................................................................................................................................................ www.ti.com TYPICAL CHARACTERISTICS DISABLED DRIVER OUTPUT CURRENT vs OUTPUT VOLTAGE Disabled Driver Output Current - mA 40 VCC = 3.3 V TA = 25C DE = 0 V 30 Other output at 0 V 20 Other output at 1.2 V 10 VOZ = VOY 0 -10 Other output at 2.4 V -20 -30 0 0.5 1 1.5 2 VO - Output Voltage - V Figure 8. DRIVER LOW-LEVEL OUTPUT VOLTAGE vs LOW-LEVEL OUTPUT CURRENT 3.5 VCC = 3.3 V TA = 25C VOH - High-Level Output Voltage - V VOL - Low-Level Output Voltage - V 3 DRIVER HIGH-LEVEL OUTPUT VOLTAGE vs HIGH-LEVEL OUTPUT CURRENT 4 3 2 1 VCC = 3.3 V TA = 25C 3 2.5 2 1.5 1 0.5 0 0 0 2 4 IOL - Low-Level Output Current - mA Figure 9. 12 2.5 Submit Documentation Feedback 6 -4 -3 -2 -1 0 IOH - High-Level Output Current - mA Figure 10. Copyright (c) 1998-2009, Texas Instruments Incorporated Product Folder Link(s): SN65LVDS179 SN65LVDS180 SN65LVDS050 SN65LVDS051 SN65LVDS179,, SN65LVDS180 SN65LVDS050, SN65LVDS051 www.ti.com ............................................................................................................................................................ SLLS301P - APRIL 1998 - REVISED APRIL 2009 TYPICAL CHARACTERISTICS (continued) RECEIVER LOW-LEVEL OUTPUT VOLTAGE vs LOW-LEVEL OUTPUT CURRENT RECEIVER HIGH-LEVEL OUTPUT VOLTAGE vs HIGH-LEVEL OUTPUT CURRENT 5 4 VCC = 3.3 V TA = 25C VOH - High-Level Output Voltage - V VOL - Low-Level Output Votlage - V VCC = 3.3 V TA = 25C 4 3 2 1 10 20 30 40 50 IOL - Low-Level Output Current - mA 2 1 0 -80 0 0 3 60 -60 Figure 11. Figure 12. VCC = 3.3 V VCC = 3 V VCC = 3.6 V 1.5 -50 -30 -10 50 30 70 TA - Free-Air Temperature - C 10 Figure 13. Copyright (c) 1998-2009, Texas Instruments Incorporated DRIVER LOW-TO-HIGH LEVEL PROPAGATION DELAY TIME vs FREE-AIR TEMPERATURE 2.5 t PLH - Low-To-High Propagation Delay Time - ns t PHL - High-To-Low Propagation Delay Time - ns DRIVER HIGH-TO-LOW LEVEL PROPAGATION DELAY TIME vs FREE-AIR TEMPERATURE 2.5 2 0 -40 -20 IOH - High-Level Output Current - mA 90 2 VCC = 3.3 V VCC = 3 V VCC = 3.6 V 1.5 -50 -30 -10 50 10 30 70 TA - Free-Air Temperature - C 90 Figure 14. Submit Documentation Feedback Product Folder Link(s): SN65LVDS179 SN65LVDS180 SN65LVDS050 SN65LVDS051 13 SN65LVDS179,, SN65LVDS180 SN65LVDS050, SN65LVDS051 SLLS301P - APRIL 1998 - REVISED APRIL 2009 ............................................................................................................................................................ www.ti.com TYPICAL CHARACTERISTICS (continued) t PLH - High-To-Low Level Propagation Delay Time - ms RECEIVER HIGH-TO-LOW LEVEL PROPAGATION DELAY TIME vs FREE-AIR TEMPERATURE 4.5 VCC = 3.3 V 4 VCC = 3 V 3.5 VCC = 3.6 V 3 2.5 -50 -30 -10 50 10 30 70 TA - Free-Air Temperature - C Figure 15. 90 t PLH - Low-To-High Level Propagation Delay Time - ns RECEIVER LOW-TO-HIGH LEVEL PROPAGATION DELAY TIME vs FREE-AIR TEMPERATURE 14 Submit Documentation Feedback 4.5 VCC = 3 V 4 VCC = 3.3 V 3.5 VCC = 3.6 V 3 2.5 -50 -30 -10 50 10 30 70 TA - Free-Air Temperature - C Figure 16. 90 Copyright (c) 1998-2009, Texas Instruments Incorporated Product Folder Link(s): SN65LVDS179 SN65LVDS180 SN65LVDS050 SN65LVDS051 SN65LVDS179,, SN65LVDS180 SN65LVDS050, SN65LVDS051 www.ti.com ............................................................................................................................................................ SLLS301P - APRIL 1998 - REVISED APRIL 2009 APPLICATION INFORMATION Equipment * * * Hewlett Packard HP6624A DC power supply Tektronix TDS7404 Real Time Scope Agilent ParBERT E4832A Hewlett Packard HP6624A DC Power Supply Agilent ParBERT (E4832A) Bench Test Board Tektronix TDS7404 Real Time Scope Figure 17. Equipment Setup (a) (b) a. Tx + Rx running at 150 Mbps; Channel 1: R, Channel 2: Y-Z b. Rx only running at 150 Mbps; Channel 1: R c. Tx only running at 400 Mbps; Channel 1: Y-Z (c) Figure 18. Typical Eye Patterns SN65LVDS179: (T = 25C; VCC = 3.6 V; PRBS = 223-1) Copyright (c) 1998-2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): SN65LVDS179 SN65LVDS180 SN65LVDS050 SN65LVDS051 15 SN65LVDS179,, SN65LVDS180 SN65LVDS050, SN65LVDS051 SLLS301P - APRIL 1998 - REVISED APRIL 2009 ............................................................................................................................................................ www.ti.com (a) (b) a. Tx + Rx running at 150 Mbps; Channel 1: R, Channel 2: Y-Z b. Rx only running at 150 Mbps; Channel 1: R c. Tx only running at 400 Mbps; Channel 1: Y-Z (c) Figure 19. Typical Eye Patterns SN65LVDS180: (T = 25C; VCC = 3.6 V; PRBS = 223-1) (a) (b) (c) a. All buffers running at 100 Mbps; Channel 1: R, Channel 2: 2R, Channel 3: 1Y-1Z, Channel 4: 2Y-2Z, b. Rx buffers only running at 100 Mbps; Channel 1: R, Channel 2: 2R c. Tx buffers only running at 400 Mbps; Channel 3: 1Y-1Z, Channel 4: 2Y-2Z, Figure 20. Typical Eye Patterns SN65LVDS050: (T = 25C; VCC = 3.6 V; PRBS = 223-1) (a) (b) (c) a. All buffers running at 100 Mbps; Channel 1: R, Channel 2: 2R, Channel 3: 1Y-1Z, Channel 4: 2Y-2Z, b. Rx buffers only running at 100 Mbps; Channel 1: R, Channel 2: 2R c. Tx buffers only running at 400 Mbps; Channel 3: 1Y-1Z, Channel 4: 2Y-2Z, Figure 21. Typical Eye Patterns SN65LVDS051: (T = 25C; VCC = 3.6 V; PRBS = 223-1) 16 Submit Documentation Feedback Copyright (c) 1998-2009, Texas Instruments Incorporated Product Folder Link(s): SN65LVDS179 SN65LVDS180 SN65LVDS050 SN65LVDS051 SN65LVDS179,, SN65LVDS180 SN65LVDS050, SN65LVDS051 www.ti.com ............................................................................................................................................................ SLLS301P - APRIL 1998 - REVISED APRIL 2009 The devices are generally used as building blocks for high-speed point-to-point data transmission. Ground differences are less than 1 V with a low common-mode output and balanced interface for low noise emissions. Devices can interoperate with RS-422, PECL, and IEEE-P1596. Drivers/receivers maintain ECL speeds without the power and dual supply requirements. Transmission Distance - m 1000 30% Jitter 100 5% Jitter 10 1 24 AWG UTP 96 (PVC Dielectric) 0.1 100k 1M 10M 100M Data Rate - Hz Figure 22. Data Transmission Distance Versus Rate FAIL SAFE One of the most common problems with differential signaling applications is how the system responds when no differential voltage is present on the signal pair. The LVDS receiver is like most differential line receivers, in that its output logic state can be indeterminate when the differential input voltage is between -100 mV and 100 mV and within its recommended input common-mode voltage range. TI's LVDS receiver is different in how it handles the open-input circuit situation, however. Open-circuit means that there is little or no input current to the receiver from the data line itself. This could be when the driver is in a high-impedance state or the cable is disconnected. When this occurs, the LVDS receiver pulls each line of the signal pair to near VCC through 300-k resistors as shown in Figure 11. The fail-safe feature uses an AND gate with input voltage thresholds at about 2.3 V to VCC - 0.4 V to detect this condition and force the output to a high-level regardless of the differential input voltage. VCC 300 k 300 k A Rt 100 Typ Y B VIT 2.3 V Figure 23. Open-Circuit Fail Safe of the LVDS Receiver It is only under these conditions that the output of the receiver will be valid with less than a 100-mV differential input voltage magnitude. The presence of the termination resistor, Rt, does not affect the fail-safe function as long as it is connected as shown in the figure. Other termination circuits may allow a dc current to ground that could defeat the pullup currents from the receiver and the fail-safe feature. Copyright (c) 1998-2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): SN65LVDS179 SN65LVDS180 SN65LVDS050 SN65LVDS051 17 PACKAGE OPTION ADDENDUM www.ti.com 16-Aug-2012 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp SN65LVDS050D ACTIVE SOIC D 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN65LVDS050DG4 ACTIVE SOIC D 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN65LVDS050DR ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN65LVDS050DRG4 ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN65LVDS050PW ACTIVE TSSOP PW 16 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN65LVDS050PWG4 ACTIVE TSSOP PW 16 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN65LVDS050PWR ACTIVE TSSOP PW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN65LVDS050PWRG4 ACTIVE TSSOP PW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN65LVDS051D ACTIVE SOIC D 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN65LVDS051DG4 ACTIVE SOIC D 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN65LVDS051DR ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN65LVDS051DRG4 ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN65LVDS051PW ACTIVE TSSOP PW 16 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN65LVDS051PWG4 ACTIVE TSSOP PW 16 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN65LVDS051PWR ACTIVE TSSOP PW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN65LVDS051PWRG4 ACTIVE TSSOP PW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN65LVDS179D ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Addendum-Page 1 (3) Samples (Requires Login) PACKAGE OPTION ADDENDUM www.ti.com Orderable Device 16-Aug-2012 Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp SN65LVDS179DG4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN65LVDS179DGK ACTIVE VSSOP DGK 8 80 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN65LVDS179DGKG4 ACTIVE VSSOP DGK 8 80 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN65LVDS179DGKR ACTIVE VSSOP DGK 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN65LVDS179DGKRG4 ACTIVE VSSOP DGK 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN65LVDS179DR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN65LVDS179DRG4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN65LVDS180D ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN65LVDS180DG4 ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN65LVDS180DR ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN65LVDS180DRG4 ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN65LVDS180PW ACTIVE TSSOP PW 14 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN65LVDS180PWG4 ACTIVE TSSOP PW 14 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN65LVDS180PWR ACTIVE TSSOP PW 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN65LVDS180PWRG4 ACTIVE TSSOP PW 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. Addendum-Page 2 (3) Samples (Requires Login) PACKAGE OPTION ADDENDUM www.ti.com 16-Aug-2012 (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. 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OTHER QUALIFIED VERSIONS OF SN65LVDS050, SN65LVDS051, SN65LVDS179, SN65LVDS180 : * Automotive: SN65LVDS050-Q1, SN65LVDS051-Q1, SN65LVDS180-Q1 * Enhanced Product: SN65LVDS179-EP NOTE: Qualified Version Definitions: * Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects * Enhanced Product - Supports Defense, Aerospace and Medical Applications Addendum-Page 3 PACKAGE MATERIALS INFORMATION www.ti.com 16-Aug-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 10.3 2.1 8.0 16.0 Q1 SN65LVDS050DR SOIC D 16 2500 330.0 16.4 6.5 SN65LVDS050PWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 SN65LVDS051DR SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1 SN65LVDS051PWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 SN65LVDS179DGKR VSSOP DGK 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 SN65LVDS179DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 SN65LVDS180DR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 SN65LVDS180PWR TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 16-Aug-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN65LVDS050DR SOIC D 16 2500 367.0 367.0 38.0 SN65LVDS050PWR TSSOP PW 16 2000 367.0 367.0 35.0 SN65LVDS051DR SOIC D 16 2500 367.0 367.0 38.0 SN65LVDS051PWR TSSOP PW 16 2000 367.0 367.0 35.0 SN65LVDS179DGKR VSSOP DGK 8 2500 358.0 335.0 35.0 SN65LVDS179DR SOIC D 8 2500 340.5 338.1 20.6 SN65LVDS180DR SOIC D 14 2500 367.0 367.0 38.0 SN65LVDS180PWR TSSOP PW 14 2000 367.0 367.0 35.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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