1
December 1997
ACS157MS
Radiation Hardened
Quad 2-Input Non-Inverting Multiplexer
Features
QML Qualified Per MIL-PRF-38535 Requirements
1.25Micron Radiation Hardened SOS CMOS
Radiation Environment
- Latch-up Free Under any Conditions
- Total Dose . . . . . . . . . . . . . . . . . . . . . .3 x 105RAD(Si)
- SEU Immunity. . . . . . . . . . . <1 x 10-10 Errors/Bit/Day
- SEU LET Threshold . . . . . . . . . . .>100MeV/(mg/cm2)
Input Logic Levels . . . VIL = (0.3)(Vcc), VIH = (0.7)(Vcc)
Output Current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±12mA
Quiescent Supply Current. . . . . . . . . . . . . . . . . . . .20µA
Propagation Delay . . . . . . . . . . . . . . . . . . . . . . . . . .14ns
Applications
4-Bit Source Selection
Data Routing
High Frequency Switching
Description
The Radiation Hardened ACS157MS is a Quad 2-Channel
Non-Inverting Multiplexer which selects four bits of data from
one of two sources under the control of a single Select pin.
The Output Enable input is active LOW and controls all out-
puts. When E is set HIGH, all outputs are forced LOW,
regardless of all other input conditions. All inputs are buff-
ered and the outputs are designed for balanced propagation
delay and transition times.
The ACS157MS is fabricated on a CMOS Silicon on Sap-
phire (SOS) process, which provides an immunity to Single
Event Latch-up and the capability of highly reliable perfor-
mance in any radiation environment. These devices offer
significant power reduction and faster performance when
compared to ALSTTL types.
Specifications for Rad Hard QML devices are controlled
by the Defense Supply Center in Columbus (DSCC). The
SMD numbers listed belo w m ust be used when or dering.
Detailed Electrical Specifications for the ACS157 are
contained in SMD 5962-98536. A “hot-link” is provided
on our homepage with instructions for downloading.
http://www.intersil.com/data/sm/index.htm
Ordering Information
Pinouts ACS157 (SBDIP)
TOP VIEW ACS157 (FLATPACK)
TOP VIEW
SMD PART NUMBER INTERSIL PART NUMBER TEMP. RANGE (oC) PACKAGE CASE OUTLINE
5962F9853601VEC ACS157DMSR-02 -55 to 125 16 Ld SBDIP CDIP2-T16
N/A ACS157D/Sample-02 25 16 Ld SBDIP CDIP2-T16
5962F9853601VXC ACS157KMSR-02 -55 to 125 16 Ld Flatpack CDFP4-F16
N/A ACS157K/Sample-02 25 16 Ld Flatpack CDFP4-F16
N/A ACS157HMSR-02 25 Die N/A
14
15
16
9
13
12
11
10
1
2
3
4
5
7
6
8
S
1I0
1I1
1Y
2I0
2I1
GND
2Y
VCC
4I0
4I1
4Y
3I0
3I1
3Y
ES
1I0
1I1
1Y
2I0
2I1
2Y
GND
2
3
4
5
6
7
8
116
15
14
13
12
11
10
9
VCC
E
4I0
4I1
4Y
3I0
3I1
3Y
File Number 4462
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
2
ACS157MS
Die Characteristics
DIE DIMENSIONS:
Size: 2390µm x 2390µm (94 mils x 94 mils)
Thickness: 525µm±25µm (20.6 mils ±1 mil)
Bond Pad: 110µm x 110µm (4.3 x 4.3 mils)
METALLIZATION: Al
Metal 1 Thickness: 0.7µm±0.1µm
Metal 2 Thickness: 1.0µm±0.1µm
SUBSTRATE POTENTIAL:
Unbiased Insulator
PASSIVATION
Type: Phosphorous Silicon Glass (PSG)
Thickness: 1.30µm±0.15µm
SPECIAL INSTRUCTIONS:
Bond VCC First
ADDITIONAL INFORMATION:
Worst Case Density: <2.0 x 105 A/cm2
Transistor Count: 150
Metallization Mask Layout
ACS157MS
1I0SV
CC OE
1I1
1Y
2I0
2I1
4I0
4I1
4Y
3I0
2Y GND 3Y 3I1
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