MT8816 ISO-CMOS 8 x 16 Analog Switch Array Features ISSUE3 * * * * * Internal control latches and address decoder Short set-up and hold times Wide operating voltage: 4.5V to 13.2V 12Vpp analog signal capability RON 65 max. @ VDD=12V, 25C * * * * * RON 10 @ VDD=12V, 25C Full CMOS switch for low distortion Minimum feedthrough and crosstalk Separate analog and digital reference supplies Low power consumption ISO-CMOS technology Ordering Information MT8816AE MT8816AP Description The Zarlink MT8816 is fabricated in Zarlink's ISOCMOS technology providing low power dissipation and high reliability. The device contains a 8 x 16 array of crosspoint switches along with a 7 to 128 line decoder and latch circuits. Any one of the 128 switches can be addressed by selecting the appropriate seven address bits. The selected switch can be turned on or off by applying a logical one or zero to the DATA input. VSS is the ground refer-ence of the digital inputs. The range of the analog signal is from VDD to VEE. Chip Select (CS) allows the crosspoint array to be cascaded for matrix expansion. Key systems PBX systems Mobile radio Test equipment/instrumentation Analog/digital multiplexers Audio/Video switching CS STROBE DATA RESET 1 AX0 40 Pin Plastic DIP 44 Pin PLCC -40 to 85C Applications * * * * * * VDD VEE VSS 1 AX2 7 to 128 Decoder 8 x 16 Switch Array Latches AY0 AY1 AY2 128 **************** AX1 AX3 March 1997 Xi I/O (i=0-15) 128 ******************* Yi I/O (i=0-7) Figure 1 - Functional Block Diagram 3-45 Y3 AY2 RESET AX3 AX0 X14 X15 X6 X7 X8 X9 X10 X11 NC Y7 VSS Y6 STROBE Y5 VEE 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 NC AX0 AX3 RESET AY2 Y3 VDD Y2 DATA Y1 CS ISO-CMOS VDD Y2 DATA Y1 CS Y0 NC X0 X1 X2 X3 X4 X5 X12 X13 AY1 AY0 AX2 AX1 Y4 6 5 4 3 2 1 44 43 42 41 40 7 39 8 38 9 37 10 36 11 35 12 34 13 33 14 32 15 31 16 30 29 17 18 19 20 21 22 23 24 25 26 27 28 X14 X15 X6 X7 X8 X9 X10 X11 NC NC Y7 Y0 NC X0 X1 X2 X3 X4 X5 X12 X13 NC VSS Y6 STROBE Y5 VEE Y4 AX1 AX2 AY0 AY1 NC MT8816 40 PIN PLASTIC DIP 44 PIN PLCC Figure 2 - Pin Connections Pin Description Pin # Name Description 1 Y3 Y3 Analog (Input/Output): this is connected to the Y3 column of the switch array. 2 2 AY2 Y2 Address Line (Input). 3 3 RESET 4,5 4,5 AX3,AX0 X3 and X0 Address Lines (Inputs). 6,7 7,8 X14, X15 X14 and X15 Analog (Inputs/Outputs): these are connected to the X14 and X15 rows of the switch array. 8-13 9-14 X6-X11 14 6,15,16 NC No Connection 15 17 Y7 Y7 Analog (Input/Output): this is connected to the Y7 column of the switch array. 16 18 VSS Digital Ground Reference. 17 19 Y6 Y6 Analog (Input/Output): this is connected to the Y6 column of the switch array. 18 20 19 21 Y5 Y5 Analog (Input/Output): this is connected to the Y5 column of the switch array. 20 22 VEE Negative Power Supply. 21 23 Y4 Y4 Analog (Input/Output): this is connected to the Y4 column of the switch array. 22, 23 24,25 AX1,AX2 X1 and X2 Address Lines (Inputs). 24, 25 26,27 AY0,AY1 Y0 and Y1 Address Lines (Inputs). 26, 27 30,31 X13, X12 X13 and X12 Analog (Inputs/Outputs): these are connected to the X13 and X12 rows of the switch array. PDIP PLCC 1 3-46 Master RESET (Input): this is used to turn off all switches regardless of the condition of CS. Active High. X6-X11 Analog (Inputs/Outputs): these are connected to the X6-X11 rows of the switch array. STROBE STROBE (Input): enables function selected by address and data. Address must be stable before STROBE goes high and DATA must be stable on the falling edge of the STROBE. Active High. ISO-CMOS MT8816 Pin Description (continued) Pin # Name Description PDIP PLCC 28 - 33 32-37 X5-X0 34 28,29, 38 NC No Connection. 35 39 Y0 Y0 Analog (Input/Output): this is connected to the Y0 column of the switch array. 36 40 CS Chip Select (Input): this is used to select the device. Active High. 37 41 Y1 Y1 Analog (Input/Output): this is connected to the Y1 column of the switch array. 38 42 DATA DATA (Input): a logic high input will turn on the selected switch and a logic low will turn off the selected switch. Active High. 39 43 Y2 Y2 Analog (Input/Output): this is connected to the Y2 column of the switch array. 40 44 VDD Positive Power Supply. X5-X0 Analog (Inputs/Outputs): these are connected to the X5-X0 rows of the switch array. Functional Description Address Decode The MT8816 is an analog switch matrix with an array size of 8 x 16. The switch array is arranged such that there are 8 columns by 16 rows. The columns are referred to as the Y inputs/outputs and the rows are the X inputs/outputs. The crosspoint analog switch array will interconnect any X I/O with any Y I/O when turned on and provide a high degree of isolation when turned off. The control memory consists of a 128 bit write only RAM in which the bits are selected by the address inputs (AY0-AY2, AX0-AX3). Data is presented to the memory on the DATA input. Data is asynchronously written into memory whenever both the CS (Chip Select) and STROBE inputs are high and are latched on the falling edge of STROBE. A logical "1" written into a memory cell turns the corresponding crosspoint switch on and a logical "0" turns the crosspoint off. Only the crosspoint switches corresponding to the addressed memory location are altered when data is written into memory. The remaining switches retain their previous states. Any combination of X and Y inputs/outputs can be interconnected by establishing appropriate patterns in the control memory. A logical "1" on the RESET input will asynchronously return all memory locations to logical "0" turning off all crosspoint switches regardless of whether CS is high or low. Two voltage reference pins (VSS and VEE) are provided for the MT8816 to enable switching of negative analog signals. The range for digital signals is from VDD to VSS while the range for analog signals is from VDD to VEE. VSS and VEE pins can be tied together if a single voltage reference is needed. The seven address inputs along with the STROBE and CS (Chip Select) are logically ANDed to form an enable signal for the resettable transparent latches. The DATA input is buffered and is used as the input to all latches. To write to a location, RESET must be low and CS must go high while the address and data are set up. Then the STROBE input is set high and then low causing the data to be latched. The data can be changed while STROBE is high, however, the corresponding switch will turn on and off in accordance with the DATA input. DATA must be stable on the falling edge of STROBE in order for correct data to be written to the latch. 3-47 MT8816 ISO-CMOS Absolute Maximum Ratings*- Voltages are with respect to VEE unless otherwise stated. Parameter Symbol Min Max Units 1 Supply Voltage VDD VSS -0.3 -0.3 16.0 VDD+0.3 V V 2 Analog Input Voltage VINA -0.3 VDD+0.3 V 3 Digital Input Voltage VIN VSS-0.3 VDD+0.3 V 4 Current on any I/O Pin 15 mA 5 Storage Temperature +150 C 6 Package Power Dissipation 0.6 W I TS PLASTIC DIP -65 PD * Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied. Recommended Operating Conditions - Voltages are with respect to VEE unless otherwise stated. Characteristics Sym Min Typ Max Units TO -40 25 85 C 1 Operating Temperature 2 Supply Voltage VDD VSS 4.5 VEE 13.2 VDD-4.5 V V 3 Analog Input Voltage VINA VEE VDD V 4 Digital Input Voltage VIN VSS VDD V DC Electrical CharacteristicsCharacteristics 1 Voltages are with respect to VEE=VSS=0V, VDD =12V unless otherwise stated. Sym Quiescent Supply Current Test Conditions Min IDD 2 Off-state Leakage Current (See G.9 in Appendix) IOFF 3 Input Logic "0" level VIL Typ Max Units Test Conditions 1 100 A All digital inputs at VIN=VSS or VDD 0.4 1.5 mA All digital inputs at VIN=2.4V + VSS; VSS=7.0V 5 15 mA All digital inputs at VIN=3.4V 1 500 nA IVXi - VYjI = VDD - VEE See Appendix, Fig. A.1 0.8+VS V VSS=7.5V; VEE=0V VSS=6.5V; VEE=0V S 4 Input Logic "1" level VIH 2.0+VSS V 5 Input Logic "1" level VIH 3.3 V 6 Input Leakage (digital pins) ILEAK 0.1 A 10 All digital inputs at VIN = VSS or VDD DC Electrical Characteristics are over recommended temperature range. Typical figures are at 25C and are for design aid only; not guaranteed and not subject to production testing. DC Electrical Characteristics- Switch Resistance - VDC is the external DC offset applied at the analog I/O pins. Characteristics Sym 25C Typ Max 70C Typ Max 85C Typ Units Test Conditions Max 1 On-state VDD=12V Resistance VDD=10V VDD= 5V (See G.1, G.2, G.3 in Appendix) RON 45 55 120 65 75 185 75 85 215 80 90 225 VSS=VEE=0V,VDC=VDD/2, IVXi-VYjI = 0.4V See Appendix, Fig. A.2 2 Difference in on-state resistance between two switches (See G.4 in Appendix) RON 5 10 10 10 VDD=12V, VSS=VEE=0, VDC=VDD/2, IVXi-VYjI = 0.4V See Appendix, Fig. A.2 3-48 MT8816 ISO-CMOS AC Electrical Characteristics - Crosspoint Performance-Voltages are with respect to VDD=5V, VSS=0V, VEE=-7V, unless otherwise stated. Characteristics 1 2 3 4 5 6 Switch I/O Capacitance Feedthrough Capacitance Frequency Response Channel "ON" 20LOG(VOUT/VXi)=-3dB Total Harmonic Distortion (See G.5, G.6 in Appendix) Feedthrough Channel "OFF" Feed.=20LOG (VOUT/VXi) (See G.8 in Appendix) Crosstalk between any two channels for switches Xi-Yi and Xj-Yj. Sym Min Typ Max Units CS CF F3dB 20 0.2 45 pF pF MHz THD 0.01 % FDT -95 dB Xtalk -45 dB -90 dB -85 dB -80 dB Xtalk=20LOG (VYj/VXi). (See G.7 in Appendix). 7 Propagation delay through switch tPS 30 ns Test Conditions f=1 MHz f=1 MHz Switch is "ON"; VINA = 2Vpp sinewave; RL = 1k See Appendix, Fig. A.3 Switch is "ON"; VINA = 2Vpp sinewave f= 1kHz; RL=1k All Switches "OFF"; VINA= 2Vpp sinewave f= 1kHz; RL= 1k. See Appendix, Fig. A.4 VINA=2Vpp sinewave f= 10MHz; RL = 75. VINA=2Vpp sinewave f= 10kHz; RL = 600. VINA=2Vpp sinewave f= 10kHz; RL = 1k. VINA=2Vpp sinewave f= 1kHz; RL = 10k. Refer to Appendix, Fig. A.5 for test circuit. RL=1k; CL=50pF Timing is over recommended temperature range. See Fig. 3 for control and I/O timing details. Typical figures are at 25C and are for design aid only; not guaranteed and not subject to production testing. Crosstalk measurements are for Plastic DIPS only, crosstalk values for PLCC packages are approximately 5dB better. AC Electrical Characteristics - Control and I/O Timings- Voltages are with respect to V =5V, V DD SS=0V, VEE=-7V, unless otherwise stated. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Characteristics Sym Control Input crosstalk to switch (for CS, DATA, STROBE, Address) Digital Input Capacitance Switching Frequency Setup Time DATA to STROBE Hold Time DATA to STROBE Setup Time Address to STROBE Hold Time Address to STROBE Setup Time CS to STROBE Hold Time CS to STROBE STROBE Pulse Width RESET Pulse Width STROBE to Switch Status Delay DATA to Switch Status Delay RESET to Switch Status Delay CXtalk CDI FO tDS tDH tAS tAH tCSS tCSH tSPW tRPW tS tD tR Min Typ Max Units Test Conditions 30 mVpp 10 pF MHz ns ns ns ns ns ns ns ns ns ns ns VIN=3V squarewave; RIN=1k, RL=10k. See Appendix, Fig. A.6 f=1MHz 20 10 10 10 10 10 10 20 40 40 50 35 100 100 100 RL= 1k, RL= 1k, RL= 1k, RL= 1k, RL= 1k, RL= 1k, RL= 1k, RL= 1k, RL= 1k, RL= 1k, RL= 1k, CL=50pF CL=50pF CL=50pF CL=50pF CL=50pF CL=50pF CL=50pF CL=50pF CL=50pF CL=50pF CL=50pF Timing is over recommended temperature range. See Fig. 3 for control and I/O timing details. Digital Input rise time (tr) and fall time (tf) = 5ns. Typical figures are at 25C and are for design aid only; not guaranteed and not subject to production testing. Refer to Appendix, Fig. A.7 for test circuit. 3-49 MT8816 ISO-CMOS tCSS tCSH 50% 50% tRPW CS 50% RESET 50% tSPW STROBE 50% 50% 50% tAS ADDRESS 50% 50% tAH DATA 50% 50% tDS tDH ON SWITCH* OFF tR tS tD tR Figure 3 - Control Memory Timing Diagram * See Appendix, Fig. A.7 for switching waveform AX0 AX1 AX2 AX3 AY0 AY1 AY2 Connection* 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 X0-Y0 X1-Y0 X2-Y0 X3-Y0 X4-Y0 X5-Y0 X12-Y0 X13-Y0 X6-Y0 X7-Y0 X8-Y0 X9-Y0 X10-Y0 X11-Y0 X14-Y0 X15-Y0 0 0 0 0 1 0 0 X0-Y1 1 1 1 1 1 0 0 X15-Y1 0 0 0 0 0 1 0 X0-Y2 1 1 1 1 0 1 0 X15-Y2 0 0 0 0 1 1 0 X0-Y3 1 1 1 1 1 1 0 X15-Y3 0 0 0 0 0 0 1 X0-Y4 1 1 1 1 0 0 1 X15-Y4 0 0 0 0 1 0 1 X0-Y5 1 1 1 1 1 0 1 X15-Y5 0 0 0 0 0 1 1 X0-Y6 1 1 1 1 0 1 1 X15-Y6 0 0 0 0 1 1 1 X0-Y7 1 1 1 1 1 1 1 X15-Y7 Table 1. Address Decode Truth Table * Switch connections are not in ascending order 3-50 MT8816 3-51 ISO-CMOS Package Outlines 3 2 1 E1 E n-2 n-1 n D A2 A L C eA b2 e eC eB b Notes: D1 1) Not to scale 2) Dimensions in inches 3) (Dimensions in millimeters) Plastic Dual-In-Line Packages (PDIP) - E Suffix DIM 8-Pin 16-Pin 18-Pin 20-Pin Plastic Plastic Plastic Plastic Min A Max Min 0.210 (5.33) Max Min 0.210 (5.33) Max Min 0.210 (5.33) Max 0.210 (5.33) A2 0.115 (2.92) 0.195 (4.95) 0.115 (2.92) 0.195 (4.95) 0.115 (2.92) 0.195 (4.95) 0.115 (2.92) 0.195 (4.95) b 0.014 (0.356) 0.022 (0.558) 0.014 (0.356) 0.022 (0.558) 0.014 (0.356) 0.022 (0.558) 0.014 (0.356) 0.022 (0.558) b2 0.045 (1.14) 0.070 (1.77) 0.045 (1.14) 0.070 (1.77) 0.045 (1.14) 0.070 (1.77) 0.045 (1.14) 0.070 (1.77) C 0.008 (0.203) 0.014 (0.356) 0.008 (0.203) 0.014(0.356) 0.008 (0.203) 0.014 (0.356) 0.008 (0.203) 0.014 (0.356) D 0.355 (9.02) 0.400 (10.16) 0.780 (19.81) 0.800 (20.32) 0.880 (22.35) 0.920 (23.37) 0.980 (24.89) 1.060 (26.9) D1 0.005 (0.13) E 0.300 (7.62) 0.325 (8.26) 0.300 (7.62) 0.325 (8.26) 0.300 (7.62) 0.325 (8.26) 0.300 (7.62) 0.325 (8.26) E1 0.240 (6.10) 0.280 (7.11) 0.240 (6.10) 0.280 (7.11) 0.240 (6.10) 0.280 (7.11) 0.240 (6.10) 0.280 (7.11) 0.005 (0.13) 0.005 (0.13) 0.005 (0.13) e 0.100 BSC (2.54) 0.100 BSC (2.54) 0.100 BSC (2.54) 0.100 BSC (2.54) eA 0.300 BSC (7.62) 0.300 BSC (7.62) 0.300 BSC (7.62) 0.300 BSC (7.62) L 0.115 (2.92) eB eC 0.150 (3.81) 0.115 (2.92) 0.430 (10.92) 0 0.060 (1.52) 0.150 (3.81) 0.430 (10.92) 0 0.060 (1.52) NOTE: Controlling dimensions in parenthesis ( ) are in millimeters. General-8 0.115 (2.92) 0.150 (3.81) 0.115 (2.92) 0.430 (10.92) 0 0.060 (1.52) 0.150 (3.81) 0.430 (10.92) 0 0.060 (1.52) Package Outlines 3 2 1 E1 E n-2 n-1 n D A2 A L C eA b2 e eB b Notes: D1 1) Not to scale 2) Dimensions in inches 3) (Dimensions in millimeters) Plastic Dual-In-Line Packages (PDIP) - E Suffix DIM 22-Pin 24-Pin 28-Pin 40-Pin Plastic Plastic Plastic Plastic Min A Max Min 0.210 (5.33) Max Min 0.250 (6.35) Max Min 0.250 (6.35) Max 0.250 (6.35) A2 0.125 (3.18) 0.195 (4.95) 0.125 (3.18) 0.195 (4.95) 0.125 (3.18) 0.195 (4.95) 0.125 (3.18) 0.195 (4.95) b 0.014 (0.356) 0.022 (0.558) 0.014 (0.356) 0.022 (0.558) 0.014 (0.356) 0.022 (0.558) 0.014 (0.356) 0.022 (0.558) b2 0.045 (1.15) 0.070 (1.77) 0.030 (0.77) 0.070 (1.77) 0.030 (0.77) 0.070 (1.77) 0.030 (0.77) 0.070 (1.77) C 0.008 (0.204) 0.015 (0.381) 0.008 (0.204) 0.015 (0.381) 0.008 (0.204) 0.015 (0.381) 0.008 (0.204) 0.015 (0.381) D 1.050 (26.67) 1.120 (28.44) 1.150 (29.3) 1.290 (32.7) 1.380 (35.1) 1.565 (39.7) 1.980 (50.3) 2.095 (53.2) D1 0.005 (0.13) E 0.390 (9.91) 0.005 (0.13) 0.430 (10.92) E E1 0.330 (8.39) 0.380 (9.65) E1 0.005 (0.13) 0.600 (15.24) 0.670 (17.02) 0.290 (7.37) .330 (8.38) 0.485 (12.32) 0.580 (14.73) 0.246 (6.25) 0.254 (6.45) 0.005 (0.13) 0.600 (15.24) 0.670 (17.02) 0.600 (15.24) 0.670 (17.02) 0.485 (12.32) 0.580 (14.73) 0.485 (12.32) 0.580 (14.73) e 0.100 BSC (2.54) 0.100 BSC (2.54) 0.100 BSC (2.54) 0.100 BSC (2.54) eA 0.400 BSC (10.16) 0.600 BSC (15.24) 0.600 BSC (15.24) 0.600 BSC (15.24) eA 0.300 BSC (7.62) eB L 0.430 (10.92) 0.115 (2.93) 0.160 (4.06) 0.115 (2.93) 0.200 (5.08) 15 Shaded areas for 300 Mil Body Width 24 PDIP only 15 0.115 (2.93) 0.200 (5.08) 15 0.115 (2.93) 0.200 (5.08) 15 Package Outlines F A G D1 D2 D H E E1 e: (lead coplanarity) A1 Notes: 1) Not to scale 2) Dimensions in inches 3) (Dimensions in millimeters) 4) For D & E add for allowable Mold Protrusion 0.010" I E2 20-Pin 28-Pin 44-Pin 68-Pin 84-Pin Dim Min Max Min Max Min Max Min Max Min Max A 0.165 (4.20) 0.180 (4.57) 0.165 (4.20) 0.180 (4.57) 0.165 (4.20) 0.180 (4.57) 0.165 (4.20) 0.200 (5.08) 0.165 (4.20) 0.200 (5.08) A1 0.090 (2.29) 0.120 (3.04) 0.090 (2.29) 0.120 (3.04) 0.090 (2.29) 0.120 (3.04) 0.090 (2.29) 0.130 (3.30) 0.090 (2.29) 0.130 (3.30) D/E 0.385 (9.78) 0.395 (10.03) 0.485 (12.32) 0.495 (12.57) 0.685 (17.40) 0.695 (17.65) 0.985 (25.02) 0.995 (25.27) 1.185 (30.10) 1.195 (30.35) D1/E1 0.350 (8.890) 0.356 0.450 0.456 0.650 0.656 0.950 0.958 1.150 1.158 (9.042) (11.430) (11.582) (16.510) (16.662) (24.130) (24.333) (29.210) (29.413) D2/E2 0.290 (7.37) 0.330 (8.38) 0.390 (9.91) 0.430 (10.92) 0.590 (14.99) 0.630 (16.00) 0.890 (22.61) 0.930 (23.62) 1.090 (27.69) 1.130 (28.70) e 0 0.004 0 0.004 0 0.004 0 0.004 0 0.004 F 0.026 (0.661) 0.032 (0.812) 0.026 (0.661) 0.032 (0.812) 0.026 (0.661) 0.032 (0.812) 0.026 (0.661) 0.032 (0.812) 0.026 (0.661) 0.032 (0.812) G 0.013 (0.331) 0.021 (0.533) 0.013 (0.331) 0.021 (0.533) 0.013 (0.331) 0.021 (0.533) 0.013 (0.331) 0.021 (0.533) 0.013 (0.331) 0.021 (0.533) H I 0.050 BSC (1.27 BSC) 0.020 (0.51) 0.050 BSC (1.27 BSC) 0.020 (0.51) 0.050 BSC (1.27 BSC) 0.020 (0.51) Plastic J-Lead Chip Carrier - P-Suffix General-10 0.050 BSC (1.27 BSC) 0.020 (0.51) 0.050 BSC (1.27 BSC) 0.020 (0.51) For more information about all Zarlink products visit our Web Site at www.zarlink.com Information relating to products and services furnished herein by Zarlink Semiconductor Inc. trading as Zarlink Semiconductor or its subsidiaries (collectively "Zarlink") is believed to be reliable. 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