3-45
MT8816
8 x 16 Analog Switch Array
Features
• Internal control latches and address decoder
• Short set-up and hold times
• Wide operating voltage: 4.5V to 13.2V
• 12Vpp analog signal capability
•R
ON
65
Ω
max. @ V
DD
=12V, 25
°
C
•
∆
R
ON
≤
10
Ω
@ V
DD
=12V, 25
°
C
• Full CMOS switch for low distortion
• Minimum feedthrough and crosstalk
• Separate analog and digital reference supplies
• Low power consumption ISO-CMOS technology
Applications
• Key systems
• PBX systems
• Mobile radio
• Test equipment/instrumentation
• Analog/digital multiplexers
• Audio/Video switching
Description
The Zarlink MT8816 is fabricated in Zarlink’s ISO-
CMOS technology providing low power dissipation
and high reliability. The device contains a 8 x 16
array of crosspoint switches along with a 7 to 128
line decoder and latch circuits. Any one of the 128
switches can be addressed by selecting the
appropriate seven address bits. The selected switch
can be turned on or off by applying a logical one or
zero to the DATA input. V
SS
is the ground refer-ence
of the digital inputs. The range of the analog signal
is from V
DD
to V
EE
. Chip Select (CS) allows the
crosspoint array to be cascaded for matrix
expansion.
Ordering Information
MT8816AE 40 Pin Plastic DIP
MT8816AP 44 Pin PLCC
-
40
°
to 85
°
C
Figure 1 - Functional Block Diagram
7 to 128
Decoder Latches
8 x 16
Switch
Array
CS STROBE DATA RESET VDD VEE VSS
Xi I/O
(i=0-15)
Yi I/O (i=0-7)
11
128128
• • • • • • • • • • • • • • • • • • •
• • • • • • • • • • • • • • • •
AX0
AX1
AY0
AY1
AY2
AX2
AX3
ISSUE3 March 1997
ISO-CMOS
MT8816
ISO-CMOS
3-46
Figure 2 - Pin Connections
Pin Description
Pin #
Name Description
PDIP PLCC
11Y3
Y3 Analog (Input/Output):
this is connected to the Y3 column of the switch array.
22AY2
Y2 Address Line (Input)
.
3 3 RESET
Master RESET (Input):
this is used to turn off all switches regardless of the
condition of CS. Active High.
4,5 4,5 AX3,AX0
X3 and X0 Address Lines (Inputs)
.
6,7 7,8 X14, X15
X14 and X15 Analog (Inputs/Outputs):
these are connected to the X14 and X15
rows of the switch array.
8-13 9-14 X6-X11
X6-X11 Analog (Inputs/Outputs):
these are connected to the X6-X11 rows of the
switch array.
14 6,15,16 NC
No Connection
15 17 Y7
Y7 Analog (Input/Output):
this is connected to the Y7 column of the switch array.
16 18 V
SS
Digital Ground Reference.
17 19 Y6
Y6 Analog (Input/Output):
this is connected to the Y6 column of the switch array.
18 20 STROBE
STROBE (Input)
: enables function selected by address and data. Address must
be stable before STROBE goes high and DATA must be stable on the falling edge
of the STROBE. Active High.
19 21 Y5
Y5 Analog (Input/Output):
this is connected to the Y5 column of the switch array.
20 22 V
EE
Negative Power Supply.
21 23 Y4
Y4 Analog (Input/Output):
this is connected to the Y4 column of the switch array.
22, 23 24,25 AX1,AX2
X1 and X2 Address Lines (Inputs)
.
24, 25 26,27 AY0,AY1
Y0 and Y1 Address Lines (Inputs)
.
26, 27 30,31 X13, X12
X13 and X12 Analog (Inputs/Outputs):
these are connected to the X13 and X12
rows of the switch array.
40 PIN PLASTIC DIP 44 PIN PLCC
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
140
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
AY2
RESET
AX3
AX0
X14
X15
X6
X7
X8
X9
X10
X11
NC
Y7
VSS
Y6
STROBE
Y5
VEE
Y3
Y2
DATA
Y1
CS
Y0
NC
X0
X1
X2
X3
X4
X5
X12
X13
AY1
AY0
AX2
AX1
Y4
VDD
X14
X15
X6
X7
X8
X9
X10
X11
NC
NC
Y7
VSS
Y6
STROBE
Y5
VEE
AX1
AX2
AY0
AY1
NC
Y4
1
65432 44434241
40
7
8
9
10
11
12
13
14
15
16
39
38
37
36
35
34
33
32
31
30
2318 19 20 21 22 24 25 26 27 28
17 29
Y0
NC
X0
X1
X2
X3
X4
X5
X12
X13
NC
CS
Y1
DATA
Y2
VDD
Y3
AY2
RESET
AX3
AX0
NC
ISO-CMOS
MT8816
3-47
28 - 33 32-37 X5-X0
X5-X0 Analog (Inputs/Outputs):
these are connected to the X5-X0 rows of the
switch array.
34 28,29,
38
NC
No Connection.
35 39 Y0
Y0 Analog (Input/Output)
: this is connected to the Y0 column of the switch array.
36 40 CS
Chip Select (Input)
: this is used to select the device. Active High.
37 41 Y1
Y1 Analog (Input/Output)
: this is connected to the Y1 column of the switch array.
38 42 DATA
DATA (Input)
: a logic high input will turn on the selected switch and a logic low will
turn off the selected switch. Active High.
39 43 Y2
Y2 Analog (Input/Output)
: this is connected to the Y2 column of the switch array.
40 44 V
DD
Positive Power Supply.
Pin Description (continued)
Pin #
Name Description
PDIP PLCC
Functional Description
The MT8816 is an analog switch matrix with an array
size of 8 x 16. The switch array is arranged such that
there are 8 columns by 16 rows. The columns are
referred to as the Y inputs/outputs and the rows are
the X inputs/outputs. The crosspoint analog switch
array will interconnect any X I/O with any Y I/O when
turned on and provide a high degree of isolation
when turned off. The control memory consists of a
128 bit write only RAM in which the bits are selected
by the address inputs (AY0-AY2, AX0-AX3). Data is
presented to the memory on the DATA input. Data is
asynchronously written into memory whenever both
the CS (Chip Select) and STROBE inputs are high
and are latched on the falling edge of STROBE. A
logical “1” written into a memory cell turns the
corresponding crosspoint switch on and a logical “0”
turns the crosspoint off. Only the crosspoint switches
corresponding to the addressed memory location are
altered when data is written into memory. The
remaining switches retain their previous states. Any
combination of X and Y inputs/outputs can be
interconnected by establishing appropriate patterns
in the control memory. A logical “1” on the RESET
input will asynchronously return all memory locations
to logical “0” turning off all crosspoint
switches regardless of whether CS is high or low.
Two voltage reference pins (V
SS
and V
EE
) are
provided for the MT8816 to enable switching of
negative analog signals. The range for digital signals
is from V
DD
to V
SS
while the range for analog signals
is from V
DD
to V
EE
. V
SS
and V
EE
pins can be tied
together if a single voltage reference is needed.
Address Decode
The seven address inputs along with the STROBE
and CS (Chip Select) are logically ANDed to form an
enable signal for the resettable transparent latches.
The DATA input is buffered and is used as the input
to all latches. To write to a location, RESET must be
low and CS must go high while the address and data
are set up. Then the STROBE input is set high and
then low causing the data to be latched. The data
can be changed while STROBE is high, however, the
corresponding switch will turn on and off in
accordance with the DATA input. DATA must be
stable on the falling edge of STROBE in order for
correct data to be written to the latch.
MT8816
ISO-CMOS
3-48
* Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied.
† DC Electrical Characteristics are over recommended temperature range.
‡ Typical figures are at 25
°
C and are for design aid only; not guaranteed and not subject to production testing.
Absolute Maximum Ratings
*
- Voltages are with respect to V
EE
unless otherwise stated.
Parameter Symbol Min Max Units
1 Supply Voltage V
DD
V
SS
-0.3
-0.3
16.0
V
DD
+0.3
V
V
2 Analog Input Voltage V
INA
-0.3 V
DD
+0.3 V
3 Digital Input Voltage V
IN
V
SS
-0.3 V
DD
+0.3 V
4 Current on any I/O Pin I
±
15 mA
5 Storage Temperature T
S
-65 +150
°
C
6 Package Power Dissipation PLASTIC DIP P
D
0.6 W
Recommended Operating Conditions
- Voltages are with respect to V
EE
unless otherwise stated.
Characteristics Sym Min Typ Max Units Test Conditions
1 Operating Temperature T
O
-40 25 85
°
C
2 Supply Voltage V
DD
V
SS
4.5
V
EE
13.2
V
DD
-4.5
V
V
3 Analog Input Voltage V
INA
V
EE
V
DD
V
4 Digital Input Voltage V
IN
V
SS
V
DD
V
DC Electrical Characteristics
†
-
Voltages are with respect to V
EE
=V
SS
=0V, V
DD
=12V unless otherwise stated.
Characteristics Sym Min Typ
‡
Max Units Test Conditions
1 Quiescent Supply Current I
DD
1 100
µA All digital inputs at VIN=VSS or
VDD
0.4 1.5 mA All digital inputs at VIN=2.4V +
VSS; VSS=7.0V
5 15 mA All digital inputs at VIN=3.4V
2 Off-state Leakage Current
(See G.9 in Appendix)
IOFF ±1±500 nA IVXi - VYjI = VDD - VEE
See Appendix, Fig. A.1
3 Input Logic “0” level VIL 0.8+VS
S
VV
SS=7.5V; VEE=0V
4 Input Logic “1” level VIH 2.0+VSS VV
SS=6.5V; VEE=0V
5 Input Logic “1” level VIH 3.3 V
6 Input Leakage (digital pins) ILEAK 0.1 10 µA All digital inputs at VIN = VSS
or VDD
DC Electrical Characteristics- Switch Resistance - VDC is the external DC offset applied at the analog I/O pins.
Characteristics Sym 25°C70°C85°C Units Test Conditions
Typ Max Typ Max Typ Max
1 On-state VDD=12V
Resistance VDD=10V
VDD= 5V
(See G.1, G.2, G.3 in
Appendix)
RON 45
55
120
65
75
185
75
85
215
80
90
225
Ω
Ω
Ω
VSS=VEE=0V,VDC=VDD/2,
IVXi-VYjI = 0.4V
See Appendix, Fig. A.2
2 Difference in on-state
resistance between two
switches
(See G.4 in Appendix)
∆RON 510 10 10 ΩVDD=12V, VSS=VEE=0,
VDC=VDD/2,
IVXi-VYjI = 0.4V
See Appendix, Fig. A.2
ISO-CMOS MT8816
3-49
† Timing is over recommended temperature range. See Fig. 3 for control and I/O timing details.
‡ Typical figures are at 25°C and are for design aid only; not guaranteed and not subject to production testing.
Crosstalk measurements are for Plastic DIPS only, crosstalk values for PLCC packages are approximately 5dB better.
† Timing is over recommended temperature range. See Fig. 3 for control and I/O timing details.
Digital Input rise time (tr) and fall time (tf) = 5ns.
‡ Typical figures are at 25°C and are for design aid only; not guaranteed and not subject to production testing.
➀ Refer to Appendix, Fig. A.7 for test circuit.
AC Electrical Characteristics† - Crosspoint Performance-Voltages are with respect to VDD=5V, VSS=0V,
VEE=-7V, unless otherwise stated.
Characteristics Sym Min Typ‡Max Units Test Conditions
1 Switch I/O Capacitance CS20 pF f=1 MHz
2 Feedthrough Capacitance CF0.2 pF f=1 MHz
3 Frequency Response
Channel “ON”
20LOG(VOUT/VXi)=-3dB
F3dB 45 MHz Switch is “ON”; VINA = 2Vpp
sinewave; RL = 1kΩ
See Appendix, Fig. A.3
4 Total Harmonic Distortion
(See G.5, G.6 in Appendix)
THD 0.01 % Switch is “ON”; VINA = 2Vpp
sinewave f= 1kHz; RL=1kΩ
5 Feedthrough
Channel “OFF”
Feed.=20LOG (VOUT/VXi)
(See G.8 in Appendix)
FDT -95 dB All Switches “OFF”; VINA=
2Vpp sinewave f= 1kHz;
RL= 1kΩ.
See Appendix, Fig. A.4
6 Crosstalk between any two
channels for switches Xi-Yi and
Xj-Yj.
Xtalk=20LOG (VYj/VXi).
(See G.7 in Appendix).
Xtalk -45 dB VINA=2Vpp sinewave
f= 10MHz; RL = 75Ω.
-90 dB VINA=2Vpp sinewave
f= 10kHz; RL = 600Ω.
-85 dB VINA=2Vpp sinewave
f= 10kHz; RL = 1kΩ.
-80 dB VINA=2Vpp sinewave
f= 1kHz; RL = 10kΩ.
Refer to Appendix, Fig. A.5
for test circuit.
7 Propagation delay through
switch
tPS 30 ns RL=1kΩ; CL=50pF
AC Electrical Characteristics† - Control and I/O Timings- Voltages are with respect to VDD=5V, VSS=0V,
VEE=-7V, unless otherwise stated.
Characteristics Sym Min Typ‡Max Units Test Conditions
1 Control Input crosstalk to switch
(for CS, DATA, STROBE,
Address)
CXtalk 30 mVpp VIN=3V squarewave;
RIN=1kΩ, RL=10kΩ.
See Appendix, Fig. A.6
2 Digital Input Capacitance CDI 10 pF f=1MHz
3 Switching Frequency FO20 MHz
4 Setup Time DATA to STROBE tDS 10 ns RL= 1kΩ, CL=50pF ➀
5 Hold Time DATA to STROBE tDH 10 ns RL= 1kΩ, CL=50pF ➀
6 Setup Time Address to STROBE tAS 10 ns RL= 1kΩ, CL=50pF ➀
7 Hold Time Address to STROBE tAH 10 ns RL= 1kΩ, CL=50pF ➀
8 Setup Time CS to STROBE tCSS 10 ns RL= 1kΩ, CL=50pF ➀
9 Hold Time CS to STROBE tCSH 10 ns RL= 1kΩ, CL=50pF ➀
10 STROBE Pulse Width tSPW 20 ns RL= 1kΩ, CL=50pF ➀
11 RESET Pulse Width tRPW 40 ns RL= 1kΩ, CL=50pF ➀
12 STROBE to Switch Status Delay tS40 100 ns RL= 1kΩ, CL=50pF ➀
13 DATA to Switch Status Delay tD50 100 ns RL= 1kΩ, CL=50pF ➀
14 RESET to Switch Status Delay tR35 100 ns RL= 1kΩ, CL=50pF ➀
MT8816 ISO-CMOS
3-50
Figure 3 - Control Memory Timing Diagram
* See Appendix, Fig. A.7 for switching waveform
Table 1. Address Decode Truth Table
* Switch connections are not in ascending order
AX0 AX1 AX2 AX3 AY0 AY1 AY2 Connection*
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
X0-Y0
X1-Y0
X2-Y0
X3-Y0
X4-Y0
X5-Y0
X12-Y0
X13-Y0
X6-Y0
X7-Y0
X8-Y0
X9-Y0
X10-Y0
X11-Y0
X14-Y0
X15-Y0
0
↓
1
0
↓
1
0
↓
1
0
↓
1
1
↓
1
0
↓
0
0
↓
0
X0-Y1
↓ ↓
X15-Y1
0
↓
1
0
↓
1
0
↓
1
0
↓
1
0
↓
0
1
↓
1
0
↓
0
X0-Y2
↓ ↓
X15-Y2
0
↓
1
0
↓
1
0
↓
1
0
↓
1
1
↓
1
1
↓
1
0
↓
0
X0-Y3
↓ ↓
X15-Y3
0
↓
1
0
↓
1
0
↓
1
0
↓
1
0
↓
0
0
↓
0
1
↓
1
X0-Y4
↓ ↓
X15-Y4
0
↓
1
0
↓
1
0
↓
1
0
↓
1
1
↓
1
0
↓
0
1
↓
1
X0-Y5
↓ ↓
X15-Y5
0
↓
1
0
↓
1
0
↓
1
0
↓
1
0
↓
0
1
↓
1
1
↓
1
X0-Y6
↓ ↓
X15-Y6
0
↓
1
0
↓
1
0
↓
1
0
↓
1
1
↓
1
1
↓
1
1
↓
1
X0-Y7
↓ ↓
X15-Y7
tCSS tCSH
tRPW
tSPW
tAS
tAH
tDH
tDtStRtR
tDS
50% 50%
50% 50%
50%50%50%
50% 50%
50% 50%
CS
RESET
STROBE
ADDRESS
DATA
SWITCH*
ON
OFF
MT8816 ISO-CMOS
3-51
Package Outlines
Plastic Dual-In-Line Packages (PDIP) - E Suffix
NOTE: Controlling dimensions in parenthesis ( ) are in millimeters.
DIM
8-Pin 16-Pin 18-Pin 20-Pin
Plastic Plastic Plastic Plastic
Min Max Min Max Min Max Min Max
A0.210 (5.33) 0.210 (5.33) 0.210 (5.33) 0.210 (5.33)
A20.115 (2.92) 0.195 (4.95) 0.115 (2.92) 0.195 (4.95) 0.115 (2.92) 0.195 (4.95) 0.115 (2.92) 0.195 (4.95)
b0.014 (0.356) 0.022 (0.558) 0.014 (0.356) 0.022 (0.558) 0.014 (0.356) 0.022 (0.558) 0.014 (0.356) 0.022 (0.558)
b20.045 (1.14) 0.070 (1.77) 0.045 (1.14) 0.070 (1.77) 0.045 (1.14) 0.070 (1.77) 0.045 (1.14) 0.070 (1.77)
C0.008
(0.203) 0.014 (0.356) 0.008 (0.203) 0.014(0.356) 0.008 (0.203) 0.014 (0.356) 0.008 (0.203) 0.014 (0.356)
D0.355 (9.02) 0.400 (10.16) 0.780 (19.81) 0.800 (20.32) 0.880 (22.35) 0.920 (23.37) 0.980 (24.89) 1.060 (26.9)
D10.005 (0.13) 0.005 (0.13) 0.005 (0.13) 0.005 (0.13)
E0.300 (7.62) 0.325 (8.26) 0.300 (7.62) 0.325 (8.26) 0.300 (7.62) 0.325 (8.26) 0.300 (7.62) 0.325 (8.26)
E10.240 (6.10) 0.280 (7.11) 0.240 (6.10) 0.280 (7.11) 0.240 (6.10) 0.280 (7.11) 0.240 (6.10) 0.280 (7.11)
e0.100 BSC (2.54) 0.100 BSC (2.54) 0.100 BSC (2.54) 0.100 BSC (2.54)
eA0.300 BSC (7.62) 0.300 BSC (7.62) 0.300 BSC (7.62) 0.300 BSC (7.62)
L0.115 (2.92) 0.150 (3.81) 0.115 (2.92) 0.150 (3.81) 0.115 (2.92) 0.150 (3.81) 0.115 (2.92) 0.150 (3.81)
eB0.430 (10.92) 0.430 (10.92) 0.430 (10.92) 0.430 (10.92)
eC0 0.060 (1.52) 0 0.060 (1.52) 0 0.060 (1.52) 0 0.060 (1.52)
E1
321
E
n-2 n-1 n
L
D
D1
b2
A2
e
b
C
eA
Notes:
1) Not to scale
2) Dimensions in inches
3) (Dimensions in millimeters)
A
eB
eC
General-8
Package Outlines
Plastic Dual-In-Line Packages (PDIP) - E Suffix
DIM
22-Pin 24-Pin 28-Pin 40-Pin
Plastic Plastic Plastic Plastic
Min Max Min Max Min Max Min Max
A0.210 (5.33) 0.250 (6.35) 0.250 (6.35) 0.250 (6.35)
A20.125 (3.18) 0.195 (4.95) 0.125 (3.18) 0.195 (4.95) 0.125 (3.18) 0.195 (4.95) 0.125 (3.18) 0.195 (4.95)
b0.014 (0.356) 0.022 (0.558) 0.014 (0.356) 0.022 (0.558) 0.014 (0.356) 0.022 (0.558) 0.014 (0.356) 0.022 (0.558)
b20.045 (1.15) 0.070 (1.77) 0.030 (0.77) 0.070 (1.77) 0.030 (0.77) 0.070 (1.77) 0.030 (0.77) 0.070 (1.77)
C0.008 (0.204) 0.015 (0.381) 0.008 (0.204) 0.015 (0.381) 0.008 (0.204) 0.015 (0.381) 0.008 (0.204) 0.015 (0.381)
D1.050 (26.67) 1.120 (28.44) 1.150 (29.3) 1.290 (32.7) 1.380 (35.1) 1.565 (39.7) 1.980 (50.3) 2.095 (53.2)
D10.005 (0.13) 0.005 (0.13) 0.005 (0.13) 0.005 (0.13)
E0.390 (9.91) 0.430 (10.92) 0.600 (15.24) 0.670 (17.02) 0.600 (15.24) 0.670 (17.02) 0.600 (15.24) 0.670 (17.02)
E0.290 (7.37) .330 (8.38)
E10.330 (8.39) 0.380 (9.65) 0.485 (12.32) 0.580 (14.73) 0.485 (12.32) 0.580 (14.73) 0.485 (12.32) 0.580 (14.73)
E10.246 (6.25) 0.254 (6.45)
e0.100 BSC (2.54) 0.100 BSC (2.54) 0.100 BSC (2.54) 0.100 BSC (2.54)
eA0.400 BSC (10.16) 0.600 BSC (15.24) 0.600 BSC (15.24) 0.600 BSC (15.24)
eA0.300 BSC (7.62)
eB0.430 (10.92)
L0.115 (2.93) 0.160 (4.06) 0.115 (2.93) 0.200 (5.08) 0.115 (2.93) 0.200 (5.08) 0.115 (2.93) 0.200 (5.08)
α15°15°15°15°
E1
321
E
n-2 n-1 n
L
D
D1
b2
A2
e
b
C
eA
Notes:
1) Not to scale
2) Dimensions in inches
3) (Dimensions in millimeters)
A
eB
α
Shaded areas for 300 Mil Body Width 24 PDIP only
Package Outlines
Plastic J-Lead Chip Carrier - P-Suffix
F
D1D
H
E1
I
A1
A
G
D2
E
E2
Dim 20-Pin 28-Pin 44-Pin 68-Pin 84-Pin
Min Max Min Max Min Max Min Max Min Max
A0.165
(4.20) 0.180
(4.57) 0.165
(4.20) 0.180
(4.57) 0.165
(4.20) 0.180
(4.57) 0.165
(4.20) 0.200
(5.08) 0.165
(4.20) 0.200
(5.08)
A10.090
(2.29) 0.120
(3.04) 0.090
(2.29) 0.120
(3.04) 0.090
(2.29) 0.120
(3.04) 0.090
(2.29) 0.130
(3.30) 0.090
(2.29) 0.130
(3.30)
D/E 0.385
(9.78) 0.395
(10.03) 0.485
(12.32) 0.495
(12.57) 0.685
(17.40) 0.695
(17.65) 0.985
(25.02) 0.995
(25.27) 1.185
(30.10) 1.195
(30.35)
D1/E10.350
(8.890) 0.356
(9.042) 0.450
(11.430) 0.456
(11.582) 0.650
(16.510) 0.656
(16.662) 0.950
(24.130) 0.958
(24.333) 1.150
(29.210) 1.158
(29.413)
D2/E20.290
(7.37) 0.330
(8.38) 0.390
(9.91) 0.430
(10.92) 0.590
(14.99) 0.630
(16.00) 0.890
(22.61) 0.930
(23.62) 1.090
(27.69) 1.130
(28.70)
e0 0.004 0 0.004 0 0.004 0 0.004 0 0.004
F0.026
(0.661) 0.032
(0.812) 0.026
(0.661) 0.032
(0.812) 0.026
(0.661) 0.032
(0.812) 0.026
(0.661) 0.032
(0.812) 0.026
(0.661) 0.032
(0.812)
G0.013
(0.331) 0.021
(0.533) 0.013
(0.331) 0.021
(0.533) 0.013
(0.331) 0.021
(0.533) 0.013
(0.331) 0.021
(0.533) 0.013
(0.331) 0.021
(0.533)
H0.050 BSC
(1.27 BSC) 0.050 BSC
(1.27 BSC) 0.050 BSC
(1.27 BSC) 0.050 BSC
(1.27 BSC) 0.050 BSC
(1.27 BSC)
I0.020
(0.51) 0.020
(0.51) 0.020
(0.51) 0.020
(0.51) 0.020
(0.51)
Notes:
1) Not to scale
2) Dimensions in inches
3) (Dimensions in millimeters)
4) For D & E add for allowable Mold Protrusion 0.010"
e: (lead coplanarity)
General-10
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