SN54160 THRU SN54163, SN54LS160A THRU SN54LS163A, SN54S162, SN54S163, SN74160 THRU SN74163, SN74LS160A THRU SN74LS163A, SN74S162, SN74S163 SYNCHRONOUS 4-BIT COUNTERS SDLS060 - OCTOBER 1976 - REVISED MARCH 1988 Copyright 1988, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 1 SN54160 THRU SN54163, SN54LS160A THRU SN54LS163A, SN54S162, SN54S163, SN74160 THRU SN74163, SN74LS160A THRU SN74LS163A, SN74S162, SN74S163 SYNCHRONOUS 4-BIT COUNTERS SDLS060 - OCTOBER 1976 - REVISED MARCH 1988 2 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 SN54LS160A THRU SN54LS163A, SN54S162, SN54S163, SN74LS160A THRU SN74LS163A, SN74S162, SN74S163 SYNCHRONOUS 4-BIT COUNTERS SDLS060 - OCTOBER 1976 - REVISED MARCH 1988 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 3 SN54160, SN54162, SN74160, SN74162 SYNCHRONOUS 4-BIT COUNTERS SDLS060 - OCTOBER 1976 - REVISED MARCH 1988 4 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 SN54161, SN54163, SN74161, SN74163 SYNCHRONOUS 4-BIT COUNTERS SDLS060 - OCTOBER 1976 - REVISED MARCH 1988 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 5 SN54LS160A, SN54LS162A, SN74LS160A, SN74LS162A SYNCHRONOUS 4-BIT COUNTERS SDLS060 - OCTOBER 1976 - REVISED MARCH 1988 6 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 SN54LS161A, SN54LS163A, SN74LS161A, SN74LS163A SYNCHRONOUS 4-BIT COUNTERS SDLS060 - OCTOBER 1976 - REVISED MARCH 1988 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 7 SN54S162, SN74S162 SYNCHRONOUS 4-BIT COUNTERS SDLS060 - OCTOBER 1976 - REVISED MARCH 1988 8 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 SN54S163, SN74S163 SYNCHRONOUS 4-BIT COUNTERS SDLS060 - OCTOBER 1976 - REVISED MARCH 1988 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 9 SN54160, SN54162, SN54LS160A, SN54LS162A, SN54S162, SN74160, SN74162, SN74LS160A, SN74LS162A, SN74S162 SYNCHRONOUS 4-BIT COUNTERS SDLS060 - OCTOBER 1976 - REVISED MARCH 1988 10 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 SN54161, SN54163, SN54LS161A, SN54LS163A, SN54S163, SN74161, SN74163, SN74LS161A, SN74LS163A, SN74S163 SYNCHRONOUS 4-BIT COUNTERS SDLS060 - OCTOBER 1976 - REVISED MARCH 1988 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 11 SN54160 THRU SN54163, SN74160 THRU SN74163 SYNCHRONOUS 4-BIT COUNTERS SDLS060 - OCTOBER 1976 - REVISED MARCH 1988 12 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 SN54160 THRU SN54163, SN74160 THRU SN74163 SYNCHRONOUS 4-BIT COUNTERS SDLS060 - OCTOBER 1976 - REVISED MARCH 1988 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 13 SN54LS160 THRU SN54LS163A, SN74LS160 THRU SN74LS163A SYNCHRONOUS 4-BIT COUNTERS SDLS060 - OCTOBER 1976 - REVISED MARCH 1988 14 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 SN54LS160 THRU SN54LS163A, SN74LS160 THRU SN74LS163A SYNCHRONOUS 4-BIT COUNTERS SDLS060 - OCTOBER 1976 - REVISED MARCH 1988 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 15 SN54S162, SN54S163, SN74S162, SN74S163 SYNCHRONOUS 4-BIT COUNTERS SDLS060 - OCTOBER 1976 - REVISED MARCH 1988 16 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 SN54S162, SN54S163, SN74S162, SN74S163 SYNCHRONOUS 4-BIT COUNTERS SDLS060 - OCTOBER 1976 - REVISED MARCH 1988 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 17 SN54160 THRU SN54163, SN54LS160A THRU SN54LS163A, SN54S162, SN54S163, SN74160 THRU SN74163, SN74LS160A THRU SN74LS163A, SN74S162, SN74S163 SYNCHRONOUS 4-BIT COUNTERS SDLS060 - OCTOBER 1976 - REVISED MARCH 1988 18 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 SN54160 THRU SN54163, SN54LS160A THRU SN54LS163A, SN74160 THRU SN74163, SN74LS160A THRU SN74LS163A, SYNCHRONOUS 4-BIT COUNTERS SDLS060 - OCTOBER 1976 - REVISED MARCH 1988 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 19 SN54S162, SN54S163, SN74S162, SN74S163 SYNCHRONOUS 4-BIT COUNTERS SDLS060 - OCTOBER 1976 - REVISED MARCH 1988 20 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 SN54160 THRU SN54163, SN54LS160A THRU SN54LS163A, SN54S162, SN54S163, SN74160 THRU SN74163, SN74LS160A THRU SN74LS163A, SN74S162, SN74S163 SYNCHRONOUS 4-BIT COUNTERS SDLS060 - OCTOBER 1976 - REVISED MARCH 1988 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 21 SN54160 THRU SN54163, SN54LS160A THRU SN54LS163A, SN54S162, SN54S163, SN74160 THRU SN74163, SN74LS160A THRU SN74LS163A, SN74S162, SN74S163 SYNCHRONOUS 4-BIT COUNTERS SDLS060 - OCTOBER 1976 - REVISED MARCH 1988 22 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI's standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. 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Copyright 1999, Texas Instruments Incorporated Product Folder:SN54LS161A, Synchronous 4-Bit Counters Texas Instruments All Semiconductors PRODUCT FOLDER Advanced Search TI Home TI_ME Employment Tech Support Comments Site Map TI Global | PRODUCT INFO: FEATURES | DESCRIPTION | DATASHEETS | PRICING/AVAILABILITY | APPLICATION NOTES | RELATED DOCUMENTS PRODUCT SUPPORT: TRAINING SN54LS161A, Synchronous 4-Bit Counters DEVICE STATUS: ACTIVE PARAMETER NAME SN54LS161A Voltage Nodes (V) 5 Vcc range (V) 4.5 to 5.5 Input Level TTL Output Level TTL Output 2S Clear Async FEATURES Back to Top Back to Top '160, '161, 'LS160A, 'LS161A ... SYNCHRONOUS COUNTERS WITH DIRECT CLEAR '162, '163, 'LS162A, 'LS163A, 'S162, 'S163 ... FULLY SYNCHRONOUS COUNTERS Internal Look-Ahead for Fast Counting Carry Output for n-Bit Cascading Synchronous Counting Synchronously Programmable Load Control Line Diode-Clamped Inputs DESCRIPTION Back to Top Back to These synchronous, presettable counters feature an internal carry look-ahead for application in high-speed Top counting designs. The '160, '162, 'LS160A, 'LS162A, and 'S162 are decade counters and the '161, '163, 'LS161A, 'LS163A, and 'S163 are 4-bit binary counters. Synchronous operation is provided by having all flip-flops clocked simultaneously so that the outputs change coincident with each other when so instructed by the count-enable inputs and internal gating. This mode of operation eliminates the output counting file:////roarer/root/export/projects/bitting1/imagin...vnet/20001221/11092000/TXII/11092000/sn54ls161a.html (1 of 3) [1/3/2001 10:44:24 AM] Product Folder:SN54LS161A, Synchronous 4-Bit Counters spikes that are normally associated with asynchronous (ripple clock) counters, however counting spikes may occur on the (RCO) ripple carry output. A buffered clock input triggers the four flip-flops on the rising edge of the clock input waveform. These counters are fully programmable; that is, the outputs may be preset to either level. As presetting is synchronous, setting up a low level at the load input disables the counter and causes the outputs to agree with the setup data after the next clock pulse regardless of the levels of the enable inputs. Low-to-high transitions at the load input of the '160 thru '163 should be avoided when the clock is low if the enable inputs are high at or before the transition. This restriction is not applicable to the 'LS160A thru 'LS163A or 'S162 or 'S163. The clear function for the '160, '161, 'LS160A, and 'LS161A is asynchronous and a low level at the clear input sets all four of the flip-flop outputs low regardless of the levels of clock, load, or enable inputs. The clear function for the '162, '163, 'LS162A, 'LS163A, 'S162, and 'S163 is synchronous and a low level at the clear input sets all four of the flip-flop outputs low after the next clock pulse, regardless of the levels of the enable inputs. This synchronous clear allows the count length to be modified easily as decoding the maximum count desired can be accomplished with one external NAND gate. The gate output is connected to the clear input to synchronously clear the counter to 0000 (LLLL). Low-to-high transitions at the clear input of the '162 and '163 should be avoided when the clock is low if the enable and load inputs are high at or before the transition. The carry look-ahead circuitry provides for cascading counters for n-bit synchronous applications without additional gating. Instrumental in accomplishing this function are two count-enable inputs and a ripple carry output. Both count-enable inputs (P and T) must be high to count, and input T is fed forward to enable the ripple carry output. The ripple carry output thus enabled will produce a high-level output pulse with a duration approximately equal to the high-level portion of the QA output. This high-level overflow ripple carry pulse can be used to enable successive cascaded stages. High-to-low level transitions at the enable P or T inputs of the '160 thru '163 should occur only when the clock input is high. Transitions at the enable P or T inputs of the 'LS160A thru 'LS163A or 'S162 and 'S163 are allowed regardless of the level of the clock input. 'LS160A thru 'LS163A, 'S162 and 'S163 feature a fully independent clock circuit. Changes at control inputs (enable P or T, or load) that will modify the operating mode have no effect until clocking occurs. The function of the counter (whether enabled, disabled, loading, or counting) will be dictated solely by the conditions meeting the stable setup and hold times. Back to Top TECHNICAL DOCUMENTS To view the following documents, Acrobat Reader 3.x is required. To download a document to your hard drive, right-click on the link and choose 'Save'. Back to Top Back to Top DATASHEET Back to Top Full datasheet in Acrobat PDF: sdls060.pdf (756 KB) (Updated: 03/01/1988) Full datasheet in Zipped PostScript: sdls060.psz (1465 KB) Back to Top APPLICATION NOTES Back to Top View Application Reports for Digital Logic Designing With Logic (SDYA009C - Updated: 06/01/1997) Designing with the SN54/74LS123 (SDLA006A - Input And Output Characteristics Of Digital Integrated Circuits (SDYA010 - Live Insertion (SDYA012 - Updated: 03/01/1997) Updated: 10/01/1996) Updated: 10/01/1996) Back to Top RELATED DOCUMENTS Back Documentation Rules (SAP) And Ordering Information (SZZU001B, 4 KB - Updated: 05/06/1999) to Top Logic Selection Guide Second Half 2000 (SDYU001N, 5035 KB - Updated: 04/17/2000) MicroStar Junior BGA Design Summary (SCET004, 167 KB - More Power In Less Space - Technical Article (SCAU001A, 850 KB - PRICING/AVAILABILITY Updated: 07/28/2000) Updated: 03/01/1996) Back to Top Back to Top file:////roarer/root/export/projects/bitting1/imagin...vnet/20001221/11092000/TXII/11092000/sn54ls161a.html (2 of 3) [1/3/2001 10:44:24 AM] Product Folder:SN54LS161A, Synchronous 4-Bit Counters ORDERABLE DEVICE PACKAGE PINS TEMP (C) STATUS BUDGETARY PRICE US$/UNIT QTY=1000+ PACK QTY DSCC NUMBER PRICING/AVAILABILITY JM38510/31504B2A FK 20 -55 TO 125 ACTIVE 8.62 165 Check stock or order JM38510/31504BEA J 16 -55 TO 125 ACTIVE 2.50 1 Check stock or order JM38510/31504BFA W 16 -55 TO 125 ACTIVE 8.62 1 Check stock or order SN54LS161AJ J 16 -55 TO 125 ACTIVE 1.04 1 Check stock or order SNJ54LS161AFK FK 20 -55 TO 125 ACTIVE 7.72 1 76008012A Check stock or order SNJ54LS161AJ J 16 -55 TO 125 ACTIVE 1.43 1 7600801EA Check stock or order SNJ54LS161AW W 16 -55 TO 125 ACTIVE 7.72 1 7600801FA Check stock or order Table Data Updated on: 11/9/2000 (c) Copyright 2000 Texas Instruments Incorporated. All rights reserved. Trademarks | Privacy Policy | Important Notice file:////roarer/root/export/projects/bitting1/imagin...vnet/20001221/11092000/TXII/11092000/sn54ls161a.html (3 of 3) [1/3/2001 10:44:24 AM] Product Folder:SN54LS163A, Synchronous 4-Bit Counters Texas Instruments All Semiconductors PRODUCT FOLDER Advanced Search TI Home TI_ME Employment Tech Support Comments Site Map TI Global | PRODUCT INFO: FEATURES | DESCRIPTION | DATASHEETS | PRICING/AVAILABILITY | APPLICATION NOTES | RELATED DOCUMENTS PRODUCT SUPPORT: TRAINING SN54LS163A, Synchronous 4-Bit Counters DEVICE STATUS: ACTIVE PARAMETER NAME SN54LS163A Voltage Nodes (V) 5 Vcc range (V) 4.5 to 5.5 Input Level TTL Output Level TTL Output 2S Clear Sync FEATURES Back to Top Back to Top '160, '161, 'LS160A, 'LS161A ... SYNCHRONOUS COUNTERS WITH DIRECT CLEAR '162, '163, 'LS162A, 'LS163A, 'S162, 'S163 ... FULLY SYNCHRONOUS COUNTERS Internal Look-Ahead for Fast Counting Carry Output for n-Bit Cascading Synchronous Counting Synchronously Programmable Load Control Line Diode-Clamped Inputs DESCRIPTION Back to Top Back to These synchronous, presettable counters feature an internal carry look-ahead for application in high-speed Top counting designs. The '160, '162, 'LS160A, 'LS162A, and 'S162 are decade counters and the '161, '163, 'LS161A, 'LS163A, and 'S163 are 4-bit binary counters. Synchronous operation is provided by having all flip-flops clocked simultaneously so that the outputs change coincident with each other when so instructed by the count-enable inputs and internal gating. This mode of operation eliminates the output counting file:////roarer/root/export/projects/bitting1/imagin...vnet/20001221/11092000/TXII/11092000/sn54ls163a.html (1 of 3) [1/3/2001 10:45:56 AM] Product Folder:SN54LS163A, Synchronous 4-Bit Counters spikes that are normally associated with asynchronous (ripple clock) counters, however counting spikes may occur on the (RCO) ripple carry output. A buffered clock input triggers the four flip-flops on the rising edge of the clock input waveform. These counters are fully programmable; that is, the outputs may be preset to either level. As presetting is synchronous, setting up a low level at the load input disables the counter and causes the outputs to agree with the setup data after the next clock pulse regardless of the levels of the enable inputs. Low-to-high transitions at the load input of the '160 thru '163 should be avoided when the clock is low if the enable inputs are high at or before the transition. This restriction is not applicable to the 'LS160A thru 'LS163A or 'S162 or 'S163. The clear function for the '160, '161, 'LS160A, and 'LS161A is asynchronous and a low level at the clear input sets all four of the flip-flop outputs low regardless of the levels of clock, load, or enable inputs. The clear function for the '162, '163, 'LS162A, 'LS163A, 'S162, and 'S163 is synchronous and a low level at the clear input sets all four of the flip-flop outputs low after the next clock pulse, regardless of the levels of the enable inputs. This synchronous clear allows the count length to be modified easily as decoding the maximum count desired can be accomplished with one external NAND gate. The gate output is connected to the clear input to synchronously clear the counter to 0000 (LLLL). Low-to-high transitions at the clear input of the '162 and '163 should be avoided when the clock is low if the enable and load inputs are high at or before the transition. The carry look-ahead circuitry provides for cascading counters for n-bit synchronous applications without additional gating. Instrumental in accomplishing this function are two count-enable inputs and a ripple carry output. Both count-enable inputs (P and T) must be high to count, and input T is fed forward to enable the ripple carry output. The ripple carry output thus enabled will produce a high-level output pulse with a duration approximately equal to the high-level portion of the QA output. This high-level overflow ripple carry pulse can be used to enable successive cascaded stages. High-to-low level transitions at the enable P or T inputs of the '160 thru '163 should occur only when the clock input is high. Transitions at the enable P or T inputs of the 'LS160A thru 'LS163A or 'S162 and 'S163 are allowed regardless of the level of the clock input. 'LS160A thru 'LS163A, 'S162 and 'S163 feature a fully independent clock circuit. Changes at control inputs (enable P or T, or load) that will modify the operating mode have no effect until clocking occurs. The function of the counter (whether enabled, disabled, loading, or counting) will be dictated solely by the conditions meeting the stable setup and hold times. Back to Top TECHNICAL DOCUMENTS To view the following documents, Acrobat Reader 3.x is required. To download a document to your hard drive, right-click on the link and choose 'Save'. Back to Top Back to Top DATASHEET Back to Top Full datasheet in Acrobat PDF: sdls060.pdf (756 KB) (Updated: 03/01/1988) Full datasheet in Zipped PostScript: sdls060.psz (1465 KB) Back to Top APPLICATION NOTES Back to Top View Application Reports for Digital Logic Designing With Logic (SDYA009C - Updated: 06/01/1997) Designing with the SN54/74LS123 (SDLA006A - Input And Output Characteristics Of Digital Integrated Circuits (SDYA010 - Live Insertion (SDYA012 - Updated: 03/01/1997) Updated: 10/01/1996) Updated: 10/01/1996) Back to Top RELATED DOCUMENTS Back Documentation Rules (SAP) And Ordering Information (SZZU001B, 4 KB - Updated: 05/06/1999) to Top Logic Selection Guide Second Half 2000 (SDYU001N, 5035 KB - Updated: 04/17/2000) MicroStar Junior BGA Design Summary (SCET004, 167 KB - More Power In Less Space - Technical Article (SCAU001A, 850 KB - PRICING/AVAILABILITY Updated: 07/28/2000) Updated: 03/01/1996) Back to Top Back to Top file:////roarer/root/export/projects/bitting1/imagin...vnet/20001221/11092000/TXII/11092000/sn54ls163a.html (2 of 3) [1/3/2001 10:45:56 AM] Product Folder:SN54LS163A, Synchronous 4-Bit Counters ORDERABLE DEVICE PACKAGE PINS TEMP (C) STATUS BUDGETARY PRICE US$/UNIT QTY=1000+ PACK QTY DSCC NUMBER PRICING/AVAILABILITY 7603401FA W 16 -55 TO 125 ACTIVE 7.72 1 Check stock or order JM38510/31512B2A FK 20 -55 TO 125 ACTIVE 8.27 165 Check stock or order JM38510/31512BEA J 16 -55 TO 125 ACTIVE 3.59 1 Check stock or order JM38510/31512BFA W 16 -55 TO 125 ACTIVE 8.62 1 Check stock or order SN54LS163AJ J 16 -55 TO 125 ACTIVE 1.20 1 Check stock or order SNJ54LS163AFK FK 20 -55 TO 125 ACTIVE 7.72 1 76034012A Check stock or order SNJ54LS163AJ J 16 -55 TO 125 ACTIVE 1.43 1 7603401EA Check stock or order SNJ54LS163AW W 16 -55 TO 125 ACTIVE 7.72 1 7603401FA Check stock or order Table Data Updated on: 11/9/2000 (c) Copyright 2000 Texas Instruments Incorporated. All rights reserved. Trademarks | Privacy Policy | Important Notice file:////roarer/root/export/projects/bitting1/imagin...vnet/20001221/11092000/TXII/11092000/sn54ls163a.html (3 of 3) [1/3/2001 10:45:56 AM] Products Development Tools Applications Search PRODUCT FOLDER | PRODUCT INFO: FEATURES | DESCRIPTION | DATASHEETS | PRICING/AVAILABILITY | APPLICATION NOTES | RELATED DOCUMENTS PRODUCT SUPPORT: TRAINING SN74LS161A, Synchronous 4-Bit Binary Counters DEVICE STATUS: ACTIVE PARAMETER NAME SN74LS161A Voltage Nodes (V) 5 Vcc range (V) 4.75 to 5.25 Input Level TTL Output Level TTL Output Drive (mA) -0.4/8 Output 2S Clear Async FEATURES Back to Top '160, '161, 'LS160A, 'LS161A ... SYNCHRONOUS COUNTERS WITH DIRECT CLEAR '162, '163, 'LS162A, 'LS163A, 'S162, 'S163 ... FULLY SYNCHRONOUS COUNTERS l l l l l l Internal Look-Ahead for Fast Counting Carry Output for n-Bit Cascading Synchronous Counting Synchronously Programmable Load Control Line Diode-Clamped Inputs DESCRIPTION Back to Top These synchronous, presettable counters feature an internal carry look-ahead for application in high-speed counting designs. The '160, '162, 'LS160A, 'LS162A, and 'S162 are decade counters and the '161, '163, 'LS161A, 'LS163A, and 'S163 are 4-bit binary counters. Synchronous operation is provided by having all flip-flops clocked simultaneously so that the outputs change coincident with each other when so instructed by the count-enable inputs and internal gating. This mode of operation eliminates the output counting spikes that are normally associated with asynchronous (ripple clock) counters, however counting spikes may occur on the (RCO) ripple carry output. A buffered clock input triggers the four flip-flops on the rising edge of the clock input waveform. These counters are fully programmable; that is, the outputs may be preset to either level. As presetting is synchronous, setting up a low level at the load input disables the counter and causes the outputs to agree with the setup data after the next clock pulse regardless of the levels of the enable inputs. Low-to-high transitions at the load input of the '160 thru '163 should be avoided when the clock is low if the enable inputs are high at or before the transition. This restriction is not applicable to the 'LS160A thru 'LS163A or 'S162 or 'S163. The clear function for the '160, '161, 'LS160A, and 'LS161A is asynchronous and a low level at the clear input sets all four of the flip-flop outputs low regardless of the levels of clock, load, or enable inputs. The clear function for the '162, '163, 'LS162A, 'LS163A, 'S162, and 'S163 is synchronous and a low level at the clear input sets all four of the flip-flop outputs low after the next clock pulse, regardless of the levels of the enable inputs. This synchronous clear allows the count length to be modified easily as decoding the maximum count desired can be accomplished with one external NAND gate. The gate output is connected to the clear input to synchronously clear the counter to 0000 (LLLL). Low-to-high transitions at the clear input of the '162 and '163 should be avoided when the clock is low if the enable and load inputs are high at or before the transition. The carry look-ahead circuitry provides for cascading counters for n-bit synchronous applications without additional gating. Instrumental in accomplishing this function are two count-enable inputs and a ripple carry output. Both count-enable inputs (P and T) must be high to count, and input T is fed forward to enable the ripple carry output. The ripple carry output thus enabled will produce a high-level output pulse with a duration approximately equal to the high-level portion of the QA output. This high-level overflow ripple carry pulse can be used to enable successive cascaded stages. High-to-low level transitions at the enable P or T inputs of the '160 thru '163 should occur only when the clock input is high. Transitions at the enable P or T inputs of the 'LS160A thru 'LS163A or 'S162 and 'S163 are allowed regardless of the level of the clock input. 'LS160A thru 'LS163A, 'S162 and 'S163 feature a fully independent clock circuit. Changes at control inputs (enable P or T, or load) that will modify the operating mode have no effect until clocking occurs. The function of the counter (whether enabled, disabled, loading, or counting) will be dictated solely by the conditions meeting the stable setup and hold times. TECHNICAL DOCUMENTS Back to Top To view the following documents, Acrobat Reader 3.x is required. To download a document to your hard drive, right-click on the link and choose 'Save'. DATASHEET Back to Top Full datasheet in Acrobat PDF: sdls060.pdf (756 KB) (Updated: 03/01/1988) Full datasheet in Zipped PostScript: sdls060.psz (1465 KB) APPLICATION NOTES Back to Top View Application Reports for Digital Logic l l l l Designing With Logic (SDYA009C - Updated: 06/01/1997) Designing with the SN54/74LS123 (SDLA006A - Updated: 03/01/1997) Input and Output Characteristics of Digital Integrated Circuits (SDYA010 Live Insertion (SDYA012 - Updated: 10/01/1996) Updated: 10/01/1996) RELATED DOCUMENTS l l l l Back to Top Documentation Rules (SAP) And Ordering Information (SZZU001B, 4 KB - Updated: 05/06/1999) Logic Selection Guide Second Half 2000 (SDYU001N, 5035 KB - Updated: 04/17/2000) MicroStar Junior BGA Design Summary (SCET004, 167 KB - Updated: 07/28/2000) More Power In Less Space - Technical Article (SCAU001A, 850 KB - Updated: 03/01/1996) PRICING/AVAILABILITY Back to Top ORDERABLE DEVICE PACKAGE PINS TEMP (C) STATUS BUDGETARY PRICE US$/UNIT QTY=1000+ PACK QTY PRICING/AVAILABILITY SN74LS161AD D 16 0 TO 70 ACTIVE 0.42 40 Check stock or order SN74LS161ADR D 16 0 TO 70 ACTIVE 0.45 2500 Check stock or order SN74LS161AN N 16 0 TO 70 ACTIVE 0.35 25 Check stock or order SN74LS161AN3 N 16 0 TO 70 OBSOLETE SN74LS161ANSR NS 16 0 TO 70 ACTIVE 0.50 2000 Check stock or order Table Data Updated on: 11/17/2000 (c) Copyright 2000 Texas Instruments Incorporated. All rights reserved. Trademarks | Privacy Policy | Important Notice