DESCRIPTION
The 3825 group is the 8-bit microcomputer based on the 740 fam-
ily core technology.
The 3825 group has the LCD drive control circuit, an 8-channel A-
D converter, and a Serial I/O as additional functions.
The various microcomputers in the 3825 group include variations
of internal memory size and packaging. For details, refer to the
section on part numbering.
For details on availability of microcomputers in the 3825 Group,
refer the section on group expansion.
FEATURES
•Basic machine-language instructions....................................... 71
•The minimum instruction execution time............................ 0.5 µs
(at 8 MHz oscillation frequency)
•Memory size
ROM .................................................................. 4 K to 60 K bytes
RAM ................................................................. 192 to 2048 bytes
•Programmable input/output ports ............................................. 43
•Software pull-up/pull-down resistors (Ports P0–P8)
•Interrupts .................................................. 17 sources, 16 vectors
(includes key input interrupt)
•Timers ........................................................... 8-bit ✕ 3, 16-bit ✕ 2
•Serial I/O ...................... 8-bit ✕ 1 (UART or Clock-synchronized)
•A-D converter .................................................. 8-bit ✕ 8 channels
•LCD drive control circuit
Bias ................................................................................... 1/2, 1/3
Duty ............................................................................1/2, 1/3, 1/4
Common output .......................................................................... 4
Segment output......................................................................... 40
•2 Clock generating circuits
(connect to external ceramic resonator or quartz-crystal oscillator)
•Power source voltage
In high-speed mode ................................................... 4.0 to 5.5 V
In middle-speed mode ............................................... 2.5 to 5.5 V
(M version: 2.2 to 5.5 V)
(Extended operating temperature version: 3.0 to 5.5 V)
In low-speed mode..................................................... 2.5 to 5.5 V
(M version: 2.2 to 5.5 V)
(Extended operating temperature version: 3.0 to 5.5 V)
•Power dissipation
In high-speed mode ...........................................................32 mW
(at 8 MHz oscillation frequency, at 5 V power source voltage)
In low-speed mode..............................................................45 µ W
(at 32 kHz oscillation frequency, at 3 V power source voltage)
•Operating temperature range ...................................– 2 0 t o 85°C
(Extended operating temperature version: –40 to 85°C)
APPLICATIONS
Camera, household appliances, consumer electronics, etc.
3825 Group
MITSUBISHI MICROCOMPUTERS
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Package type : 100P6S-A (100-pin plastic-molded QFP)
Fig. 1 Pin configuration of M38258MCMXXXFP
(The pin configuration of 100D0 is same as this.)
PIN CONFIGURATION (TOP VIEW)
12 3 4 5 6 7 8 9 101112131
41
51
61
71
81
92
02122232425262
72
82
93
0
3
1
3
2
33
34
35
3
6
3
7
3
8
3
9
40
41
4
2
43
4
4
4
5
4
6
4
7
4
8
49
50
5
15
25
35
45
55
65
75
85
96
06
16263646566676869707
172737
47
57
67
77
87
98
0
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
10
0
M38258MCMXXXFP
S
E
G
9
P
3
1
/
S
E
G
1
9
P
3
0
/
S
E
G
1
8
P
3
2
/
S
E
G
2
0
P
3
3
/
S
E
G
2
1
P
3
4
/
S
E
G
2
2
S
E
G
1
0
S
E
G
1
1
S
E
G
1
2
S
E
G
1
3
S
E
G
1
4
S
E
G
1
5
P
3
5
/
S
E
G
2
3
P
3
6
/
S
E
G
2
4
P
3
7
/
S
E
G
2
5
P
0
0
/
S
E
G
2
6
P
0
1
/
S
E
G
2
7
P
0
2
/
S
E
G
2
8
P
0
3
/
S
E
G
2
9
P
0
4
/
S
E
G
3
0
P
0
5
/
S
E
G
3
1
P
0
6
/
S
E
G
3
2
P
0
7
/
S
E
G
3
3
P
1
0
/
S
E
G
3
4
P
1
1
/
S
E
G
3
5
P
1
2
/
S
E
G
3
6
P
1
3
/
S
E
G
3
7
P
1
4
/
S
E
G
3
8
P
1
5
/
S
E
G
3
9
C
1
V
L
1
P
6
7
/
A
N
7
P
6
6
/
A
N
6
P
6
5
/
A
N
5
P
6
4
/
A
N
4
P
6
3
/
A
N
3
P
6
2
/
A
N
2
P
6
1
/
A
N
1
P
6
0
/
A
N
0
P
5
7
/
A
D
T
P
5
6
/
T
O
U
T
P
5
5
/
C
N
T
R
1
P
5
4
/
C
N
T
R
0
P
5
3
/
R
T
P
1
P
5
2
/
R
T
P
0
P
5
1
/
I
N
T
3
P
5
0
/
I
N
T
2
P
4
6
/
S
C
L
K
P
4
5
/
T
X
D
P
4
4
/
R
X
D
P
4
3
/
I
N
T
1
P
4
2
/
I
N
T
0
P
4
1
/
f
(
X
I
N
)
/
5
/
f
(
X
I
N
)
/
1
0
P
4
0
/
f
(
X
I
N
)
/
f
(
X
I
N
)
/
2
P
7
7
P
7
6
P
7
5
P
7
4
C
2
V
L2
V
L3
C
O
M
0
C
O
M
1
C
O
M
2
V
R
E
F
A
V
S
S
V
CC
SEG
8
SEG
0
S
E
G
1
S
E
G
2
S
E
G
4
S
E
G
5
S
E
G
6
S
E
G
7
S
E
G
3
P7
2
P7
3
P7
1
P
7
0
P
8
1
/
X
C
I
N
P
8
0
/
X
C
O
U
T
X
I
N
X
O
U
T
V
S
S
P2
7
P2
6
P
2
5
P2
4
P
2
3
P
2
1
P
1
6
P
2
2
P2
0
P1
7
R
E
S
E
T
S
E
G
1
6
S
E
G
1
7
C
O
M
3
P
4
7
/
S
R
D
Y
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
3825 Group
2
Package type : GP........................... 100P6Q-A (100-pin plastic-molded LQFP)
Package type : HP ........................... 100PFB-A (100-pin plastic-molded TQFP)
PIN CONFIGURATION (TOP VIEW)
Fig. 2 Pin configuration of M38258MCMXXXGP, M38258MCMXXXHP
12 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
2
6
27
28
2
9
3
0
3
1
32
3
3
3
4
35
36
3
7
3
8
39
4
0
4
1
4
2
4
3
4
4
4
5
4
6
4
7
4
8
4
9
5
0
5
15
25
35
45
55
65
7585
96
06
1626
364656667686
9707
17
2737475
7
6
7
7
7
8
7
9
8
0
8
1
8
2
8
3
8
4
8
5
8
6
8
7
88
8
9
9
0
9
1
92
9
3
9
4
9
5
9
6
97
98
9
9
0
01
M
3
8
2
5
8
M
C
M
X
X
X
G
P
M
3
8
2
5
8
M
C
M
X
X
X
H
P
S
E
G
1
2
S
E
G
1
1
S
E
G
1
0
S
E
G
9
S
E
G
8
S
E
G
7
S
E
G
6
S
E
G
5
S
E
G
4
S
E
G
3
S
E
G
2
SEG
1
S
E
G
0
V
C
C
V
R
E
F
AV
SS
C
O
M
3
C
O
M
2
C
O
M
1
COM
0
V
L
3
V
L
2
C
2
C
1
V
L
1
P
6
7
/
A
N
7
P
6
6
/
A
N
6
P
6
5
/
A
N
5
P
6
4
/
A
N
4
P
6
3
/
A
N
3
P
6
2
/
A
N
2
P
6
1
/
A
N
1
P
6
0
/
A
N
0
P
5
7
/
A
D
T
P
5
6
/
T
O
U
T
P
5
5
/
C
N
T
R
1
P
5
4
/
C
N
T
R
0
P
5
3
/
R
T
P
1
P
5
2
/
R
T
P
0
P
5
1
/
I
N
T
3
P
5
0
/
I
N
T
2
P
4
6
/
S
C
L
K
P
4
5
/
T
X
D
P
4
4
/
R
X
D
P
4
3
/
I
N
T
1
P
4
2
/
I
N
T
0
P
4
1
/
f
(
X
I
N
)
/
5
/
f
(
X
I
N
)
/
1
0
P
4
0
/
f
(
X
I
N
)
/
f
(
X
I
N
)
/
2
P
7
7
P
4
7
/
S
R
D
Y
P
7
2
P7
3
P
7
1
P7
0
P
8
1
/
X
C
I
N
P8
0
/X
COUT
X
I
N
X
O
U
T
V
SS
P
2
7
P
2
6
P2
5
P
2
4
P
2
3
P
2
1
P
1
6
P
2
2
P
2
0
P
1
7
R
E
S
E
T
P
7
6
P7
5
P
7
4
P
1
5
/
S
E
G
3
9
P
1
4
/
S
E
G
3
8
P
3
1
/
S
E
G
1
9
P
3
0
/
S
E
G
1
8
P
3
2
/
S
E
G
2
0
P
3
3
/
S
E
G
2
1
P
3
4
/
S
E
G
2
2
S
E
G
1
3
S
E
G
1
4
S
E
G
1
5
P
3
5
/
S
E
G
2
3
P
3
6
/
S
E
G
2
4
P
3
7
/
S
E
G
2
5
P
0
0
/
S
E
G
2
6
P
0
1
/
S
E
G
2
7
P
0
2
/
S
E
G
2
8
P
0
3
/
S
E
G
2
9
P
0
4
/
S
E
G
3
0
P
0
5
/
S
E
G
3
1
P
0
6
/
S
E
G
3
2
P
0
7
/
S
E
G
3
3
P
1
0
/
S
E
G
3
4
P
1
1
/
S
E
G
3
5
P
1
2
/
S
E
G
3
6
P
1
3
/
S
E
G
3
7
S
E
G
1
6
S
E
G
1
7
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
3825 Group
3
FUNCTIONAL BLOCK DIAGRAM (Package : 100P6S-A)
Fig. 3 Functional block diagram
A
D
T
C
N
T
R0,
C
N
T
R1
TO
U
T
C
P
UA
X
Y
S
P
CHP
CL
P
S
R
O
M
S
I
/
O
(
8
)
VL
1
VL
2
VL
3
C
O
M0
C
O
M1
C
O
M2
C
O
M3
3
8
φ
L
C
D
d
r
i
v
e
c
o
n
t
r
o
l
c
i
r
c
u
i
t
R
A
M
L
C
D
d
i
s
p
l
a
y
R
A
M
(
2
0
b
y
t
e
s
)
T
i
m
e
r
X
(
1
6
)
T
i
m
e
r
Y
(
1
6
)
T
i
m
e
r
1
(
8
)T
i
m
e
r
2
(
8
)
T
i
m
e
r
3
(
8
)
D
a
t
a
b
u
s
C
l
o
c
k
g
e
n
e
r
a
t
i
n
g
c
i
r
c
u
i
t
C
l
o
c
k
i
n
p
u
t
XI
N
C
l
o
c
k
o
u
t
p
u
t
XO
U
T
XC
O
U
T
S
u
b
-
c
l
o
c
k
o
u
t
p
u
t
XC
I
N
S
u
b
-
c
l
o
c
k
i
n
p
u
t
VC
C
R
e
s
e
t
i
n
p
u
t(
5
V
)
R
E
S
E
T
K
e
y
-
o
n
w
a
k
e
u
p
R
e
a
l
t
i
m
e
p
o
r
t
f
u
n
c
t
i
o
n
I
N
T0,
I
N
T1
A
-
D
c
o
n
v
e
r
t
e
r
(
8
)
R
T
P0,
R
T
P1
3
93
5 9
14
0
VS
S
(
0
V
)
9
9
9
8
9
7
9
6
9
5
9
4
9
0
8
9
8
8
8
7
8
6
8
5
8
4
8
3
8
2
8
1
8
0
7
9S
E
G1
1
S
E
G1
S
E
G2
S
E
G3
S
E
G4
S
E
G5
S
E
G6
S
E
G7
S
E
G8
S
E
G9
S
E
G1
0
S
E
G0
5
76
4
O
u
t
p
u
t
p
o
r
t
P
0
P
0
(
8
)
6
36
26
16
0
5
95
8
4
95
6
O
u
t
p
u
t
p
o
r
t
P
1
P
1
(
8
)
5
55
45
35
25
15
0
4
14
8
I
/
O
p
o
r
t
P
2
P
2
(
8
)
4
74
64
54
4
4
34
2
P
4
(
8
)
1
92
6
I
/
O
p
o
r
t
P
4
2
52
42
32
2
2
12
0
1
11
8
I
/
O
p
o
r
t
P
5
P
5
(
8
)
1
71
61
51
4
1
31
2
I
N
T2
,
I
N
T3
9
39
2
VR
E
F
A
VS
S
(
0
V
)
P
6
(
8
)
31
0
I
/
O
p
o
r
t
P
6
9876
54
P
8
(
2
)
XC
I
N
XC
O
U
T
3
73
6
I
/
O
p
o
r
t
P
8
1
2
10
0
C1
C2
7
8
7
7
7
6
7
5
7
4
7
3S
E
G1
7
S
E
G1
2
S
E
G1
3
S
E
G1
4
S
E
G1
5
S
E
G1
6
O
u
t
p
u
t
p
o
r
t
P
3
P
3
(
8
)
6
57
27
17
06
96
86
76
6
P
7
(
8
)
2
73
4
I
/
O
p
o
r
t
P
7
3
33
23
13
02
92
8
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
3825 Group
4
PIN DESCRIPTION
Table 1. Pin description (1)
Function
•Apply voltage of power source to VCC, and 0 V to VSS. (For the limits of VCC, refer to “Recom-
mended operating conditions”.)
•Reference voltage input pin for A-D converter.
•GND input pin for A-D converter.
•Connect to VSS.
•Reset input pin for active “L”
•Input and output pins for the main clock generating circuit.
•Feedback resistor is built in between XIN pin and XOUT pin.
•Connect a ceramic resonator or a quartz-crystal oscillator between the XIN and XOUT pins to set
the oscillation frequency.
•If an external clock is used, connect the clock source to the XIN pin and leave the XOUT pin open.
•This clock is used as the oscillating source of system clock.
•Input 0 ≤ VL1 ≤ VL2 ≤ VL3 ≤ VCC voltage
•Input 0 – VL3 voltage to LCD
•External capacitor pins for a voltage multiplier (3 times) of LCD contorl.
•LCD common output pins
•COM2 and COM3 are not used at 1/2 duty ratio.
•COM3 is not used at 1/3 duty ratio.
•LCD segment output pins
•8-bit output port
•CMOS 3-state output structure
•Pull-down control is enabled.
•Port output control is enabled.
•6-bit output port
•CMOS 3-state output structure
•Pull-down control is enabled.
•Port output control is enabled.
•2-bit I/O port
•CMOS compatible input level
•CMOS 3-state output structure
•I/O direction register allows each pin to be individually programmed as either input or output.
•Pull-up control is enabled.
•8-bit Input port
•CMOS compatible input level
•CMOS 3-state output structure
•I/O direction register allows each pin to be individually
programmed as either input or output.
•Pull-up control is enabled.
•8-bit output port
•CMOS 3-state output structure
•Pull-down control is enabled.
•Port output control is enabled.
•LCD segment pins
•Key input (key-on wake up) interrupt
input pins
•LCD segment pins
Pin
VCC, VSS
VREF
AVSS
RESET
XIN
XOUT
VL1 – VL3
C1, C2
COM
0
– COM
3
SEG
0
– SEG
17
P00/
SEG
26
–
P07/
SEG
33
P10/
SEG
34
–
P15/
SEG
39
P16
,
P17
P20
– P27
P30/
SEG
18
–
P37/
SEG
25
Name
Power source
Analog reference
voltage
Analog power
source
Reset input
Clock input
Clock output
LCD power source
Charge-pump
capacitor pin
Common output
Segment output
Output port P0
Output port P1
I/O port P1
I/O port P2
Output port P3
Function except a port function
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
3825 Group
5
Function
•8-bit I/O port
•CMOS compatible input level
•CMOS 3-state output structure
•I/O direction register allows each pin to be individually
programmed as either input or output.
•Pull-up control is enabled.
•8-bit I/O port
•CMOS compatible input level
•CMOS 3-state output structure
•I/O direction register allows each pin to be individually
programmed as either input or output.
•Pull-up control is enabled.
•8-bit I/O port
•CMOS compatible input level
•CMOS 3-state output structure
•I/O direction register allows each pin to be individually
programmed as either input or output.
•Pull-up control is enabled.
•1-bit input port
•CMOS compatible input level
•7-bit I/O port
•CMOS compatible input level
•CMOS 3-state output structure
•I/O direction register allows each pin to be individually programmed as either input or output.
•Pull-up control is enabled.
•2-bit I/O port
•CMOS compatible input level
•CMOS 3-state output structure
•I/O direction register allows each pin to be individually
programmed as either input or output.
•Pull-up control is enabled.
Pin
P40/f(XIN)/
f(XIN)/2,
P41/f(XIN)/5/
f(XIN)/10
P42/INT0,
P43/INT1
P44/RXD,
P45/TXD,
P46/SCLK,
P47/SRDY
P50/INT2,
P51/INT3
P52/RTP0,
P53/RTP1
P54/CNTR0,
P55/CNTR1
P56/TOUT
P57/ADT
P60/AN0–
P67/AN7
P70
P71–P77
P80/XCOUT,
P81/XCIN
Name
I/O port P4
I/O port P5
I/O port P6
Input port P7
I/O port P7
I/O port P8
Function except a port function
•Clock output pins
•Interrupt input pins
•Serial I/O function pins
•Interrupt input pins
•Real time port function pins
•Timers X, Y functions pins
•Timer 2 output pin
•A-D trigger input pin
•A-D conversion input pins
Table 2. Pin description (2)
•Sub-clock generating circuit I/O pins
(Connect a resonator. External clock
cannot be used.)
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
3825 Group
6
PART NUMBERING
Fig. 4 Part numbering
M
3
8
2
5
8 M
C
M X
X
X
H
P
Product
ROM/PROM size
1
2
3
4
5
6
7
8
: 4096 bytes
: 8192 bytes
: 12288 bytes
: 16384 bytes
: 20480 bytes
: 24576 bytes
: 28672 bytes
: 32768 bytes
T
h
e
f
i
r
s
t
1
2
8
b
y
t
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s
a
n
d
t
h
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l
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s
t
2
b
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e
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o
f
R
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a
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b
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d
.
M
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m
o
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t
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p
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M
E
: Mask ROM version
: EPR OM or One Time PROM version
R
A
M
s
i
z
e
0
1
2
3
4
5
6
7
8
9
: 192 bytes
: 256 bytes
: 384 bytes
: 512 bytes
: 640 bytes
: 768 bytes
: 896 bytes
: 1024 bytes
: 1536 bytes
: 2048 bytes
R
O
M
n
u
m
b
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:
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F
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H
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G
P
F
S
: 100P6S-A package
: 100PFB-A package
: 100P6Q-A package
: 100D0 package
9
A
B
C
D
E
F
: 36864 bytes
: 40960 bytes
: 45056 bytes
: 49152 bytes
: 53248 bytes
: 57344 bytes
: 61440 bytes
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
3825 Group
7
GROUP EXPANSION (STANDARD, ONE TIME
PROM VERSION, EPROM VERSION)
Mitsubishi plans to expand the 3825 group(Standard, One Time
PROM version, EPROM version) as follows.
Memory Type
Support for mask ROM, One Time PROM, and EPROM versions.
Memory Size
ROM size ............................................................ 16 K t o 6 0 Kbytes
RAM size ............................................................ 640 to 2048 bytes
Packages
100PFB-A ................................0.4 mm-pitch plastic molded TQFP
100P6Q-A ................................0.5 mm-pitch plastic molded LQFP
100P6S-A ................................0.65 mm-pitch plastic molded QFP
100D0 ................... 0.65 mm-pitch ceramic LCC (EPROM version)
Memory Expansion Plan
Fig. 5 Memory expansion plan
6
0
K
5
6
K
5
2
K
4
8
K
4
4
K
3
6
K
32K
2
8
K
24K
2
0
K
16K
1
2
K
8K
4
K
40K
R
O
M
s
i
z
e
(
b
y
t
e
s
)
256 1
,
0
2
41
,
5
3
6 2,048
R
A
M
s
i
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e
(
b
y
t
e
s
)
M
a
s
s
p
r
o
d
u
c
t
Mass product
M
a
s
s
p
r
o
d
u
c
t
M38254M6
M
a
s
s
p
r
o
d
u
c
t
5
1
27
6
86
4
0
M
3
8
2
5
4
M
4
M
3
8
2
5
7
M
8
/
E
8
M38259EF
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
3825 Group
8
Currently products are listed below.
Table 3. List of products As of Dec. 2000
Remarks
Mask ROM version
Mask ROM version
Mask ROM version
Mask ROM version
Mask ROM version
One Time PROM version (blank)
Mask ROM version
One Time PROM version (blank)
EPROM version
One Time PROM version (blank)
One Time PROM version (blank)
One Time PROM version (blank)
EPROM version
Package
100P6S-A
100P6Q-A
100P6S-A
100P6Q-A
100P6S-A
100P6S-A
100P6Q-A
100P6Q-A
100D0
100P6S-A
100PFB-A
100P6Q-A
100D0
Product
M38254M4-XXXFP
M38254M4-XXXGP
M38254M6-XXXFP
M38254M6-XXXGP
M38257M8-XXXFP
M38257E8FP
M38257M8-XXXGP
M38257E8GP
M38257E8FS
M38259EFFP
M38259EFHP
M38259EFGP
M38259EFFS
RAM size (bytes)
640
640
16384
(16254)
ROM size (bytes)
ROM size for User in ( )
32768
(32638)
24576
(24446)
61440
(61310) 2048
1024
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
3825 Group
9
GROUP EXPANSION
(EXTENDED OPERATING TEMPERATURE VERSION)
Mitsubishi plans to expand the 3825 group (Extended operating
temperature version) as follows.
Memory Type
Support for mask ROM, one time PROM version.
Memory Size
ROM size ............................................................ 16 K t o 6 0 Kbytes
RAM size ............................................................ 640 to 2048 bytes
Packages
100P6S-A ................................0.65 mm-pitch plastic molded QFP
Memory Expansion Plan
Currently products are listed below.
Table 4. List of products for extended operating temperature version As of Dec. 2000
Fig. 6 Memory expansion plan for extended operating temperature version
Remarks
Mask ROM version
Mask ROM version
Mask ROM version
Mask ROM version
One Time PROM version (blank)
RAM size (bytes)
640
640
1024
1536
2048
16384
(16254)
24576
(24446)
32768
(32638)
49152
(49022)
61440
(61310)
Package
100P6S-A
100P6S-A
100P6S-A
100P6S-A
100P6S-A
Product
M38254M4DXXXFP
M38254M6DXXXFP
M38257M8DXXXFP
M38258MCDXXXFP
M38259EFDFP
ROM size (bytes)
ROM size for User in ( )
M
a
s
s
p
r
o
d
u
c
t
6
0
K
5
6
K
5
2
K
4
8
K
4
4
K
36K
3
2
K
2
8
K
24K
20K
16K
1
2
K
8
K
4K
4
0
K
R
O
M
s
i
z
e
(
b
y
t
e
s
)
2
5
61
,
5
3
6 2,048
RAM size (bytes)
Mass product
Mass product
Mass product
Mass product
M38254M6D
5
1
27686
4
0
M
3
8
2
5
4
M
4
D
1
,
0
2
4
M38257M8D
M38258MCD
M
3
8
2
5
9
E
F
D
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
3825 Group
10
GROUP EXPANSION
(M VERSION)
Mitsubishi plans to expand the 3825 group (M version) as follows.
Memory Type
Support for mask ROM version.
Memory Size
ROM size .........................................................................48 Kbytes
RAM size ....................................................................... 1536 bytes
Packages
100PFB-A ................................0.4 mm-pitch plastic molded TQFP
100P6Q-A ................................0.5 mm-pitch plastic molded LQFP
100P6S-A ................................0.65 mm-pitch plastic molded QFP
Memory Expansion Plan
Currently products are listed below.
Table 5. List of products for low power source version As of Dec. 2000
Fig. 7 Memory expansion plan for M version
RAM size (bytes)
49152
(49022)
Package
100P6S-A
100PFB-A
100P6Q-A
Product
M38258MCMXXXFP
M38258MCMXXXHP
M38258MCMXXXGP
ROM size (bytes)
ROM size for User in ( )
1536
Remarks
Mask ROM version
Mask ROM version
Mask ROM version
6
0
K
5
6
K
5
2
K
48K
44K
3
6
K
3
2
K
28K
2
4
K
2
0
K
1
6
K
12K
8K
4
K
4
0
K
R
O
M
s
i
z
e
(
b
y
t
e
s
)
2
5
65
1
27
6
8 1,024 1
,
5
3
62
,
0
4
8
R
A
M
s
i
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e
(
b
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t
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s
)
Mass product M
3
8
2
5
8
M
C
M
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
3825 Group
11
FUNCTIONAL DESCRIPTION
CENTRAL PROCESSING UNIT (CPU)
The 3825 group uses the standard 740 family instruction set. Re-
fer to the table of 740 family addressing modes and machine
instructions or the 740 Family Software Manual for details on the
instruction set.
Machine-resident 740 family instructions are as follows:
The FST and SLW instruction cannot be used.
The STP, WIT, MUL, and DIV instruction can be used.
[Accumulator (A)]
The accumulator is an 8-bit register. Data operations such as data
transfer, etc., are executed mainly through the accumulator.
[Index Register X (X)]
The index register X is an 8-bit register. In the index addressing
modes, the value of the OPERAND is added to the contents of
register X and specifies the real address.
[Index Register Y (Y)]
The index register Y is an 8-bit register. In partial instruction, the
value of the OPERAND is added to the contents of register Y and
specifies the real address.
[Stack Pointer (S)]
The stack pointer is an 8-bit register used during subroutine calls
and interrupts. This register indicates start address of stored area
(stack) for storing registers during subroutine calls and interrupts.
The low-order 8 bits of the stack address are determined by the
contents of the stack pointer. The high-order 8 bits of the stack
address are determined by the stack page selection bit. If the
stack page selection bit is “0” , the high-order 8 bits becomes
“0016”. If the stack page selection bit is “1”, the high-order 8 bits
becomes “0116”.
The operations of pushing register contents onto the stack and
popping them from the stack are shown in Figure 9.
Store registers other than those described in Figure 9 with pro-
gram when the user needs them during interrupts or subroutine
calls.
[Program Counter (PC)]
The program counter is a 16-bit counter consisting of two 8-bit
registers PCH and PCL. It is used to indicate the address of the
next instruction to be executed.
Fig. 8 740 Family CPU register structure
A Accumulator
b7
b7
b7
b7 b0
b7b15 b0
b7 b0
b0
b0
b0
X Index register X
Y Index register Y
S Stack pointer
PC
L
Program counterPC
H
N V T B D I Z C Processor status register (PS)
Carry flag
Zero flag
Interrupt disable flag
Decimal mode flag
Break flag
Index X mode flag
Overflow flag
Negative flag
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
3825 Group
12
Table 6 Push and pop instructions of accumulator or processor status register
Accumulator
Processor status register
Push instruction to stack
PHA
PHP
Pop instruction from stack
PLA
PLP
Fig. 9 Register push and pop at interrupt generation and subroutine call
N
o
t
e:
C
o
n
d
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t
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f
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r
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c
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p
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a
b
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f
l
a
g
i
s
“
1
”
E
x
e
c
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e
J
S
R
O
n
-
g
o
i
n
g
R
o
u
t
i
n
e
M
(
S
)(
P
CH)
(
S
)
(
S
)
–
1
M
(
S
)(
P
CL)
E
x
e
c
u
t
e
R
T
S
(
P
CL)M
(
S
)
(
S
)
(
S
)
–
1
(
S
)
(
S
)
+
1
(
S
)
(
S
)
+
1
(
P
CH)M
(
S
)
S
u
b
r
o
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t
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e
P
O
P
re
t
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n
a
d
d
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m
s
t
a
c
k
P
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h
r
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t
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n
a
d
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s
s
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t
a
c
kM
(
S
)(
P
S
)
E
x
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c
u
t
e
R
T
I
(
P
S
)M
(
S
)
(
S
)
(
S
)
–
1
(
S
)
(
S
)
+
1
I
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r
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f
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m
s
t
a
c
k
M
(
S
)(
P
CH)
(
S
)
(
S
)
–
1
M
(
S
)(
P
CL)
(
S
)
(
S
)
–
1
(
P
CL)M
(
S
)
(
S
)
(
S
)
+
1
(
S
)
(
S
)
+
1
(
P
CH)M
(
S
)
P
O
P
r
e
t
u
r
n
a
d
d
r
e
s
s
f
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o
m
s
t
a
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k
I
F
l
a
g
i
s
s
e
t
f
r
o
m
“
0
”
t
o
“
1
”
F
e
t
c
h
t
h
e
j
u
m
p
v
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c
t
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r
P
u
s
h
r
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t
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n
a
d
d
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t
a
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c
k
I
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r
u
p
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e
q
u
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s
t
(
N
o
t
e
)
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n
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r
r
u
p
t
d
i
s
a
b
l
e
f
l
a
g
i
s
“
0
”
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
3825 Group
13
[Processor status register (PS)]
The processor status register is an 8-bit register consisting of 5
flags which indicate the status of the processor after an arithmetic
operation and 3 flags which decide MCU operation. Branch opera-
tions can be performed by testing the Carry (C) flag , Zero (Z) flag,
Overflow (V) flag, or the Negative (N) flag. In decimal mode, the Z,
V, N flags are not valid.
•Bit 0: Carry flag (C)
The C flag contains a carry or borrow generated by the arithmetic
logic unit (ALU) immediately after an arithmetic operation. It can
also be changed by a shift or rotate instruction.
•Bit 1: Zero flag (Z)
The Z flag is set if the result of an immediate arithmetic operation
or a data transfer is “0”, and cleared if the result is anything other
than “0”.
•Bit 2: Interrupt disable flag (I)
The I flag disables all interrupts except for the interrupt
generated by the BRK instruction.
Interrupts are disabled when the I flag is “1”.
•Bit 3: Decimal mode flag (D)
The D flag determines whether additions and subtractions are
executed in binary or decimal. Binary arithmetic is executed when
this flag is “0”; decimal arithmetic is executed when it is “1”.
Decimal correction is automatic in decimal mode. Only the ADC
•Bit 4: Break flag (B)
The B flag is used to indicate that the current interrupt was
generated by the BRK instruction. The BRK flag in the processor
status register is always “0”. When the BRK instruction is used to
generate an interrupt, the processor status register is pushed
onto the stack with the break flag set to “1”.
•Bit 5: Index X mode flag (T)
When the T flag is “0”, arithmetic operations are performed
between accumulator and memory. When the T flag is “1”, direct
arithmetic operations and direct data transfers are enabled
between memory locations.
•Bit 6: Overflow flag (V)
The V flag is used during the addition or subtraction of one byte
of signed data. It is set if the result exceeds +127 to -128. When
the BIT instruction is executed, bit 6 of the memory location
operated on by the BIT instruction is stored in the overflow flag.
•Bit 7: Negative flag (N)
The N flag is set if the result of an arithmetic operation or data
transfer is negative. When the BIT instruction is executed, bit 7 of
the memory location operated on by the BIT instruction is stored
in the negative flag.
Table 7 Set and clear instructions of each bit of processor status register
Set instruction
Clear instruction
C flag
SEC
CLC
Z flag
–
–
I flag
SEI
CLI
D flag
SED
CLD
B flag
–
–
T flag
SET
CLT
V flag
–
CLV
N flag
–
–
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
3825 Group
14
[CPU Mode Register (CPUM)] 003B16
The CPU mode register contains the stack page selection bit and
the internal system clock selection bit.
The CPU mode register is allocated at address 003B16.
Fig. 10 Structure of CPU mode register
N
o
t
a
v
a
i
l
a
b
l
e
P
roc essor mo
d
e
bi
ts
b1 b0
0 0 : Single-chip mode
0 1 :
1 0 :
1 1 :
Stack page selection bit
0 : 0 page
1 : 1 page
Not used (retu rns “1” when r ead)
(Do no t write “0” to this bit)
Port XC switch bit
0 : I/O port function (stop oscillati ng)
1 : XCIN–XCOUT oscillating function
Main clock (XIN–XOUT) stop bit
0 : Oscillating
1 : Stopped
Main clock division ratio selection bit
0 : f(XIN)/2 (high - speed mode)
1 : f(XIN)/8 (middle-speed mode)
Internal system clock selection bit
0 : XIN–XOUT selected ( middle-/high-speed mode)
1 : XCIN–XCOUT selecte d ( low-s peed mode)
CPU
mo
d
e reg
i
ster
(
C
P
U
M
(
C
M
)
:
a
d
d
r
e
s
s
0
0
3
B
1
6
)
b
7
b
0
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
3825 Group
15
MEMORY
Special Function Register (SFR) Area
The Special Function Register area in the zero page contains con-
trol registers such as I/O ports and timers.
RAM
RAM is used for data storage and for stack area of subroutine
calls and interrupts.
ROM
The first 128 bytes and the last 2 bytes of ROM are reserved for
device testing and the rest is user area for storing programs.
Interrupt Vector Area
The interrupt vector area contains reset and interrupt vectors.
Zero Page
The 256 bytes from addresses 000016 to 00FF16 are called the
zero page area. The internal RAM and the special function regis-
ters (SFR) are allocated to this area.
The zero page addressing mode can be used to specify memory
and register addresses in the zero page area. Access to this area
with only 2 bytes is possible in the zero page addressing mode.
Special Page
The 256 bytes from addresses FF0016 to FFFF16 are called the
special page area. The special page addressing mode can be
used to specify memory addresses in the special page area. Ac-
cess to this area with only 2 bytes is possible in the special page
addressing mode.
Fig. 11 Memory map diagram
192
256
384
512
640
768
896
1024
1536
2048
00
FF
16
013F
16
01BF
16
023F
16
02BF
16
033F
16
03BF
16
043F
16
063F
16
083F
16
RAM
area
R
A
M
s
i
z
e
(
b
y
t
e
s
)
A
d
d
r
e
s
s
X
X
X
X
1
6
409
6
819
2
1228
8
1638
4
2048
0
2457
6
2867
2
3276
8
3686
4
4096
0
4505
6
4915
2
5324
8
5734
4
6144
0
F
000
16
E000
16
D000
16
C000
16
B000
16
A000
16
9000
16
8000
16
7000
16
6000
16
5000
16
4000
16
3000
16
2000
16
1000
16
F
080
16
E080
16
D080
16
C080
16
B080
16
A080
16
9080
16
8080
16
7080
16
6080
16
5080
16
4080
16
3080
16
2080
16
1080
16
ROM
area
ROM
s
i
ze
(bytes)
A
d
d
r
e
s
s
Y
Y
Y
Y
1
6
A
d
d
r
e
s
s
Z
Z
Z
Z
1
6
0100
16
0000
16
0040
16
0840
16
FF
00
16
FFDC
16
F
F
F
E
1
6
FFFF
16
XXXX
16
YYYY
16
ZZZZ
16
RAM
R
O
M
0054
16
R
eserve
d
area
S
F
R
a
r
e
a
N
ot use
d
I
n
t
e
r
r
u
p
t
v
e
c
t
o
r
a
r
e
a
R
eserve
d
ROM
area
(128 bytes )
Z
e
r
o
p
a
g
e
S
pec
i
a
l
page
LCD
di
sp
l
ay
RAM
area
R
e
s
e
r
v
e
d
R
O
M
a
r
e
a
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
3825 Group
16
Fig. 12 Memory map of special function register (SFR)
002016
002116
002216
002316
002416
002516
002616
002716
002816
002916
002
A
16
002
B
16
0
0
2
C
1
6
0
0
2
D
1
6
002
E
16
002
F
16
003016
003116
003216
003316
003416
003516
003616
003716
003816
003916
003
A
16
003
B
16
0
0
3
C
1
6
003
D
16
003
E
16
003
F
16
0
0
0
01
6
000116
000216
0
0
0
31
6
0
0
0
41
6
000516
0
0
0
61
6
0
0
0
71
6
0
0
0
81
6
0
0
0
91
6
000
A
16
0
0
0
B
1
6
000
C
16
000
D
16
0
0
0
E
1
6
000
F
16
001016
001116
001216
0
0
1
31
6
0
0
1
41
6
001516
001616
001716
0
0
1
81
6
0
0
1
91
6
001
A
16
001
B
16
001
C
16
001
D
16
001
E
16
0
0
1
F
1
6
P
o
r
t
P
0
(
P
0
)
P
ort
P
1
(P
1
)
P
o
r
t
P
1
o
u
t
p
u
t
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
(
P
1
C
)
P
o
r
t
P
2
(
P
2
)
P
ort
P
2
di
rect
i
on reg
i
ster
(P
2
D)
P
o
r
t
P
3
(
P
3
)
P
o
r
t
P
4
(
P
4
)
P
o
r
t
P
4
d
i
r
e
c
t
i
o
n
r
e
g
i
s
t
e
r
(
P
4
D
)
P
ort
P
5
(P
5
)
P
o
r
t
P
5
d
i
r
e
c
t
i
o
n
r
e
g
i
s
t
e
r
(
P
5
D
)
P
o
r
t
P
6
(
P
6
)
P
o
r
t
P
6
d
i
r
e
c
t
i
o
n
r
e
g
i
s
t
e
r
(
P
6
D
)
P
o
r
t
P
7
(
P
7
)
P
o
r
t
P
7
d
i
r
e
c
t
i
o
n
r
e
g
i
s
t
e
r
(
P
7
D
)
S
er
i
a
l
I
/
O
status reg
i
ster
(SIOSTS)
S
er
i
a
l
I
/
O
cont ro
l
re g
i
ster
(SIO
1
CON)
U
A
R
T
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
(
U
A
R
T
C
O
N
)
B
au
d
rate generator
(BRG)
I
n
t
e
r
r
u
p
t
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
2
(
I
C
O
N
2
)
T
i
m
e
r
3
(
T
3
)
Ti
mer
X
mo
d
e reg
i
ster
(TXM)
I
n
t
e
r
r
u
p
t
e
d
g
e
s
e
l
e
c
t
i
o
n
r
e
g
i
s
t
e
r
(
I
N
T
E
D
G
E
)
C
P
U
m
o
d
e
r
e
g
i
s
t
e
r
(
C
P
U
M
)
I
nterrupt request reg
i
ster 1
(IREQ
1
)
I
nterrupt request reg
i
ster 2
(IREQ
2
)
I
n
t
e
r
r
u
p
t
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
1
(
I
C
O
N
1
)
Ti
mer
X
(l
ow
)
(TXL)
T
i
m
e
r
Y
(
l
o
w
)
(
T
Y
L
)
Ti
me r 1
(T
1
)
Ti
me r 2
(T
2
)
T
i
m
e
r
X
(
h
i
g
h
)
(
T
X
H
)
T
i
m
e
r
Y
(
h
i
g
h
)
(
T
Y
H
)
PULL
reg
i
ster
A
(PULLA)
P
U
L
L
r
e
g
i
s
t
e
r
B
(
P
U
L
L
B
)
Ti
mer
Y
mo
d
e reg
i
ster
(TYM)
Ti
me r 123 m o
d
e reg
i
ster
(T
123
M)
Cl
oc
k
output contro
l
reg
i
ster
(TCON)
S
egment output ena
bl
e reg
i
ster
(SEG)
L
C
D
m
o
d
e
r
e
g
i
s
t
e
r
(
L
M
)
A
-
D
contro
l
reg
i
ster
(ADCON)
A
-
D
convers
i
on reg
i
ster
(AD)
T
ransm
i
t/
R
ece
i
ve
b
u
ff
er reg
i
ster
(TB
/
RB)
P
o
r
t
P
8
(
P
8
)
P
ort
P
8
di
rect
i
on reg
i
ster
(P
8
D)
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
3825 Group
17
I/O PORTS
Direction Registers
The 3825 group has 43 programmable I/O pins arranged in seven
I/O ports (ports P16, P17, P2, P4–P6, P71–P77, P80 and P81). The
I/O ports have direction registers which determine the input/output
direction of each individual pin. (Ports P16 and P17 are shared
with bits 6 and 7 of the port P1 output control register). Each bit in
a direction register corresponds to one pin, and each pin can be
set to be input port or output port.
When “0” is written to the bit corresponding to a pin, that pin be-
comes an input pin. When “1” is written to that bit, that pin be-
comes an output pin.
If data is read from a pin set to output, the value of the port output
latch is read, not the value of the pin itself. Pins set to input are
floating. If a pin set to input is written to, only the port output latch
is written to and the pin remains floating.
Port P1 Output Control Register
Bit 0 of the port P1 output control register (address 000316) en-
ables control of the output of ports P10 to P15.
When the bit is set to “1”, the port output function is valid.
In this case, setting of the PULL register A to ports P10 to P15 is
invalid.
When resetting, bit 0 of the port P1 output control register is set to
“0” (the port output function is invalid.)
Pull-up/Pull-down Control
By setting the PULL register A (address 001616) or the PULL reg-
ister B (address 001716), ports P0 to P8 except P70 can control ei-
ther pull-down or pull-up (pins that are shared with the segment
output pins for LCD are pull-down; all other pins are pull-up) with
a program.
However, the contents of PULL register A and PULL register B do
not affect ports programmed as the output ports. (except for ports
P0 and P3).
Ports P0 and P3 share the port output control function with bit 0 of
the PULL register A. When set to “1”, the port output function is in-
valid (Pull-down is valid).
When set to “0”, the port output function is valid (Pull-down is in-
valid).
The PULL register A setting is invalid for pins set to segment out-
put with the segment output enable register.
Fig. 13 Structure of PULL register A and PULL register B
P
0
,
P
10–
P
15,
P
3
p
u
l
l
-
d
o
w
n
(
s
h
a
r
e
d
w
i
t
h
P
0
a
n
d
P
3
o
u
t
p
u
t
c
o
n
t
r
o
l
:
r
e
f
e
r
t
o
t
h
e
t
e
x
t
)
P
16–
P
17
p
u
l
l
-
u
p
P
20–
P
27
p
u
l
l
-
u
p
P
80,
P
81
p
u
l
l
-
u
p
P
40–
P
43
p
u
l
l
-
u
p
P
44–
P
47
p
u
l
l
-
u
p
N
o
t
u
s
e
d
(
r
e
t
u
r
n
“
0
”
w
h
e
n
r
e
a
d
)
PULL
reg
i
ster
A
(P ULLA : addres s 001616)
b
7
b
0
P
50–
P
53
p
u
l
l
-
u
p
P
54–
P
57
p
u
l
l
-
u
p
P
60–
P
63
p
u
l
l
-
u
p
P
64–
P
67
p
u
l
l
-
u
p
P
71–
P
73
p
u
l
l
-
u
p
P
74–
P
77
p
u
l
l
-
u
p
N
o
t
u
s
e
d
(
r
e
t
u
r
n
“
0
”
w
h
e
n
r
e
a
d
)
0
:
D
i
s
a
b
l
e
1
:
E
n
a
b
l
e
P
U
L
L
r
e
g
i
s
t
e
r
B
(
P
U
L
L
B
:
a
d
d
r
e
s
s
0
0
1
71
6)
b
7
b
0
N
ote:
Th
e contents o
f
PULL
reg
i
ster
A
an
d
PULL
reg
i
ster
B
do not affect ports programmed as the output port.
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
3825 Group
18
Table 8. I/O ports functions
Related SFRs
PULL register A
Segment output enable
register
PULL register A
Segment output enable
register
Port P1 output
control register
PULL register A
PULL register A
Interrupt control register 2
PULL register A
Segment output enable
register
Clock output control
register
PULL register A
PULL register A
Interrupt edge selection
register
PULL register A
Serial I/O control register
Serial I/O status register
UART control register
PULL register B
Interrupt edge selection
register
PULL register B
Timer X mode register
PULL register B
Timer X mode register
PULL register B
Timer Y mode register
PULL register B
Timer 123 mode register
PULL register B
A-D control register
PULL register B
A-D control register
PULL register B
PULL register A
CPU mode register
LCD mode register
Input/Output
Output
Output
Input/output,
individual bits
Input/output,
individual bits
Output
Input/output,
individual bits
Input/output,
individual bits
Input/output,
individual bits
Input
Input/output,
individual bits
Input/output,
individual bits
Output
Output
Name
Port P0
Port P1
Port P2
Port P3
Port P4
Port P5
Port P6
Port P7
Port P8
Common
Segment
Pin
P00/SEG26–
P07/SEG33
P10/SEG34–
P15/SEG39
P16 , P17
P20–P27
P30/SEG18–
P37/SEG25
P40/f(XIN)/
f(XIN)/2,
P41/f(XIN)/5/
f(XIN)/10
P42/INT0,
P43/INT1
P44/RXD
P54/TXD
P46/SCLK
P47/SRDY
P50/INT2,
P51/INT3
P52/RTP0,
P53/RTP1
P54/CNTR0
P55/CNTR1
P56/TOUT
P57/ADT
P60/AN0–
P67/AN7
P70
P71–P77
P80/XCOUT
P81/XCIN
COM0–COM3
SEG0–SEG17
Non-Port Function
LCD segment output
LCD segment output
Key-on wake up
interrupt input
LCD segment output
Clock output
External interrupt input
Serial I/O function I/O
External interrupt input
Real time port
function output
Timer X function I/O
Timer Y function input
Timer 2 output
A-D trigger input
A-D conversion input
Sub-clock
generating circuit
I/O Format
CMOS 3-state output
CMOS 3-state output
CMOS compatible
input level
CMOS 3-state output
CMOS compatible
input level
CMOS 3-state output
CMOS 3-state output
CMOS compatible
input level
CMOS 3-state output
CMOS compatible
input level
CMOS 3-state output
CMOS compatible
input level
CMOS 3-state output
CMOS compatible
input level
CMOS compatible
input level
CMOS 3-state output
CMOS compatible
input level
CMOS 3-state output
LCD common output
LCD segment output
Diagram No.
(1)
(1)
(2)
(2)
(1)
(2)
(3)
(4)
(5)
(6)
(2)
(7)
(8)
(9)
(8)
(9)
(10)
(11)
(12)
(13)
(14)
(15)
(16)
Note 1: When using double-function ports as functional I/O pins, refer the method to the relevant sections.
2: Make sure that the input level at each pin is either 0 V or VCC during execution of the STP instruction.
When an input level is at an intermediate potential, a current will flow from VCC to VSS through the input-stage gate.
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
3825 Group
19
Fig. 14 Port block diagram (1)
(
3
)
P
o
r
t
P
4
4
P
u
ll
-up contr o
l
S
e
r
i
a
l
I
/
O
e
n
a
b
l
e
b
i
t
S
er
i
a
l
I
/
O
i
nput
D
ata
b
us
Di
rect
i
on
register
P
ort
l
atc
h
(
4
)
P
ort
P
4
5
P
u
l
l
-
u
p
c
o
n
t
r
o
l
Di
rect
i
on
register
D
ata
b
us
P
ort
l
atc
h
S
er
i
a
l
I
/
O
out pu
t
P
4
5
/
T
X
D
P
-
c
h
a
n
n
e
l
o
u
t
p
u
t
d
i
s
a
b
l
e
b
i
t
S
er
i
a
l
I
/
O
ena
bl
e
bit
Transmi ssion en able bi
t
(
6
)
P
ort
P
4
7
S
er
i
a
l
I
/
O
re a
d
y output
S
e
r
i
a
l
I
/
O
m
o
d
e
s
e
l
e
c
t
i
o
n
b
i
t
S
e
r
i
a
l
I
/
O
e
n
a
b
l
e
b
i
t
S
R
D
Y
o
u
t
p
u
t
e
n
a
b
l
e
b
i
t
D
a
t
a
b
u
s
P
u
ll
-up contr o
l
D
i
r
e
c
t
i
o
n
r
e
g
i
s
t
e
r
P
ort
l
atc
h
(
7
)
P
orts
P
5
2
,
P
5
3
R
ea
l
t
i
me contro
l
bit
P
u
l
l
-
u
p
c
o
n
t
r
o
l
D
ata
b
us
P
o
r
t
l
a
t
c
h
D
i
r
e
c
t
i
o
n
r
e
g
i
s
t
e
r
R
ea
l
t
i
me port
d
ata
(
1
)
P
o
r
t
s
P
0
,
P
1
0
–
P
1
5
,
P
3
V
L
2
/
V
L
3
/
V
C
C
D
a
t
a
b
u
s
P
o
r
t
l
a
t
c
h
I
n
t
e
r
f
a
c
e
l
o
g
i
c
l
e
v
e
l
s
h
i
f
t
c
i
r
c
u
i
t
P
u
ll
-
d
own
P
ort
S
e
g
m
e
n
t
V
L
1
/
V
S
S
S
egment/
P
ort
L
C
D
d
r
i
v
e
t
i
m
i
n
g
P
o
r
t
/
S
e
g
m
e
n
t
S
e
g
m
e
n
t
d
a
t
a
P
o
r
t
O
N
/
O
F
F
(
2
)
P
o
r
t
s
P
1
6
,
P
1
7
,
P
2
,
P
4
0
–
P
4
3
,
P
5
0
,
P
5
1
K
e
y
-
o
n
w
a
k
e
u
p
i
n
t
e
r
r
u
p
t
i
n
p
u
t
I
N
T
0
–
I
N
T
3
i
n
t
e
r
r
u
p
t
i
n
p
u
t
P
u
ll
-up contr o
l
D
ata
b
us
P
ort
l
atc
h
Di
rect
i
on
register
E
xcept
P
1
6
,
P
1
7
,
P
4
0
,
P
4
1
(
5
)
P
ort
P
4
6
S
er
i
a
l
I
/
O
ena
bl
e
bi
t
S
er
i
a
l
I
/
O
c
l
oc
k
i
nput
P
u
ll
-up contr o
l
D
a
t
a
b
u
s
S
er
i
a
l
I
/
O
c
l
oc
k
output
S
er
i
a
l
I
/
O
sync
h
ron
i
zat
i
on c
l
oc
k
selection bit
D
i
r
e
c
t
i
o
n
r
e
g
i
s
t
e
r
P
o
r
t
l
a
t
c
h
S
er
i
a
l
I
/
O
mo
d
e se
l
ect
i
on
bit
Seria l I/O enabl e bi
t
R
e
c
e
p
t
i
o
n
e
n
a
b
l
e
b
i
t
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
3825 Group
20
Fig. 15 Port block diagram (2)
(
9
)
P
o
r
t
s
P
55,
P
57
D
ata
b
us
P
u
l
l
-
u
p
c
o
n
t
r
o
l
C
N
T
R
1
i
n
t
e
r
r
u
p
t
i
n
p
u
t
A
-
D
t
r
i
g
g
e
r
i
n
t
e
r
r
u
p
t
i
n
p
u
t
Di
rect
i
on
register
P
o
r
t
l
a
t
c
h
(
10
)
P
ort
P
6
D
ata
b
us
P
u
l
l
-
u
p
c
o
n
t
r
o
l
Di
rect
i
on
register
P
o
r
t
l
a
t
c
h
A
-
D
c
o
n
v
e
r
s
i
o
n
i
n
p
u
t
A
n
a
l
o
g
i
n
p
u
t
p
i
n
s
e
l
e
c
t
i
o
n
b
i
t
(
1
3
)
P
o
r
t
P
80
D
a
t
a
b
u
s
P
o
r
t
X
c
s
w
i
t
c
h
b
i
t
+
P
u
l
l
-
u
p
c
o
n
t
r
o
l
P
ort
X
C sw
i
tc
h
bi
t
O
sc
ill
at
i
on c
i
rcu
i
t
P
ort
P
81
P
ort
X
C sw
i
tc
h
bi
t
D
i
r
e
c
t
i
o
n
r
e
g
i
s
t
e
r
P
o
r
t
l
a
t
c
h
(
1
5
)
C
O
M
0–
C
O
M
3
V
L3
V
L
2
V
L
1
Th
e gat e
i
nput s
i
gna
l
o
f
eac
h
transistor is controlled by the
LCD duty ratio and the bia
s
value.
V
S
S
(
16
)
SEG
0–
SEG
17
T
h
e
v
o
l
t
a
g
e
a
p
p
l
i
e
d
t
o
t
h
e
s
o
u
r
c
e
s
o
f
P
-
c
h
a
n
n
e
l
a
n
d
N
-
c
h
a
n
n
e
l
t
r
a
n
s
i
s
t
o
r
s
i
s
t
h
e
c
o
n
t
r
o
l
l
e
d
v
o
l
t
a
g
e
b
y
t
h
e
b
i
a
s
v
a
l
u
e
.
V
L
2/
V
L
3
V
L1/
V
SS
P
u
l
s
e
o
u
t
p
u
t
m
o
d
e
C
N
T
R
0
i
n
t
e
r
r
u
p
t
i
n
p
u
t
T
i
m
e
r
o
u
t
p
u
t
D
i
r
e
c
t
i
o
n
r
e
g
i
s
t
e
r
P
o
r
t
l
a
t
c
h
D
a
t
a
b
u
s
P
54
o
n
l
y
(
1
1
)
P
o
r
t
P
70
(
12
)
P
orts
P
71–
P
77
D
a
t
a
b
u
s
Di
rect
i
on
register
P
o
r
t
l
a
t
c
h
(
14
)
P
ort
P
81
D
ata
b
us
P
o
r
t
X
C
s
w
i
t
c
h
b
i
t
S
u
b
-c
l
oc
k
generat
i
ng c
i
rcu
i
t
i
nput
D
i
r
e
c
t
i
o
n
r
e
g
i
s
t
e
r
P
ort
l
atc
h
P
u
ll
-up contr o
l
D
a
t
a
b
u
s
P
u
l
l
-
u
p
c
o
n
t
r
o
l
(
8
)
P
o
r
t
s
P
54,
P
56
P
o
r
t
X
c
s
w
i
t
c
h
b
i
t
+
P
u
l
l
-
u
p
c
o
n
t
r
o
l
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
3825 Group
21
Remarks
Non-maskable
External interrupt
(active edge selectable)
External interrupt
(active edge selectable)
Valid when serial I/O is selected
Valid when serial I/O is selected
External interrupt
(active edge selectable)
External interrupt
(active edge selectable)
External interrupt
(active edge selectable)
External interrupt
(active edge selectable)
External interrupt
(valid when an “L” level is applied)
Valid when A-D interrupt is
selected
Non-maskable software interrupt
Interrupt Request
Generating Conditions
At reset
At detection of either rising or
falling edge of INT0 input
At detection of either rising or
falling edge of INT1 input
At completion of serial I/O data
reception
At completion of serial I/O transmit
shift or when transmission buffer is
empty
At timer X underflow
At timer Y underflow
At timer 2 underflow
At timer 3 underflow
At detection of either rising or
falling edge of CNTR0 input
At detection of either rising or
falling edge of CNTR1 input
At timer 1 underflow
At detection of either rising or
falling edge of INT2 input
At detection of either rising or
falling edge of INT3 input
At falling of conjunction of input
level for port P2 (at input mode)
At falling of ADT input
At completion of A-D conversion
At BRK instruction execution
Valid when ADT interrupt is selected
External interrupt
(Valid at falling)
Notes 1: Vector addresses contain interrupt jump destination addresses.
2: Reset function in the same way as an interrupt with the highest priority.
INTERRUPTS
Interrupts occur by seventeen sources: eight external, eight inter-
nal, and one software.
Interrupt Control
Each interrupt is controlled by an interrupt request bit, an interrupt
enable bit, and the interrupt disable flag except for the software in-
terrupt set by the BRK instruction. An interrupt occurs if the corre-
sponding interrupt request and enable bits are “1” and the inter-
rupt disable flag is “0”.
Interrupt enable bits can be set or cleared by software.
Interrupt request bits can be cleared by software, but cannot be
set by software.
The BRK instruction cannot be disabled with any flag or bit. The I
flag disables all interrupts except the BRK instruction interrupt.
When several interrupts occur at the same time, the interrupts are
received according to priority.
Interrupt Operation
By acceptance of an interrupt, the following operations are auto-
matically performed:
1. The contents of the program counter and the processor status
register are automatically pushed onto the stack.
2. The interrupt disable flag is set and the corresponding interrupt
request bit is cleared.
3. The interrupt jump destination address is read from the vector
table into the program counter.
Interrupt Source
Reset (Note 2)
INT0
INT1
Serial I/O
reception
Serial I/O
transmission
Timer X
T imer Y
Timer 2
Timer 3
CNTR0
CNTR1
Timer 1
INT2
INT3
Key input
(Key-on wake up)
ADT
A-D conversion
BRK instruction
Low
FFFC16
FFFA16
FFF816
FFF616
FFF416
FFF216
FFF016
FFEE16
FFEC16
FFEA16
FFE816
FFE616
FFE416
FFE216
FFE016
FFDE16
FFDC16
High
FFFD16
FFFB16
FFF916
FFF716
FFF516
FFF316
FFF116
FFEF16
FFED16
FFEB16
FFE916
FFE716
FFE516
FFE316
FFE116
FFDF16
FFDD16
Table 9. Interrupt vector addresses and priority
Priority
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
Vector Addresses (Note 1)
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
3825 Group
22
Fig. 16 Interrupt control
Fig. 17 Structure of interrupt-related registers
I
n
t
e
r
r
u
p
t
r
e
q
u
e
s
t
b
i
t
I
n
t
e
r
r
u
p
t
e
n
a
b
l
e
b
i
t
I
n
t
e
r
r
u
p
t
d
i
s
a
b
l
e
f
l
a
g
(
I
)
B
R
K
i
n
s
t
r
u
c
t
i
o
n
R
e
s
e
t
I
n
t
e
r
r
u
p
t
r
e
q
u
e
s
t
b
7
b
0
I
n
t
e
r
r
u
p
t
e
d
g
e
s
e
l
e
c
t
i
o
n
r
e
g
i
s
t
e
r
I
N
T
0
i
n
t
e
r
r
u
p
t
e
d
g
e
s
e
l
e
c
t
i
o
n
b
i
t
I
N
T
1
i
n
t
e
r
r
u
p
t
e
d
g
e
s
e
l
e
c
t
i
o
n
b
i
t
I
N
T
2
i
n
t
e
r
r
u
p
t
e
d
g
e
s
e
l
e
c
t
i
o
n
b
i
t
I
N
T
3
i
n
t
e
r
r
u
p
t
e
d
g
e
s
e
l
e
c
t
i
o
n
b
i
t
N
o
t
u
s
e
d
(
r
e
t
u
r
n
“
0
”
w
h
e
n
r
e
a
d
)
(INTEDGE
: a
dd
ress 003
A
16
)
I
n
t
e
r
r
u
p
t
r
e
q
u
e
s
t
r
e
g
i
s
t
e
r
1
I
N
T
0
i
n
t
e
r
r
u
p
t
r
e
q
u
e
s
t
b
i
t
I
N
T
1
i
n
t
e
r
r
u
p
t
r
e
q
u
e
s
t
b
i
t
S
e
r
i
a
l
I
/
O
r
e
c
e
i
v
e
i
n
t
e
r
r
u
p
t
r
e
q
u
e
s
t
b
i
t
S
e
r
i
a
l
I
/
O
t
r
a
n
s
m
i
t
i
n
t
e
r
r
u
p
t
r
e
q
u
e
s
t
b
i
t
T
i
m
e
r
X
i
n
t
e
r
r
u
p
t
r
e
q
u
e
s
t
b
i
t
T
i
m
e
r
Y
i
n
t
e
r
r
u
p
t
r
e
q
u
e
s
t
b
i
t
T
i
m
e
r
2
i
n
t
e
r
r
u
p
t
r
e
q
u
e
s
t
b
i
t
T
i
m
e
r
3
i
n
t
e
r
r
u
p
t
r
e
q
u
e
s
t
b
i
t
I
n
t
e
r
r
u
p
t
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
1
I
N
T
0
i
n
t
e
r
r
u
p
t
e
n
a
b
l
e
b
i
t
I
N
T
1
i
n
t
e
r
r
u
p
t
e
n
a
b
l
e
b
i
t
S
e
r
i
a
l
I
/
O
r
e
c
e
i
v
e
i
n
t
e
r
r
u
p
t
e
n
a
b
l
e
b
i
t
S
e
r
i
a
l
I
/
O
t
r
a
n
s
m
i
t
i
n
t
e
r
r
u
p
t
e
n
a
b
l
e
b
i
t
T
i
m
e
r
X
i
n
t
e
r
r
u
p
t
e
n
a
b
l
e
b
i
t
T
i
m
e
r
Y
i
n
t
e
r
r
u
p
t
e
n
a
b
l
e
b
i
t
T
i
m
e
r
2
i
n
t
e
r
r
u
p
t
e
n
a
b
l
e
b
i
t
T
i
m
e
r
3
i
n
t
e
r
r
u
p
t
e
n
a
b
l
e
b
i
t
0
:
N
o
i
n
t
e
r
r
u
p
t
r
e
q
u
e
s
t
i
s
s
u
e
d
1
:
I
n
t
e
r
r
u
p
t
r
e
q
u
e
s
t
i
s
s
u
e
d
(
I
R
E
Q
1
:
a
d
d
r
e
s
s
0
0
3
C
1
6
)
(
I
C
O
N
1
:
a
d
d
r
e
s
s
0
0
3
E
1
6
)
I
n
t
e
r
r
u
p
t
r
e
q
u
e
s
t
r
e
g
i
s
t
e
r
2
CNTR
0
i
nterrupt request
bi
t
CNTR
1
interrupt request bit
Timer 1 interrupt request bit
INT
2
interrupt request bit
INT
3
interrupt request bit
Key input interrupt request b it
ADT/AD conversion interrupt request bit
Not used (retu rns “0” when r ead)
(
I
R
E
Q
2
:
a
d
d
r
e
s
s
0
0
3
D
1
6
)
I
nterrupt contr o
l
reg
i
ster 2
C
N
T
R
0
i
n
t
e
r
r
u
p
t
e
n
a
b
l
e
b
i
t
C
N
T
R
1
i
n
t
e
r
r
u
p
t
e
n
a
b
l
e
b
i
t
T
i
m
e
r
1
i
n
t
e
r
r
u
p
t
e
n
a
b
l
e
b
i
t
I
N
T
2
i
n
t
e
r
r
u
p
t
e
n
a
b
l
e
b
i
t
I
N
T
3
i
n
t
e
r
r
u
p
t
e
n
a
b
l
e
b
i
t
K
e
y
i
n
p
u
t
i
n
t
e
r
r
u
p
t
e
n
a
b
l
e
b
i
t
A
D
T
/
A
D
c
o
n
v
e
r
s
i
o
n
i
n
t
e
r
r
u
p
t
e
n
a
b
l
e
b
i
t
N
o
t
u
s
e
d
(
r
e
t
u
r
n
s
“
0
”
w
h
e
n
r
e
a
d
)
(
D
o
n
o
t
w
r
i
t
e
“
1
”
t
o
t
h
i
s
b
i
t
)
0
:
I
n
t
e
r
r
u
p
t
s
d
i
s
a
b
l
e
d
1
:
I
n
t
e
r
r
u
p
t
s
e
n
a
b
l
e
d
(ICON
2 : a
dd
ress 003
F
16
)
0
:
F
a
l
l
i
n
g
e
d
g
e
a
c
t
i
v
e
1
:
R
i
s
i
n
g
e
d
g
e
a
c
t
i
v
e
b
7
b
0
b
7
b
0
b
7
b
0
b
7
b
0
■Notes on interrupts
When setting the followings, the interrupt request bit may be set to
“1”.
•When setting external interrupt active edge
Related register: Interrupt edge selection register (address 3A16)
Timer X mode register (address 2716)
Timer Y mode register (address 2816)
•When switching interrupt sources of an interrupt vector address
where two or more interrupt sources are allocated
Related register: A-D control regsiter (address 3416)
When not requiring for the interrupt occurrence synchronized with
these setting, take the following sequence.
➀Set the corresponding interrupt enable bit to “0” (disabled).
➁Set the interrupt edge select bit or the interrupt source select bit
to “1”.
➂Set the corresponding interrupt request bit to “0” after 1 or more
instructions have been executed.
➃Set the corresponding interrupt enable bit to “1” (enabled).
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
3825 Group
23
Key Input Interrupt (Key-on Wake Up)
A Key-on wake up interrupt request is generated by applying a
falling edge to any pin of port P2 that have been set to input mode.
In other words, it is generated when AND of input level goes from
“1” to “0”. An example of using a key input interrupt is shown in
Figure 18, where an interrupt request is generated by pressing
one of the keys consisted as an active-low key matrix which inputs
to ports P20–P23.
Fig. 18 Connection example when using key input interrupt and port P2 block diagram
✽
✽
✽
✽
✽ ✽
✽
✽
✽
✽
✽
✽
✽
✽
✽✽
✽
✽
✽
✽
✽
✽
✽
✽P
o
r
t
P
20
l
a
t
c
h
Port P20
direction register = “0”
P
o
r
t
P
21
l
a
t
c
h
Port P21
direction register = “0”
Port P22
latch
Port P22
direction register = “0”
P
o
r
t
P
23
l
a
t
c
h
Port P23
direction register = “0”
Port P24
latch
Port P24
direction register = “1”
Port P25
latch
Port P25
direction register = “1”
P
o
r
t
P
26
l
a
t
c
h
P
o
r
t
P
26
d
i
r
e
c
t
i
o
n
r
e
g
i
s
t
e
r
=
“
1
”
P
o
r
t
P
27
l
a
t
c
h
P
o
r
t
P
27
d
i
r
e
c
t
i
o
n
r
e
g
i
s
t
e
r
=
“
1
”
P
20
i
n
p
u
t
P21 input
P
22
i
n
p
u
t
P23 input
P24 output
P25 output
P
26
o
u
t
p
u
t
P27 output
P
U
L
L
r
e
g
i
s
t
e
r
A
B
i
t
2
=
“
1
”
Port P2
Input reading circuit
P
o
r
t
P
X
x
“
L
”
l
e
v
e
l
o
u
t
p
u
t
✽ P
-
c
h
a
n
n
e
l
t
r
a
n
s
i
s
t
o
r
f
o
r
p
u
l
l
-
u
p
✽
✽
C
M
O
S
o
u
t
p
u
t
b
u
f
f
e
r
K
e
y
i
n
p
u
t
i
n
t
e
r
r
u
p
t
r
e
q
u
e
s
t
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
3825 Group
24
TIMERS
The 3825 group has five timers: timer X, timer Y, timer 1, timer 2,
and timer 3. Timer X and timer Y are 16-bit timers, and timer 1,
timer 2, and timer 3 are 8-bit timers.
All timers are down count timers. When the timer reaches “0016”,
an underflow occurs at the next count pulse and the correspond-
ing timer latch is reloaded into the timer and the count is contin-
ued. When a timer underflows, the interrupt request bit corre-
sponding to that timer is set to “1”.
Read and write operation on 16-bit timer must be performed for
both high- and low-order bytes. When reading a 16-bit timer, read
the high-order byte first. When writing to a 16-bit timer, write the
low-order byte first. The 16-bit timer cannot perform the correct op-
eration when reading during the write operation, or when writing
during the read operation.
Fig. 19 Timer block diagram
CNTR
0
act
i
ve
edge switch bit
T
i
m
e
r
1
c
o
u
n
t
s
o
u
r
c
e
s
e
l
e
c
t
i
o
n
b
i
t
R
ea
l
t
i
me port
contr ol bit “0”
“
1
”
P
5
5
/
CNTR
1
“0”
f(X
IN
)
/16
(
f
(
X
CIN
)
/16 in lo w-s
p
eed mode
]
)
C
N
T
R
1
a
c
t
i
v
e
e
d
g
e
s
w
i
t
c
h
b
i
t
“10”
Ti
mer
Y
stop
contr ol bit
Falling edge detection
P
er
i
o
d
measurement mode
Ti
mer
Y
interrupt
request
Pul s e width HL c ontinuously m easurem ent mo de
Rising edge detection
“
0
0
”
,
“
0
1
”
,
“
1
1
”
T
i
m
e
r
Y
o
p
e
r
a
t
i
n
g
m
o
d
e
b
i
t
s
Ti
mer
X
interrupt
request
Ti
mer
X
mo
d
e reg
i
ster
write signal
P
5
4
/
C
N
T
R
0
Q
Q
T
S
P
5
4
d
i
r
e
c
t
i
o
n
r
e
g
i
s
t
e
r
P
u
l
se outpu t mo
d
e
P
5
4
l
atc
h
T
i
m
e
r
X
s
t
o
p
c
o
n
t
r
o
l
b
i
t
“0”
“1”
T
i
m
e
r
X
w
r
i
t
e
c
o
n
t
r
o
l
b
i
t
Q
D
L
a
t
c
h
Q
D
L
a
t
c
h
“1”
“0”
“
1
”“
1
0
”
Timer X operat-
ing m ode bit s
“00”,“01”,“11”
f
(
X
I
N
)
/
1
6
(
f
(
X
C
I
N
)
/
1
6
i
n
l
o
w
-
s
p
e
e
d
m
o
d
e
✽
)
P
u
l
se w
id
t
h
measurement
mode
C
N
T
R
0
a
c
t
i
v
e
e
d
g
e
s
w
i
t
c
h
b
i
t
P
u
l
se outpu t mo
d
e
Q
Q
T
S
“0”
P
5
6
di
rect
i
on r eg
i
ster
P
5
6
l
a
t
c
h
“
1
”
T
O
U
T
o
u
t
p
u
t
a
c
t
i
v
e
e
d
g
e
s
w
i
t
c
h
b
i
t
“
0
”
T
i
m
e
r
2
w
r
i
t
e
c
o
n
t
r
o
l
b
i
t
“0”
“1”
T
OUT
output
contr ol bit
“
1
”
P
5
6
/
T
O
U
T
X
CIN
T
i
m
e
r
3
c
o
u
n
t
s
o
u
r
c
e
s
e
l
e
c
t
i
o
n
b
i
t
“0”
“
1
”
Ti
me r 2
interrupt
request
Ti
me r 3
interrupt
request
T
O
U
T
o
u
t
p
u
t
c
o
n
t
r
o
l
b
i
t
Ti
mer 2 count source
selection bi t
Ti
me r 1
interrupt
request
D
a
t
a
b
u
s
f
(
X
I
N
)
/
1
6
(
f
(
X
C
I
N
)
/
1
6
i
n
l
o
w
-
s
p
e
e
d
m
o
d
e
]
)
f(X
IN
)/16
(
f
(
X
CIN
)
/1 6 in low-s
p
eed m ode]
)
f
(
XIN
)
/16
(
f
(
XCIN
)
/16 in low-s
p
eed mode]
)
✽Internal clock
φ
= X
CIN
/2.
CNTR
0
interrupt
request
C
N
T
R
1
i
n
t
e
r
r
u
p
t
r
e
q
u
e
s
t
Ti
mer
Y
operat
i
ng m o
d
e
bi
t
s
“00”,“01”,“10
”
“11”
P
5
2
di
rect
i
on r eg
i
ster “0”
R
e
a
l
t
i
m
e
p
o
r
t
c
o
n
t
r
o
l
b
i
t
“
1
”
P
5
2
P
5
2
l
a
t
c
h
P
5
3
d
i
r
e
c
t
i
o
n
r
e
g
i
s
t
e
r
“
0
”
R
ea
l
t
i
me port
contr ol bit “1”
P
5
3
P
5
3
l
a
t
c
h
P
5
2
d
a
t
a
f
o
r
r
e
a
l
t
i
m
e
p
o
r
t
P
5
3
d
ata
f
or rea
l
t
i
me port
Timer Y (low) (8) Timer Y (high) (8)
Ti
me r 3
l
atc
h
(
8
)
Ti
mer 3
(
8
)
T
i
m
e
r
1
l
a
t
c
h
(
8
)
Ti
me r 1
(
8
)
T
i
m
e
r
2
l
a
t
c
h
(
8
)
Ti
mer 2
(
8
)
T
i
m
e
r
X
(
l
o
w
)
(
8
)T
i
m
e
r
X
(
h
i
g
h
)
(
8
)
T
i
m
e
r
X
(
l
o
w
)
l
a
t
c
h
(
8
)T
i
m
e
r
X
(
h
i
g
h
)
l
a
t
c
h
(
8
)
Timer Y (low) latch (8) Timer Y (high) lat ch (8)
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
3825 Group
25
Timer X
Timer X is a 16-bit timer that can be selected in one of four modes
and can be controlled the timer X write and the real time port by
setting the timer X mode register.
(1) Timer mode
The timer counts f(XIN)/16 (or f(XCIN)/16 in low-speed mode).
(2) Pulse output mode
Each time the timer underflows, a signal output from the CNTR0
pin is inverted. Except for this, the operation in pulse output mode
is the same as in timer mode. When using a timer in this mode,
set the corresponding port P54 direction register to output mode.
(3) Event counter mode
The timer counts signals input through the CNTR0 pin.
Except for this, the operation in event counter mode is the same
as in timer mode. When using a timer in this mode, set the corre-
sponding port P54 direction register to input mode.
(4) Pulse width measurement mode
The count source is f(XIN)/16 (or f(XCIN)/16 in low-speed mode). If
CNTR0 active edge switch bit is “0”, the timer counts while the in-
put signal of CNTR0 pin is at “H”. If it is “1”, the timer counts while
the input signal of CNTR0 pin is at “L”. When using a timer in this
mode, set the corresponding port P54 direction register to input
mode.
●Timer X Write Control
If the timer X write control bit is “0”, when the value is written in the
address of timer X, the value is loaded in the timer X and the latch
at the same time.
If the timer X write control bit is “1”, when the value is written in the
address of timer X, the value is loaded only in the latch. The value
in the latch is loaded in timer X after timer X underflows.
If the value is written in latch only, unexpected value may be set in
the high-order counter when the writing in high-order latch and the
underflow of timer X are performed at the same timing.
●Real Time Port Control
While the real time port function is valid, data for the real time port
are output from ports P52 and P53 each time the timer X
underflows. (However, if the real time port control bit is changed
from “0” to “1” after set of the real time port data, data are output
independent of the timer X operation.) If the data for the real time
port is changed while the real time port function is valid, the
changed data are output at the next underflow of timer X.
Before using this function, set the corresponding port direction
registers to output mode.
■Note on CNTR0 interrupt active edge selection
CNTR0 interrupt active edge depends on the CNTR0 active edge
switch bit.
Fig. 20 Structure of timer X mode register
T
i
m
e
r
X
m
o
d
e
r
e
g
i
s
t
e
r
(
T
X
M
:
a
d
d
r
e
s
s
0
0
2
7
1
6
)
T
i
m
e
r
X
w
r
i
t
e
c
o
n
t
r
o
l
b
i
t
0
:
W
r
i
t
e
v
a
l
u
e
i
n
l
a
t
c
h
a
n
d
c
o
u
n
t
e
r
1
:
W
r
i
t
e
v
a
l
u
e
i
n
l
a
t
c
h
o
n
l
y
R
e
a
l
t
i
m
e
p
o
r
t
c
o
n
t
r
o
l
b
i
t
0
:
R
e
a
l
t
i
m
e
p
o
r
t
f
u
n
c
t
i
o
n
i
n
v
a
l
i
d
1
:
R
e
a
l
t
i
m
e
p
o
r
t
f
u
n
c
t
i
o
n
v
a
l
i
d
P
5
2
d
a
t
a
f
o
r
r
e
a
l
t
i
m
e
p
o
r
t
P
5
3
d
a
t
a
f
o
r
r
e
a
l
t
i
m
e
p
o
r
t
T
i
m
e
r
X
o
p
e
r
a
t
i
n
g
m
o
d
e
b
i
t
s
b
5
b
4
00
:
T
i
m
e
r
m
o
d
e
01
:
P
u
l
s
e
o
u
t
p
u
t
m
o
d
e
10
:
E
v
e
n
t
c
o
u
n
t
e
r
m
o
d
e
11
:
P
u
l
s
e
w
i
d
t
h
m
e
a
s
u
r
e
m
e
n
t
m
o
d
e
C
N
T
R
0
a
c
t
i
v
e
e
d
g
e
s
w
i
t
c
h
b
i
t
0
:
C
o
u
n
t
a
t
r
i
s
i
n
g
e
d
g
e
i
n
e
v
e
n
t
c
o
u
n
t
e
r
m
o
d
e
S
t
a
r
t
f
r
o
m
“
H
”
o
u
t
p
u
t
i
n
p
u
l
s
e
o
u
t
p
u
t
m
o
d
e
M
e
a
s
u
r
e
“
H
”
p
u
l
s
e
w
i
d
t
h
i
n
p
u
l
s
e
w
i
d
t
h
m
e
a
s
u
r
e
m
e
n
t
m
o
d
e
F
a
l
l
i
n
g
e
d
g
e
a
c
t
i
v
e
f
o
r
C
N
T
R
0
i
n
t
e
r
r
u
p
t
1
:
C
o
u
n
t
a
t
f
a
l
l
i
n
g
e
d
g
e
i
n
e
v
e
n
t
c
o
u
n
t
e
r
m
o
d
e
S
t
a
r
t
f
r
o
m
“
L
”
o
u
t
p
u
t
i
n
p
u
l
s
e
o
u
t
p
u
t
m
o
d
e
M
e
a
s
u
r
e
“
L
”
p
u
l
s
e
w
i
d
t
h
i
n
p
u
l
s
e
w
i
d
t
h
m
e
a
s
u
r
e
m
e
n
t
m
o
d
e
R
i
s
i
n
g
e
d
g
e
a
c
t
i
v
e
f
o
r
C
N
T
R
0
i
n
t
e
r
r
u
p
t
T
i
m
e
r
X
s
t
o
p
c
o
n
t
r
o
l
b
i
t
0
:
C
o
u
n
t
s
t
a
r
t
1
:
C
o
u
n
t
s
t
o
p
b
7
b
0
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
3825 Group
26
Timer Y
T imer Y is a 16-bit timer that can be selected in one of four modes.
(1) Timer mode
The timer counts f(XIN)/16 (or f(XCIN)/16 in low-speed mode).
(2) Period measurement mode
CNTR1 interrupt request is generated at rising/falling edge of
CNTR1 pin input signal. Simultaneously, the value in timer Y latch
is reloaded in timer Y and timer Y continues counting down. Ex-
cept for the above-mentioned, the operation in period measure-
ment mode is the same as in timer mode.
The timer value just before the reloading at rising/falling of CNTR1
pin input signal is retained until the timer Y is read once after the
reload.
The rising/falling timing of CNTR1 pin input signal is found by
CNTR1 interrupt. When using a timer in this mode, set the corre-
sponding port P55 direction register to input mode.
(3) Event counter mode
The timer counts signals input through the CNTR1 pin.
Except for this, the operation in event counter mode is the same
as in timer mode. When using a timer in this mode, set the corre-
sponding port P55 direction register to input mode.
(4) Pulse width HL continuously measure-
ment mode
CNTR1 interrupt request is generated at both rising and falling
edges of CNTR1 pin input signal. Except for this, the operation in
pulse width HL continuously measurement mode is the same as in
period measurement mode. When using a timer in this mode, set
the corresponding port P55 direction register to input mode.
■Note on CNTR1 interrupt active edge selection
CNTR1 interrupt active edge depends on the CNTR1 active edge
switch bit. However, in pulse width HL continuously measurement
mode, CNTR1 interrupt request is generated at both rising and
falling edges of CNTR1 pin input signal regardless of the setting of
CNTR1 active edge switch bit.
Fig. 21 Structure of timer Y mode register
T
i
m
e
r
Y
m
o
d
e
r
e
g
i
s
t
e
r
(
T
Y
M
:
a
d
d
r
e
s
s
0
0
2
8
1
6
)
b
7
b
0
Not used (retu rn “0” when read )
Ti me r Y opera t ing mo de bits
b5 b4
0 0 : Timer mode
0 1 : Period measurement mode
1 0 : Event cou nte r mode
1 1 : Pulse width HL continuously
measurement mode
CNTR
1
act i ve edge sw i tch bit
0 : Count at rising edge in event counter mode
Mea s ur e the f all i ng edg e t o fal lin g edge
period in period measurement mode
Falling edge act iv e for CNTR
1
interrupt
1 : Count at falling edge in event counter mode
Measure the rising edge period in period
measurement mode
Rising edge active for CNTR
1
interrupt
Ti mer Y stop con trol b i t
0 : Cou nt start
1 : Cou nt stop
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
3825 Group
27
Timer 1, Timer 2, Timer 3
Timer 1, timer 2, and timer 3 are 8-bit timers. The count source for
each timer can be selected by timer 123 mode register. The timer
latch value is not affected by a change of the count source. How-
ever, because changing the count source may cause an inadvert-
ent count down of the timer. Therefore, rewrite the value of timer
whenever the count source is changed.
●Timer 2 Write Control
If the timer 2 write control bit is “0”, when the value is written in the
address of timer 2, the value is loaded in the timer 2 and the latch
at the same time.
If the timer 2 write control bit is “1”, when the value is written in the
address of timer 2, the value is loaded only in the latch. The value
in the latch is loaded in timer 2 after timer 2 underflows.
●Timer 2 Output Control
When the timer 2 (TOUT) is output enabled, an inversion signal
from pin TOUT is output each time timer 2 underflows.
In this case, set the port P56 shared with the port TOUT to the out-
put mode.
■Note on Timer 1 to Timer 3
When the count source of timers 1 to 3 is changed, the timer
counting value may be changed large because a thin pulse is gen-
erated in count input of timer. If timer 1 output is selected as the
count source of timer 2 or timer 3, when timer 1 is written, the
counting value of timer 2 or timer 3 may be changed large be-
cause a thin pulse is generated in timer 1 output.
Therefore, set the value of timer in the order of timer 1, timer 2
and timer 3 after the count source selection of timer 1 to 3.
Fig. 22 Structure of timer 123 mode register
T
OUT
output act
i
ve e
d
ge sw
i
tc
h
bi
t
0 : Start at “H” output
1 : Start at “L” output
T
OUT
output control bit
0 : T
OUT
output disabled
1 : T
OUT
output enabled
Timer 2 write control bit
0 : Write data in latch and counter
1 : Write data in latch only
Timer 2 count source selection bit
0 : Timer 1 output
1 : f(X
IN
)/16
(or f(X
CIN
)/16 in low-sp eed mode)
Timer 3 count source selection bit
0 : Timer 1 output
1 : f(X
IN
)/16
(or f(X
CIN
)/16 in low-sp eed mode)
Timer 1 count source selection bit
0 : f(X
IN
)/16
(or f(X
CIN
)/16 in low-sp eed mode)
1 : f(X
CIN
)
Not used (retu rn “0” when read )
T
i
m
e
r
1
2
3
m
o
d
e
r
e
g
i
s
t
e
r
(
T
1
2
3
M
:
a
d
d
r
e
s
s
0
0
2
9
1
6
)
N
o
t
e
:
I
n
t
e
r
n
a
l
c
l
o
c
k
φ
i
s
f
(
X
C
I
N
)
/
2
i
n
t
h
e
l
o
w
-
s
p
e
e
d
m
o
d
e
.
b
7
b
0
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
3825 Group
28
SERIAL I/O
Serial I/O can be used as either clock synchronous or asynchro-
nous (UART) serial I/O. A dedicated timer (baud rate generator) is
also provided for baud rate generation.
(1) Clock Synchronous Serial I/O Mode
Clock synchronous serial I/O mode can be selected by setting the
mode selection bit of the serial I/O control register to “1”.
For clock synchronous serial I/O, the transmitter and the receiver
must use the same clock. If an internal clock is used, transfer is
started by a write signal to the TB/RB (address 001816).
Fig. 23 Block diagram of clock synchronous serial I/O
Fig. 24 Operation of clock synchronous serial I/O function
P
46/
S
C
L
K
P
47/
S
R
D
Y
P
44/
R
X
D
P
45/
T
X
D
f
(
X
I
N
)
1
/
4
1/4
F
/
F
S
e
r
i
a
l
I
/
O
s
t
a
t
u
s
r
e
g
i
s
t
e
r
Serial I/O c ontrol register
R
e
c
e
i
v
e
b
u
f
f
e
r
r
e
g
i
s
t
e
r
A
d
d
r
e
s
s
0
0
1
81
6
Receive shift register
R
ece
i
ve
b
u
ff
er
f
u
ll
fl
ag
(RBF)
R
e
c
e
i
v
e
i
n
t
e
r
r
u
p
t
r
e
q
u
e
s
t
(
R
I
)
Clock control circuit
S
h
i
f
t
c
l
o
c
k
S
er
i
a
l
I
/
O
sync
h
ron
i
zat
i
on
clock selection bit
Frequency division ratio 1/(n+1)
B
a
u
d
r
a
t
e
g
e
n
e
r
a
t
o
r
Add
ress 001
C
16
BRG
count source se
l
ect
i
on
bi
t
Clock control circuit
F
a
l
l
i
n
g
-
e
d
g
e
d
e
t
e
c
t
o
r
D
ata
b
us
Add
ress 001816
S
h
i
f
t
c
l
o
c
k
T
ransm
i
t s
hif
t reg
i
ster s
hif
t com p
l
et
i
on
fl
ag
(TSC)
T
ransm
i
t
b
u
ff
er empty
fl
ag
(TBE)
T
ransm
i
t
i
nterrupt request
(TI)
T
ransm
i
t
i
nterrupt source se
l
ect
i
on
bi
t
A
d
d
r
e
s
s
0
0
1
91
6
D
ata
b
us
A
d
d
r
e
s
s
0
0
1
A
1
6
T
r
a
n
s
m
i
t
b
u
f
f
e
r
r
e
g
i
s
t
e
r
(
T
B
)
T
r
a
n
s
m
i
t
s
h
i
f
t
r
e
g
i
s
t
e
r
(
f
(
X
C
I
N
)
i
n
l
o
w
-
s
p
e
e
d
m
o
d
e
)
R
e
c
e
i
v
e
e
n
a
b
l
e
s
i
g
n
a
l
S
R
D
Y
D
7
D
0
D
1
D
2
D
3
D
4
D
5
D
6
RBF
= 1
TSC = 1
T
B
E
=
0
TBE
= 1
TSC = 0
T
r
a
n
s
f
e
r
s
h
i
f
t
c
l
o
c
k
(
1
/
2
t
o
1
/
2
0
4
8
o
f
t
h
e
i
n
t
e
r
n
a
l
c
l
o
c
k
,
o
r
a
n
e
x
t
e
r
n
a
l
c
l
o
c
k
)
S
er
i
a
l
out pu t
T
X
D
S
e
r
i
a
l
i
n
p
u
t
R
X
D
W
r
i
t
e
s
i
g
n
a
l
t
o
r
e
c
e
i
v
e
/
t
r
a
n
s
m
i
t
b
u
f
f
e
r
r
e
g
i
s
t
e
r
(
a
d
d
r
e
s
s
0
0
1
81
6)
O
ver run error
(OE)
detection
N
o
t
e
s1
:
T
h
e
t
r
a
n
s
m
i
t
i
n
t
e
r
r
u
p
t
(
T
I
)
c
a
n
b
e
g
e
n
e
r
a
t
e
d
e
i
t
h
e
r
w
h
e
n
t
h
e
t
r
a
n
s
m
i
t
b
u
f
f
e
r
r
e
g
i
s
t
e
r
h
a
s
e
m
p
t
i
e
d
(
T
B
E
=
1
)
o
r
a
f
t
e
r
t
h
e
t
r
a
n
s
m
i
t
s
h
i
f
t
o
p
e
r
a
t
i
o
n
h
a
s
e
n
d
e
d
(
T
S
C
=
1
)
,
b
y
s
e
t
t
i
n
g
t
h
e
t
r
a
n
s
m
i
t
i
n
t
e
r
r
u
p
t
s
o
u
r
c
e
s
e
l
e
c
t
i
o
n
b
i
t
(
T
I
C
)
o
f
t
h
e
s
e
r
i
a
l
I
/
O
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
.
2
:
I
f
d
a
t
a
i
s
w
r
i
t
t
e
n
t
o
t
h
e
t
r
a
n
s
m
i
t
b
u
f
f
e
r
r
e
g
i
s
t
e
r
w
h
e
n
T
S
C
=
0
,
t
h
e
t
r
a
n
s
m
i
t
c
l
o
c
k
i
s
g
e
n
e
r
a
t
e
d
c
o
n
t
i
n
u
o
u
s
l
y
a
n
d
s
e
r
i
a
l
d
a
t
a
i
s
o
u
t
p
u
t
c
o
n
t
i
n
u
o
u
s
l
y
f
r
o
m
t
h
e
TXD
p
i
n
.
3
:
T
h
e
r
e
c
e
i
v
e
i
n
t
e
r
r
u
p
t
(
R
I
)
i
s
s
e
t
w
h
e
n
t
h
e
r
e
c
e
i
v
e
b
u
f
f
e
r
f
u
l
l
f
l
a
g
(
R
B
F
)
b
e
c
o
m
e
s
“
1
”
.
D
7
D
0
D
1
D
2
D
3
D
4
D
5
D
6
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
3825 Group
29
(2) Asynchronous Serial I/O (UART) Mode
Clock asynchronous serial I/O mode (UART) can be selected by
clearing the serial I/O mode selection bit of the serial I/O control
register to “0”.
Eight serial data transfer formats can be selected, and the transfer
formats used by a transmitter and receiver must be identical.
The transmit and receive shift registers each have a buffer regis-
ter, but the two buffers have the same address in memory. Since
the shift register cannot be written to or read from directly, transmit
data is written to the transmit buffer, and receive data is read from
the receive buffer.
The transmit buffer can also hold the next data to be transmitted,
and the receive buffer register can hold a character while the next
character is being received.
Fig. 25 Block diagram of UART serial I/O
Fig. 26 Operation of UART serial I/O function
f(X
IN
)
1
/
4
O
E
P
E
F
E
1/16
1/16
D
ata
b
us
R
e
c
e
i
v
e
b
u
f
f
e
r
r
e
g
i
s
t
e
r
A
d
d
r
e
s
s
0
0
1
81
6
R
e
c
e
i
v
e
s
h
i
f
t
r
e
g
i
s
t
e
r
R
e
c
e
i
v
e
b
u
f
f
e
r
f
u
l
l
f
l
a
g
(
R
B
F
)
R
e
c
e
i
v
e
i
n
t
e
r
r
u
p
t
r
e
q
u
e
s
t
(
R
I
)
B
au
d
rate generator
F
requency
di
v
i
s
i
on rat
i
o 1/
(
n+1
)
Add
ress 001
C
16
ST /SP /PA generat or
Tr ans m it bu ff er r egister
D
ata
b
us
T
r
a
n
s
m
i
t
s
h
i
f
t
r
e
g
i
s
t
e
r
Add
ress 001816
T
ransm
i
t s
hif
t reg
i
ster s
hif
t com p
l
et
i
on
fl
ag
(TSC)
T
ransm
i
t
b
u
ff
er empty
fl
ag
(TBE)
T
ransm
i
t
i
nterrupt request
(TI)
Add
ress 001916
S
T
d
e
t
e
c
t
o
r
S
P
d
e
t
e
c
t
o
r
U
A
R
T
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
Add
ress 001
B
16
C
h
a
r
a
c
t
e
r
l
e
n
g
t
h
s
e
l
e
c
t
i
o
n
b
i
t
A
d
d
r
e
s
s
0
0
1
A
1
6
B
R
G
c
o
u
n
t
s
o
u
r
c
e
s
e
l
e
c
t
i
o
n
b
i
t
T
ransm
i
t
i
nterrupt source se
l
ect
i
on
bit
S
er
i
a
l
I
/
O
sync
h
ron
i
zat
i
on c
l
oc
k
se
l
ect
i
on
bi
t
C
l
o
c
k
c
o
n
t
r
o
l
c
i
r
c
u
i
t
C
h
a
r
a
c
t
e
r
l
e
n
g
t
h
s
e
l
e
c
t
i
o
n
b
i
t
7
b
i
t
s
8
b
i
t
s
S
e
r
i
a
l
I
/
O
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
P
46/
S
C
L
K
S
er
i
a
l
I
/
O
status reg
i
ster
P
44/
R
X
D
P
45/
T
X
D
(
f
(
X
C
I
N
)
i
n
l
o
w
-
s
p
e
e
d
m
o
d
e
)
T
S
C
=
0
T
B
E
=
1
RBF
=0
T
B
E
=
0
TBE
=0
R
B
F
=
1
R
B
F
=
1
S
T
D
0
D
1
S
P
D0
D
1
S
T
SP
TBE
=1 TSC=1✽
ST
D
0
D
1
SP
D
0
D
1
ST
S
P
T
r
a
n
s
m
i
t
b
u
f
f
e
r
w
r
i
t
e
s
i
g
n
a
l
✽ Generated at 2nd bit in 2-stop-bit mode
1
s
t
a
r
t
b
i
t
7
o
r
8
d
a
t
a
b
i
t
s
1
o
r
0
p
a
r
i
t
y
b
i
t
1
o
r
2
s
t
o
p
b
i
t
(
s
)
1
:
E
r
r
o
r
f
l
a
g
d
e
t
e
c
t
i
o
n
o
c
c
u
r
s
a
t
t
h
e
s
a
m
e
t
i
m
e
t
h
a
t
t
h
e
R
B
F
f
l
a
g
b
e
c
o
m
e
s
“
1
”
(
a
t
1
s
t
s
t
o
p
b
i
t
,
d
u
r
i
n
g
r
e
c
e
p
t
i
o
n
)
.
2
:
T
h
e
t
r
a
n
s
m
i
t
i
n
t
e
r
r
u
p
t
(
T
I
)
c
a
n
b
e
g
e
n
e
r
a
t
e
d
t
o
o
c
c
u
r
w
h
e
n
e
i
t
h
e
r
t
h
e
T
B
E
o
r
T
S
C
f
l
a
g
b
e
c
o
m
e
s
“
1
”
,
d
e
p
e
n
d
i
n
g
o
n
t
h
e
s
e
t
t
i
n
g
o
f
t
h
e
t
r
a
n
s
m
i
t
i
n
t
e
r
r
u
p
t
s
o
u
r
c
e
s
e
l
e
c
t
i
o
n
b
i
t
(
T
I
C
)
o
f
t
h
e
s
e
r
i
a
l
I
/
O
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
.
3
:
T
h
e
r
e
c
e
i
v
e
i
n
t
e
r
r
u
p
t
(
R
I
)
i
s
s
e
t
w
h
e
n
t
h
e
R
B
F
f
l
a
g
b
e
c
o
m
e
s
“
1
”
.
4
:
A
f
t
e
r
d
a
t
a
i
s
w
r
i
t
t
e
n
t
o
t
h
e
t
r
a
n
s
m
i
t
b
u
f
f
e
r
r
e
g
i
s
t
e
r
w
h
e
n
T
S
C
=
1
,
0
.
5
t
o
1
.
5
c
y
c
l
e
s
o
f
t
h
e
d
a
t
a
s
h
i
f
t
c
y
c
l
e
i
s
n
e
c
e
s
s
a
r
y
u
n
t
i
l
c
h
a
n
g
i
n
g
t
o
T
S
C
=
0
.
N
o
t
e
s
S
er
i
a
l
outpu t
T
X
D
S
e
r
i
a
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i
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p
u
t
R
X
D
R
e
c
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i
v
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b
u
f
f
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r
r
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a
d
s
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n
a
l
T
r
a
n
s
m
i
t
o
r
r
e
c
e
i
v
e
c
l
o
c
k
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
3825 Group
30
[Transmit Buffer/Receive Buffer Register (TB/
RB)] 001816
The transmit buffer register and the receive buffer register are lo-
cated at the same address. The transmit buffer register is write-
only and the receive buffer register is read-only. If a character bit
length is 7 bits, the MSB of data stored in the receive buffer regis-
ter is “0”.
[Serial I/O Status Register (SIOSTS)] 001916
The read-only serial I/O status register consists of seven flags
(bits 0 to 6) which indicate the operating status of the serial I/O
function and various errors.
Three of the flags (bits 4 to 6) are valid only in UART mode.
The receive buffer full flag (bit 1) is cleared to “0” when the receive
buffer is read.
If there is an error, it is detected at the same time that data is
transferred from the receive shift register to the receive buffer reg-
ister, and the receive buffer full flag is set. A write to the serial I/O
status register clears all the error flags OE, PE, FE, and SE (bit 3
to bit 6, respectively). Writing “0” to the serial I/O enable bit SIOE
(bit 7 of the Serial I/O Control Register) also clears all the status
flags, including the error flags.
All bits of the serial I/O status register are initialized to “0” at reset,
but if the transmit enable bit (bit 4) of the serial I/O control register
has been set to “1”, the transmit shift register shift completion flag
(bit 2) and the transmit buffer empty flag (bit 0) become “1”.
[Serial I/O Control Register (SIOCON)] 001A16
The serial I/O control register contains eight control bits for the se-
rial I/O function.
[UART Control Register (UARTCON)] 001B16
The UART control register consists of four control bits (bits 0 to 3)
which are valid when asynchronous serial I/O is selected and set
the data format of an data transfer. One bit in this register (bit 4) is
always valid and sets the output structure of the P45/TXD pin.
[Baud Rate Generator (BRG)] 001C16
The baud rate generator determines the baud rate for serial trans-
fer.
The baud rate generator divides the frequency of the count source
by 1/(n + 1), where n is the value written to the baud rate genera-
tor.
■Notes on serial I/O
When setting the transmit enable bit to “1”, the serial I/O transmit
interrupt request bit is automatically set to “1”. When not requiring
the interrupt occurrence synchronized with the transmission
enalbed, take the following sequence.
➀Set the serial I/O transmit interrupt enable bit to “0” (disabled).
➁Set the transmit enable bit to “1”.
➂Set the serial I/O transmit interrupt request bit to “0” after 1 or
more instructions have been executed.
➃Set the serial I/O transmit interrupt enable bit to “1” (enabled).
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
3825 Group
31
Fig. 27 Structure of serial I/O control registers
B
R
G
c
o
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(
C
S
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(
X
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f
(
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f
(
X
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(
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(
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4
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6
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t
p
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a
b
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b
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t
(
S
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D
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)
0
:
P
4
7
p
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p
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r
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s
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d
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1
:
P
4
7
p
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R
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s
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l
e
c
t
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n
b
i
t
(
T
I
C
)
0
:
I
n
t
e
r
r
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p
t
w
h
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n
t
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m
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T
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m
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n
a
b
l
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b
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t
(
T
E
)
0
:
T
r
a
n
s
m
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t
d
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s
a
b
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d
1
:
T
r
a
n
s
m
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t
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n
a
b
l
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d
R
e
c
e
i
v
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e
n
a
b
l
e
b
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t
(
R
E
)
0
:
R
e
c
e
i
v
e
d
i
s
a
b
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d
1
:
R
e
c
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i
v
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n
a
b
l
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d
S
e
r
i
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m
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d
e
s
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l
e
c
t
i
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n
b
i
t
(
S
I
O
M
)
0
:
A
s
y
n
c
h
r
o
n
o
u
s
s
e
r
i
a
l
I
/
O
(
U
A
R
T
)
1
:
C
l
o
c
k
s
y
n
c
h
r
o
n
o
u
s
s
e
r
i
a
l
I
/
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S
e
r
i
a
l
I
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O
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n
a
b
l
e
b
i
t
(
S
I
O
E
)
0
:
S
e
r
i
a
l
I
/
O
d
i
s
a
b
l
e
d
(
p
i
n
s
P
4
4
–
P
4
7
o
p
e
r
a
t
e
a
s
o
r
d
i
n
a
r
y
I
/
O
p
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n
s
)
1
:
S
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r
i
a
l
I
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n
a
b
l
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d
(
p
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n
s
P
4
4
–
P
4
7
o
p
e
r
a
t
e
a
s
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r
i
a
l
I
/
O
p
i
n
s
)
S
er
i
a
l
I
/
O
cont ro
l
re g
i
ster
(SIOCON : address 001A
16
)
b7 b0
T
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n
s
m
i
t
b
u
f
f
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r
e
m
p
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f
l
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(
T
B
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)
0
:
B
u
f
f
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r
f
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1
:
B
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m
p
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R
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b
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r
f
u
l
l
f
l
a
g
(
R
B
F
)
0
:
B
u
f
f
e
r
e
m
p
t
y
1
:
B
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f
f
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r
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T
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p
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t
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f
l
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g
(
T
S
C
)
0
:
T
r
a
n
s
m
i
t
s
h
i
f
t
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p
r
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g
r
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s
1
:
T
r
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m
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r
r
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r
r
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r
f
l
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g
(
O
E
)
0
:
N
o
e
r
r
o
r
1
:
O
v
e
r
r
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r
r
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r
P
a
r
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t
y
e
r
r
o
r
f
l
a
g
(
P
E
)
0
:
N
o
e
r
r
o
r
1
:
P
a
r
i
t
y
e
r
r
o
r
F
r
a
m
i
n
g
e
r
r
o
r
f
l
a
g
(
F
E
)
0
:
N
o
e
r
r
o
r
1
:
F
r
a
m
i
n
g
e
r
r
o
r
S
u
m
m
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n
g
e
r
r
o
r
f
l
a
g
(
S
E
)
0
:
(
O
E
)
U
(
P
E
)
U
(
F
E
)
=
0
1
:
(
O
E
)
U
(
P
E
)
U
(
F
E
)
=
1
N
o
t
u
s
e
d
(
r
e
t
u
r
n
s
“
1
”
w
h
e
n
r
e
a
d
)
S
e
r
i
a
l
I
/
O
s
t
a
t
u
s
r
e
g
i
s
t
e
r
(
S
I
O
S
T
S
:
a
d
d
r
e
s
s
0
0
1
9
1
6
)
b7 b0
U
A
R
T
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
(
U
A
R
T
C
O
N
:
a
d
d
r
e
s
s
0
0
1
B
1
6
)
Ch
aracter
l
engt
h
se
l
ect
i
on
bi
t
(CHAS)
0: 8 bits
1: 7 bits
Parity enable bit (PARE)
0: Parity checking disabled
1: Parit y checking enabled
Parity selection bit (PARS)
0: Even parit y
1: Odd parity
Stop bit length selection bit (STPS)
0: 1 stop bit
1: 2 stop bits
P4
5
/T
X
D P-channel output disable bit (POFF)
0: CMOS output (in output mode)
1: N-channel open-drain output (in output mode)
Not used (retu rn “1” when read )
b7 b0
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
3825 Group
32
A-D CONVERTER
The functional blocks of the A-D converter are described below.
[A-D Conversion Register (AD)] 003516
The A-D conversion register is a read-only register that contains
the result of an A-D conversion. When reading this register during
an A-D conversion, the previous conversion result is read.
[A-D Control Register (ADCON)] 003416
The A-D control register controls the A-D conversion process. Bits
0 to 2 of this register select specific analog input pins. Bit 3 signals
the completion of an A-D conversion. The value of this bit remains
at “0” during an A-D conversion, then changes to “1” when the A-
D conversion is completed. Writing “0” to this bit starts the A-D
conversion. Bit 4 controls the transistor which breaks the through
current of the resistor ladder. When bit 5, which is the AD external
trigger valid bit, is set to “1”, this bit enables A-D conversion even
by a falling edge of an ADT input. Set ports which share with ADT
pins to input when using an A-D external trigger.
Comparison Voltage Generator
The comparison voltage generator divides the voltage between
AVSS and VREF by 256, and outputs the divided voltages.
Channel Selector
The channel selector selects one of the input ports P67/AN7–P60/
AN0.
Comparator and Control Circuit
The comparator and control circuit compare an analog input volt-
age with the comparison voltage and store the result in the A-D
conversion register. When an A-D conversion is completed, the
control circuit sets the AD conversion completion bit and the AD
interrupt request bit to “1”.
Note that the comparator is constructed linked to a capacitor, so
set f(XIN) to at least 500kHz during A-D conversion.
Use the clock divided from the main clock XIN as the internal clock
φ.
Fig. 29 A-D converter block diagram
Fig. 28 Structure of A-D control register
A
-
D
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
(
A
D
C
O
N
:
a
d
d
r
e
s
s
0
0
3
4
1
6
)
A
D
c
o
n
v
e
r
s
i
o
n
c
o
m
p
l
e
t
i
o
n
b
i
t
0
:
C
o
n
v
e
r
s
i
o
n
i
n
p
r
o
g
r
e
s
s
1
:
C
o
n
v
e
r
s
i
o
n
c
o
m
p
l
e
t
e
d
A
n
a
l
o
g
i
n
p
u
t
p
i
n
s
e
l
e
c
t
i
o
n
b
i
t
s
0
0
0
:
P
6
0
/
A
N
0
0
0
1
:
P
6
1
/
A
N
1
0
1
0
:
P
6
2
/
A
N
2
0
1
1
:
P
6
3
/
A
N
3
1
0
0
:
P
6
4
/
A
N
4
1
0
1
:
P
6
5
/
A
N
5
1
1
0
:
P
6
6
/
A
N
6
1
1
1
:
P
6
7
/
A
N
7
V
R
E
F
i
n
p
u
t
s
w
i
t
c
h
b
i
t
0
:
O
F
F
1
:
O
N
A
D
e
x
t
e
r
n
a
l
t
r
i
g
g
e
r
v
a
l
i
d
b
i
t
0
:
A
-
D
e
x
t
e
r
n
a
l
t
r
i
g
g
e
r
i
n
v
a
l
i
d
1
:
A
-
D
e
x
t
e
r
n
a
l
t
r
i
g
g
e
r
v
a
l
i
d
b
7
b
0
I
n
t
e
r
r
u
p
t
s
o
u
r
c
e
s
e
l
e
c
t
i
o
n
b
i
t
0
:
I
n
t
e
r
r
u
p
t
r
e
q
u
e
s
t
a
t
A
-
D
c
o
n
v
e
r
s
i
o
n
c
o
m
p
l
e
t
e
d
1
:
I
n
t
e
r
r
u
p
t
r
e
q
u
e
s
t
a
t
A
D
T
i
n
p
u
t
f
a
l
l
i
n
g
N
o
t
u
s
e
d
(
r
e
t
u
r
n
s
“
0
”
w
h
e
n
r
e
a
d
)
C
o
m
p
a
r
a
t
o
r
A
-
D
c
o
n
t
r
o
l
c
i
r
c
u
i
t
A
D
T
/
A
-
D
i
n
t
e
r
r
u
p
t
r
e
q
u
e
s
t
AV
S
S
V
R
E
F
P
6
0
/
A
N
0
D
a
t
a
b
u
s
A
-
D
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
b
7
b
0
A
-
D
convers
i
on
register
R
es
i
stor
l
a
dd
e
r
C
h
a
n
n
e
l
s
e
l
e
c
t
o
r
P
6
7
/
A
N
7
P
6
6
/
A
N
6
P
6
5
/
A
N
5
P
6
4
/
A
N
4
P
6
3
/
A
N
3
P
6
2
/
A
N
2
P
6
1
/
A
N
1
P
5
7
/
A
D
T
8
3
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
3825 Group
33
LCD DRIVE CONTROL CIRCUIT
The 3825 group has the built-in Liquid Crystal Display (LCD) drive
control circuit consisting of the following.
•LCD display RAM
•Segment output enable register
•LCD mode register
•Voltage multiplier
•Selector
•Timing controller
•Common driver
•Segment driver
•Bias control circuit
A maximum of 40 segment output pins and 4 common output pins
can be used.
Up to 160 pixels can be controlled for LCD display. When the LCD
Fig. 30 Structure of segment output enable register and LCD mode register
enable bit is set to “1” after data is set in the LCD mode register,
the segment output enable register and the LCD display RAM, the
LCD drive control circuit starts reading the display data automati-
cally, performs the bias control and the duty ratio control, and dis-
plays the data on the LCD panel.
Table 10. Maximum number of display pixels at each duty ratio
Duty ratio Maximum number of display pixel
80 dots
or 8 segment LCD 10 digits
120 dots
or 8 segment LCD 15 digits
160 dots
or 8 segment LCD 20 digits
2
3
4
S
e
g
m
e
n
t
o
u
t
p
u
t
e
n
a
b
l
e
b
i
t
0
0
:
O
u
t
p
u
t
p
o
r
t
s
P
30–
P
35
1
:
S
e
g
m
e
n
t
o
u
t
p
u
t
S
E
G1
8–
S
E
G2
3
S
e
g
m
e
n
t
o
u
t
p
u
t
e
n
a
b
l
e
b
i
t
1
0
:
O
u
t
p
u
t
p
o
r
t
s
P
36,
P
37
1
:
S
e
g
m
e
n
t
o
u
t
p
u
t
S
E
G2
4,
S
E
G2
5
S
e
g
m
e
n
t
o
u
t
p
u
t
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n
a
b
l
e
b
i
t
2
0
:
O
u
t
p
u
t
p
o
r
t
s
P
00–
P
05
1
:
S
e
g
m
e
n
t
o
u
t
p
u
t
S
E
G2
6–
S
E
G3
1
S
e
g
m
e
n
t
o
u
t
p
u
t
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n
a
b
l
e
b
i
t
3
0
:
O
u
t
p
u
t
p
o
r
t
s
P
06,
P
07
1
:
S
e
g
m
e
n
t
o
u
t
p
u
t
S
E
G3
2,
S
E
G3
3
S
e
g
m
e
n
t
o
u
t
p
u
t
e
n
a
b
l
e
b
i
t
4
0
:
O
u
t
p
u
t
p
o
r
t
P
10
1
:
S
e
g
m
e
n
t
o
u
t
p
u
t
S
E
G3
4
S
e
g
m
e
n
t
o
u
t
p
u
t
e
n
a
b
l
e
b
i
t
5
0
:
O
u
t
p
u
t
p
o
r
t
s
P
11–
P
15
1
:
S
e
g
m
e
n
t
o
u
t
p
u
t
S
E
G3
5–
S
E
G3
9
N
o
t
u
s
e
d
(
r
e
t
u
r
n
“
0
”
w
h
e
n
r
e
a
d
)
(
D
o
n
o
t
w
r
i
t
e
“
1
”
t
o
t
h
i
s
b
i
t
)
S
egment output ena
bl
e reg
i
ster
(SEG : address 003816)
b
7
b
0
LCD
mo
d
e reg
i
ster
(LM : address 0 039 16)
D
uty rat
i
o se
l
ect
i
on
bi
ts
0 0 : Not used
0 1 : 2 duty (use COM0, COM1)
1 0 : 3 duty (use COM0–COM2)
1 1 : 4 duty (use COM0–COM3)
Bias control bit
0 : 1/3 bias
1 : 1/2 bias
LCD enable bit
0 : LCD OFF
1 : LCD ON
Voltage multipl ier control bit
0 : Voltag e multiplier dis ab l e
1 : Voltag e multiplier ena ble
LCD circuit divider division ratio selection bits
0 0 : Clock input
0 1 : 2 division of Clock input
1 0 : 4 division of Clock input
1 1 : 8 division of Clock input
LCDCK c ount source selection bit (Note)
0 : f(XCIN)/32
1 : f(XIN)/8192 (f(XCIN)/8192 in low- s peed mo de)
N
o
t
e
:
L
C
D
C
K
i
s
a
c
l
o
c
k
f
o
r
a
L
C
D
t
i
m
i
n
g
c
o
n
t
r
o
l
l
e
r
.
b
7
b
0
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
3825 Group
34
Fig. 31 Block diagram of LCD controller/driver
D
a
t
a
b
u
s
T
i
m
i
n
g
c
o
n
t
r
o
l
l
e
r
L
C
D
d
i
v
i
d
e
rf
(
X
I
N
)
/
8
1
9
2
(
f
(
X
C
I
N
)
/
8
1
9
2
i
n
l
o
w
-
s
p
e
e
d
m
o
d
e
)
f
(
X
C
I
N
)
/
3
2
C
O
M
0
C
O
M
1
C
O
M
2
C
O
M
3
V
S
S
V
L
1
V
L
2
V
L
3
S
E
G
3
S
E
G
2
S
E
G
1
S
E
G
0
A
d
d
r
e
s
s
0
0
4
0
1
6
A
d
d
r
e
s
s
0
0
4
1
1
6
“
1
”
“
0
”
L
C
D
C
K
L
C
D
C
K
c
o
u
n
t
s
o
u
r
c
e
s
e
l
e
c
t
i
o
n
b
i
t
L
C
D
c
i
r
c
u
i
t
d
i
v
i
d
e
r
d
i
v
i
s
i
o
n
r
a
t
i
o
s
e
l
e
c
t
i
o
n
b
i
t
s
B
i
a
s
c
o
n
t
r
o
l
b
i
t
L
C
D
e
n
a
b
l
e
b
i
t
D
u
t
y
r
a
t
i
o
s
e
l
e
c
t
i
o
n
b
i
t
s
22
S
e
l
e
c
t
o
rS
e
l
e
c
t
o
rS
e
l
e
c
t
o
rS
e
l
e
c
t
o
rS
e
l
e
c
t
o
rS
e
l
e
c
t
o
r
L
C
D
d
i
s
p
l
a
y
R
A
M
A
d
d
r
e
s
s
0
0
5
3
1
6
P
1
4
/
S
E
G
3
8
P
3
0
/
S
E
G
1
8
P
1
5
/
S
E
G
3
9
L
e
v
e
l
s
h
i
f
tL
e
v
e
l
s
h
i
f
tL
e
v
e
l
s
h
i
f
tL
e
v
e
l
s
h
i
f
tL
e
v
e
l
s
h
i
f
tL
e
v
e
l
s
h
i
f
t
C
o
m
m
o
n
d
r
i
v
e
rC
o
m
m
o
n
d
r
i
v
e
rC
o
m
m
o
n
d
r
i
v
e
rC
o
m
m
o
n
d
r
i
v
e
r
C
1
C
2
V
o
l
t
a
g
e
m
u
l
t
i
p
l
i
e
r
c
o
n
t
r
o
l
b
i
t
L
e
v
e
l
S
h
i
f
tL
e
v
e
l
S
h
i
f
tL
e
v
e
l
S
h
i
f
tL
e
v
e
l
S
h
i
f
t
S
e
g
m
e
n
t
d
r
i
v
e
rS
e
g
m
e
n
t
d
r
i
v
e
rS
e
g
m
e
n
t
d
r
i
v
e
rS
e
g
m
e
n
t
d
r
i
v
e
rS
e
g
m
e
n
t
d
r
i
v
e
rS
e
g
m
e
n
t
d
r
i
v
e
r
B
i
a
s
c
o
n
t
r
o
l
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
3825 Group
35
Voltage Multiplier (3 Times)
The voltage multiplier performs threefold boosting. This circuit in-
puts a reference voltage for boosting from LCD power input pin
VL1. (However, when using a 1/2 bias, connect VL1 and VL2 and
apply voltage by external resistor division.)
The voltage multiplier control bit (bit 4 of the LCD mode register)
controls the voltage multiplier.
When voltage is input to the VL1 pin during operating the voltage
multiplier, voltage that is twice as large as VL1 occurs at the VL2
pin, and voltage that is three times as large as VL1 occurs at the
VL3 pin.
When using the voltage multiplier; after applying 1.3 V ≤ Voltage ≤ 2.3 V
to the VL1 pin, set the voltage multiplier control bit to “1” to select the
voltage multiplier enable.
When not using the voltage multiplier, apply proper voltage to the
LCD power input pins (VL1–VL3).
Bias Control and Applied Voltage to LCD
Power Input Pins
To the LCD power input pins (VL1–VL3), apply the voltage shown
in Table 11 according to the bias value.
Select a bias value by the bias control bit (bit 2 of the LCD mode
register).
Common Pin and Duty Ratio Control
The common pins (COM0–COM3) to be used are determined by
duty ratio.
Select duty ratio by the duty ratio selection bits (bits 0 and 1 of the
LCD mode register).
Fig. 32 Example of circuit at each bias
Table 11. Bias control and applied voltage to VL1–VL3
Bias value
1/3 bias
1/2 bias
Voltage value
VL3=VLCD
VL2=2/3 VLCD
VL1=1/3 VLCD
VL3=VLCD
VL2=VL1=1/2 VLCD
Note : VLCD is the maximum value of supplied voltage for the
LCD panel.
Table 12. Duty ratio control and common pins used
Duty
ratio
2
3
4
Common pins used
Notes 1: COM2 and COM3 are open.
2: COM3 is open.
Bit 1
0
1
1
Bit 0
1
0
1
COM0, COM1 (Note 1)
COM0–COM2 (Note 2)
COM0–COM3
Duty ratio selection bits
V
L
3
V
L
2
C
2
C
1
V
L
1
1
/
3
b
i
a
s
w
h
e
n
u
s
i
n
g
t
h
e
v
o
l
t
a
g
e
m
u
l
t
i
p
l
i
e
r
V
L3
V
L2
C
2
C
1
V
L1
1
/
3
b
i
a
s
w
h
e
n
n
o
t
u
s
i
n
g
t
h
e
v
o
l
t
a
g
e
m
u
l
t
i
p
l
i
e
r
O
p
e
n
O
p
e
n
R
2
R
1
R
3
R
1
=
R
2
=
R
3
C
ontrast contro
l
V
L
3
V
L
2
C
2
C
1
V
L
1
1/2
bi
as
O
p
e
n
O
p
e
n
R
4
R
5
R
4=
R
5
C
o
n
t
r
a
s
t
c
o
n
t
r
o
l
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
3825 Group
36
LCD Display RAM
Address 004016 to 005316 is the designated RAM for the LCD dis-
play. When “1” are written to these addresses, the corresponding
segments of the LCD display panel are turned on.
LCD Drive Timing
The LCDCK timing frequency (LCD drive timing) is generated in-
ternally and the frame frequency can be determined with the fol-
lowing equation;
(frequency of count source for LCDCK)
(divider division ratio for LCD)
f(LCDCK)=
f(LCDCK)
duty ratio
Frame frequency=
Fig. 33 LCD display RAM map
0
0
4
01
6
0
0
4
11
6
0
0
4
21
6
0
0
4
31
6
0
0
4
41
6
0
0
4
51
6
0
0
4
61
6
0
0
4
71
6
0
0
4
81
6
0
0
4
91
6
0
0
4
A1
6
0
0
4
B1
6
0
0
4
C1
6
0
0
4
D1
6
0
0
4
E1
6
0
0
4
F1
6
0
0
5
01
6
0
0
5
11
6
0
0
5
21
6
0
0
5
31
6
B
i
t
Add
ress
S
E
G
1
S
E
G3
S
E
G5
S
E
G7
S
E
G9
S
E
G1
1
S
E
G1
3
S
E
G1
5
S
E
G1
7
S
E
G1
9
S
E
G2
1
S
E
G2
3
S
E
G2
5
S
E
G2
7
S
E
G2
9
S
E
G3
1
S
E
G3
3
S
E
G3
5
S
E
G3
7
S
E
G3
9
76543210
C
O
M
3
COM
0
C
O
M
2
COM
1
C
O
M
0
C
O
M
3
C
O
M
2
C
O
M
1
S
E
G
0
S
E
G2
S
E
G4
S
E
G6
S
E
G8
S
E
G1
0
S
E
G1
2
S
E
G1
4
S
E
G1
6
S
E
G1
8
S
E
G2
0
S
E
G2
2
S
E
G2
4
S
E
G2
6
S
E
G2
8
S
E
G3
0
S
E
G3
2
S
E
G3
4
S
E
G3
6
S
E
G3
8
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
3825 Group
37
Fig. 34 LCD drive waveform (1/2 bias)
Internal logic
LCDCK timing
1
/
4
d
u
t
yV
o
l
t
a
g
e
l
e
v
e
l
V
L
3
V
L
2
=
V
L
1
V
S
S
V
L
3
V
S
S
C
O
M
0
C
O
M
1
C
O
M
2
C
O
M
3
SEG
0
OFF ON OFF ON
COM
3
COM
2
COM
1
COM
0
COM
3
COM
2
COM
1
COM
0
1
/
3
d
u
t
y
V
L3
V
L2
=V
L1
V
SS
V
L3
V
SS
O
F
FO
NON O
F
F O
NOFF
1
/
2
d
u
t
y
COM
0
C
O
M
1
C
O
M
2
S
E
G
0
C
O
M
0
C
O
M
1
S
E
G
0
V
L
3
V
L
2
=
V
L
1
V
S
S
V
L
3
V
S
S
O
F
FO
NOFFON OFFO
NOFFO
N
C
O
M
0
C
O
M
2
COM
1
COM
0
COM
2
COM
1
COM
0
C
O
M
2
C
O
M
1
C
O
M
0
COM
1
COM
0
COM
1
COM
0
COM
1
C
O
M
0
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
3825 Group
38
Fig. 35 LCD drive waveform (1/3 bias)
I
n
t
e
r
n
a
l
l
o
g
i
c
L
C
D
C
K
t
i
m
i
n
g
1
/
4
d
u
t
yV
o
l
t
a
g
e
l
e
v
e
l
VL
3
VS
S
C
O
M0
C
O
M1
C
O
M2
C
O
M3
S
E
G0
OFF ON OFF ON
COM3C
O
M2COM1C
O
M0COM3COM2C
O
M1C
O
M0
1
/
3
d
u
t
y
OFFO
N O
NO
F
F O
NO
F
F
1/2 duty
COM0
COM1
C
O
M2
SEG0
C
O
M0
COM1
S
E
G0
OFFO
N O
F
FO
N O
F
FO
N O
F
FON
VL3
VL2
VSS
VL1
VL3
VL2
VSS
VL1
VL
3
VSS
VL3
VL2
VSS
VL1
VL3
VSS
C
O
M0C
O
M2COM1C
O
M0C
O
M2COM1C
O
M0C
O
M2
COM1COM0COM1C
O
M0COM1COM0COM1COM0
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
3825 Group
39
CLOCK OUTPUT FUNCTION
Input/output ports P40 and P41 can output clock. The input/output
ports and clock output function are put under double function con-
trolled by the clock output control register (address 002A16).
Selection of Input/Output Ports and Clock
Output Function
Bits 0 and 1 of the clock output control register can select between
the input/output ports and the clock output function.
When selecting the clock output function, clocks are output while
the direction register of ports P40 and P41 are set to output.
At the next cycle of rewriting the clock output control bit, P40 is
switched between the port output and the clock output.
In synchronization with the fall of the clock (resulting from dividing
XIN by 5) on rewriting the clock output control bit, P41 is switched
between the port output and the clock output.
Fig. 37 Clock output function block diagram
Fig. 36 Structure of clock output control register
Selection of Output Clock Frequency
Bit 2 (output clock frequency selection bit) of the clock output con-
trol register selects an output clock frequency.
When setting the output clock frequency selection bit to “0”, port
P40 becomes the frequency of f(XIN) and port P41 becomes the
frequency of f(XIN)/5.
At this time, the output pulse of port P40 depends on the XIN input
pulse, while the output pulse of port P41 has duty ratio of about
40%.
When setting the output clock frequency selection bit to “1”, port
P40 becomes the frequency of f(XIN)/2 and port P41 becomes the
frequency of f(XIN)/10. At this time, the output pulses of both ports
P40 and P41 have duty ratio of 50%.
P
4
0
c
l
oc
k
output contro
l
bi
t
0 : I/O po rt
1 : Clock ou tput
P4
1
clock output control bit
0 : I/O po rt
1 : Clock ou tput
Output clock frequency selection bit
0 : P4
0
←f(X
IN
), P4
1
←f(X
IN
)/5
1 : P4
0
←f(X
IN
)/2, P4
1
←f(X
IN
)/10
Not used (retu rn “0” when read )
Cl
oc
k
output contro
l
reg
i
ster
(T CO N : addr ess 002 A
16
)
b
7
b
0
P
4
0
1
/
2
P
4
0
d
i
r
e
c
t
i
o
n
r
e
g
i
s
t
e
r
P
4
0
c
l
o
c
k
o
u
t
p
u
t
c
o
n
t
r
o
l
b
i
t
“0”
“1”
P
4
0
port
l
atc
h
“0”
“1”
O
u
t
p
u
t
c
l
o
c
k
f
r
e
q
u
e
n
c
y
s
e
l
e
c
t
i
o
n
b
i
t
X
IN
P
4
1
1
/
2
P
4
1
d
i
r
e
c
t
i
o
n
r
e
g
i
s
t
e
r
P
4
1
c
l
o
c
k
o
u
t
p
u
t
c
o
n
t
r
o
l
b
i
t
“
0
”
“
1
”
P
4
1
p
o
r
t
l
a
t
c
h
“
0
”
“
1
”
O
utput c
l
oc
k
frequency
sel e ct i on bit
1
/
5
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
3825 Group
40
Fig. 39 Internal state of microcomputer immediately after re-
set
Fig. 38 Example of reset circuit
RESET CIRCUIT
To reset the microcomputer, RESET pin should be held at an “L”
level for 2 µs or more. Then the RESET pin is returned to an “H”
level (the power source voltage should be between VCC(min.) and
5.5 V, and the quartz-crystal oscillator should be stable), reset is
released. After the reset is completed, the program starts from the
address contained in address FFFD16 (high-order byte) and ad-
dress FFFC16 (low-order byte). Make sure that the reset input
voltage meets VIL spec. when a power source voltage passes
VCC(min.).
P
o
w
e
r
o
n
P
o
w
e
r
s
o
u
r
c
e
v
o
l
t
a
g
e
R
e
s
e
t
i
n
p
u
t
v
o
l
t
a
g
e
Power source voltage
detection circuit
V
I
L
s
p
e
c
.
0
V
0
V
V
CC
R
E
S
E
T
V
CC
RESET
N
ote:
Th
e con tents o
f
a
ll
ot
h
er reg
i
sters an
d
RAM
are un
d
e
fi
ne
d
a
f
ter
reset, so they mu st be in itialized by software.
✕ : Undefined
R
e
g
i
s
t
e
r
c
o
n
t
e
n
t
s
A
d
d
r
e
s
s
0000
16
0002
16
0003
16
0004
16
0005
16
0006
16
0008
16
0009
16
000
A
16
000
B
16
0
0
0
C
1
6
0
0
0
D
1
6
000
E
16
0
0
0
F
1
6
0010
16
0011
16
0016
16
0017
16
0019
16
001
A
16
001
B
16
0020
16
0021
16
0022
16
0023
16
0024
16
0025
16
0026
16
0027
16
0028
16
0029
16
002
A
16
0034
16
0038
16
0039
16
003
A
16
003
B
16
0
0
3
C
1
6
0
0
3
D
1
6
003
E
16
0
0
3
F
1
6
(
P
S
)
(
P
C
H
)
(
P
C
L
)
(
1
0
)
(
1
1
)
(
1
2
)
(
1
3
)
(
1
4
)
(
1
5
)
(
1
6
)
(
1
7
)
(
1
8
)
(
1
9
)
(
2
0
)
(
21
)
(
22
)
(
23
)
(
24
)
(
25
)
(
2
6
)
(
2
7
)
(
2
8
)
(
2
9
)
(
3
0
)
(
3
1
)
(
3
2
)
(
3
3
)
(
3
4
)
(
1
)
(
2
)
(
3
)
(
4
)
(
5
)
(
6
)
(
7
)
(
8
)
(
9
)
(
3
5
)
(
3
6
)
(
3
7
)
(
3
8
)
(
3
9
)
(
4
0
)
(
4
1
)
(
4
2
)
(
4
3
)
Timer Y (low)
Port P5 directi on r egister
Port P6
Port P6 directi on r egister
PULL register B
Timer Y (high)
Serial I/O c ontrol register
UART control register
Timer X (high)
Timer X (low)
Timer X mode register
Timer Y mode register
Tim er 123 mode register
Serial I/O s tatus re gis ter
Port P7
Port P7 directi on r egister
Port P8
A-D c ontro l r egister
Segment outp ut enabl e register
LC D m ode register
PULL register A
Interr upt edge selection regi ste r
CPU mode register
Interrupt request registe r 1
Interrupt request registe r 2
Interrupt control register 1
Interrupt control register 2
Processor status register
Program counter
Port P5
Port P4 directi on r egister
Port P4
Port P3
Port P2 directi on r egister
Port P2
Port P1 output contro l r egister
Port P1
Port P0
Port P8 directi on r egister
Timer 1
Timer 2
Timer 3
Cl oc k output control registe r
111000 00
100000 00
000010 0
0
10010000
✕1
✕✕ ✕✕ ✕✕
0
0
1
6
0
0
1
6
0
0
1
6
0
0
1
6
00
16
00
16
00
16
0
0
1
6
F
F
1
6
F
F
1
6
F
F
1
6
F
F
1
6
F
F
1
6
0
1
1
6
FF
16
0
0
1
6
00
16
0
0
1
6
0
0
1
6
00
16
0
0
1
6
00
16
00
16
0
0
1
6
0
0
1
6
0
0
1
6
0
0
1
6
0
0
1
6
0
0
1
6
0
0
1
6
0
0
1
6
0
0
1
6
0
0
1
6
0
0
1
6
00
16
0
0
1
6
0
1
1
6
0
0
1
6
C
o
n
t
e
n
t
s
o
f
a
d
d
r
e
s
s
F
F
F
D1
6
C
o
n
t
e
n
t
s
o
f
a
d
d
r
e
s
s
F
F
F
C1
6
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
3825 Group
41
Fig. 40 Reset sequence
AD
L
FFFC
FFFD
A
D
H
,
?
?
?
?
X
IN
: a
b
out 8000
clock cycles
N
o
t
e
s
1
:
X
I
N
a
n
d
φ
a
r
e
i
n
t
h
e
r
e
l
a
t
i
o
n
s
h
i
p
:
f
(
X
I
N
)
=
8
•
f
(
φ
)
2
:
A
q
u
e
s
t
i
o
n
m
a
r
k
(
?
)
i
n
d
i
c
a
t
e
s
a
n
u
n
d
e
f
i
n
e
d
s
t
a
t
u
s
t
h
a
t
d
e
p
e
n
d
s
o
n
t
h
e
p
r
e
v
i
o
u
s
s
t
a
t
u
s
.
R
e
s
e
t
a
d
d
r
e
s
s
f
r
o
m
v
e
c
t
o
r
t
a
b
l
e
R
E
S
E
T
I
n
t
e
r
n
a
l
r
e
s
e
t
A
d
d
r
e
s
s
D
a
t
a
S
Y
N
C
φ
X
I
N
A
D
H
A
D
L
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
3825 Group
42
CLOCK GENERATING CIRCUIT
The 3825 group has two built-in oscillation circuits. An oscillation
circuit can be formed by connecting a resonator between XIN and
XOUT (XCIN and XCOUT). Use the circuit constants in accordance
with the resonator manufacturer's recommended values. No exter-
nal resistor is needed between XIN and XOUT since a feed-back
resistor exists on-chip. However, an external feed-back resistor is
needed between XCIN and XCOUT.
To supply a clock signal externally, input it to the XIN pin and make
the XOUT pin open. The sub-clock XCIN-XCOUT oscillation circuit
cannot directly input clocks that are externally generated. Accord-
ingly, be sure to cause an external resonator to oscillate.
Immediately after poweron, only the XIN oscillation circuit starts
oscillating, and XCIN and XCOUT pins function as I/O ports.
Frequency Control
(1) Middle-speed mode
The internal clock φ is the frequency of XIN divided by 8.
After reset, this mode is selected.
(2)High-speed mode
The internal clock φ is half the frequency of XIN.
(3) Low-speed mode
•The internal clock φ is half the frequency of XCIN.
•A low-power consumption operation can be realized by stopping
the main clock XIN in this mode. To stop the main clock, set bit 5
of the CPU mode register to “1”.
When the main clock XIN is restarted, set enough time for oscil-
lation to stabilize by programming.
Note: If you switch the mode between middle/high-speed and low-
speed, stabilize both XIN and XCIN oscillations. The suffi-
cient time is required for the sub-clock to stabilize, espe-
cially immediately after power-on and at returning from stop
mode. When switching the mode between middle/high-
speed and low-speed, set the frequency in the condition
that f(XIN) > 3•f(XCIN). Fig. 41 Ceramic resonator circuit
Fig. 42 External clock input circuit
Oscillation Control
(1) Stop mode
If the STP instruction is executed, the internal clock φ stops at an
“H” level, and XIN and XCIN oscillators stop. Timer 1 is set to “FF16”
and timer 2 is set to “0116”.
Either XIN or XCIN divided by 16 is input to timer 1 as count
source, and the output of timer 1 is connected to timer 2.
The bits of the timer 123 mode register except bit 4 are cleared to
“0”. Set the timer 1 and timer 2 interrupt enable bits to disabled
(“0”) before executing the STP instruction.
Oscillator restarts at reset or when an external interrupt is re-
ceived, but the internal clock φ is not supplied to the CPU until
timer 2 underflows. This allows time for the clock circuit oscillation
to stabilize.
(2) Wait mode
If the WIT instruction is executed, the internal clock φ stops at an
“H” level. The states of XIN and XCIN are the same as the state be-
fore the executing the WIT instruction. The internal clock restarts
at reset or when an interrupt is received. Since the oscillator does
not stop, normal operation can be started immediately after the
clock is restarted.
X
C
I
N
C
I
N
C
O
U
T
C
C
I
N
C
C
O
U
T
R
fRd
X
C
O
U
T
X
I
N
X
O
U
T
X
I
N
X
O
U
T
External oscillation circuit
O
p
e
n
V
CC
V
S
S
C
C
I
N
C
C
O
U
T
Rf R
d
X
C
I
N
X
C
O
U
T
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
3825 Group
43
Fig. 43 Clock generating circuit block diagram
W
I
T
i
n
s
t
r
u
c
t
i
o
n
STP
i
nstruct
i
on
Ti
m
i
ng φ
(Interna l cloc k)
S
R
Q
STP
i
nstruct
i
on
S
R
Q
M
a
i
n
c
l
o
c
k
s
t
o
p
b
i
t
S
R
Q
T
i
m
e
r
2
Ti
me r 1
1
/
21/4
X
I
N
X
O
U
T
X
COUT
X
C
I
N
I
nterrupt reques
t
R
eset
P
o
r
t
X
C
s
w
i
t
c
h
b
i
t
“
1
”“
0
”
T
i
m
e
r
1
c
o
u
n
t
s
o
u
r
c
e
s
e
l
e
c
t
i
o
n
b
i
t
Ti
me r 2 co u n t
source selection
bit
L
o
w
-
s
p
e
e
d
m
o
d
e
M
i
d
d
l
e
-
/
H
i
g
h
-
s
p
e
e
d
m
o
d
e
I
n
t
e
r
n
a
l
s
y
s
t
e
m
c
l
o
c
k
s
e
l
e
c
t
i
o
n
b
i
t
(
N
o
t
e
)
Middl
e-spee
d
mo
d
e
H
i
g
h
-
s
p
e
e
d
m
o
d
e
o
r
L
o
w
-
s
p
e
e
d
m
o
d
e
N
ote:
Wh
en us
i
ng t
h
e
l
ow-spee
d
mo
d
e, set t
h
e port
X
C
sw
i
tc
h
bi
t to “1”.
M
a
i
n c
l
oc
k
di
v
i
s
i
on rat
i
o se
l
ect
i
on
bi
t
“
1
”
“
0
”
“1”
“0”“
1
”
“0”
I
n
t
e
r
r
u
p
t
d
i
s
a
b
l
e
f
l
a
g
I
1
/
2
“1”
“
0
”
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
3825 Group
44
Fig. 44 State transitions of internal clock φ
N
otes 1:
S
w
i
tc
h
t
h
e mo
d
e
b
y t
h
e a
ll
ows s
h
own
b
etween t
h
e mo
d
e
bl
oc
k
s.
(D
o not sw
i
tc
h
b
etw een t
h
e mo
d
e
di
rect
l
y w
i
t
h
out an a
ll
ow.
)
2: The all modes can be switched to the stop mode or the wait mode and returned to the source mode when the stop mode or the w ait
mode is ended.
3: Timer and LCD operate in the w ait mode.
4: When the stop mode is ended, a delay of approximately 1 ms occurs automaticall y by timer 1 and timer 2 in middle-/high-speed mode.
5: When the stop mode is ended, a delay of approximately 0.25 s occurs automatically by timer 1 and timer 2 in low-speed mode.
6: Wait until osc illation stabilizes a fter osc illating the main clock X
IN
before the switching from the low-speed mode to middl e-/high-
speed mode.
7: The example assumes that 8 MHz is being applied to the X
IN
pin and 32 kHz to the X
CIN
pin. f indicates the internal clock.
CM
4
:
P
ort
X
c sw
i
tc
h
bi
t
0: I/O po rt
1: X
CIN
, X
COUT
CM
5
: Main clock (X
IN
–X
OUT
) stop bit
0: Oscillating
1: Stopped
CM
6
: Main clock division ratio selection bit
0: f(X
IN
)/2 (high-speed mode)
1: f(X
IN
)/8 (middle-speed mode)
CM
7
: Internal system clock selection bit
0: X
IN
–X
OUT
selected
(middle-/high- sp eed mode)
1: X
CIN
–X
COUT
selected
(low-speed mode)
CPU
mo
d
e reg
i
ster
(CPUM : address 003B
16
)
b
7
b
4
R
e
s
e
t
C
M
6
“0”
“
1
”
C
M
4
“
0
”
“
1
”
C
M
7
=
0
(
8
M
H
z
s
e
l
e
c
t
e
d
)
C
M
6
=
1
(
M
i
d
d
l
e
-
s
p
e
e
d
)
C
M
5
=
0
(
8
M
H
z
o
s
c
i
l
l
a
t
i
n
g
)
C
M
4
=
0
(
3
2
k
H
z
s
t
o
p
p
e
d
)
M
i
d
d
l
e
-
s
p
e
e
d
m
o
d
e
(
f
(φ)
=
1
M
H
z
)
C
M
7
=
0
(
8
M
H
z
s
e
l
e
c
t
e
d
)
C
M
6
=
1
(
M
i
d
d
l
e
-
s
p
e
e
d
)
C
M
5
=
0
(
8
M
H
z
o
s
c
i
l
l
a
t
i
n
g
)
C
M
4
=
1
(
3
2
k
H
z
o
s
c
i
l
l
a
t
i
n
g
)
Middle- speed mod e (f(φ) = 1 MHz )
CM
7
= 0 ( 8 MHz selected)
CM
6
= 0 (High-speed)
CM
5
= 0 (8 MHz oscill ating)
CM
4
= 0 (32 kHz stopped)
High-speed m ode (f( φ) = 4 MHz)
CM
7
= 0 ( 8 MHz selected)
CM
6
= 0 (High-speed)
CM
5
= 0 (8 MHz oscill ating)
CM
4
= 1 (32 kHz oscillating)
H
i
g
h
-
s
p
e
e
d
m
o
d
e
(
f
(φ)
=
4
M
H
z
)
CM
7
= 1 ( 32 kHz selected)
CM
6
= 1 (Middle-speed)
CM
5
= 0 (8 MHz oscill ating)
CM
4
= 1 (32 kHz oscillating)
Low-speed mode (f(φ) =16 kHz)
CM
7
= 1 ( 32 kHz selected)
CM
6
= 0 (High-speed)
CM
5
= 0 (8 MHz oscill ating)
CM
4
= 1 (32 kHz oscillating)
Low-speed mode (f(φ) =16 kHz)
CM
7
= 1 ( 32 kHz selected)
CM
6
= 1 (Middle-speed)
CM
5
= 1 (8 MHz stopped)
CM
4
= 1 (32 kHz oscillating)
L
o
w
-
s
p
e
e
d
m
o
d
e
(
f
(φ)
=
1
6
k
H
z
)
CM
7
= 1 ( 32 kHz selected)
CM
6
= 0 (High-speed)
CM
5
= 1 (8 MHz stopped)
CM
4
= 1 (32 kHz oscillating)
Low-speed mode (f(φ) =16 kHz)
CM
6
“0”“1”
CM
6
“0”“
1
”
CM
6
“
0
”“1”
C
M
4
“
0
”
“
1
”
C
M
7
“
0
”
“
1
”
C
M
7
“
0
”
“
1
”
C
M
5
“
0
”“
1
”
C
M
5
“
0
”“
1
”
C
M
4
C
M
6
“
0
”
“
1
”
“
0
”
“
1
”
C
M
4
C
M
6
“
0
”
“
1
”
“
1
”
“
0
”
C
M
5
C
M
6
“
0
”
“
1
”
“
0
”
“
1
”
C
M
5
C
M
6
“
0
”
“
1
”
“
1
”
“
0
”
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
3825 Group
45
NOTES ON PROGRAMMING
Processor Status Register
The contents of the processor status register (PS) after a reset are
undefined, except for the interrupt disable flag (I) which is “1”. Af-
ter a reset, initialize flags which affect program execution.
In particular, it is essential to initialize the index X mode (T) and
the decimal mode (D) flags because of their effect on calculations.
Interrupt
The contents of the interrupt request bits do not change immedi-
ately after they have been written. After writing to an interrupt re-
quest register, execute at least one instruction before performing a
BBC or BBS instruction.
Decimal Calculations
To calculate in decimal notation, set the decimal mode flag (D) to
“1”, then execute an ADC or SBC instruction. Only the ADC and
SBC instructions yield proper decimal results. After executing an
ADC or SBC instruction, execute at least one instruction before
executing a SEC, CLC, or CLD instruction.
In decimal mode, the values of the negative (N), overflow (V), and
zero (Z) flags are invalid.
Timers
If a value n (between 0 and 255) is written to a timer latch, the fre-
quency division ratio is 1/(n + 1).
Multiplication and Division Instructions
The index mode (T) and the decimal mode (D) flags do not affect
the MUL and DIV instruction.
The execution of these instructions does not change the contents
of the processor status register.
Ports
The contents of the port direction registers cannot be read.
The following cannot be used:
•The data transfer instruction (LDA, etc.)
•The operation instruction when the index X mode flag (T) is “1”
•The addressing mode which uses the value of a direction regis-
ter as an index
•The bit-test instruction (BBC or BBS, etc.) to a direction register
•The read-modify-write instruction (ROR, CLB, or SEB, etc.) to a
direction register
Use instructions such as LDM and STA, etc., to set the port direc-
tion registers.
Serial I/O
In clock synchronous serial I/O, if the receive side is using an ex-
ternal clock and it is to output the SRDY signal, set the transmit en-
able bit, the receive enable bit, and the SRDY output enable bit to
“1”.
Serial I/O continues to output the final bit from the TXD pin after
transmission is completed.
A-D Converter
The comparator uses internal capacitors whose charge will be lost
if the clock frequency is too low.
Make sure that f(XIN) is at least 500kHz during an A-D conversion.
Do not execute the STP or WIT instruction during an A-D conver-
sion.
Instruction Execution Time
The instruction execution time is obtained by multiplying the fre-
quency of the internal clock φ by the number of cycles needed to
execute an instruction.
The number of cycles required to execute an instruction is shown
in the list of machine instructions.
The frequency of the internal clock φ is half of the XIN frequency.
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
3825 Group
46
DATA REQUIRED FOR MASK ORDERS
The following are necessary when ordering a mask ROM produc-
tion:
1.Mask ROM Order Confirmation Form✽
2.Mark Specification Form✽
3.Data to be written to ROM, in EPROM form (three identical cop-
ies) or one floppy disk.
✽For the mask ROM confirmation and the mark specifications, re-
fer to the “Mitsubishi MCU Technical Information” Homepage
(http://www.infomicom.mesc.co.jp/indexe.htm).
ROM PROGRAMMING METHOD
The built-in PROM of the blank One Time PROM version and built-
in EPROM version can be read or programmed with a general-
purpose PROM programmer using a special programming
adapter. Set the address of PROM programmer in the user ROM
area.
Table 13. Programming adapter
The PROM of the blank One Time PROM version is not tested or
screened in the assembly process and following processes. To en-
sure proper operation after programming, the procedure shown in
Figure 45 is recommended to verify programming.
Fig. 45 Programming and testing of One Time PROM version
Package
100PFB-A
100P6Q-A
100P6S-A
100D0
Name of Programming Adapter
PCA4738H-100A
PCA4738G-100A
PCA4738F-100A
PCA4738L-100A
Programming wit h PROM
programmer
Screening (Caution)
(150°C for 40 hours)
Verification with
PROM programmer
F
u
n
c
t
i
o
n
a
l
c
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e
c
k
i
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t
a
r
g
e
t
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i
c
e
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e
s
c
r
e
e
n
i
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g
t
e
m
p
e
r
a
t
u
r
e
i
s
f
a
r
h
i
g
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e
r
t
h
a
n
t
h
e
s
t
o
r
a
g
e
t
e
m
p
e
r
a
t
u
r
e
.
N
e
v
e
r
e
x
p
o
s
e
t
o
1
5
0
°
C
e
x
c
e
e
d
i
n
g
1
0
0
h
o
u
r
s
.
Caution :
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
3825 Group
47
High-speed mode f(XIN) = 8 MHz
Middle-speed mode f(XIN) = 8 MHz
Low-speed mode
Power source voltage
A-D conversion reference voltage
Analog power source voltage
Analog input voltage AN0–AN7
“H” input voltage P16, P17, P40, P41, P45, P47, P52, P53, P56,
P60–P67, P70–P77, P80, P81 (CM4=0)
“H” input voltage P20–P27, P42–P44, P46, P50, P51, P54, P55, P57
“H” input voltage RESET
“H” input voltage XIN
“L” input voltage P16, P17, P40, P41, P45, P47, P52, P53, P56,
P60–P67, P70–P77, P80, P81 (CM4=0)
“L” input voltage P20–P27, P42–P44, P46, P50, P51, P54, P55, P57
“L” input voltage RESET
“L” input voltage XIN
5.5
5.5
5.5
VCC
VCC
VCC
VCC
VCC
VCC
0.3VCC
0.2VCC
0.2V
CC
0.2VCC
VCC
VSS
VREF
AVSS
VIA
VIH
VIH
VIH
VIH
VIL
VIL
VIL
VIL
Symbol Parameter Limits
Min.
V
V
V
V
V
V
V
V
V
V
V
V
V
Unit
4.0
2.5
2.5
2.0
AVSS
0.7VCC
0.8VCC
0.8VCC
0.8VCC
0
0
0
0
5.0
5.0
5.0
0
0
Typ. Max.
Power source voltage
Table 14. Absolute maximum ratings (Standard, One time PROM version)
–0.3 to 7.0
–0.3 to VCC +0.3
–0.3 to VCC +0.3
–0.3 to VL2
VL1 to VL3
VL2 to 7.0
–0.3 to 7.0
–0.3 to VCC +0.3
–0.3 to 7.0
–0.3 to VCC
–0.3 to VL3
–0.3 to VCC +0.3
–0.3 to 7.0
–0.3 to VL3
–0.3 to VCC +0.3
300
–20 to 85
–40 to 125
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
mW
°C
°C
Power source voltage
Input voltage P16, P17, P20–P27, P40–P47,
P50–P57, P60–P67, P80, P81
Input voltage P70–P77
Input voltage VL1
Input voltage VL2
Input voltage VL3
Input voltage C1, C2
Input voltage RESET, XIN
Output voltage C1, C2
Output voltage P00–P07, P10–P15, P30–P37
Output voltage P16, P17, P20–P27, P40–P47,
P50–P57, P60–P67, P71–P77,
P80, P81
Output voltage VL3
Output voltage VL2, SEG0–SEG17
Output voltage XOUT
Power dissipation
Operating temperature
Storage temperature
VCC
VI
VI
VI
VI
VI
VI
VI
VO
VO
VO
VO
VO
VO
Pd
Topr
Tstg
Symbol Parameter Conditions Ratings Unit
All voltages are based on VSS.
Output transistors are cut off.
At output port
At segment output
Ta = 25°C
Table 15. Recommended operating conditions (Standard, One time PROM version)
(VCC = 2.5 to 5.5 V, Ta = –20 to 85°C, unless otherwise noted.)
ELECTRICAL CHARACTERISTICS (Standard, One Time PROM Version)
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
3825 Group
48
Table 16. Recommended operating conditions (Standard, One time PROM version)
(VCC = 2.5 to 5.5 V, Ta = –20 to 85°C, unless otherwise noted)
–20
–20
20
20
40
–10
–10
10
10
20
–0.5
–5.0
5.0
–0.1
–2.5
2.5
5.0
Note 1: The total output current is the sum of all the currents flowing through all the applicable ports. The total average current is an aver-
age value measured over 100 ms. The total peak current is the peak value of all the currents.
2: The peak output current is the peak current flowing in each port.
3: The average output current is an average value measured over 100 ms.
4: When the oscillation frequency has a duty cycle of 50%.
5: When using the microcomputer in low-speed mode, make sure that the sub-clock input oscillation frequency on condition that
f(XCIN) < f(XIN)/3.
“H” total peak output current
P0
0
–P0
7
, P1
0
–P1
7
, P2
0
–P2
7
, P3
0
–P3
7
(Note 1)
“H” total peak output current P40–P47,P50–P57, P60–P67, P71–P77, P80, P81
(Note 1)
“L” total peak output current
P0
0
–P0
7
, P1
0
–P1
7
, P2
0
–P2
7
, P3
0
–P3
7
(Note 1)
“L” total peak output current P40–P47,P50–P57, P60–P67, P80, P81 (Note 1)
“L” total peak output current
P7
1
–P7
7
(Note 1)
“H” total average output current P00–P07,P10–P17, P20–P27, P30–P37 (Note 1)
“H” total average output current P40–P47, P50–P57, P60–P67, P71–P77, P80, P81
(Note 1)
“L” total average output current P00–P07, P10–P17, P20–P27, P30–P37 (Note 1)
“L” total average output current P40–P47, P50–P57, P60–P67, P80, P81 (Note 1)
“L” total average output current
P7
1
–P7
7
(Note 1)
“H” peak output current P00–P07, P10–P15, P30–P37 (Note 2)
“H” peak output current P16, P17, P20–P27, P40–P47, P50–P57, P60–P67,
P71–P77, P80, P81 (Note 2)
“L” peak output current P00–P07, P10–P15, P30–P37 (Note 2)
“L” peak output current P16, P17, P20–P27, P40–P47, P50–P57, P60–P67,
P70–P77, P80, P81 (Note 2)
“H” average output current P00–P07, P10–P15, P30–P37 (Note 3)
“H” average output current P16, P17, P20–P27, P40–P47, P50–P57, P60–P67,
P71–P77, P80, P81 (Note 3)
“L” average output current P00–P07, P10–P15, P30–P37 (Note 3)
“L” average output current P16, P17, P20–P27, P40–P47, P50–P57, P60–P67,
P71–P77, P80, P81 (Note 3)
Input frequency for timers X and Y
(duty cycle 50%)
Main clock input oscillation frequency
(Note 4)
Sub-clock input oscillation frequency (Note 4, 5)
ΣIOH(peak)
ΣIOH(peak)
ΣIOL(peak)
ΣIOL(peak)
ΣIOL(peak)
ΣIOH(avg)
ΣIOH(avg)
ΣIOL(avg)
ΣIOL(avg)
ΣIOL(avg)
IOH(peak)
IOH(peak)
IOL(peak)
IOL(peak)
IOH(avg)
IOH(avg)
IOL(avg)
IOL(avg)
f(CNTR0)
f(CNTR1)
f(XIN)
f(XCIN)
Symbol Parameter Limits
Min. mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
MHz
MHz
MHz
MHz
MHz
kHz
Unit
Typ. Max.
(4.0 V ≤ VCC ≤ 5.5 V)
(VCC ≤ 4.0 V)
High-speed mode
(4.0 V ≤ VCC ≤ 5.5 V)
High-speed mode
(VCC ≤ 4.0 V)
Middle-speed mode
4.0
(2✕VCC)
–4
8.0
(4✕VCC)
–8
8.0
5032.768
10
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
3825 Group
49
Table 17. Electrical characteristics (Standard, One time PROM version)
(VCC =4.0 to 5.5 V, Ta = –20 to 85°C, unless otherwise noted)
VCC–2.0
VCC–1.0
VCC–2.0
VCC–0.5
VCC–1.0
–30
–6.0
30
6.0
VT+ – VT–
VT+ – VT–
VT+ – VT–
IIH
IIH
IIH
IIL
IIL
IIL
IIL
ILOAD
ILEAK
Note: When “1” is set to port XC switch bit (bit 4 of address 003B16) of CPU mode register, the drive ability of port P80 is different from the
value above mentioned.
“H” output voltage P0
0
–P0
7
, P1
0
–P1
5
, P3
0
–P3
7
“H” output voltage P1
6
, P1
7
, P2
0
–P2
7
, P4
0
–P4
7
,
P5
0
–P5
7
, P6
0
–P6
7
, P7
1
–P7
7
,
P8
0
, P8
1
(Note)
“L” output voltage P0
0
–P0
7
, P1
0
–P1
5
, P3
0
–P3
7
“L” output voltage P1
6
, P1
7
, P2
0
–P2
7
,P4
0
–P4
7
,
P5
0
–P5
7
, P6
0
–P6
7
, P7
1
–P7
7
,
P8
0
, P8
1
(Note)
Hysteresis
INT0–INT3, ADT, CNTR0,
CNTR1, P20–P27
Hysteresis S
CLK
, R
X
D
Hysteresis RESET
“H” input current P1
6
, P1
7
, P2
0
–P2
7
,P4
0
–P4
7
,
P5
0
–P5
7
, P6
0
–P6
7
, P7
0
–P7
7
,
P8
0
, P8
1
“H” input current RESET
“H” input current X
IN
“L” input current P1
6
, P1
7
, P2
0
–P2
7
,P4
0
–P4
7
,
P5
0
–P5
7
, P6
0
–P6
7
, P7
1
–P7
7
,
P8
0
, P8
1
“L” input current P7
0
“L” input current RESET
“L” input current X
IN
Output load current P0
0
–P0
7
, P1
0
–P1
5
, P3
0
–P3
7
Output leak current P0
0
–P0
7
, P1
0
–P1
5
, P3
0
–P3
7
Symbol Parameter Limits
Min. V
Unit
0.5
0.5
0.5
4.0
–70
–25
–4.0
70
25
Typ. Max.
IOH = –0.1 mA
IOH = –25 µA
VCC = 2.5 V
IOH = –5 mA
IOH = –1.25 mA
IOH = –1.25 mA
VCC = 2.5 V
IOL = 5 mA
IOL = 1.25 mA
IOL = 1.25 mA
VCC = 2.5 V
IOL = 10 mA
IOL = 2.5 mA
IOL = 2.5 mA
VCC = 2.5 V
RESET: VCC=2.5 V to 5.5 V
VI = VCC
VI = VCC
VI = VCC
VI = VSS
Pull-ups “off”
VCC = 5 V, VI = VSS
Pull-ups “on”
VCC = 3 V, VI = VSS
Pull-ups “on”
VI = VSS
VI = VSS
V
CC
= 5.0 V, V
O
= V
CC
, Pull-downs “on”
Output transistors “off”
V
CC
= 3.0 V, V
O
= V
CC
, Pull-downs “on”
Output transistors “off”
V
O
= V
CC
, Pull-downs “off”
Output transistors “off”
V
O
= V
SS
, Pull-downs “off”
Output transistors “off”
Test conditions
VOH
VOH
VOL
VOL
2.0
0.5
1.0
2.0
0.5
1.0
5.0
5.0
–5.0
–140
–45
–5.0
–5.0
140
45
5.0
–5.0
V
V
V
V
V
V
V
V
V
V
V
V
V
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
3825 Group
50
Table 18. Electrical characteristics (Standard, One time PROM version)
(VCC =2.5 to 5.5 V, Ta = –20 to 85°C, unless otherwise noted)
mA
mA
µA
µA
µA
µA
µA
V
µA
13
3.2
36
14
22
9.0
1.0
10
2.3
6.0
50
• High-speed mode, VCC = 5 V
f(XIN) = 8 MHz
f(XCIN) = 32.768 kHz
Output transistors “off”
A-D converter in operating
• High-speed mode, VCC = 5 V
f(XIN) = 8 MHz (in WIT state)
f(XCIN) = 32.768 kHz
Output transistors “off”
A-D converter in operating
• Low-speed mode, VCC = 5 V, Ta ≤ 55°C
f(XIN) = stopped
f(XCIN) = 32.768 kHz
Output transistors “off”
• Low-speed mode, VCC = 5 V, Ta = 25°C
f(XIN) = stopped
f(XCIN) = 32.768 kHz (in WIT state)
Output transistors “off”
• Low-speed mode, VCC = 3 V, Ta ≤ 55°C
f(XIN) = stopped
f(XCIN) = 32.768 kHz
Output transistors “off”
• Low-speed mode, VCC = 3 V, Ta = 25°C
f(XIN) = stopped
f(XCIN) = 32.768 kHz (in WIT state)
Output transistors “off”
All oscillation stopped
(in STP state)
Output transistors “off”
Symbol Parameter Limits
Min. Unit
Typ. Max.
Ta = 25 °C
Ta = 85 °C
Test conditions
ICC
Power source current
6.4
1.6
25
7.0
15
4.5
0.1
1.8
3.0
10
VRAM
RAM retention voltage At clock stop mode
2.0 5.5 V
When using voltage multiplier
VL1 = 1.8 V
VL1 < 1.3 V
VL1
IL1
Power source voltage
Power source current (V
L1
)
(Note)
1.3
Note : When the voltage multiplier control bit of the LCD mode register (bit 4 at address 003916) is “1”.
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
3825 Group
51
Table 19. A-D converter characteristics (Standard, One time PROM version)
(
VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –20 to 85°C, 4 MHz ≤ f(XIN) ≤ 8 MHz, in middle-/high-speed mode, unless otherwise noted.)
Symbol Parameter Limits
Min. Unit
Typ. Max.
Test conditions
–
–
tCONV
RLADDER
IVREF
IIA
Resolution
Absolute accuracy (excluding quantization error)
Conversion time
Ladder resistor
Reference input current
Analog port input current
V
CC
= V
REF
= 5 V
12
50
Bits
LSB
µs
kΩ
µA
µA
f(X
IN
) = 8 MHz
V
REF
= 5 V
12.5
(Note)
35
150
8
±2
100
200
5.0
Note : When an internal trigger is used in middle-speed mode, it is 14 µs.
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
3825 Group
52
2
125
45
40
250
105
105
80
80
800
370
370
220
100
Note : When f(XIN) = 8 MHz and bit 6 of address 001A16 is “1” (Clock synchronous).
Divide this value by four when f(XIN) = 8 MHz and bit 6 of address 001A16 is “0” (UART).
Reset input “L” pulse width
Main clock input cycle time (XIN input)
Main clock input “H” pulse width
Main clock input “L” pulse width
CNTR0, CNTR1 input cycle time
CNTR0, CNTR1 input “H” pulse width
CNTR0, CNTR1 input “L” pulse width
INT0 to INT3 input “H” pulse width
INT0 to INT3 input “L” pulse width
Serial I/O clock input cycle time (Note)
Serial I/O clock input “H” pulse width (Note)
Serial I/O clock input “L” pulse width (Note)
Serial I/O input set up time
Serial I/O input hold time
tw(RESET)
tc(XIN)
twH(XIN)
twL(XIN)
tc(CNTR)
twH(CNTR)
twL(CNTR)
twH(INT)
twL(INT)
tc(SCLK)
twH(SCLK)
twL(SCLK)
t
su(R
X
D–S
CLK
)
t
h(S
CLK
–R
X
D)
Symbol Parameter Limits
Min. µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Unit
Typ. Max.
Table 20. Timing requirements 1 (Standard, One time PROM version)
(VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –20 to 85°C, unless otherwise noted.)
2
125
45
40
500/
(VCC–2)
250/
(VCC–2)–20
250/
(VCC–2)–20
230
230
2000
950
950
400
200
Reset input “L” pulse width
Main clock input cycle time (XIN input)
Main clock input “H” pulse width
Main clock input “L” pulse width
CNTR0, CNTR1 input cycle time
CNTR0, CNTR1 input “H” pulse width
CNTR0, CNTR1 input “L” pulse width
INT0 to INT3 input “H” pulse width
INT0 to INT3 input “L” pulse width
Serial I/O clock input cycle time (Note)
Serial I/O clock input “H” pulse width (Note)
Serial I/O clock input “L” pulse width (Note)
Serial I/O input set up time
Serial I/O input hold time
tw(RESET)
tc(XIN)
twH(XIN)
twL(XIN)
tc(CNTR)
twH(CNTR)
twL(CNTR)
twH(INT)
twL(INT)
tc(SCLK)
twH(SCLK)
twL(SCLK)
t
su(R
X
D–S
CLK
)
t
h(S
CLK
–R
X
D)
Symbol Parameter Limits
Min. µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Unit
Typ. Max.
Note: When f(XIN) = 8 MHz and bit 6 of address 001A16 is “1” (Clock synchronous).
Divide this value by four when f(XIN) = 8 MHz and bit 6 of address 001A16 is “0” (UART).
Table 21. Timing requirements 2 (Standard, One time PROM version)
(VCC = 2.5 to 4.0 V, VSS = 0 V, Ta = –20 to 85°C, unless otherwise noted.)
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
3825 Group
53
Notes 1 : When the P45/TXD P-channel output disable bit of the UART control register (bit 4 of address 001B16) is “0”.
2 : XOUT and XCOUT pins are excluded.
Serial I/O clock output “H” pulse width
Serial I/O clock output “L” pulse width
Serial I/O output delay time (Note 1)
Serial I/O output valid time (Note 1)
Serial I/O clock output rising time
Serial I/O clock output falling time
CMOS output rising time (Note 2)
CMOS output falling time (Note 2)
140
30
30
30
30
Symbol Parameter Limits
Min. ns
ns
ns
ns
ns
ns
ns
ns
Unit
t
c(S
CLK
)
/2–30
t
c(S
CLK
)
/2–30
–30
10
10
Typ. Max.
twH(SCLK)
twL(SCLK)
t
d(S
CLK
–T
X
D)
t
v(S
CLK
–T
X
D)
tr(SCLK)
tf(SCLK)
tr(CMOS)
tf(CMOS)
Table 22. Switching characteristics 1 (Standard, One time PROM version)
(VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –20 to 85°C, unless otherwise noted.)
ns
ns
ns
ns
ns
ns
ns
ns
Unit
Notes 1 : When the P45/TXD P-channel output disable bit of the UART control register (bit 4 of address 001B16) is “0”.
2 : XOUT and XCOUT pins are excluded.
Serial I/O clock output “H” pulse width
Serial I/O clock output “L” pulse width
Serial I/O output delay time (Note 1)
Serial I/O output valid time (Note 1)
Serial I/O clock output rising time
Serial I/O clock output falling time
CMOS output rising time (Note 2)
CMOS output falling time (Note 2)
350
50
50
50
50
Symbol Parameter Limits
Min.
t
c(S
CLK
)
/2–50
t
c(S
CLK
)
/2–50
–30
20
20
Max.
twH(SCLK)
twL(SCLK)
t
d(S
CLK
–T
X
D)
t
v(S
CLK
–T
X
D)
tr(SCLK)
tf(SCLK)
tr(CMOS)
tf(CMOS)
Typ.
Table 23. Switching characteristics 2 (Standard, One time PROM version)
(VCC = 2.5 to 4.0 V, VSS = 0 V, Ta = –20 to 85°C, unless otherwise noted.)
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
3825 Group
54
ELECTRICAL CHARACTERISTICS (Extended Operating Temperature Version)
Power source voltage
Input voltage P16, P17, P20–P27, P40–P47,
P50–P57, P60–P67, P80, P81
Input voltage P70–P77
Input voltage VL1
Input voltage VL2
Input voltage VL3
Input voltage C1, C2
Input voltage RESET, XIN
Output voltage C1, C2
Output voltage P00–P07, P10–P15, P30–P37
Output voltage P16, P17, P20–P27, P40–P47,
P50–P57, P60–P67, P71–P77,
P80, P81
Output voltage VL3
Output voltage VL2, SEG0–SEG17
Output voltage XOUT
Power dissipation
Operating temperature
Storage temperature
VCC
VI
VI
VI
VI
VI
VI
VI
VO
VO
VO
VO
VO
VO
Pd
Topr
Tstg
Symbol Parameter Conditions Ratings
–0.3 to 7.0
–0.3 to VCC +0.3
–0.3 to VCC +0.3
–0.3 to VL2
VL1 to VL3
VL2 to 7.0
–0.3 to 7.0
–0.3 to VCC +0.3
–0.3 to 7.0
–0.3 to VCC
–0.3 to VL3
–0.3 to VCC +0.3
–0.3 to 7.0
–0.3 to VL3
–0.3 to VCC +0.3
300
–40 to 85
–65 to 150
Unit
All voltages are based on VSS.
Output transistors are cut off.
At output port
At segment output
Ta = 25°C
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
mW
°C
°C
High-speed mode f(XIN)=8 MHz
Middle-speed mode
f(XIN) = 8 MHz
Low-speed mode
Power source voltage
A-D conversion reference voltage
Analog power source voltage
Analog input voltage AN0–AN7
“H” input voltage P16, P17, P40, P41, P45, P47, P52, P53, P56,
P60–P67, P70–P77, P80, P81 (CM4=0)
“H” input voltage P20–P27, P42–P44, P46, P50, P51, P54, P55, P57
“H” input voltage RESET
“H” input voltage XIN
“L” input voltage P16, P17, P40, P41, P45, P47, P52, P53, P56,
P60–P67, P70–P77, P80, P81 (CM4=0)
“L” input voltage P20–P27, P42–P44, P46, P50, P51, P54, P55, P57
“L” input voltage RESET
“L” input voltage XIN
Ta = –20 to 85°C
Ta = –40 to –20°C
Ta = –20 to 85°C
Ta = –40 to –20°C
Table 25. Recommended operating conditions (Extended operating temperature version)
(VCC = 2.5 to 5.5 V, Ta = –20 to 85°C, and VCC = 3.0 to 5.5 V, Ta = –40 to –20°C, unless otherwise noted.)
5.5
5.5
5.5
5.5
5.5
VCC
VCC
VCC
VCC
VCC
VCC
0.3VCC
0.2VCC
0.2V
CC
0.2VCC
VCC
VSS
VREF
AVSS
VIA
VIH
VIH
VIH
VIH
VIL
VIL
VIL
VIL
Symbol Parameter Limits
Min.
V
V
V
V
V
V
V
V
V
Unit
4.0
2.5
3.0
2.5
3.0
2.0
AVSS
0.7VCC
0.8VCC
0.8VCC
0.8VCC
0
0
0
0
5.0
5.0
5.0
5.0
5.0
0
0
Typ. Max.
Power source voltage
V
V
V
V
Table 24. Absolute maximum ratings (Extended operating temperature version)
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
3825 Group
55
50
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
Table 26. Recommended operating conditions (Extended operating temperature version)
(VCC = 2.5 to 5.5 V, Ta = –20 to 85°C, and VCC = 3.0 to 5.5 V, Ta = –40 to –20°C, unless otherwise noted.)
mA
mA
–20
–20
20
20
40
–10
–10
10
10
20
–0.5
–5.0
5.0
10
–0.1
–2.5
2.5
5.0
4.0
“H” total peak output current
P0
0
–P0
7
, P1
0
–P1
7
, P2
0
–P2
7
, P3
0
–P3
7
(Note 1)
“H” total peak output current P40–P47,P50–P57, P60–P67, P71–P77, P80, P81
(Note 1)
“L” total peak output current
P0
0
–P0
7
, P1
0
–P1
7
, P2
0
–P2
7
, P3
0
–P3
7
(Note 1)
“L” total peak output current P40–P47,P50–P57, P60–P67, P80, P81 (Note 1)
“L” total peak output current
P7
1
–P7
7
(Note 1)
“H” total average output current P00–P07, P10–P17, P20–P27, P30–P37 (Note 1)
“H” total average output current P40–P47, P50–P57, P60–P67, P70–P71, P80, P81
(Note 1)
“L” total average output current P00–P07, P10–P17, P20–P27, P30–P37 (Note 1)
“L” total average output current P40–P47, P50–P57, P60–P67, P80, P81 (Note 1)
“L” total average output current P71–P77 (Note 1)
“H” peak output current P00–P07, P10–P15, P30–P37 (Note 2)
“H” peak output current P16, P17, P20–P27, P40–P47, P50–P57, P60–P67,
P71–P77, P80, P81 (Note 2)
“L” peak output current P00–P07, P10–P15, P30–P37 (Note 2)
“L” peak output current P16, P17, P20–P27, P40–P47, P50–P57, P60–P67,
P71–P77, P80, P81 (Note 2)
“H” average output current P00–P07, P10–P15, P30–P37 (Note 3)
“H” average output current P16, P17, P20–P27, P40–P47, P50–P57, P60–P67,
P71–P77, P80, P81 (Note 3)
“H” average output current P00–P07, P10–P15, P30–P37 (Note 3)
“H” average output current P16, P17, P20–P27, P40–P47, P50–P57, P60–P67,
P71–P77, P80, P81 (Note 3)
Input frequency for timers X and Y
(duty cycle 50%)
Main clock input oscillation frequency
(Note 4)
Sub-clock input oscillation frequency (Note 4, 5)
Notes 1 : The total output current is the sum of all the currents flowing through all the applicable ports. The total average current is an av-
erage value measured over 100 ms. The total peak current is the peak value of all the currents.
2 : The peak output current is the peak current flowing in each port.
3 : The average output current is an average value measured over 100 ms.
4 : When the oscillation frequency has a duty cycle of 50%.
5 : When using the microcomputer in low-speed mode, make sure that the sub-clock input oscillation frequency on condition that
f(XCIN) < f(XIN)/3.
ΣIOH(peak)
ΣIOH(peak)
ΣIOL(peak)
ΣIOL(peak)
ΣIOL(peak)
ΣIOH(avg)
ΣIOH(avg)
ΣIOL(avg)
ΣIOL(avg)
ΣIOL(avg)
IOH(peak)
IOH(peak)
IOL(peak)
IOL(peak)
IOH(avg)
IOH(avg)
IOL(avg)
IOL(avg)
f(CNTR0)
f(CNTR1)
f(XIN)
f(XCIN)
Symbol Parameter Limits
Min. Unit
Typ. Max.
(4.0 V ≤ VCC ≤ 5.5 V)
(VCC ≤ 4.0 V)
32.768
High-speed mode
(4.0 V ≤ VCC ≤ 5.5 V)
High-speed mode
(VCC ≤ 4.0 V)
Middle-speed mode
(2✕VCC)–4
8.0
(4✕VCC)–8
8.0
MHz
MHz
MHz
MHz
MHz
kHz
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
3825 Group
56
Table 27. Electrical characteristics (Extended operating temperature version)
(VCC = 2.5 to 5.5 V, Ta = –20 to 85°C, and VCC = 3.0 to 5.5V, Ta = –40 to –20°C, unless otherwise noted)
µA
µA
µA
µA
µA
V
V
V
V
VCC–2.0
VCC–0.9
VCC–2.0
VCC–0.5
VCC–0.9
VT+ – VT–
VT+ – VT–
VT+ – VT–
IIH
IIH
IIH
IIL
IIL
IIL
IIL
ILOAD
ILEAK
Note : When “1” is set to port XC switch bit (bit 4 of address 003B16) of CPU mode register, the drive ability of port P80 is different from the
value above mentioned.
“H” output voltage P0
0
–P0
7
, P1
0
–P1
5
, P3
0
–P3
7
“H” output voltage P1
6
, P1
7
, P2
0
–P2
7
,P4
0
–P4
7
,
P5
0
–P5
7
, P6
0
–P6
7
, P7
1
–P7
7
,
P8
0
, P8
1
(Note)
“L” output voltage P0
0
–P0
7
, P1
0
–P1
5
, P3
0
–P3
7
“L” output voltage P1
6
, P1
7
, P2
0
–P2
7
,P4
0
–P4
7
,
P5
0
–P5
7
, P6
0
–P6
7
, P7
1
–P7
7
,
P8
0
, P8
1
(Note)
Hysteresis
INT0–INT3, ADT, CNTR0,
CNTR1, P20–P27
Hysteresis S
CLK
, R
X
D
Hysteresis RESET
“H” input current P1
6
, P1
7
, P2
0
–P2
7
,P4
0
–P4
7
,
P5
0
–P5
7
, P6
0
–P6
7
, P7
0
–P7
7
,
P8
0
, P8
1
“H” input current RESET
“H” input current X
IN
“L” input current P1
6
, P1
7
, P2
0
–P2
7
,P4
0
–P4
7
,
P5
0
–P5
7
, P6
0
–P6
7
, P7
1
–P7
7
,
P8
0
, P8
1
“L” input current P7
0
“L” input current RESET
“L” input current X
IN
Output load current P0
0
–P0
7
, P1
0
–P1
5
, P3
0
–P3
7
Output leak current P0
0
–P0
7
, P1
0
–P1
5
, P3
0
–P3
7
Symbol Parameter Limits
Min. V
Unit
0.5
0.5
0.5
4.0
–70
–25
–4.0
70
25
Typ. Max.
IOH = –2.5 mA
IOH = –0.6 mA
VCC = 3.0 V
IOH = –5 mA
IOH = –1.25 mA
IOH = –1.25 mA
VCC = 3.0 V
IOL = 5 mA
IOL = 1.25 mA
IOL = 1.25 mA
VCC = 3.0 V
IOL = 10 mA
IOL = 2.5 mA
IOL = 2.5 mA
VCC = 3.0 V
RESET: VCC=2.5 V to 5.5 V
VI = VCC
VI = VCC
VI = VCC
VI = VSS
Pull-ups “off”
VCC = 5 V, VI = VSS
Pull-ups “on”
VCC = 3 V, VI = VSS
Pull-ups “on”
VI = VSS
VI = VSS
V
CC
= 5.0 V, V
O
= V
CC
, Pull-downs “on”
Output transistors “off”
V
CC
= 3.0 V, V
O
= V
CC
, Pull-downs “on”
Output transistors “off”
V
O
= V
CC
, Pull-downs “off”
Output transistors “off”
V
O
= V
SS
, Pull-downs “off”
Output transistors “off”
Test conditions
VOH
VOH
VOL
VOL
2.0
0.5
1.1
2.0
0.5
1.1
5.0
5.0
–5.0
–140
–45
–5.0
–5.0
170
55
5.0
–5.0
V
V
V
V
V
V
V
V
V
µA
µA
µA
µA
µA
µA
µA
µA
–30
–6.0
30
6.0
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
3825 Group
57
mA
mA
µA
µA
µA
µA
µA
V
µA
13
3.2
36
14
22
9.0
1.0
10
2.3
6.0
50
• High-speed mode, VCC = 5 V
f(XIN) = 8 MHz
f(XCIN) = 32.768 kHz
Output transistors “off”
A-D converter in operating
• High-speed mode, VCC = 5 V
f(XIN) = 8 MHz (in WIT state)
f(XCIN) = 32.768 kHz
Output transistors “off”
A-D converter in operating
• Low-speed mode, VCC = 5 V, Ta ≤ 55°C
f(XIN) = stopped
f(XCIN) = 32.768 kHz
Output transistors “off”
• Low-speed mode, VCC = 5 V, Ta = 25°C
f(XIN) = stopped
f(XCIN) = 32.768 kHz (in WIT state)
Output transistors “off”
• Low-speed mode, VCC = 3 V, Ta ≤ 55°C
f(XIN) = stopped
f(XCIN) = 32.768 kHz
Output transistors “off”
• Low-speed mode, VCC = 3 V, Ta = 25°C
f(XIN) = stopped
f(XCIN) = 32.768 kHz (in WIT state)
Output transistors “off”
All oscillation stopped
(in STP state)
Output transistors “off”
Symbol Parameter Limits
Min. Unit
Typ. Max.
Ta = 25°C
Ta = 85°C
Test conditions
ICC
Power source current
6.4
1.6
25
7.0
15
4.5
0.1
1.8
3.0
10
VRAM
RAM retention voltage At clock stop mode
2.0 5.5 V
When using voltage multiplier
VL1 = 1.8 V
VL1 < 1.3 V
VL1
IL1
Power source voltage
Power source current (V
L1
)
(Note)
1.3
Note : When the voltage multiplier control bit of the LCD mode register (bit 4 at address 003916) is “1”.
Table 29. A-D converter characteristics (Extended operating temperature version)
(VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –40 to 85°C, 4 MHz ≤ f(XIN) ≤ 8 MHz, in middle-/high-speed mode, unless otherwise noted.)
Table 28. Electrical characteristics (Extended operating temperature version)
(VCC = 2.5 to 5.5 V, Ta = –20 to 85°C, and VCC = 3.0 to 5.5 V, Ta = –40 to –20°C, unless otherwise noted.)
Symbol Parameter Limits
Min. Unit
Typ. Max.
Test conditions
–
–
tCONV
RLADDER
IVREF
IIA
Resolution
Absolute accuracy (excluding quantization error)
Conversion time
Ladder resistor
Reference input current
Analog iinput current
V
CC
= V
REF
= 5 V
12
50
Bits
LSB
µs
kΩ
µA
µA
f(X
IN
) = 8 MHz
V
REF
= 5 V
12.5
(Note)
35
150
8
±2
100
200
5.0
Note : When an internal trigger is used in middle-speed mode, it is 14 µs.
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
3825 Group
58
Table 30. Timing reguirements 1 (Extended operating temperature version)
(VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –40 to 85°C, unless otherwise noted.)
2
125
45
40
250
105
105
80
80
800
370
370
220
100
Note : When f(XIN) = 8 MHz and bit 6 of address 001A16 is “1” (Clock synchronous).
Divide this value by four when f(XIN) = 8 MHz and bit 6 of address 001A16 is “0” (UART).
Reset input “L” pulse width
Main clock input cycle time (XIN input)
Main clock input “H” pulse width
Main clock input “L” pulse width
CNTR0, CNTR1 input cycle time
CNTR0, CNTR1 input “H” pulse width
CNTR0, CNTR1 input “L” pulse width
INT0 to INT3 input “H” pulse width
INT0 to INT3 input “L” pulse width
Serial I/O clock input cycle time (Note)
Serial I/O clock input “H” pulse width (Note)
Serial I/O clock input “L” pulse width (Note)
Serial I/O input set up time
Serial I/O input hold time
tw(RESET)
tc(XIN)
twH(XIN)
twL(XIN)
tc(CNTR)
twH(CNTR)
twL(CNTR)
twH(INT)
twL(INT)
tc(SCLK)
twH(SCLK)
twL(SCLK)
t
su(R
X
D–S
CLK
)
t
h(S
CLK
–R
X
D)
Symbol Parameter Limits
Min. µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Unit
Typ. Max.
Table 31. Timing reguirements 2 (Extended operating temperature version)
(VCC = 2.5 to 4.0 V, VSS = 0 V, Ta = –20 to 85°C, and VCC = 3.0 to 4.0 V, VSS = 0 V, Ta = –40 to –20°C, unless otherwise noted.)
Note: When f(XIN) = 8 MHz and bit 6 of address 001A16 is “1” (Clock synchronous).
Divide this value by four when f(XIN) = 8 MHz and bit 6 of address 001A16 is “0” (UART).
2
125
45
40
500/
(VCC–2)
250/
(VCC–2)–20
250/
(VCC–2)–20
230
230
2000
950
950
400
200
Reset input “L” pulse width
Main clock input cycle time (XIN input)
Main clock input “H” pulse width
Main clock input “L” pulse width
CNTR0, CNTR1 input cycle time
CNTR0, CNTR1 input “H” pulse width
CNTR0, CNTR1 input “L” pulse width
INT0 to INT3 input “H” pulse width
INT0 to INT3 input “L” pulse width
Serial I/O clock input cycle time (Note)
Serial I/O clock input “H” pulse width (Note)
Serial I/O clock input “L” pulse width (Note)
Serial I/O input set up time
Serial I/O input hold time
tw(RESET)
tc(XIN)
twH(XIN)
twL(XIN)
tc(CNTR)
twH(CNTR)
twL(CNTR)
twH(INT)
twL(INT)
tc(SCLK)
twH(SCLK)
twL(SCLK)
t
su(R
X
D–S
CLK
)
t
h(S
CLK
–R
X
D)
Symbol Parameter Limits
Min. µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Unit
Typ. Max.
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
3825 Group
59
Table 32. Switching characteristics 1 (Extended operating temperature version)
(VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –40 to 85°C, unless otherwise noted.)
Notes 1 : When the P45/TXD P-channel output disable bit of the UART control register (bit 4 of address 001B16) is “0”.
2 : XOUT and XCOUT pins are excluded.
Serial I/O clock output “H” pulse width
Serial I/O clock output “L” pulse width
Serial I/O output delay time (Note 1)
Serial I/O output valid time (Note 1)
Serial I/O clock output rising time
Serial I/O clock output falling time
CMOS output rising time (Note 2)
CMOS output falling time (Note 2)
140
30
30
30
30
Symbol Parameter Limits
Min. ns
ns
ns
ns
ns
ns
ns
ns
Unit
t
c(S
CLK
)
/2–30
t
c(S
CLK
)
/2–30
–30
10
10
Typ. Max.
twH(SCLK)
twL(SCLK)
t
d(S
CLK
–T
X
D)
t
v(S
CLK
–T
X
D)
tr(SCLK)
tf(SCLK)
tr(CMOS)
tf(CMOS)
Table 33. Switching characteristics 2 (Extended operating temperature version)
(VCC = 2.5 to 4.0 V, VSS = 0 V, Ta = –20 to 85°C, and VCC = 3.0 to 4.0 V, VSS = 0 V, Ta = –40 to –20°C, unless otherwise noted.)
Notes 1 : When the P45/TXD P-channel output disable bit of the UART control register (bit 4 of address 001B16) is “0”.
2 : XOUT and XCOUT pins are excluded.
Serial I/O clock output “H” pulse width
Serial I/O clock output “L” pulse width
Serial I/O output delay time (Note 1)
Serial I/O output valid time (Note 1)
Serial I/O clock output rising time
Serial I/O clock output falling time
CMOS output rising time (Note 2)
CMOS output falling time (Note 2)
350
50
50
50
50
Symbol Parameter Limits
Min. ns
ns
ns
ns
ns
ns
ns
ns
Unit
t
c(S
CLK
)
/2–50
t
c(S
CLK
)
/2–50
–30
20
20
Max.
twH(SCLK)
twL(SCLK)
t
d(S
CLK
–T
X
D)
t
v(S
CLK
–T
X
D)
tr(SCLK)
tf(SCLK)
tr(CMOS)
tf(CMOS)
Typ.
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
3825 Group
60
(VCC = 2.2 to 5.5 V, Ta = –20 to 85°C, unless otherwise noted.)
Table 34. Absolute maximum ratings (M version)
Power source voltage
Input voltage P16, P17, P20–P27, P40–P47,
P50–P57, P60–P67, P80, P81
Input voltage P70–P77
Input voltage VL1
Input voltage VL2
Input voltage VL3
Input voltage C1, C2
Input voltage RESET, X IN
Output voltage C1, C2
Output voltage P00–P07, P10–P15, P30–P37
Output voltage P16, P17, P20–P27, P40–P47,
P50–P57, P60–P67, P71–P77
P80, P81
Output voltage VL3
Output voltage VL2, SEG0–SEG17
Output voltage XOUT
Power dissipation
Operating temperature
Storage temperature
VCC
VI
VI
VI
VI
VI
VI
VI
VO
VO
VO
VO
VO
VO
Pd
Topr
Tstg
Symbol Parameter Conditions Ratings
–0.3 to 7.0
–0.3 to VCC +0.3
–0.3 to VCC +0.3
–0.3 to VL2
VL1 to VL3
VL2 to 7.0
–0.3 to 7.0
–0.3 to VCC +0.3
–0.3 to 7.0
–0.3 to VCC
–0.3 to VL3
–0.3 to VCC +0.3
–0.3 to 7.0
–0.3 to VL3
–0.3 to VCC +0.3
300
–20 to 85
–40 to 125
Unit
All voltages are based on VSS.
Output transistors are cut off.
At output port
At segment output
Ta = 25°C
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
mW
°C
°C
High-speed mode, f(XIN)=8 MHz
Middle-speed mode, f(XIN) = 8 MHz
Low-speed mode
Table 35. Recommended operating conditions (M version)
5.5
5.5
5.5
VCC
VCC
VCC
VCC
VCC
VCC
0.3VCC
0.2VCC
0.2V
CC
0.2VCC
VCC
Symbol Parameter Limits
Min.
V
Unit
4.0
2.2
2.2
2.0
AVSS
0.7VCC
0.8VCC
0.8VCC
0.8VCC
0
0
0
0
5.0
5.0
5.0
0
0
Typ. Max.
Power source voltage
Power source voltage
A-D conversion reference voltage
Analog power source voltage
Analog input voltage AN0–AN7
“H” input voltage P16, P17, P40, P41, P45, P47, P52, P53, P56,
P60–P67, P70–P77, P80, P81 (CM4=0)
“H” input voltage P20–P27, P42–P44, P46, P50, P51, P54, P55, P57
“H” input voltage RESET
“H” input voltage XIN
“L” input voltage P16, P17, P40, P41, P45, P47, P52, P53, P56,
P60–P67, P70–P77, P80, P81 (CM4=0)
“L” input voltage P20–P27, P42–P44, P46, P50, P51, P54, P55, P57
“L” input voltage RESET
“L” input voltage XIN
VSS
VREF
AVSS
VIA
VIH
VIH
VIH
VIH
VIL
VIL
VIL
VIL
V
V
V
V
V
V
V
V
V
V
V
V
ELECTRICAL CHARACTERISTICS (M Version)
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
3825 Group
61
50
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
Table 36. Recommended operating conditions (M version)
(VCC = 2.2 to 5.5 V, Ta = –20 to 85°C, unless otherwise noted.)
mA
mA
–20
–20
20
20
40
–10
–10
10
10
20
–0.5
–5.0
5.0
10
–0.1
–2.5
2.5
5.0
4.0
“H” total peak output current
P0
0
–P0
7
, P1
0
–P1
7
, P2
0
–P2
7
, P3
0
–P3
7
(Note 1)
“H” total peak output current P40–P47,P50–P57, P60–P67, P71–P77, P80, P81
(Note 1)
“L” total peak output current
P0
0
–P0
7
, P1
0
–P1
7
, P2
0
–P2
7
, P3
0
–P3
7
(Note 1)
“L” total peak output current P40–P47,P50–P57, P60–P67, P80, P81 (Note 1)
“L” total peak output current
P7
1
–P7
7
(Note 1)
“H” total average output current P00–P07, P10–P17, P20–P27, P30–P37 (Note 1)
“H” total average output current P40–P47, P50–P57, P60–P67, P71–P77, P80, P81
(Note 1)
“L” total average output current P00–P07, P10–P17, P20–P27, P30–P37 (Note 1)
“L” total average output current P40–P47, P50–P57, P60–P67, P80, P81 (Note 1)
“L” total average output current P71–P77 (Note 1)
“H” peak output current P00–P07, P10–P15, P30–P37 (Note 2)
“H” peak output current P16, P17, P20–P27, P40–P47, P50–P57, P60–P67,
P71–P77, P80, P81 (Note 2)
“L” peak output current P00–P07, P10–P15, P30–P37 (Note 2)
“L” peak output current P16, P17, P20–P27, P40–P47, P50–P57, P60–P67,
P71–P77, P80, P81 (Note 2)
“H” average output current P00–P07, P10–P15, P30–P37 (Note 3)
“H” average output current P16, P17, P20–P27, P40–P47, P50–P57, P60–P67,
P71–P77, P80, P81 (Note 3)
“H” average output current P00–P07, P10–P15, P30–P37 (Note 3)
“H” average output current P16, P17, P20–P27, P40–P47, P50–P57, P60–P67,
P71–P77, P80, P81 (Note 3)
Input frequency for timers X and Y
(duty cycle 50%)
Main clock input oscillation frequency
(Note 4)
Sub-clock input oscillation frequency (Note 4, 5)
Notes 1 : The total output current is the sum of all the currents flowing through all the applicable ports. The total average current is an av-
erage value measured over 100 ms. The total peak current is the peak value of all the currents.
2 : The peak output current is the peak current flowing in each port.
3 : The average output current is an average value measured over 100 ms.
4 : When the oscillation frequency has a duty cycle of 50%.
5 : When using the microcomputer in low-speed mode, make sure that the sub-clock input oscillation frequency on condition that
f(XCIN) < f(XIN)/3.
ΣIOH(peak)
ΣIOH(peak)
ΣIOL(peak)
ΣIOL(peak)
ΣIOL(peak)
ΣIOH(avg)
ΣIOH(avg)
ΣIOL(avg)
ΣIOL(avg)
ΣIOL(avg)
IOH(peak)
IOH(peak)
IOL(peak)
IOL(peak)
IOH(avg)
IOH(avg)
IOL(avg)
IOL(avg)
f(CNTR0)
f(CNTR1)
f(XIN)
f(XCIN)
Symbol Parameter Limits
Min. Unit
Typ. Max.
(4.0 V ≤ VCC ≤ 5.5 V)
(2.2 V ≤ VCC ≤ 4.0 V)
32.768
High-speed mode
(4.0 V ≤ VCC ≤ 5.5 V)
High-speed mode
(2.2 V ≤ VCC ≤ 4.0 V)
Middle-speed mode
(10 ✕ V
CC
–
4) / 9
8.0
8.0
MHz
MHz
MHz
MHz
MHz
kHz
(20 ✕ V
CC
–
8) / 9
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
3825 Group
62
Table 37. Electrical characteristics (M version)
(VCC = 2.2 to 5.5 V, Ta = –20 to 85°C, unless otherwise noted)
µA
µA
µA
µA
µA
V
V
V
V
VCC–2.0
VCC–0.8
VCC–2.0
VCC–0.5
VCC–0.8
VT+ – VT–
VT+ – VT–
VT+ – VT–
IIH
IIH
IIH
IIL
IIL
IIL
IIL
ILOAD
ILEAK
Note : When “1” is set to port XC switch bit (bit 4 of address 003B16) of CPU mode register, the drive ability of port P80 is different from the
value above mentioned.
“H” output voltage P0
0
–P0
7
, P1
0
–P1
5
, P3
0
–P3
7
“H” output voltage P1
6
, P1
7
, P2
0
–P2
7
,P4
0
–P4
7
,
P5
0
–P5
7
, P6
0
–P6
7
, P7
1
–P7
7
,
P8
0
, P8
1
(Note)
“L” output voltage P0
0
–P0
7
, P1
0
–P1
5
, P3
0
–P3
7
“L” output voltage P1
6
, P1
7
, P2
0
–P2
7
,P4
0
–P4
7
,
P5
0
–P5
7
, P6
0
–P6
7
, P7
1
–P7
7
,
P8
0
, P8
1
(Note)
Hysteresis
INT0–INT3, ADT, CNTR0,
CNTR1, P20–P27
Hysteresis S
CLK
, R
X
D
Hysteresis RESET
“H” input current P1
6
, P1
7
, P2
0
–P2
7
,P4
0
–P4
7
,
P5
0
–P5
7
, P6
0
–P6
7
, P7
0
–P7
7
,
P8
0
, P8
1
“H” input current RESET
“H” input current X
IN
“L” input current P1
6
, P1
7
, P2
0
–P2
7
,P4
0
–P4
7
,
P5
0
–P5
7
, P6
0
–P6
7
, P7
0
–P7
7
,
P8
0
, P8
1
“L” input current P7
0
“L” input current RESET
“L” input current X
IN
Output load current P0
0
–P0
7
, P1
0
–P1
5
, P3
0
–P3
7
Output leak current P0
0
–P0
7
, P1
0
–P1
5
, P3
0
–P3
7
Symbol Parameter Limits
Min. V
Unit
0.5
0.5
0.5
4.0
–70
–25
–4.0
70
25
Typ. Max.
IOH = –2.5 mA
IOH = –0.25 mA
VCC = 2.2 V
IOH = –5 mA
IOH = –1.25 mA
IOH = –1.25 mA
VCC = 2.2 V
IOL = 5 mA
IOL = 1.25 mA
IOL = 1.25 mA
VCC = 2.2 V
IOL = 10 mA
IOL = 2.5 mA
IOL = 2.5 mA
VCC = 2.2 V
RESET: VCC=2.2 V to 5.5 V
VI = VCC
VI = VCC
VI = VCC
VI = VSS
Pull-ups “off”
VCC = 5 V, VI = VSS
Pull-ups “on”
VCC = 2.2 V, VI = VSS
Pull-ups “on”
VI = VSS
VI = VSS
V
CC
= 5.0 V, V
O
= V
CC
, Pull-downs “on”
Output transistors “off”
V
CC
= 2.2 V, V
O
= V
CC
, Pull-downs “on”
Output transistors “off”
V
O
= V
CC
, Pull-downs “off”
Output transistors “off”
V
O
= V
SS
, Pull-downs “off”
Output transistors “off”
Test conditions
VOH
VOH
VOL
VOL
2.0
0.5
0.8
2.0
0.5
0.8
5.0
5.0
–5.0
–140
–45
–5.0
–5.0
140
45
5.0
–5.0
V
V
V
V
V
V
V
V
V
µA
µA
µA
µA
µA
µA
µA
µA
–30
–6.0
30
6.0
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
3825 Group
63
mA
mA
µA
µA
µA
µA
µA
V
µA
13
3.2
36
14
22
9.0
1.0
10
2.3
6.0
50
• High-speed mode, VCC = 5 V
f(XIN) = 8 MHz
f(XCIN) = 32.768 kHz
Output transistors “off”
A-D converter in operating
• High-speed mode, VCC = 5 V
f(XIN) = 8 MHz (in WIT state)
f(XCIN) = 32.768 kHz
Output transistors “off”
A-D converter in operating
• Low-speed mode, VCC = 5 V, Ta ≤ 55°C
f(XIN) = stopped
f(XCIN) = 32.768 kHz
Output transistors “off”
• Low-speed mode, VCC = 5 V, Ta = 25°C
f(XIN) = stopped
f(XCIN) = 32.768 kHz (in WIT state)
Output transistors “off”
• Low-speed mode, VCC = 3 V, Ta ≤ 55°C
f(XIN) = stopped
f(XCIN) = 32.768 kHz
Output transistors “off”
• Low-speed mode, VCC = 3 V, Ta = 25°C
f(XIN) = stopped
f(XCIN) = 32.768 kHz (in WIT state)
Output transistors “off”
All oscillation stopped
(in STP state)
Output transistors “off”
Symbol Parameter Limits
Min. Unit
Typ. Max.
Ta = 25°C
Ta = 85°C
Test conditions
ICC
Power source current
6.4
1.6
25
7.0
15
4.5
0.1
1.8
3.0
10
VRAM
RAM retention voltage At clock stop mode
2.0 5.5 V
When using voltage multiplier
VL1 = 1.8 V
VL1 < 1.3 V
VL1
IL1
Power source voltage
Power source current (V
L1
)
(Note)
1.3
Note : When the voltage multiplier control bit of the LCD mode register (bit 4 at address 003916) is “1”.
Table 39. A-D converter characteristics (M version)
(VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –20 to 85°C, 4 MHz ≤ f(XIN) ≤ 8 MHz, in middle-/high-speed mode, unless otherwise noted.)
Table 38. Electrical characteristics (M version)
(VCC = 2.2 to 5.5 V, Ta = –20 to 85°C, unless otherwise noted.)
Symbol Parameter Limits
Min. Unit
Typ. Max.
Test conditions
–
–
tCONV
RLADDER
IVREF
IIA
Resolution
Absolute accuracy (excluding quantization error)
Conversion time
Ladder resistor
Reference input current
Analog iinput current
V
CC
= V
REF
= 5 V
12
50
Bits
LSB
µs
kΩ
µA
µA
f(X
IN
) = 8 MHz
V
REF
= 5 V
12.5
(Note)
35
150
8
±2
100
200
5.0
Note : When an internal trigger is used in middle-speed mode, it is 14 µs.
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
3825 Group
64
Table 40. Timing reguirements 1 (M Version)
(VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –20 to 85°C, unless otherwise noted.)
2
125
45
40
250
105
105
80
80
800
370
370
220
100
Note : When f(XIN) = 8 MHz and bit 6 of address 001A16 is “1” (Clock synchronous).
Divide this value by four when f(XIN) = 8 MHz and bit 6 of address 001A16 is “0” (UART).
Reset input “L” pulse width
Main clock input cycle time (XIN input)
Main clock input “H” pulse width
Main clock input “L” pulse width
CNTR0, CNTR1 input cycle time
CNTR0, CNTR1 input “H” pulse width
CNTR0, CNTR1 input “L” pulse width
INT0 to INT3 input “H” pulse width
INT0 to INT3 input “L” pulse width
Serial I/O clock input cycle time (Note)
Serial I/O clock input “H” pulse width (Note)
Serial I/O clock input “L” pulse width (Note)
Serial I/O input set up time
Serial I/O input hold time
tw(RESET)
tc(XIN)
twH(XIN)
twL(XIN)
tc(CNTR)
twH(CNTR)
twL(CNTR)
twH(INT)
twL(INT)
tc(SCLK)
twH(SCLK)
twL(SCLK)
t
su(R
X
D–S
CLK
)
t
h(S
CLK
–R
X
D)
Symbol Parameter Limits
Min. µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Unit
Typ. Max.
Table 41. Timing reguirements 2 (M Version)
(VCC = 2.2 to 4.0 V, VSS = 0 V, Ta = –20 to 85°C, unless otherwise noted.)
Note: When f(XIN) = 8 MHz and bit 6 of address 001A16 is “1” (Clock synchronous).
Divide this value by four when f(XIN) = 8 MHz and bit 6 of address 001A16 is “0” (UART).
2
125
45
40
900 /
(VCC – 0.4)
450 /
(VCC – 0.4) – 20
450 /
(VCC – 0.4) – 20
230
230
2000
950
950
400
200
Reset input “L” pulse width
Main clock input cycle time (XIN input)
Main clock input “H” pulse width
Main clock input “L” pulse width
CNTR0, CNTR1 input cycle time
CNTR0, CNTR1 input “H” pulse width
CNTR0, CNTR1 input “L” pulse width
INT0 to INT3 input “H” pulse width
INT0 to INT3 input “L” pulse width
Serial I/O clock input cycle time (Note)
Serial I/O clock input “H” pulse width (Note)
Serial I/O clock input “L” pulse width (Note)
Serial I/O input set up time
Serial I/O input hold time
tw(RESET)
tc(XIN)
twH(XIN)
twL(XIN)
tc(CNTR)
twH(CNTR)
twL(CNTR)
twH(INT)
twL(INT)
tc(SCLK)
twH(SCLK)
twL(SCLK)
t
su(R
X
D–S
CLK
)
t
h(S
CLK
–R
X
D)
Symbol Parameter Limits
Min. µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Unit
Typ. Max.
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
3825 Group
65
Table 42. Switching characteristics 1 (M version)
(VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –20 to 85°C, unless otherwise noted.)
Notes 1 : When the P45/TXD P-channel output disable bit of the UART control register (bit 4 of address 001B16) is “0”.
2 : XOUT and XCOUT pins are excluded.
Serial I/O clock output “H” pulse width
Serial I/O clock output “L” pulse width
Serial I/O output delay time (Note 1)
Serial I/O output valid time (Note 1)
Serial I/O clock output rising time
Serial I/O clock output falling time
CMOS output rising time (Note 2)
CMOS output falling time (Note 2)
140
30
30
30
30
Symbol Parameter Limits
Min. ns
ns
ns
ns
ns
ns
ns
ns
Unit
t
c(S
CLK
)
/2–30
t
c(S
CLK
)
/2–30
–30
10
10
Typ. Max.
twH(SCLK)
twL(SCLK)
t
d(S
CLK
–T
X
D)
t
v(S
CLK
–T
X
D)
tr(SCLK)
tf(SCLK)
tr(CMOS)
tf(CMOS)
Table 43. Switching characteristics 2 (M version)
(VCC = 2.2 to 4.0 V, VSS = 0 V, Ta = –20 to 85°C, unless otherwise noted.)
Notes 1 : When the P45/TXD P-channel output disable bit of the UART control register (bit 4 of address 001B16) is “0”.
2 : XOUT and XCOUT pins are excluded.
Serial I/O clock output “H” pulse width
Serial I/O clock output “L” pulse width
Serial I/O output delay time (Note 1)
Serial I/O output valid time (Note 1)
Serial I/O clock output rising time
Serial I/O clock output falling time
CMOS output rising time (Note 2)
CMOS output falling time (Note 2)
350
50
50
50
50
Symbol Parameter Limits
Min. ns
ns
ns
ns
ns
ns
ns
ns
Unit
t
c(S
CLK
)
/2–50
t
c(S
CLK
)
/2–50
–30
20
20
Max.
twH(SCLK)
twL(SCLK)
t
d(S
CLK
–T
X
D)
t
v(S
CLK
–T
X
D)
tr(SCLK)
tf(SCLK)
tr(CMOS)
tf(CMOS)
Typ.
Fig. 46 Circuit for measuring output switching characteristics
M
e
a
s
u
r
e
m
e
n
t
o
u
t
p
u
t
p
i
n
1
0
0
p
F
C
M
O
S
o
u
t
p
u
t
N
ote:
Wh
en
bi
t 4 o
f
t
h
e
UART
contro
l
reg
i
ster
(
a
dd
ress
001B
16
) is “1” (N-channel open-drain output mode).
N
-
c
h
a
n
n
e
l
o
p
e
n
-
d
r
a
i
n
o
u
t
p
u
t
(
N
o
t
e
)
1
k
Ω
1
0
0
p
F
M
easurement output p
i
n
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
3825 Group
66
TIMING DIAGRAM
Fig. 47 Timing diagram
t
W(RESET)
0
.
8
V
C
C
0
.
2
V
C
C
R
E
S
E
T
t
C(X
IN
)
t
C(CNTR)
t
W
H
(
C
N
T
R
)
t
W
L
(
C
N
T
R
)
0
.
8
V
C
C
0.2
V
C
C
C
N
T
R
0
,
C
N
T
R
1
t
WH(INT)
t
W
L
(
I
N
T
)
0
.
8
V
C
C
0
.
2
V
C
C
I
N
T
0
–
I
N
T
3
t
WH(X
IN
)
t
W
L
(
X
I
N
)
0
.
8
V
C
C
0.2
V
C
C
X
I
N
t
C(S
CLK
)
t
WL(S
CLK
)
t
WH(S
CLK
)
0
.
2
V
C
C
0.8
V
C
C
S
C
L
K
t
r
t
f
t
d
(
S
C
L
K
-
T
X
D
)
t
v
(
S
C
L
K
-
T
X
D
)
T
X
D
R
X
D
0
.
2
V
C
C
0
.
8
V
C
C
t
s
u
(
R
X
D
-
S
C
L
K
)
t
h
(
S
C
L
K
-
R
X
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)
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
3825 Group
67
PACKAGE OUTLINES
QFP100-P-1420-0.65 1.58
Weight(g)
–
JEDEC Code
EIAJ Package Code Lead Material
Alloy 42
100P6S-A Plastic 100pin 14✕20mm body QFP
–
0.1
–
––
0.2
–
–
––
–
–––
–
Symbol Min Nom Max
A
A2
b
c
D
E
HE
L
L1
y
b2
Dimension in Millimeters
HD
A1
0.35 ––
I21.3 ––
MD14.6 ––
ME20.6
10°0°0.1
1.4 0.80.60.4 23.122.822.5 17.116.816.5 0.65 20.220.019.8 14.214.013.8 0.20.150.13 0.40.30.25 2.8
03.05
e
e
e
E
c
HE
1
30
31
81
50
80
51
HD
D
MD
ME
A
F
A1A2
L1
L
y
b2
I2
Recommended Mount Pad
Detail F
100
x – – 0.13
bxM
MMP
LQFP100-P-1414-0.50 Weight(g)
–0.63
JEDEC Code
EIAJ Package Code Lead Material
Cu Alloy
100P6Q-A Plastic 100pin 14✕14mm body LQFP
–
0.1
–
––
0.2
–
–
––
–
–––
–
Symbol Min Nom Max
A
A2
b
c
D
E
HE
L
L1
y
b2
Dimension in Millimeters
HD
A1
0.225 ––
I20.9 ––
MD14.4 ––
ME14.4
10°0°0.1
1.0 0.70.50.3 16.216.015.8 16.216.015.8 0.5 14.114.013.9 14.114.013.9 0.1750.1250.105 0.280.180.13 1.4
01.7
e
e
E
HE
1
76
75
51
5026
25
HD
D
A
F
y
100
Lp 0.45
–
–
0.6
0.25
–
0.75
–
0.08
x
A3
bxM
A1A2
L1
L
Detail F Lp
A3
c
MD
l2
b2
ME
e
Recommended Mount Pad
MMP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
3825 Group
68
TQFP100-P-1212-0.40 Weight(g)
–0.37
JEDEC Code
EIAJ Package Code Lead Material
Cu Alloy
100PFB-A Plastic 100pin 12✕12mm body TQFP
––
––
–
–
––
–
–––
–
Symbol Min Nom Max
A
A2
b
c
D
E
HE
L
L1
y
b2
Dimension in Millimeters
HD
A1 0.150.1
0.225 ––
I21.0 ––
MD12.4 ––
ME12.4
10°0° 0.08
0.07
1.0 0.6 0.50.4 14.214.013.8 14.214.013.8 0.4 12.112.011.9 12.112.011.9 0.1750.1250.105 0.230.180.13 1.0
0.05 1.2
e
HE
E
D
HD
1
25
75
76
100
26 50
51
F
e
A
y
L1
A1A2
L
Lp
A3
Detail F
c
Lp 0.45
–0.6
0.25 0.75
–
x
A3 ––
bxM
MD
e
ME
b2
I2
Recommended Mount Pad
MMP
Weight(g)
JEDEC Code
EIAJ Package Code
100D0 Glass seal 100pin QFN
––
31
50 81
51 80
30
1
1.075TYP
0.45TYP0.65TYP
INDEX
3.5TYP
5.0MAX
0.65TYP
1.075TYP
0.35TYP 0.65TYP
12.35±0.15
15.6±0.13
21.0±0.13
18.85±0.15
100
© 2001 MITSUBISHI ELECTRIC CORP.
Specifications subject to change without notice.
Notes regarding these materials
• These materials are intended as a reference to assist our customers in the selection of the Mitsubishi semiconductor product best suited to the customer’s application; they do not convey any license under any intellectual property
rights, or any other rights, belonging to Mitsubishi Electric Corporation or a third party.
• Mitsubishi Electric Corporation assumes no responsibility for any damage, or infringement of any third-party’s rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples
contained in these materials.
• All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these materials, and are subject to change by
Mitsubishi Electric Corporation without notice due to product improvements or other reasons. It is therefore recommended that customers contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product
distributor for the latest product information before purchasing a product listed herein.
The information described here may contain technical inaccuracies or typographical errors. Mitsubishi Electric Corporation assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors.
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• Mitsubishi Electric Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to
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HEAD OFFICE: 2-2-3, MARUNOUCHI, CHIYODA-KU, TOKYO 100-8310, JAPAN
REVISION HISTORY 3825 GROUP DATA SHEET
Rev. Date Description
Page Summary
(1/1)
1.0 01/23/98 First Edition
2.0 05/15/98
7 to 10
17
43
53
The followings are mainly revised:
Group expnasion
(11) Port P70 of port bock diagram
Name in Table 11
The “L” input current parameter of IIL in Tables 25 and 35 is not P7 0–P77 but P71–
P77.
Low power source version is added.
2.1 07/13/99
3.0 12/11/00 1
1
4
6
7
8
9
10
10
11 to 13
20
24
34
40
40
42
43
45
46
46
48
50
57
60 to 65
60
61
63
“•2 Clock generating circuits” of “FEATURES” is partly eliminated.
“•Power source voltage” of “FEATURES” is partly revised.
“Function” of “Vcc, Vss” into Table 1 is partly revised.
Figure 4 is partly revised.
Clause name and explanations of “GROUP EXPANSION (STANDARD, ONE TIME
PROM VERSION, EPROM VERSION)” are partly revised.
Table 3 is partly eliminated.
Table 4 is partly eliminated.
Clause name and explanations of “GROUP EXPANSION (M VERSION)” are partly
revised.
Figure name of Figure 7 is partly revised.
Explanations of “CENTRAL PROCESSING UNIT (CPU)” are added.
(12), (13), (14) into Figure 15 is partly revised.
Figure 19 is partly revised.
Figure 31 is partly revised.
Explanations of “RESET CIRCUIT” are partly revised.
Figure 38 is partly revised.
Explanations of “CLOCK GENERATING CIRCUIT” are partly eliminated.
Figure 43 is partly revised.
Explanations of “Decimal Calculations” of “NOTES ON PROGRAMMING” are partly
eliminated.
Explanations of “DATA REQUIRED FOR MASK ORDERS” are partly added.
Explanations of “DATA REQUIRED FOR WRITING ORDERS” in Rev.2.1 are elimi-
nated.
Note number of “IOH(avg) P00–P07, P10–P15, P30–P37” into Table 16 is revised.
Test conditions of Icc into Table 18 are partly revised.
Test conditions of Icc into Table 28 are partly revised.
Table names of Tables 34 to 43 are partly revised.
Limits of AVss into Table 35 is partly revised.
Parameter of ΣIOH(avg) into Table 36 is partly revised.
Test conditions of Icc into Table 38 is partly revised.
3.1 02/06/01 22
24
30
46
Explanations of “■Notes on interrupts” are partly revised.
Figure 19 is partly revised.
“■Notes on serial I/O” is added.
Explanations of “DATA REQUIRED FOR MASK ORDERS” are partly revised.
