Freescale Semiconductor
Data Sheet: Technical Data
Document Number: MCF5275EC
Rev. 4, 02/2009
Contents
© Freescale Semiconductor, Inc., 2009. All rights reserved.
The MCF5275 family is a highly integrated
implementation of the ColdFire® family of reduced
instruction set computing (RISC) microprocessors. This
document describes pertinent features and functions
characteristics of the MCF5275 family. The MCF5275
family includes the MCF5275, MCF5275L, MCF5274
and MCF5274L microprocessors. The differences
between these parts are summarized in Table 1. This
document is written from the perspective of the
MCF5275 and unless otherwise noted, the information
applies also to the MCF5275L, MCF5274 and
MCF5274L.
The MCF5275 family delivers a new level of
performance and integration on the popular version 2
ColdFire core with up to 159 (Dhrystone 2.1) MIPS @
166MHz. These highly integrated microprocessors build
upon the widely used peripheral mix on the popular
MCF5272 ColdFire microprocessor (10/100 Mbps
Ethernet MAC and USB device) by adding a second
10/100 Mbps Ethernet MAC (MCF5274 and MCF5275)
and hardware encryption (MCF5275L and MCF5275).
1 MCF5275 Family Configurations . . . . . . . . . . . . . . . . . . . 2
2 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
4 Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
5 Design Recommendations . . . . . . . . . . . . . . . . . . . . . . . 9
6 Mechanicals/Pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
7 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
8 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 18
9 Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
10 Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
MCF5275 Integrated
Microprocessor Family Hardware
Specification
by: Microcontroller Solutions Group
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 4
MCF5275 Family Configurations
Freescale Semiconductor2
In addition, the MCF5275 family features an enhanced multiply accumulate unit (EMAC), large on-chip
memory (64 Kbytes SRAM, 16 Kbytes configurable cache), and a 16-bit DDR SDRAM memory
controller.
These devices are ideal for cost-sensitive applications requiring significant control processing for file
management, connectivity, data buffering, and user interface, as well as signal processing in a variety of
key markets such as security, imaging, networking, gaming, and medical. This leading package of
integration and high performance allows fast time to market through easy code reuse and extensive third
party tool support.
To locate any published errata or updates for this document, refer to the ColdFire products website at
http://www.freescale.com/coldfire.
1 MCF5275 Family Configurations
Table 1. MCF5275 Family Configurations
Module MCF5274L MCF5275L MCF5274 MCF5275
ColdFire Version 2 Core with EMAC (Enhanced Multiply-Accumulate Unit) ••••
System Clock up to 166 MHz
Performance (Dhrystone 2.1 MIPS) up to 159
Instruction/Data Cache 16 Kbytes (configurable)
Static RAM (SRAM) 64 Kbytes
Interrupt Controllers (INTC) 2222
Edge Port Module (EPORT) ••••
External Interface Module (EIM) ••••
4-channel Direct-Memory Access (DMA) ••••
DDR SDRAM Controller ••••
Fast Ethernet Controller (FEC) 1122
Watchdog Timer Module (WDT) ••••
4-channel Programmable Interval Timer Module (PIT) ••••
32-bit DMA Timers 4444
USB ••••
QSPI ••••
UART(s) 3333
I2C••••
PWM 4444
General Purpose I/O Module (GPIO) ••••
CIM = Chip Configuration Module + Reset Controller Module ••••
Debug BDM ••••
JTAG - IEEE 1149.1 Test Access Port ••••
Hardware Encryption — •—•
Package 196 MAPBGA 256 MAPBGA
Block Diagram
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 4
Freescale Semiconductor 3
2 Block Diagram
The superset device in the MCF5275 family comes in a 256 Mold Array Plastic Ball Grid Array
(MAPBGA) package. Figure 1 shows a top-level block diagram of the MCF5275, the superset device.
Figure 1. MCF5275 Block Diagram
3Features
For a detailed feature list see the MCF5275 Reference Manual (MCF5275RM).
64 Kbytes
SRAM
(8Kx16)x4
EIM
V2 ColdFire CPU
INTC0
Watchdog
PIT0
JTAG
TAP
CACHE
(1Kx32)x4
PIT1 PIT2 PIT3
4 CH DMA
UART
0
UART
1I2CQSPI
DTIM
0
DTIM
1
DTIM
2
DTIM
3
Timer
PLL
CLKGEN
UART
2
16 Kbytes
Edge
Port
SDRAMC
CHIP
EBI
SELECTS
(To/From PADI)
(To/From
PORTS
CIM
(GPIO)
DIV EMAC
DREQ[1:0]
INTC1
Arbiter
(To/From SRAM backdoor)
(To/From Arbiter backdoor)
SKHARNGAMDHA
Cryptography
Modules
DACK[3:0]
BDM
(To/From INTC)
MUX
PADI)
JTAG_EN
PADI – Pin Muxing
BS[3:2]
PWMx
USB
FEC0
DTINx
DTOUTx
RXDx
TXDx
I2C_SDA
I2C_SCL
DDR
QSPI
RTSx
CTSx
D[31:16]
A[23:0]
R/
W
CS[3:0]
TA
TSIZ[1:0]
TEA
FEC1
JTAG_EN
TRST
TCLK
TMS
TDI
TDO
(To/From
PADI)
(To/From PADI) FAST ETHERNET
CONTROLLER
(FEC1)
FAST ETHERNET
CONTROLLER
(FEC0)
4 CH PWM
(To/From PADI)
USB 2.0
Full Speed
(To/From PADI)
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 4
Signal Descriptions
Freescale Semiconductor4
4 Signal Descriptions
This section describes signals that connect off chip, including a table of signal properties. For a more
detailed discussion of the MCF5275 signals, consult the MCF5275 Reference Manual (MCF5275RM).
Table 2 lists the signals for the MCF5275 in functional group order. The “Dir” column is the direction for
the primary function of the pin. Refer to Section 6, “Mechanicals/Pinouts,” for package diagrams.
NOTE
In this table and throughout this document a single signal within a group is
designated without square brackets (i.e., A24), while designations for
multiple signals within a group use brackets (i.e., A[23:21]) and is meant to
include all signals within the two bracketed numbers when these numbers
are separated by a colon.
NOTE
The primary functionality of a pin is not necessarily its default functionality.
Pins that are muxed with GPIO will default to their GPIO functionality.
Table 2. MCF5274 and MCF5275 Signal Information and Muxing
Signal Name GPIO Alternate1 Alternate2 Dir.1
MCF5274
MCF5275
256 MAPBGA
MCF5274L
MCF5275L
196 MAPBGA
Reset
RESET ———IN15 K12
RSTOUT ———ON14 L12
Clock
EXTAL ———I L16 M14
XTAL ———OM16 N14
CLKOUT ———OT12 P9
Mode Selection
CLKMOD[1:0] ———IN13, P13 M11, N11
RCON ———IP8 M6
External Memory Interface and Ports
A[23:21] PADDR[7:5] CS[6:4] — O A11, B11, C11 A8, B8, C8
A[20:0] — — — O A12, B12, C12,
A13, B13, C13,
A14, B14, C14,
B15, C15, B16,
C16, D14, D15,
E14:16, F14:16
B9, D9, C9,
C10, B10, A11,
C11, B11, A12,
D11, C12, B13,
C13, D12, E11,
D13, E12, F11,
D14, E13, F13
Signal Descriptions
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 4
Freescale Semiconductor 5
D[31:16] ———OM1, N1, N2, N3,
P1, P2, R1, R2,
P3, R3, T3, N4,
P4, R4, T4, N5
J3, L1, K2, K3,
M1, L2, L3, L4,
K4, J4, M2, N1,
N2, M3, M4, N3
BS[3:2] PBS[3:2] CAS[3:2] — O M3, R5 K1, L5
OE PBUSCTL[7] — — O K1 H4
TA PBUSCTL[6] — — I L13 K14
TEA PBUSCTL[5] DREQ1 —I T8 —
R/W PBUSCTL[4] — — O P7 L6
TSIZ1 PBUSCTL[3] DACK1 — OD16 B14
TSIZ0 PBUSCTL[2] DACK0 — OG16 E14
TS PBUSCTL[1] DACK2 — OL4 H2
TIP PBUSCTL[0] DREQ0 — O P6 —
Chip Selects
CS[7:1] PCS[7:1] — — O D10:13, E13,
F13, N7
D8, A9, A10,
D10, B12, C14,
P4
CS0 — — — O R6 N5
DDR SDRAM Controller
DDR_CLKOUT ———OT7 P6
DDR_CLKOUT ———OT6 P5
SD_CS[1:0] PSDRAM[7:6] CS[3:2] — O M2, T5 H3, M5
SD_SRAS PSDRAM[5] — — O L2 H1
SD_SCAS PSDRAM[4] — — O L1 G3
SD_WE PSDRAM[3] — — O K2 G4
SD_A10 ———ON6 N4
SD_DQS[3:2] PSDRAM[2:1] ——I/OM4, P5 J2, P3
SD_CKE PSDRAM[0] — — O L3 J1
SD_VREF — — — I A15, T2 A13, P2
External Interrupts Port
IRQ[7:5] PIRQ[7:5] ——I G13, H16, H15 F14, G13, G14
IRQ[4] PIRQ[4] DREQ2 —IH14 H11
IRQ[3:2] PIRQ[3:2] DREQ[3:2] —I J14, J13 H14, H12
Table 2. MCF5274 and MCF5275 Signal Information and Muxing (continued)
Signal Name GPIO Alternate1 Alternate2 Dir.1
MCF5274
MCF5275
256 MAPBGA
MCF5274L
MCF5275L
196 MAPBGA
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 4
Signal Descriptions
Freescale Semiconductor6
IRQ1 PIRQ[1] ——I K13 J13
FEC0
FEC0_MDIO PFECI2C[5] I2C_SDA U2RXD I/O A7 A3
FEC0_MDC PFECI2C[4] I2C_SCL U2TXD OB7 C5
FEC0_TXCLK PFEC0H[7] ——IC3 C1
FEC0_TXEN PFEC0H[6] ——OD4 C3
FEC0_TXD[0] PFEC0H[5] ——OG4 D2
FEC0_COL PFEC0H[4] ——IA6 B4
FEC0_RXCLK PFEC0H[3] ——IB6 B3
FEC0_RXDV PFEC0H[2] ——IB5 C4
FEC0_RXD[0] PFEC0H[1] ——IC6 D5
FEC0_CRS PFEC0H[0] ——IC7 A2
FEC0_TXD[3:1] PFEC0L[7:5] ——OE3, F3, F4 D1, E3, D3
FEC0_TXER PFEC0L[4] ——OD3 C2
FEC0_RXD[3:1] PFEC0L[3:1] ——ID5, C5, D6 D4, B1, B2
FEC0_RXER PFEC0L[0] ——IC4 E4
FEC1
FEC1_MDIO PFECI2C[3] ——I/O G1 —
FEC1_MDC PFECI2C[2] ——OG2 —
FEC1_TXCLK PFEC1H[7] ——IC1 —
FEC1_TXEN PFEC1H[6] ——OD2 —
FEC1_TXD[0] PFEC1H[5] ——OF1 —
FEC1_COL PFEC1H[4] ——IA5 —
FEC1_RXCLK PFEC1H[3] ——IB4 —
FEC1_RXDV PFEC1H[2] ——IA3 —
FEC1_RXD[0] PFEC1H[1] ——IB3 —
FEC1_CRS PFEC1H[0] ——IA4 —
FEC1_TXD[3:1] PFEC1L[7:5] ——OE1, E2, F2 —
FEC1_TXER PFEC1L[4] ——OD1 —
FEC1_RXD[3:1] PFEC1L[3:1] ——IB1, B2, A2 —
FEC1_RXER PFEC1L[0] ——IC2 —
Table 2. MCF5274 and MCF5275 Signal Information and Muxing (continued)
Signal Name GPIO Alternate1 Alternate2 Dir.1
MCF5274
MCF5275
256 MAPBGA
MCF5274L
MCF5275L
196 MAPBGA
Signal Descriptions
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 4
Freescale Semiconductor 7
I2C
I2C_SDA PFECI2C[1] U2RXD — I/O B10 B7
I2C_SCL PFECI2C[0] U2TXD — I/O C10 A7
DMA
DACK[3:0] and DREQ[3:0] do not have a dedicated bond pads.
Please refer to the following pins for muxing:
PCS3/PWM3 for DACK3, PCS2/PWM2 for DACK2, TSIZ1 for
DACK1, TSIZ0 for DACK0, IRQ3 for DREQ3, IRQ2 and TA for
DREQ2, TEA for DREQ1, and TIP for DREQ0.
— —
QSPI
QSPI_CS[3:2] PQSPI[6:5] PWM[3:2] DACK[3:2] OR13, N12 P10, N9
QSPI_CS1 PQSPI[4] — — O T14 N10
QSPI_CS0 PQSPI[3] — — O P12 M9
QSPI_CLK PQSPI[2] I2C_SCL — O T15 L11
QSPI_DIN PQSPI[1] I2C_SDA — I T13 M10
QSPI_DOUT PQSPI[0] — — O R12 L10
UARTs
U2RXD PUARTH[3] — — I T9 —
U2TXD PUARTH[2] — — O R9 —
U2CTS PUARTH[1] PWM1 — I P9 —
U2RTS PUARTH[0] PWM0 — O R8 —
U1RXD PUARTL[7] — — I A9 A6
U1TXD PUARTL[6] — — O B9 D7
U1CTS PUARTL[5] — — I C9 C7
U1RTS PUARTL[4] — — O D9 B6
U0RXD PUARTL[3] — — I A8 A4
U0TXD PUARTL[2] — — O B8 A5
U0CTS PUARTL[1] — — I C8 C6
U0RTS PUARTL[0] — — O D7 B5
USB
USB_SPEED PUSBH[0] — — I/O G14 G11
USB_CLK PUSBL[7] — — I G15 F12
Table 2. MCF5274 and MCF5275 Signal Information and Muxing (continued)
Signal Name GPIO Alternate1 Alternate2 Dir.1
MCF5274
MCF5275
256 MAPBGA
MCF5274L
MCF5275L
196 MAPBGA
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 4
Signal Descriptions
Freescale Semiconductor8
USB_RN PUSBL[6] — — I J16 H13
USB_RP PUSBL[5] — — I J15 J11
USB_RXD PUSBL[4] — — I L15 L14
USB_SUSP PUSBL[3] — — O M13 N13
USB_TN PUSBL[2] — — O K14 J14
USB_TP PUSBL[1] — — O K15 J12
USB_TXEN PUSBL[0] — — O L14 K13
Timers (and PWMs)
DT3IN PTIMERH[3] DT3OUT U2RTS I J4 G2
DT3OUT PTIMERH[2] PWM3 U2CTS OK3 G1
DT2IN PTIMERH[1] DT2OUT — I J2 F3
DT2OUT PTIMERH[0] PWM2 — O J3 F4
DT1IN PTIMERL[3] DT1OUT — I H1 F1
DT1OUT PTIMERL[2] PWM1 — O H2 F2
DT0IN PTIMERL[1] DT0OUT — I H3 E1
DT0OUT PTIMERL[0] PWM0 — O G3 E2
BDM/JTAG2
DSCLK —TRST — I P14 P13
PSTCLK —TCLK — O P16 P12
BKPT —TMS — I R15 N12
DSI —TDI — I R16 M12
DSO —TDO — O P15 K11
JTAG_EN — — — I R14 P11
DDATA[3:0] — — — O P10, N10, P11,
N11
M7, N7, P8, L9
PST[3:0] — — — O T10, R10, T11,
R11
P7, L8, M8, N8
Test
TEST — — — I N9 N6
PLL_TEST — — — I M14 —
Power Supplies
VDDPLL — — — I M15 M13
Table 2. MCF5274 and MCF5275 Signal Information and Muxing (continued)
Signal Name GPIO Alternate1 Alternate2 Dir.1
MCF5274
MCF5275
256 MAPBGA
MCF5274L
MCF5275L
196 MAPBGA
Design Recommendations
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 4
Freescale Semiconductor 9
5 Design Recommendations
5.1 Layout
• Use a 4-layer printed circuit board with the VDD and GND pins connected directly to the power
and ground planes for the MCF5275.
• See application note AN1259 System Design and Layout Techniques for Noise Reduction in
MCU-Based Systems.
• Match the PC layout trace width and routing to match trace length to operating frequency and board
impedance. Add termination (series or therein) to the traces to dampen reflections. Increase the
PCB impedance (if possible) keeping the trace lengths balanced and short. Then do cross-talk
analysis to separate traces with significant parallelism or are otherwise "noisy". Use 6 mils trace
and separation. Clocks get extra separation and more precise balancing.
5.2 Power Supply
• 33uF, 0.1 μF, and 0.01 μF across each power supply
VSSPLL — — — I K16 L13
VSS — — — I A1, A10, A16,
E5, E12, F6,
F11, G7:10,
H7:10, J1,
J7:10, K7:10,
L6, L11, M5,
N16, R7, T1,
T16
F7, F8, G6:9,
H6:9, J7, J8
OVDD — — — I E6:8, F5, F7, F8,
G5, G6, H5, H6,
J11, J12, K11,
K12, L9, L10,
L12, M9:11
E5:7, F5, F6,
H10, J9, J10,
K8:10
VDD — — — I D8, H13, K4, N8 D6, G5, G12, L7
SD_VDD — — — I E9:11, F9, F10,
F12, G11, G12,
H11, H12, J5,
J6, K5, K6, L5,
L7, L8, M6, M7,
M8
E8:10, F9, F10,
G10, H5, J5, J6,
K5:7
1Refers to pin’s primary function. All pins which are configurable for GPIO have a pullup enabled in GPIO
mode with the exception of PBUSCTL[7], PBUSCTL[4:0], PADDR, PBS, PSDRAM.
2If JTAG_EN is asserted, these pins default to Alternate 1 (JTAG) functionality. The GPIO module is not
responsible for assigning these pins.
Table 2. MCF5274 and MCF5275 Signal Information and Muxing (continued)
Signal Name GPIO Alternate1 Alternate2 Dir.1
MCF5274
MCF5275
256 MAPBGA
MCF5274L
MCF5275L
196 MAPBGA
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 4
Design Recommendations
Freescale Semiconductor10
5.2.1 Supply Voltage Sequencing and Separation Cautions
Figure 2 shows situations in sequencing the I/O VDD (OVDD), SDRAM VDD (SDVDD), PLL VDD
(PLLVDD), and Core VDD (VDD).
Figure 2. Supply Voltage Sequencing and Separation Cautions
The relationship between SDVDD and OVDD is non-critical during power-up and power-down sequences.
SDVDD (2.5V or 3.3V) and OVDD are specified relative to VDD.
5.2.1.1 Power Up Sequence
If OVDD/SDVDD are powered up with VDD at 0 V, then the sense circuits in the I/O pads cause all pad
output drivers connected to the OVDD/SDVDD to be in a high impedance state. There is no limit on how
long after OVDD/SDVDD powers up before VDD must powered up. VDD should not lead the OVDD,
SDVDD, or PLLVDD by more than 0.4 V during power ramp-up or high current will be in the internal ESD
protection diodes. The rise times on the power supplies should be slower than 1 μs to avoid turning on the
internal ESD protection clamp diodes.
The recommended power up sequence is as follows:
1. Use 1 μs or slower rise time for all supplies.
2. VDD/PLLVDD and OVDD/SDVDD should track up to 0.9 V, then separate for the completion of
ramps with OVDD/SD VDD going to the higher external voltages. One way to accomplish this is to
use a low drop-out voltage regulator.
SDVDD (2.5V)
Supplies Stable
2
1
3.3V
2.5V
1.5V
0
Time
Notes:
VDD should not exceed OVDD, SDVDD or PLLVDD by more than
0.4 V at any time, including power-up.
Recommended that VDD should track OVDD/SDVDD/PLLVDD up to
0.9 V, then separate for completion of ramps.
Input voltage must not be greater than the supply voltage (OVDD, SDVDD,
VDD, or PLLVDD) by more than 0.5 V at any time, including during power-up.
Use 1 ms or slower rise time for all supplies.
1.
2.
3.
4.
DC Power Supply Voltage
VDD,
OVDD, SDVDD, PLLVDD
Design Recommendations
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 4
Freescale Semiconductor 11
5.2.1.2 Power Down Sequence
If VDD is powered down first, then sense circuits in the I/O pads cause all output drivers to be in a high
impedance state. There is no limit on how long after VDD powers down before OVDD, SDVDD, or PLLVDD
must power down. VDD should not lag OVDD, SDVDD, or PLLVDD going low by more than 0.4 V during
power down or undesired high current will be in the ESD protection diodes. There are no requirements for
the fall times of the power supplies.
The recommended power down sequence is as follows:
1. Drop VDD to 0 V.
2. Drop OVDD/SDVDD/PLLVDD supplies.
5.3 Decoupling
• Place the decoupling capacitors as close to the pins as possible, but they can be outside the footprint
of the package.
• 0.1 μF and 0.01 μF at each supply input
5.4 Buffering
• Use bus buffers on all data/address lines for all off-board accesses and for all on-board accesses
when excessive loading is expected. See electricals.
5.5 Pull-up Recommendations
• Use external pull-up resistors on unused inputs. See pin table.
5.6 Clocking Recommendations
• Use a multi-layer board with a separate ground plane.
• Place the crystal and all other associated components as close to the EXTAL and XTAL (oscillator
pins) as possible.
• Do not run a high frequency trace around crystal circuit.
• Ensure that the ground for the bypass capacitors is connected to a solid ground trace.
• Tie the ground trace to the ground pin nearest EXTAL and XTAL. This prevents large loop currents
in the vicinity of the crystal.
• Tie the ground pin to the most solid ground in the system.
• Do not connect the trace that connects the oscillator and the ground plane to any other circuit
element. This tends to make the oscillator unstable.
• Tie XTAL to ground when an external oscillator is clocking the device.
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 4
Design Recommendations
Freescale Semiconductor12
5.7 Interface Recommendations
5.7.1 DDR SDRAM Controller
5.7.1.1 SDRAM Controller Signals in Synchronous Mode
Table 3 shows the behavior of SDRAM signals in synchronous mode.
5.7.1.2 Address Multiplexing
See the SDRAM controller module chapter in the MCF5275 Reference Manual for details on address
multiplexing.
5.7.2 Ethernet PHY Transceiver Connection
The FEC supports an MII interface for 10/100 Mbps Ethernet and a seven-wire serial interface for 10 Mbps
Ethernet. The interface mode is selected by R_CNTRL[MII_MODE]. In MII mode, the 802.3 standard
defines and the FEC module supports 18 signals. These are shown in Table 4.
Table 3. Synchronous DRAM Signal Connections
Signal Description
SD_SRAS Synchronous row address strobe. Indicates a valid SDRAM row address is present and can be
latched by the SDRAM. SD_SRAS should be connected to the corresponding SDRAM
SD_SRAS. Do not confuse SD_SRAS with the DRAM controller’s SDRAM_CS[1:0], which
should not be interfaced to the SDRAM SD_SRAS signals.
SD_SCAS Synchronous column address strobe. Indicates a valid column address is present and can be
latched by the SDRAM. SD_SCAS should be connected to the corresponding signal labeled
SD_SCAS on the SDRAM.
SD_WE DRAM read/write. Asserted for write operations and negated for read operations.
SD_CS[1:0] Row address strobe. Select each memory block of SDRAMs connected to the MCF5275. One
SDRAM_CS signal selects one SDRAM block and connects to the corresponding CS signals.
SD_CKE Synchronous DRAM clock enable. Connected directly to the CKE (clock enable) signal of
SDRAMs. Enables and disables the clock internal to SDRAM. When CKE is low, memory can
enter a power-down mode where operations are suspended or they can enter self-refresh
mode. SD_CKE functionality is controlled by DCR[COC]. For designs using external
multiplexing, setting COC allows SD_CKE to provide command-bit functionality.
BS[3:2] Column address strobe. For synchronous operation, BS[3:2] function as byte enables to the
SDRAMs. They connect to the DQM signals (or mask qualifiers) of the SDRAMs.
DDR_CLKOUT Bus clock output. Connects to the CLK input of SDRAMs.
Table 4. MII Mode
Signal Description MCF5275 Pin
Transmit clock FECn_TXCLK
Transmit enable FECn_TXEN
Transmit data FECn_TXD[3:0]
Transmit error FECn_TXER
Design Recommendations
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 4
Freescale Semiconductor 13
The serial mode interface operates in what is generally referred to as AMD mode. The MCF5275
configuration for seven-wire serial mode connections to the external transceiver are shown in Table 5.
Refer to the M5275EVB evaluation board user’s manual for an example of how to connect an external
PHY. Schematics for this board are accessible at the MCF5275 site by navigating to:
http://www.freescale.com/coldfire.
5.7.3 BDM
Use the BDM interface as shown in the M5275EVB evaluation board user’s manual. The schematics for
this board are accessible at the MCF5275 site by navigating to: http://www.freescale.com/coldfire.
Collision FECn_COL
Carrier sense FECn_CRS
Receive clock FECn_RXCLK
Receive enable FECn_RXDV
Receive data FECn_RXD[3:0]
Receive error FECn_RXER
Management channel clock FECn_MDC
Management channel serial data FECn_MDIO
Table 5. Seven-Wire Mode Configuration
Signal Description MCF5275 Pin
Transmit clock FECn_TXCLK
Transmit enable FECn_TXEN
Transmit data FECn_TXD[0]
Collision FECn_COL
Receive clock FECn_RXCLK
Receive enable FECn_RXDV
Receive data FECn_RXD[0]
Unused, configure as PB14 FECn_RXER
Unused input, tie to ground FECn_CRS
Unused, configure as PB[13:11] FECn_RXD[3:1]
Unused output, ignore FECn_TXER
Unused, configure as PB[10:8] FECn_TXD[3:1]
Unused, configure as PB15 FECn_MDC
Input after reset, connect to ground FECn_MDIO
Table 4. MII Mode (continued)
Signal Description MCF5275 Pin
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 4
Mechanicals/Pinouts
Freescale Semiconductor14
6 Mechanicals/Pinouts
6.1 256 MAPBGA Pinout
Figure 3 is a consolidated MCF5274/75 pinout for the 256 MAPBGA package. Table 2 lists the signals by
group and shows which signals are muxed and bonded on each of the device packages.
Figure 3. MCF5274 and MCF5275 Pinout (256 MAPBGA)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
AVSS FEC1_
RXD1
FEC1_
RXDV
FEC1_
CRS
FEC1_
COL
FEC0_
COL
FEC0_
MDIO U0RXD U1RXD VSS A23 A20 A17 A14 SD_
VREF VSS A
BFEC1_
RXD3
FEC1_
RXD2
FEC1_
RXD0
FEC1_
RXCLK
FEC0_
RXDV
FEC0_
RXCLK
FEC0_
MDC U0TXD U1TXD I2C_
SDA A22 A19 A16 A13 A11 A9 B
CFEC1_
TXCLK
FEC1_
RXER
FEC0_
TXCLK
FEC0_
RXER
FEC0_
RXD2
FEC0_
RXD0
FEC0_
CRS U0CTS U1CTS I2C_
SCL A21 A18 A15 A12 A10 A8 C
DFEC1_
TXER
FEC1_
TXEN
FEC0_
TXER
FEC0_
TXEN
FEC0_
RXD3
FEC0_
RXD1 U0RTS VDD U1RTS CS7 CS6 CS5 CS4 A7 A6 TSIZ1 D
EFEC1_
TXD3
FEC1_
TXD2
FEC0_
TXD3 NC VSS OVDD OVDD OVDD SD_VDD SD_VDD SD_VDD VSS CS3 A5 A4 A3 E
FFEC1_
TXD0
FEC1_
TXD1
FEC0_
TXD2
FEC0_
TXD1 OVDD VSS OVDD OVDD SD_VDD SD_VDD VSS SD_VDD CS2 A2 A1 A0 F
GFEC1_
MDIO
FEC1_
MDC DT0OUT FEC0_
TXD0 OVDD OVDD VSS VSS VSS VSS SD_VDD SD_VDD IRQ7 USB_
SPEED
USB_
CLK TSIZ0 G
HDT1IN DT1OUT DT0IN NC OVDD OVDD VSS VSS VSS VSS SD_VDD SD_VDD VDD IRQ4 IRQ5 IRQ6 H
JVSS DT2IN DT2OUT DT3IN SD_VDD SD_VDD VSS VSS VSS VSS OVDD OVDD IRQ2 IRQ3 USB_RP USB_RN J
KOE SD_WE DT3OUT VDD SD_VDD SD_VDD VSS VSS VSS VSS OVDD OVDD IRQ1 USB_TN USB_TP VSSPLL K
LSD_
SCAS
SD_
SRAS SD_CKE TS SD_VDD VSS SD_VDD SD_VDD OVDD OVDD VSS OVDD TA USB_
TXEN
USB_
RXD EXTAL L
MD31 SD_CS1 BS3 SD_DQS3 VSS SD_VDD SD_VDD SD_VDD OVDD OVDD OVDD NC USB_
SUSP
PLL_
TEST VDDPLL XTAL M
ND30 D29 D28 D20 D16 SD_A10 CS1 VDD TEST DDATA2 DDATA0 QSPI_
CS2
CLK
MOD1 RSTOUT RESET VSS N
PD27 D26 D23 D19 SD_DQS2 TIP R/W RCON U2CTS DDATA3 DDATA1 QSPI_
CS0
CLK
MOD0
TRST/
DSCLK
TDO/
DSO
TCLK/
PSTCLK P
RD25 D24 D22 D18 BS2 CS0 VSS U2RTS U2TXD PST2 PST0 QSPI_
DOUT
QSPI_
CS3
JTAG_
EN
TMS/
BKPT TDI/DSI R
TVSS SD_
VREF D21 D17 SD_CS0 DDR_CLK
OUT
DDR_CLK
OUT TEA U2RXD PST3 PST1 CLKOUT QSPI_
DIN
QSPI_
CS1
QSPI_
CLK VSS T
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
Mechanicals/Pinouts
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 4
Freescale Semiconductor 15
6.2 Package Dimensions - 256 MAPBGA
Figure 6 shows MCF5275 256 MAPBGA package dimensions.
Figure 4. 256 MAPBGA Package Dimensions
X
Y
D
E
LASER MARK FOR PIN A1
IDENTIFICATION IN
THIS AREA
0.20
METALIZED MARK FOR
PIN A1 IDENTIFICATION
IN THIS AREA
M
M
3
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
123456710111213141516
e15X
e15X
b256X
M
0.25 YZ
M
0.10
X
Z
S
DETAIL K
VIEW M-M
ROTATED 90 CLOCKWISE
°
S
A
ZZ
A2
A1
40.15
Z0.30
256X
5
K
NOTES:
1. DIMENSIONS ARE IN MILLIMETERS.
2. INTERPRET DIMENSIONS AND TOLERANCES
PER ASME Y14.5M, 1994.
3. DIMENSION b IS MEASURED AT THE
MAXIMUM SOLDER BALL DIAMETER,
PARALLEL TO DATUM PLANE Z.
4. DATUM Z (SEATING PLANE) IS DEFINED BY
THE SPHERICAL CROWNS OF THE SOLDER
BALLS.
5. PARALLELISM MEASUREMENT SHALL
EXCLUDE ANY EFFECT OF MARK ON TOP
SURFACE OF PACKAGE.
DIM MIN MAX
MILLIMETERS
A1.25 1.60
A1 0.27 0.47
A2 1.16 REF
b0.40 0.60
D17.00 BSC
E17.00 BSC
e1.00 BSC
S0.50 BSC
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 4
Mechanicals/Pinouts
Freescale Semiconductor16
6.3 196 MAPBGA Pinout
Figure 5 is a consolidated MCF5274L/75L pinout for the 196 MAPBGA package. Table 2 lists the signals
by group and shows which signals are muxed and bonded on each of the device packages.
Figure 5. MCF5274L and MCF5275L Pinout (196 MAPBGA)
1234567891011121314
ANC FEC0_
CRS
FEC0_
MDIO U0RXD U0TXD U1RXD I2C_SCL A23 CS6 CS5 A15 A12 SD_
VREF NC A
BFEC0_
RXD2
FEC0_
RXD1
FEC0_
RXCLK
FEC0_
COL U0RTS U1RTS I2C_SDA A22 A20 A16 A13 CS3 A9 TSIZ1 B
CFEC0_
TXCLK
FEC0_
TXER
FEC0_
TXEN
FEC0_
RXDV
FEC0_
MDC U0CTS U1CTS A21 A18 A17 A14 A10 A8 CS2 C
DFEC0_
TXD3
FEC0_
TXD0
FEC0_
TXD1
FEC0_
RXD3
FEC0_
RXD0 VDD U1TXD CS7 A19 CS4 A11 A7 A5 A2 D
EDT0IN DT0OUT FEC0_
TXD2
FEC0_
RXER OVDD OVDD OVDD SD_VDD2 SD_VDD2 SD_VDD2 A6 A4 A1 TSIZ0 E
FDT1IN DT1OUT DT2IN DT2OUT OVDD OVDD VSS VSS SD_VDD2 SD_VDD2 A3 USB_CLK A0 IRQ7 F
GDT3OUT DT3IN SD_CAS SD_WE VDD VSS VSS VSS VSS SD_VDD2 USB_
SPEED VDD IRQ6 IRQ5 G
HSD_SRAS TS SD_CS1 OE SD_VDD1 VSS VSS VSS VSS OVDD IRQ4 IRQ2 USB_RN IRQ3 H
JSD_CKE SD_DQS3 D31 D22 SD_VDD1 SD_VDD1 VSS VSS OVDD OVDD USB_RP USB_TP IRQ1 USB_TN J
KBS3 D29 D28 D23 SD_VDD1 SD_VDD1 SD_VDD1 OVDD OVDD OVDD TDO/DSO RESET USB_
TXEN TA K
LD30 D26 D25 D24 BS2 R/W VDD PST2 DDATA0 QSPI_
DOUT QSPI_CLK RSTOUT VSSPLL USB_RXD L
MD27 D21 D18 D17 SD_CS0 RCON DDATA3 PST1 QSPI_
CS0 QSPI_DIN CLKMOD1 TDI/DSI VDDPLL EXTAL M
ND20 D19 D16 SD_A10 CS0 TEST DDATA2 PST0 QSPI_
CS2
QSPI_
CS1 CLKMOD0 TMS/BKPT USB_
SUSP XTAL N
PNC SD_
VREF SD_DQS2 CS1 DDR_CLK
OUT
DDR_CLK
OUT PST3 DDATA1 CLKOUT QSPI_
CS3 JTAG_EN TCLK/PST
CLK
TRST/DSC
LK NC P
1234567891011121314
Mechanicals/Pinouts
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 4
Freescale Semiconductor 17
6.4 Package Dimensions - 196 MAPBGA
Figure 6 shows MCF5275 196 MAPBGA package dimensions.
Figure 6. 196 MAPBGA Package Dimensions
X
TOL
Laser mark for pin 1
identification in
this area
e13X
D
E
M
S
A1
A2
A
0.10 Z
0.20 Z
Z
Rotated 90° Clockwise
Detail K
5
View M-M
e13X
S
M
X0.15 YZ
0.08 Z
3
b196X
Metalized mark for
pin 1 identification
in this area
14 13 12 11 5 4 3 2
B
C
D
E
F
G
H
J
K
L
4
NOTES:
1. Dimensions are in millimeters.
2. Interpret dimensions and tolerances
per ASME Y14.5M, 1994.
3. Dimension b is measured at the
maximum solder ball diameter,
parallel to datum plane Z.
4. Datum Z (seating plane) is defined
by the spherical crowns of the solder
balls.
5. Parallelism measurement shall
exclude any effect of mark on top
surface of package.
Y
K
M
N
P
A
1610 9
DIM
Millimeters
Min Max
A1.25 1.60
A1 0.27 0.47
A2 1.16 REF
b0.45 0.55
D15.00 BSC
E15.00 BSC
e1.00 BSC
S0.50 BSC
196X
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 4
Ordering Information
Freescale Semiconductor18
7 Ordering Information
8 Electrical Characteristics
This appendix contains electrical specification tables and reference timing diagrams for the MCF5275
microcontroller unit. This section contains detailed information on power considerations, DC/AC
electrical characteristics, and AC timing specifications of MCF5275.
NOTE
The parameters specified in this appendix supersede any values found in the
module specifications.
8.1 Maximum Ratings
Table 6. Orderable Part Numbers
Freescale Part
Number Description Package Speed Temperature
MCF5274LVM166 MCF5274L RISC Microprocessor 196 MAPBGA 166 MHz 0° to +70° C
MCF5274LCVM166 -40° to +85° C
MCF5274VM166 MCF5274 RISC Microprocessor 256 MAPBGA 166 MHz 0° to +70° C
MCF5274CVM166 -40° to +85° C
MCF5275LCVM166 MCF5275L RISC Microprocessor 196 MAPBGA 166 MHz -40° to +85° C
MCF5275CVM166 MCF5275 RISC Microprocessor 256 MAPBGA 166 MHz -40° to +85° C
Table 7. Absolute Maximum Ratings1, 2
1Functional operating conditions are given in DC Electrical Specifications. Absolute Maximum Ratings
are stress ratings only, and functional operation at the maxima is not guaranteed. Stress beyond those
listed may affect device reliability or cause permanent damage to the device.
Rating Symbol Value Unit
Core Supply Voltage VDD – 0.5 to +2.0 V
I/O Pad Supply Voltage (3.3V) OVDD – 0.3 to +4.0 V
Memory Interface SSTL 2.5V Pad Supply Voltage SDVDD – 0.3 to + 2.8 V
Memory Interface SSTL 3.3V Pad Supply Voltage SDVDD – 0.3 to +4.0 V
PLL Supply Voltage VDDPLL – 0.3 to +4.0 V
Digital Input Voltage 3VIN – 0.3 to + 4.0 V
EXTAL pin voltage VEXTAL 0 to 3.3 V
XTAL pin voltage VXTAL 0 to 3.3 V
Instantaneous Maximum Current
Single pin limit (applies to all pins) 4, 5 ID25 mA
Operating Temperature Range (Packaged) TA
(TL - TH)
– 40 to 85 °C
Storage Temperature Range Tstg – 65 to 150 °C
Electrical Characteristics
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 4
Freescale Semiconductor 19
8.2 Thermal Characteristics
Table 8 lists thermal resistance values
2This device contains circuitry protecting against damage due to high static voltage or electrical fields;
however, it is advised that normal precautions be taken to avoid application of any voltages higher than
maximum-rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused
inputs are tied to an appropriate logic voltage level (e.g., VSS or O VDD).
3Input must be current limited to the value specified. To determine the value of the required
current-limiting resistor, calculate resistance values for positive and negative clamp voltages, then use
the larger of the two values.
4All functional non-supply pins are internally clamped to VSS and O VDD.
5Power supply must maintain regulation within operating O VDD range during instantaneous and
operating maximum current conditions. If positive injection current (Vin > O VDD) is greater than IDD, the
injection current may flow out of O VDD and could result in external power supply going out of
regulation. Ensure the external O VDD load shunts current greater than maximum injection current. This
is the greatest risk when the MCU is not consuming power (ex; no clock).Power supply must maintain
regulation within operating VDD range during instantaneous and operating maximum current conditions.
Table 8. Thermal characteristics
Characteristic Symbol 256MBGA 196MBGA Unit
Junction to ambient, natural convection Four layer board (2s2p) θJMA 261,2
1θJMA and Ψjt parameters are simulated in conformance with EIA/JESD Standard 51-2 for natural convection. Freescale
recommends the use of θJmA and power dissipation specifications in the system design to prevent device junction
temperatures from exceeding the rated specification. System designers should be aware that device junction temperatures
can be significantly influenced by board layout and surrounding devices. Conformance to the device junction temperature
specification can be verified by physical measurement in the customer’s system using the Ψjt parameter, the device power
dissipation, and the method described in EIA/JESD Standard 51-2.
2Per JEDEC JESD51-6 with the board horizontal.
321,2 °C / W
Junction to ambient (@200 ft/min) Four layer board (2s2p) θJMA 231,2 291,2 °C / W
Junction to board θJB 153
3Thermal resistance between the die and the printed circuit board in conformance with JEDEC JESD51-8. Board
temperature is measured on the top surface of the board near the package.
203°C / W
Junction to case θJC 104
4Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883
Method 1012.1).
104°C / W
Junction to top of package Natural convection Ψjt 21,5
5Thermal characterization parameter indicating the temperature difference between package top and the junction
temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter is written
in conformance with Psi-JT.
21,5 °C / W
Maximum operating junction temperature Tj105 105 oC
The average chip-junction temperature (TJ) in °C can be obtained from:
(1)
Where:
TA= Ambient Temperature, °C
ΘJMA = Package Thermal Resistance, Junction-to-Ambient, °C/W
PD= PINT + PI/O
TJTAPDΘJMA
×()+=
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 4
Electrical Characteristics
Freescale Semiconductor20
8.3 ESD Protection
PINT = IDD × VDD, Watts - Chip Internal Power
PI/O = Power Dissipation on Input and Output Pins — User Determined
For most applications PI/O < PINT and can be ignored. An approximate relationship between PD and TJ (if PI/O is
neglected) is:
(2)
Solving equations 1 and 2 for K gives:
K = PD × (TA + 273 °C) + ΘJMA × PD 2 (3)
where K is a constant pertaining to the particular part. K can be determined from equation (3) by measuring PD (at
equilibrium) for a known TA. Using this value of K, the values of PD and TJ can be obtained by solving equations (1)
and (2) iteratively for any value of TA.
Table 9. ESD Protection Characteristics1, 2
1All ESD testing is in conformity with CDF-AEC-Q100 Stress Test Qualification for Automotive
Grade Integrated Circuits.
2A device is defined as a failure if after exposure to ESD pulses the device no longer meets the
device specification requirements. Complete DC parametric and functional testing is
performed per applicable device specification at room temperature followed by hot
temperature, unless specified otherwise in the device specification.
Characteristics Symbol Value Units
ESD Target for Human Body Model HBM 2000 V
ESD Target for Machine Model MM 200 V
HBM Circuit Description Rseries 1500 Ω
C 100 pF
MM Circuit Description Rseries 0Ω
C 200 pF
Number of pulses per pin (HBM)
positive pulses
negative pulses
—
—
1
1
—
Number of pulses per pin (MM)
positive pulses
negative pulses
—
—
3
3
—
Interval of Pulses — 1 sec
PDKT
J273°C+()÷=
Electrical Characteristics
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 4
Freescale Semiconductor 21
8.4 DC Electrical Specifications
Table 10. DC Electrical Specifications1
Characteristic Symbol Min Max Unit
Core Supply Voltage VDD 1.4 1.6 V
I/O Pad Supply Voltage OVDD 3.0 3.6 V
PLL Supply Voltage VDDPLL 3.0 3.6 V
SSTL I/O Pad Supply Voltage SDVDD 2.3 2.7 V
SSTL I/O Pad Supply Voltage SDVDD 3.0 3.6 V
SSTL Memory pads reference voltage (SD VDD = 2.5V) VREF 0.5 SD VDD —2V
SSTL Memory pads reference voltage (SD VDD = 3.3V) VREF 0.45 SD VDD —2V
Input High Voltage 3.3V I/O Pads VIH 0.7 x OVDD OVDD + 0.3 V
Input Low Voltage 3.3V I/O Pads VIL VSS – 0.3 0.35 x OVDD V
Output High Voltage 3.3V I/O Pads
IOH = –2.0 mA
VOH OVDD - 0.5 — V
Output Low Voltage 3.3V I/O Pads
IOL = 2.0mA
VOL —0.5V
Input Hysteresis 3.3V I/O Pads VHYS 0.06 x VDD —mV
Input High Voltage SSTL 3.3V/2.5V3VIH VREF + 0.3 SDVDD + 0.3 V
Input Low Voltage SSTL 3.3V/2.5V3VIL VSS - 0.3 VREF - 0.3 V
Output High Voltage SSTL 3.3V/2.5V4
IOH = –5.0 mA
VOH SDVDD - 0.25V — V
Output Low Voltage SSTL 3.3V/2.5V4
IOL = 5.0 mA
VOL —0.35V
Input Leakage Current
Vin = VDD or VSS, Input-only pins
Iin -1.0 1.0 μA
High Impedance (Off-State) Leakage Current
Vin = VDD or VSS, All input/output and output pins
IOZ -1.0 1.0 μA
Weak Internal Pull Up Device Current, tested at VIL Max.5IAPU -10 -130 μA
Input Capacitance 6
All input-only pins
All input/output (three-state) pins
Cin
—
—
7
7
pF
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 4
Electrical Characteristics
Freescale Semiconductor22
Load Capacitance7
Low Drive Strength
High Drive Strength
CL—
—
25
50
pF
Core Operating Supply Current8
Master Mode
WAIT
DOZE
STOP
IDD
—
—
—
—
175
15
10
100
mA
mA
mA
μA
I/O Pad Operating Supply Current
Master Mode
Low Power Modes
OIDD
—
—
250
250
mA
μA
DC Injection Current 3, 9, 10, 11
VNEGCLAMP =VSS– 0.3 V, VPOSCLAMP = VDD + 0.3
Single Pin Limit
Total MCU Limit, Includes sum of all stressed pins
IIC
-1.0
-10
1.0
10
mA
1Refer to Table 11 for additional PLL specifications.
2VREF is specified as a nominal value only instead of a range, so no maximum value is listed.
3This specification is guaranteed by design and is not 100% tested.
4The actual VOH and VOL values for SSTL pads are dependent on the termination and drive strength used. The specifications
numbers assume no parallel termination.
5Refer to the MCF5274 signals chapter for pins having weak internal pull-up devices.
6This parameter is characterized before qualification rather than 100% tested.
7pF load ratings are based on DC loading and are provided as an indication of driver strength. High speed interfaces
require transmission line analysis to determine proper drive strength and termination.
8Current measured at maximum system clock frequency, all modules active, and default drive strength with matching load.
9All functional non-supply pins are internally clamped to VSS and their respective VDD.
10 Input must be current limited to the value specified. To determine the value of the required current-limiting resistor,
calculate resistance values for positive and negative clamp voltages, then use the larger of the two values.
11 Power supply must maintain regulation within operating VDD range during instantaneous and operating maximum current
conditions. If positive injection current (Vin > VDD) is greater than IDD, the injection current may flow out of VDD and could
result in external power supply going out of regulation. Ensure the external VDD load shunts current greater than
maximum injection current. This is the greatest risk when the MCU is not consuming power. Examples are: if no system
clock is present, or if clock rate is very low which would reduce overall power consumption. Also, at power-up, system
clock is not present during the power-up sequence until the PLL has attained lock.
Table 10. DC Electrical Specifications1 (continued)
Characteristic Symbol Min Max Unit
Electrical Characteristics
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 4
Freescale Semiconductor 23
8.5 Oscillator and Phase Lock Loop (PLLMRFM) Electrical
Specifications
Table 11. PLL Electrical Specifications1
1All values given are initial design targets and subject to change.
Characteristic Symbol Min Max Unit
PLL Reference Frequency Range
Crystal reference
External reference
1:1 Mode (NOTE: fsys/2 = 2 × fref_1:1)
fref_crystal
fref_ext
fref_1:1
8
8
24
25
25
83
MHz
Core frequency
CLKOUT Frequency 2
External reference
On-Chip PLL Frequency
2All internal registers retain data at 0 Hz.
fcore
fsys/2
0
fref / 32
166
83
83
MHz
MHz
MHz
Loss of Reference Frequency 3, 5
3“Loss of Reference Frequency” is the reference frequency detected internally, which transitions the PLL into self
clocked mode.
fLOR 100 1000 kHz
Self Clocked Mode Frequency 4, 5 fSCM TBD TBD MHz
Crystal Start-up Time 5, 6 tcst —10ms
EXTAL Input High Voltage
Crystal Mode
All other modes (Dual Controller (1:1), Bypass, External)
VIHEXT
VIHEXT TBD
TBD
TBD
TBD
V
EXTAL Input Low Voltage
Crystal Mode
All other modes (Dual Controller (1:1), Bypass, External)
VILEXT
VILEXT TBD
TBD
TBD
TBD
V
XTAL Output High Voltage
IOH = 1.0 mA
VOH
TBD —
V
XTAL Output Low Voltage
IOL = 1.0 mA
VOL
—TBD
V
XTAL Load Capacitance7530pF
PLL Lock Time 8tlpll — 750 μs
Power-up To Lock Time 6, 9
With Crystal Reference
Without Crystal Reference10
tlplk
—
—
11
750
ms
μs
1:1 Mode Clock Skew (between CLKOUT and EXTAL) 11 tskew -1 1 ns
Duty Cycle of reference 5 tdc 40 60 % fsys/2
Frequency un-LOCK Range fUL -3.8 4.1 % fsys/2
Frequency LOCK Range fLCK -1.7 2.0 % fsys/2
CLKOUT Period Jitter, 5, 6, 9,12, 13 Measured at fsys/2 Max
Peak-to-peak Jitter (Clock edge to clock edge)
Long Term Jitter (Averaged over 2 ms interval)
Cjitter
—
—
5
.01
% fsys/2
Frequency Modulation Range Limit14, 15
(fsys/2Max must not be exceeded)
Cmod 0.8 2.2 % fsys/2
ICO Frequency. fico = fref * 2 * (MFD+2)16 fico 48 83 MHz
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 4
Electrical Characteristics
Freescale Semiconductor24
8.6 External Interface Timing Characteristics
Table 12 lists processor bus input timings.
NOTE
All processor bus timings are synchronous; that is, input setup/hold and
output delay with respect to the rising edge of a reference clock. The
reference clock is the CLKOUT output.
All other timing relationships can be derived from these values.
4Self clocked mode frequency is the frequency that the PLL operates at when the reference frequency falls below
fLOR with default MFD/RFD settings.
5This parameter is guaranteed by characterization before qualification rather than 100% tested.
6Proper PC board layout procedures must be followed to achieve specifications.
7Load capacitance determined from crystal manufacturer specifications and includes circuit board parasitics.
8This specification applies to the period required for the PLL to relock after changing the MFD frequency control bits
in the synthesizer control register (SYNCR).
9Assuming a reference is available at power up, lock time is measured from the time VDD and VDDPLL are valid to
RSTOUT negating. If the crystal oscillator is being used as the reference for the PLL, then the crystal start up time
must be added to the PLL lock time to determine the total start-up time.
10 tlpll = (64 * 4 * 5 + 5 x τ) x Tref, where Tref = 1/Fref_crystal = 1/Fref_ext = 1/Fref_1:1, and τ = 1.57x10-6 x 2(MFD + 2)
11 PLL is operating in 1:1 PLL mode.
12 Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum
fsys/2. Measurements are made with the device powered by filtered supplies and clocked by a stable external clock
signal. Noise injected into the PLL circuitry via VDDPLL and VSSPLL and variation in crystal oscillator frequency
increase the jitter percentage for a given interval.
13 Based on slow system clock of 33MHz maximum frequency.
14 Modulation percentage applies over an interval of 10μs, or equivalently the modulation rate is 100KHz.
15 Modulation rate selected must not result in fsys/2 value greater than the fsys/2 maximum specified value. Modulation
range determined by hardware design.
16 fsys/2 = fico / (2 * 2RFD)
Table 12. Processor Bus Input Timing Specifications
Name Characteristic1
1Timing specifications have been indicated taking into account the full drive strength for the pads.
Symbol Min Max Unit
B0 CLKOUT tCYC 12 — ns
Control Inputs
B1a Control input valid to CLKOUT high2
2TEA and TA pins are being referred to as control inputs.
tCVCH 9—ns
B1b BKPT valid to CLKOUT high3
3 Refer to figure A-19.
tBKVCH 9—ns
B2a CLKOUT high to control inputs invalid2tCHCII 0—ns
B2b CLKOUT high to asynchronous control input BKPT invalid3tBKNCH 0—ns
Data Inputs
B4 Data input (D[31:16]) valid to CLKOUT high tDIVCH 4—ns
B5 CLKOUT high to data input (D[31:16]) invalid tCHDII 0—ns
Electrical Characteristics
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 4
Freescale Semiconductor 25
Timings listed in Table 12 are shown in Figure 7.
Figure 7. General Input Timing Requirements
8.7 Processor Bus Output Timing Specifications
Table 13 lists processor bus output timings.
Table 13. External Bus Output Timing Specifications
Name Characteristic Symbol Min Max Unit
Control Outputs
B6a CLKOUT high to chip selects (CS[7:0]) valid1tCHCV —0.5t
CYC + 5.5 ns
B6b CLKOUT high to byte enables (BS[3:2]) valid1tCHBV —0.5t
CYC + 5.5 ns
B6c CLKOUT high to output enable (OE) valid1tCHOV —0.5t
CYC + 5.5 ns
B7 CLKOUT high to control output (BS[3:2], OE) invalid tCHCOI 0.5tCYC + 1.0 — ns
B7a CLKOUT high to chip selects invalid tCHCI 0.5tCYC + 1.0 — ns
Address and Attribute Outputs
B8 CLKOUT high to address (A[23:0]) and control (TS,
TSIZ[1:0], TIP
, R/W) valid
tCHAV —9ns
B9 CLKOUT high to address (A[23:0]) and control (TS,
TSIZ[1:0], TIP
, R/W) invalid
tCHAI 1.0 — ns
Invalid Invalid
CLKOUT (83MHz)
TSETUP THOLD
Input Setup And Hold
trise
Vh = VIH
Vl = VIL
Valid
tfall
Vh = VIH
Vl = VIL
Input Rise Time
Input Fall Time
* The timings are also valid for inputs sampled on the negative clock edge.
Inputs
CLKOUT B4
B5
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 4
Electrical Characteristics
Freescale Semiconductor26
Read/write bus timings listed in Table 13 are shown in Figure 8, Figure 9, and Figure 10.
Figure 8. Read/Write (Internally Terminated) SRAM Bus Timing
Data Outputs
B11 CLKOUT high to data output (D[31:16]) valid tCHDOV —9ns
B12 CLKOUT high to data output (D[31:16]) invalid tCHDOI 1.0 — ns
B13 CLKOUT high to data output (D[31:16]) high impedance tCHDOZ —9ns
1CS, BS, and OE transition after the falling edge of CLKOUT.
Table 13. External Bus Output Timing Specifications (continued)
Name Characteristic Symbol Min Max Unit
CLKOUT
CSn
A[23:0]
R/W
BS[3:2]
D[31:16]
TA
(H)
(H)
S0
S2 S3
S1 S4 S5 S0 S1 S2 S3 S4 S5
TEA (H)
B6a
B8
B7a
B6c B7
B6b
B7
B4
B5
B11 B12
B9
B9
B8
B6b
B13
OE
B0
B7
B9
TS
TIP
B8
B8
B9
B8
B9
TSIZ[1:0]
B7a
B6a
B8
Electrical Characteristics
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 4
Freescale Semiconductor 27
Figure 9 shows a bus cycle terminated by TA showing timings listed in Table 13.
Figure 9. SRAM Read Bus Cycle Terminated by TA
CLKOUT
CSn
A[23:0]
OE
R/W
BS[3:2]
TA
(H)
S0 S2 S3
S1 S4 S5 S0 S1
TEA
(H)
B6a
B8
B7a
B9
B6c
B7
B6b B7
B2a
B1a
D[31:16]
B4
B5
B8
B9
TS
B9
TIP
B8
TSIZ[1:0]
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 4
Electrical Characteristics
Freescale Semiconductor28
Figure 10 shows an SRAM bus cycle terminated by TEA showing timings listed in Table 13.
Figure 10. SRAM Read Bus Cycle Terminated by TEA
CLKOUT
CSn
A[23:0]
OE
R/W
BS[3:2]
TEA
(H)
S0
S2 S3
S1 S4 S5 S0 S1
TA
(H)
B6a
B8
B7a
B9
B6c
B7
B6b B7
B2a
B1a
D[31:16]
B8
B9
TS
B9
TIP
B8
TSIZ[1:0]
Electrical Characteristics
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 4
Freescale Semiconductor 29
8.8 DDR SDRAM AC Timing Characteristics
The DDR SDRAM controller uses SSTL2 and I/O drivers. Class I or Class II drive strength is available
and is user programmable. DDR Clock timing specifications are given in Table 14 and Figure 11.
Figure 11. DDR Clock Timing Diagram
When using the DDR SDRAM controller the timing numbers in Table 15 must be followed to properly
latch or drive data onto the memory bus. All timing numbers are relative to the two DQS byte lanes.
Table 14. DDR Clock Timing Specifications1
1SD VDD is nominally 2.5V.
Symbol Characteristic Min Max Unit
VMP Clock output mid-point voltage 1.05 1.45 V
VOUT Clock output voltage level -0.3 SDVDD + 0.3 V
VID Clock output differential voltage (peak to peak swing) 0.7 SDVDD + 0.6 V
VIX Clock crossing point voltage 1.05 1.45 V
Table 15. DDR Timing
NUM Characteristic1Symbol Min Max Unit
Frequency of operation2TBD 83 MHz
DD1 Clock Period (DDR_CLKOUT) tCK 12 TBD ns
DD2 Pulse Width High3tCKH 0.45 0.55 tCK
DD3 Pulse Width Low3tCKl 0.45 0.55 tCK
DD4 DDR_CLKOUT high to DDR address, SD_CKE,
SD_CS[1:0], SD_SCAS, SD_SRAS, SD_WE valid
tCMV — 0.5 x tCK + 1 ns
DD5 DDR_CLKOUT high to DDR address, SD_CKE, SD_CS,
SD_SCAS, SD_SRAS, SD_WE invalid
tCMH 2—ns
DD6 Write command to first SD_DQS Latching Transition tDQSS —1.25t
CK
DD7 SD_DQS high to Data and DM valid (write) - setup4,5 tQS 1.5 — ns
DD8 SD_DQS high to Data and DM invalid (write) - hold4tQH 1—ns
DD9 SD_DQS high to Data valid (read) - setup6tIS —1ns
DD10 SD_DQS high to Data invalid (read) - hold7tIH 0.25 x tCK + 1 — ns
DD11 SD_DQS falling edge to CLKOUT high - setup tDSS 0.5 — ns
DD12 SD_DQS falling edge to CLKOUT high - hold tDSH 0.5 — ns
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 4
Electrical Characteristics
Freescale Semiconductor30
Figure 13 shows a DDR SDRAM write cycle.
Figure 12. DDR_CLKOUT and DDR_CLKOUT Crossover Timing
DD13 DQS input read preamble width (tRPRE)t
RPRE 0.9 1.1 tCK
DD14 DQS input read postamble width (tRPST)t
RPST 0.4 0.6 tCK
DD15 DQS output write preamble width (tWPRE)t
WPRE 0.25 — tCK
DD16 DQS output write postamble width (tWPST)t
WPST 0.4 0.6 tCK
1All timing specifications are based on taking into account, a 25pF load on the SDRAM output pins.
2DDR_CLKOUT operates at half the frequency of the PLLMRFM output and the ColdFire core.
3tCKH + tCKL must be less than or equal to tCK.
4D[31:24] is relative to SD_DQS3 and D[23:16] is relative to SD_DQS2.
5The first data beat is valid before the first rising edge of SD_DQS and after the SD_DQS write preamble. The remaining
data beats are valid for each subsequent SD_DQS edge
6Data input skew is derived from each SD_DQS clock edge. It begins with a SD_DQS transition and ends when the last data
line becomes valid. This input skew must include DDR memory output skew and system level board skew (due to routing or
other factors).
7Data input hold is derived from each SD_DQS clock edge. It begins with a SD_DQS transition and ends when the first data
line becomes invalid.
Table 15. DDR Timing (continued)
NUM Characteristic1Symbol Min Max Unit
DDR_CLKOUT
DDR_CLKOUT
VIX
VMP
VIX
VID
Electrical Characteristics
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 4
Freescale Semiconductor 31
Figure 13. DDR Write Timing
DDR_CLKOUT
SD_CSn,SD_WE,
DM[3:2]
D[31:16]
A[13:0]
SD_SRAS,SD_SCAS CMD
ROW
DD1
DD5
DD4
COL
WD1 WD2 WD3 WD4
DD7
SD_DQS[3:2]
DD8
DD8
DD7
DDR_CLKOUT
DD3
DD2
DD6
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 4
Electrical Characteristics
Freescale Semiconductor32
Figure 14. DDR Read Timing
8.9 General Purpose I/O Timing
GPIO can be configured for certain pins of the QSPI, DDR control, timers, UARTS, FEC0, FEC1,
Interrupts and USB interfaces. When in GPIO mode the timing specification for these pins is given in
Table 16 and Figure 15.
Table 16. GPIO Timing
NUM Characteristic Symbol Min Max Unit
G1 CLKOUT High to GPIO Output Valid tCHPOV —10ns
G2 CLKOUT High to GPIO Output Invalid tCHPOI 1.0 — ns
G3 GPIO Input Valid to CLKOUT High tPVCH 9—ns
G4 CLKOUT High to GPIO Input Invalid tCHPI 1.5 — ns
CLKOUT
SD_CSn,SD_WE,
SD_DQS[3:2]
D[31:16]
A[13:0]
SD_SRAS,SD_SCAS CMD
ROW
DD1
DD5
DD4
WD1 WD2 WD3 WD4
SD_DQS[3:2]
DD9
CLKOUT
DD3
DD2
D[31:16]
WD1 WD2 WD3 WD4
DD10
CL=2
CL=2.5
COL
DQS Read
Preamble
DQS Read
Postamble
DQS Read
Preamble
DQS Read
Postamble
CL = 2.5 CL = 2
Electrical Characteristics
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 4
Freescale Semiconductor 33
Figure 15. GPIO Timing
8.10 Reset and Configuration Override Timing
RESET and Configuration Override Timing
Table 17. Reset and Configuration Override Timing
(VDD = 2.7 to 3.6 V, VSS = 0 V, TA = TL to TH)1
1All AC timing is shown with respect to 50% OVDD levels unless otherwise noted.
NUM Characteristic Symbol Min Max Unit
R1 RESET Input valid to CLKOUT High tRVCH 9—ns
R2 CLKOUT High to RESET Input invalid tCHRI 1.5 — ns
R3 RESET Input valid Time 2
2During low power STOP, the synchronizers for the RESET input are bypassed and RESET is asserted
asynchronously to the system. Thus, RESET must be held a minimum of 100 ns.
tRIVT 5—t
CYC
R4 CLKOUT High to RSTOUT Valid tCHROV —10ns
R5 RSTOUT valid to Config. Overrides valid tROVCV 0—ns
R6 Configuration Override Setup Time to RSTOUT invalid tCOS 20 — tCYC
R7 Configuration Override Hold Time after RSTOUT invalid tCOH 0—ns
R8 RSTOUT invalid to Configuration Override High Impedance tROICZ — 1 x tCYC ns
G1
CLKOUT
GPIO Outputs
G2
G3 G4
GPIO Inputs
R1 R2
CLKOUT
RESET
RSTOUT
R3
R4
R8
R7R6R5
Configuration Overrides1:
R4
(RCON, Override pins])
1. Refer to the Coldfire Integration Module (CIM) section for more information.
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 4
Electrical Characteristics
Freescale Semiconductor34
8.11 Fast Ethernet AC Timing Specifications
MII signals use TTL signal levels compatible with devices operating at 5.0 V or 3.3 V.
8.11.1 MII Receive Signal Timing (FECn_RXD[3:0], FECn_RXDV,
FECn_RXER, and FECn_RXCLK)
The receiver functions correctly up to a FECn_RXCLK maximum frequency of 25 MHz +1%. The
processor clock frequency must exceed twice the FECn_RXCLK frequency.
Table 18 lists MII receive channel timings.
Figure 16 shows MII receive signal timings listed in Table 18.
Figure 16. MII Receive Signal Timing Diagram
8.11.2 MII Transmit Signal Timing (FECn_TXD[3:0], FECn_TXEN,
FECn_TXER, FECn_TXCLK)
Table 19 lists MII transmit channel timings.
The transmitter functions correctly up to a FECn_TXCLK maximum frequency of 25 MHz +1%. The
processor clock frequency must exceed twice the FECn_TXCLK frequency.
Table 18. MII Receive Signal Timing
Num Characteristic Min Max Unit
M1 FECn_RXD[3:0], FECn_RXDV, FECn_RXER to FECn_RXCLK
setup
5— ns
M2 FECn_RXCLK to FECn_RXD[3:0], FECn_RXDV, FECn_RXER
hold
5— ns
M3 FECn_RXCLK pulse width high 35% 65% FECn_RXCLK
period
M4 FECn_RXCLK pulse width low 35% 65% FECn_RXCLK
period
M1 M2
FECn_RXCLK (input)
FECn_RXD[3:0] (inputs)
FECn_RXDV
FECn_RXER
M3 M4
Electrical Characteristics
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 4
Freescale Semiconductor 35
Figure 17 shows MII transmit signal timings listed in Table 19.
Figure 17. MII Transmit Signal Timing Diagram
8.11.3 MII Async Inputs Signal Timing (FECn_CRS and FECn_COL)
Table 20 lists MII asynchronous inputs signal timing.
Figure 18 shows MII asynchronous input timings listed in Table 20.
Figure 18. MII Async Inputs Timing Diagram
Table 19. MII Transmit Channel Timing
Num Characteristic Min Max Unit
M5 FECn_TXCLK to FECn_TXD[3:0], FECn_TXEN, FECn_TXER
invalid
5— ns
M6 FECn_TXCLK to FECn_TXD[3:0], FECn_TXEN, FECn_TXER
valid
—25 ns
M7 FECn_TXCLK pulse width high 35% 65% FECn_TXCLK period
M8 FECn_TXCLK pulse width low 35% 65% FECn_TXCLK period
Table 20. MII Asynchronous Input Signal Timing
Num Characteristic Min Max Unit
M9 FECn_CRS, FECn_COL minimum pulse width 1.5 — FECn_TXCLK period
M6
FECn_TXCLK (input)
FECn_TXD[3:0] (outputs)
FECn_TXEN
FECn_TXER
M5
M7 M8
FECn_CRS
M9
FECn_COL
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 4
Electrical Characteristics
Freescale Semiconductor36
8.11.4 MII Serial Management Channel Timing (FECn_MDIO and
FECn_MDC)
Table 21 lists MII serial management channel timings. The FEC functions correctly with a maximum
MDC frequency of 2.5 MHz.
Figure 19 shows MII serial management channel timings listed in Table 21.
Figure 19. MII Serial Management Channel Timing Diagram
Table 21. MII Serial Management Channel Timing
Num Characteristic Min Max Unit
M10 FECn_MDC falling edge to FECn_MDIO output invalid (minimum
propagation delay)
0— ns
M11 FECn_MDC falling edge to FECn_MDIO output valid (max prop delay) — 25 ns
M12 FECn_MDIO (input) to FECn_MDC rising edge setup 10 — ns
M13 FECn_MDIO (input) to FECn_MDC rising edge hold 0 — ns
M14 FECn_MDC pulse width high 40% 60% MDC period
M15 FECn_MDC pulse width low 40% 60% MDC period
M11
FECn_MDC (output)
FECn_MDIO (output)
M12 M13
FECn_MDIO (input)
M10
M14
M15
Electrical Characteristics
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 4
Freescale Semiconductor 37
8.11.5 USB Interface AC Timing Specifications
Table 22 lists USB Interface timings.
Figure 20 shows USB interface timings listed in Table 22.
Figure 20. USB Signals Timing Diagram
Table 22. USB Interface Timing
Num Characteristic Min Max Units
US1 USB_CLK frequency of operation 48 48 MHz
US2 USB_CLK fall time (VIH = 2.4 V to VIL = 0.5 V) — 2 ns
US3 USB_CLK rise time (VIL = 0.5 V to VIH = 2.4 V) — 2 ns
US4 USB_CLK duty cycle (at 0.5 x O VDD)4555%
Data Inputs
US5 USB_RP, USB_RN, USB_RXD valid to USB_CLK high 6 — ns
US6 USB_CLK high to USB_RP, USB_RN, USB_RXD invalid 6 — ns
Data Outputs
US7 USB_CLK high to USB_TP, USB_TN, USB_SUSP valid — 12 ns
US8 USB_CLK high to USB_TP, USB_TN, USB_SUSP invalid 3 — ns
US7
USB_CLK
USB Outputs
US8
US5 US6
USB Inputs
trise
Vh = VIH
Vl = VIL
tfall
Vh = VIH
Vl = VIL
Input Rise Time
Input Fall Time
US1
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 4
Electrical Characteristics
Freescale Semiconductor38
8.12 I2C Input/Output Timing Specifications
Table 23 lists specifications for the I2C input timing parameters shown in Figure 21.
Table 24 lists specifications for the I2C output timing parameters shown in Figure 21.
Table 23. I2C Input Timing Specifications between I2C_SCL and I2C_SDA
Num Characteristic Min Max Units
I1 Start condition hold time 2 x tCYC —ns
I2 Clock low period 8 x tCYC —ns
I3 I2C_SCL/I2C_SDA rise time (VIL = 0.5 V to VIH = 2.4 V) — 1 ms
I4 Data hold time 0 — ns
I5 I2C_SCL/I2C_SDA fall time (VIH = 2.4 V to VIL = 0.5 V) — 1 ms
I6 Clock high time 4 x tCYC —ns
I7 Data setup time 0 — ns
I8 Start condition setup time (for repeated start condition only) 2 x tCYC —ns
I9 Stop condition setup time 2 x tCYC —ns
Table 24. I2C Output Timing Specifications between I2C_SCL and I2C_SDA
Num Characteristic Min Max Units
I11
1Output numbers depend on the value programmed into the IFDR; an IFDR programmed with the
maximum frequency (IFDR = 0x20) results in minimum output timings as shown in Ta b l e 2 4 . The
I2C interface is designed to scale the actual data transition time to move it to the middle of the
I2C_SCL low period. The actual position is affected by the prescale and division values
programmed into the IFDR; however, the numbers given in Ta b l e 2 4 are minimum values.
Start condition hold time 6 x tCYC —ns
I2 1Clock low period 10 x tCYC —ns
I3 2
2Because I2C_SCL and I2C_SDA are open-collector-type outputs, which the processor can only
actively drive low, the time I2C_SCL or I2C_SDA take to reach a high level depends on external
signal capacitance and pull-up resistor values.
I2C_SCL/I2C_SDA rise time
(VIL = 0.5 V to VIH = 2.4 V)
——µs
I4 1Data hold time 7 x tCYC —ns
I5 3
3Specified at a nominal 50-pF load.
I2C_SCL/I2C_SDA fall time
(VIH = 2.4 V to VIL = 0.5 V)
—3ns
I6 1Clock high time 10 x tCYC —ns
I7 1Data setup time 2 x tCYC —ns
I8 1Start condition setup time (for repeated start
condition only)
20 x tCYC —ns
I9 1Stop condition setup time 10 x tCYC —ns
Electrical Characteristics
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 4
Freescale Semiconductor 39
Figure 21 shows timing for the values in Table 23 and Table 24.
Figure 21. I2C Input/Output Timings
8.13 DMA Timers Timing Specifications
8.14 QSPI Electrical Specifications
Table 25. Timer Module AC Timing Specifications
Name Characteristic 1
1All timing references to CLKOUT are given to its rising edge.
Min Max Unit
T1 T0IN / T1IN / T2IN / T3IN cycle time 3 x tCYC —ns
T2 T0IN / T1IN / T2IN / T3IN pulse width 1 x tCYC —ns
Table 26. QSPI Modules AC Timing Specifications
Name Characteristic Min Max Unit
QS1 QSPI_CS[3:0] to QSPI_CLK 1 510 tCYC
QS2 QSPI_CLK high to QSPI_DOUT valid. — 10 ns
QS3 QSPI_CLK high to QSPI_DOUT invalid (Output hold) 2 — ns
QS4 QSPI_DIN to QSPI_CLK (Input setup) 9 — ns
QS5 QSPI_DIN to QSPI_CLK (Input hold) 9 — ns
I2 I6
I1 I4
I7
I8 I9
I5
I3
SCL
SDA
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 4
Electrical Characteristics
Freescale Semiconductor40
Figure 22. QSPI Timing
8.15 JTAG and Boundary Scan Timing
Table 27. JTAG and Boundary Scan Timing
Num Characteristics1
1JTAG_EN is expected to be a static signal. Hence, it is not associated with any timing.
Symbol Min Max Unit
J1 TCLK Frequency of Operation fJCYC DC 1/4 fsys/2
J2 TCLK Cycle Period tJCYC 4 x tCYC —ns
J3 TCLK Clock Pulse Width tJCW 26 — ns
J4 TCLK Rise and Fall Times tJCRF 03ns
J5 Boundary Scan Input Data Setup Time to TCLK Rise tBSDST 4—ns
J6 Boundary Scan Input Data Hold Time after TCLK Rise tBSDHT 26 — ns
J7 TCLK Low to Boundary Scan Output Data Valid tBSDV 033ns
J8 TCLK Low to Boundary Scan Output High Z tBSDZ 033ns
J9 TMS, TDI Input Data Setup Time to TCLK Rise tTAPBST 4—ns
J10 TMS, TDI Input Data Hold Time after TCLK Rise tTAPBHT 10 — ns
J11 TCLK Low to TDO Data Valid tTDODV 026ns
J12 TCLK Low to TDO High Z tTDODZ 08ns
J13 TRST Assert Time tTRSTAT 100 — ns
J14 TRST Setup Time (Negation) to TCLK High tTRSTST 10 — ns
QSPI_CS[3:0]
QSPI_CLK
QSPI_DOUT
QS5
QS1
QSPI_DIN
QS3 QS4
QS2
Electrical Characteristics
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 4
Freescale Semiconductor 41
Figure 23. Test Clock Input Timing
Figure 24. Boundary Scan (JTAG) Timing
Figure 25. Test Access Port Timing
Figure 26. TRST Timing
TCLK
VIL
VIH
J3 J3
J4 J4
J2
(input)
Input Data Valid
Output Data Valid
Output Data Valid
TCLK
Data Inputs
Data Outputs
Data Outputs
Data Outputs
VIL VIH
J5 J6
J7
J8
J7
Input Data Valid
Output Data Valid
Output Data Valid
TCLK
TDI
TDO
TDO
TDO
TMS
VIL VIH
J9 J10
J11
J12
J11
TCLK
TRST
14
13
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 4
Electrical Characteristics
Freescale Semiconductor42
8.16 Debug AC Timing Specifications
Table 28 lists specifications for the debug AC timing parameters shown in Figure 28.
Figure 27 shows real-time trace timing for the values in Table 28.
Figure 27. Real-Time Trace AC Timing
Figure 28 shows BDM serial port AC timing for the values in Table 28.
Figure 28. BDM Serial Port AC Timing
Table 28. Debug AC Timing Specification
Num Characteristic
166 MHz
Units
Min Max
D0 PSTCLK cycle time — 0.5 tCYC
D1 PST, DDATA to PSTCLK setup 4 — ns
D2 CLKOUT to PST, DDATA hold 1.0 — ns
D3 DSI-to-DSCLK setup 1 x tCYC —ns
D4 1
1DSCLK and DSI are synchronized internally. D4 is measured from the synchronized DSCLK input
relative to the rising edge of PSTCLK.
DSCLK-to-DSO hold 4 x tCYC —ns
D5 DSCLK cycle time 5 x tCYC —ns
D6 BKPT input data setup time to PSTCLK Rise 4 — ns
D7 BKPT input data hold time to PSTCLK Rise 1.5 — ns
D8 PSTCLK high to BKPT high Z 0.0 10.0 ns
PSTCLK
PST[3:0]
D2D1
DDATA[3:0]
DSI
DSO
Current Next
PSTCLK
Past Current
DSCLK
D3
D4
D5
Documentation
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 4
Freescale Semiconductor 43
9 Documentation
Documentation regarding the MCF5275 and their development support tools is available from a local
Freescale distributor, a Freescale semiconductor sales office, the Freescale Literature Distribution Center,
or through the Freescale web address at http://www.freescale.com/coldfire.
10 Revision History
Table 29 provides a revision history for this hardware specification.
Table 29. Document Revision History
Rev. No. Substantive Change(s)
0 Initial release.
1 Added Figure 6.
1.1 Removed duplicate information in the module description sections. The information is all in the Signals
Description Table.
1.2 Removed Overview, Features, Signal Descriptions, Modes of Operation, and Address Multiplexing sections. This
information can be found in the MCF5275 Reference Manual.
Removed list of documentation in Section 9, “Documentation.”. An up-to-date list is always available on our web
site.
Changed CLKOUT -> PSTCLK in Section 8.16, “Debug AC Timing Specifications.”
Ta bl e 1 0 : Update VDD spec from 1.35-1.65 to 1.4-1.6.
Ta bl e 1 3 : Timings B6a, B6b, B6c, B7, B7a, B9, B12 updated:
B6a, B6b, B6c maximum changed from “0.5tCYC + 5” to “0.5tCYC +5.5”
B7, B7a minimum changed from “0.5tCYC + 1.5” to “0.5tCYC +1.0”
B9, B11 minimum changed from “1.5” to “1.0”
1.3 Added Section 5.2.1, “Supply Voltage Sequencing and Separation Cautions.”
Added thermal characteristics for 196 MAPBGA in Ta bl e 8 .
Updated package dimensions drawing, Figure 6.
2 Removed second sentence from Section 8.11.1, “MII Receive Signal Timing (FECn_RXD[3:0], FECn_RXDV,
FECn_RXER, and FECn_RXCLK),” and Section 8.11.2, “MII Transmit Signal Timing (FECn_TXD[3:0],
FECn_TXEN, FECn_TXER, FECn_TXCLK),” regarding no minimum frequency requirement for TXCLK.
Removed third and fourth paragraphs from Section 8.11.2, “MII Transmit Signal Timing (FECn_TXD[3:0],
FECn_TXEN, FECn_TXER, FECn_TXCLK),” as this feature is not supported on this device.
3 Corrected Ordering Information, Ta b l e 6 .
Figure 2: Moved PLLVDD from 1.5V to 3.3V supply line and corrected relevant text in sections below table.
Ta bl e 1 0 : Corrected maximum “Input High Voltage 3.3V I/O Pads”, VIH specification.
4Ta bl e 1 0 , added PLL supply voltage row
Document Number: MCF5275EC
Rev. 4
02/2009
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