To our customers, Old Company Name in Catalogs and Other Documents On April 1st, 2010, NEC Electronics Corporation merged with Renesas Technology Corporation, and Renesas Electronics Corporation took over all the business of both companies. Therefore, although the old company name remains in this document, it is a valid Renesas Electronics document. We appreciate your understanding. Renesas Electronics website: http://www.renesas.com April 1st, 2010 Renesas Electronics Corporation Issued by: Renesas Electronics Corporation (http://www.renesas.com) Send any inquiries to http://www.renesas.com/inquiry. Notice 1. 2. 3. 4. 5. 6. 7. All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please confirm the latest product information with a Renesas Electronics sales office. Also, please pay regular and careful attention to additional and different information to be disclosed by Renesas Electronics such as that disclosed through our website. Renesas Electronics does not assume any liability for infringement of patents, copyrights, or other intellectual property rights of third parties by or arising from the use of Renesas Electronics products or technical information described in this document. No license, express, implied or otherwise, is granted hereby under any patents, copyrights or other intellectual property rights of Renesas Electronics or others. You should not alter, modify, copy, or otherwise misappropriate any Renesas Electronics product, whether in whole or in part. Descriptions of circuits, software and other related information in this document are provided only to illustrate the operation of semiconductor products and application examples. You are fully responsible for the incorporation of these circuits, software, and information in the design of your equipment. Renesas Electronics assumes no responsibility for any losses incurred by you or third parties arising from the use of these circuits, software, or information. When exporting the products or technology described in this document, you should comply with the applicable export control laws and regulations and follow the procedures required by such laws and regulations. You should not use Renesas Electronics products or the technology described in this document for any purpose relating to military applications or use by the military, including but not limited to the development of weapons of mass destruction. Renesas Electronics products and technology may not be used for or incorporated into any products or systems whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. Renesas Electronics has used reasonable care in preparing the information included in this document, but Renesas Electronics does not warrant that such information is error free. Renesas Electronics assumes no liability whatsoever for any damages incurred by you resulting from errors in or omissions from the information included herein. Renesas Electronics products are classified according to the following three quality grades: "Standard", "High Quality", and "Specific". The recommended applications for each Renesas Electronics product depends on the product's quality grade, as indicated below. You must check the quality grade of each Renesas Electronics product before using it in a particular application. You may not use any Renesas Electronics product for any application categorized as "Specific" without the prior written consent of Renesas Electronics. Further, you may not use any Renesas Electronics product for any application for which it is not intended without the prior written consent of Renesas Electronics. Renesas Electronics shall not be in any way liable for any damages or losses incurred by you or third parties arising from the use of any Renesas Electronics product for an application categorized as "Specific" or for which the product is not intended where you have failed to obtain the prior written consent of Renesas Electronics. The quality grade of each Renesas Electronics product is "Standard" unless otherwise expressly specified in a Renesas Electronics data sheets or data books, etc. "Standard": 8. 9. 10. 11. 12. Computers; office equipment; communications equipment; test and measurement equipment; audio and visual equipment; home electronic appliances; machine tools; personal electronic equipment; and industrial robots. "High Quality": Transportation equipment (automobiles, trains, ships, etc.); traffic control systems; anti-disaster systems; anticrime systems; safety equipment; and medical equipment not specifically designed for life support. "Specific": Aircraft; aerospace equipment; submersible repeaters; nuclear reactor control systems; medical equipment or systems for life support (e.g. artificial life support devices or systems), surgical implantations, or healthcare intervention (e.g. excision, etc.), and any other applications or purposes that pose a direct threat to human life. You should use the Renesas Electronics products described in this document within the range specified by Renesas Electronics, especially with respect to the maximum rating, operating supply voltage range, movement power voltage range, heat radiation characteristics, installation and other product characteristics. Renesas Electronics shall have no liability for malfunctions or damages arising out of the use of Renesas Electronics products beyond such specified ranges. Although Renesas Electronics endeavors to improve the quality and reliability of its products, semiconductor products have specific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use conditions. Further, Renesas Electronics products are not subject to radiation resistance design. Please be sure to implement safety measures to guard them against the possibility of physical injury, and injury or damage caused by fire in the event of the failure of a Renesas Electronics product, such as safety design for hardware and software including but not limited to redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other appropriate measures. Because the evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or system manufactured by you. Please contact a Renesas Electronics sales office for details as to environmental matters such as the environmental compatibility of each Renesas Electronics product. Please use Renesas Electronics products in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances, including without limitation, the EU RoHS Directive. Renesas Electronics assumes no liability for damages or losses occurring as a result of your noncompliance with applicable laws and regulations. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior written consent of Renesas Electronics. Please contact a Renesas Electronics sales office if you have any questions regarding the information contained in this document or Renesas Electronics products, or if you have any other inquiries. (Note 1) "Renesas Electronics" as used in this document means Renesas Electronics Corporation and also includes its majorityowned subsidiaries. (Note 2) "Renesas Electronics product(s)" means any product developed or manufactured by or for Renesas Electronics. PRELIMINARY DATA SHEET MOS INTEGRATED CIRCUIT PD78F0034Y 8-BIT SINGLE-CHIP MICROCONTROLLER DESCRIPTION The PD78F0034Y is a product of the PD780034Y Subseries in the 78K/0 Series and equivalent to the PD780034Y with a flash memory in place of internal ROM. The PD78F0034Y incorporates a flash memory, which can be programmed and erased without being removed from the substrate. Functions are described in detail in the following user's manuals. Be sure to read them before designing. PD780024, 780024Y, 780034, 780034Y Subseries User's Manual : U12022E 78K/0 Series User's Manual -- Instructions : U12326E FEATURES * I2C bus serial interface supporting multimaster * Pin-compatible with mask ROM versions (except VPP pin) * Flash memory : 32 Kbytes * Internal high-speed RAM : 1024 bytesNote * Power supply voltage : VDD = 2.7 to 5.5 V Note The flash memory and internal high-speed RAM capacities can be changed with the memory size switching register (IMS). Remark For the differences between the flash memory versions and the mask ROM versions, refer to 1. DIFFERENCES BETWEEN PD78F0034Y AND MASK ROM VERSIONS. ORDERING INFORMATION Part Number Package Internal ROM PD78F0034YCW 64-pin plastic shrink DIP (750 mils) Flash memory PD78F0034YGC-AB8 64-pin plastic QFP (14 x 14 mm) Flash memory PD78F0034YGK-8A8 64-pin plastic LQFP (12 x 12 mm) Flash memory The information in this document is subject to change without notice. Document No. U11994EJ1V0DS00 (1st edition) Date Published March 1998 N CP (K) Printed in Japan The mark shows major revised points. (c) 1997 PD78F0034Y 78K/0 SERIES DEVELOPMENT The products in the 78K/0 Series are listed below. The names enclosed in boxes are subseries names. Products in mass production Products under development Y subseries products are compatible with I2C bus. Control 100-pin PD78075B 100-pin PD78078 PD78078Y Timer was added to the PD78054, and external interface function was enhanced 100-pin PD78070A PD78070AY ROM-less versions of the PD78078 80-pin PD780058 PD780018AY PD780058YNote 80-pin 80-pin PD78058F PD78054 PD78058FY PD78054Y EMI-noise reduced version of the PD78054 UART and D/A converter were added to the PD78014, and I/O was enhanced 64-pin PD780034 PD780034Y A/D converter of the PD780024 was enhanced 64-pin 64-pin PD780024 PD78014H PD780024Y 100-pin 78K/0 Series EMI-noise reduced version of the PD78078 Serial I/O of the PD78078Y was enhanced, and only selected functions are provided Serial I/O of the PD78054 was enhanced, EMI-noise reduced version Serial I/O of the PD78018F was enhanced EMI-noise reduced version of the PD78018F 64-pin PD78018F PD78018FY Low-voltage (1.8 V) operation versions of the PD78014 with several ROM and RAM capacities available 64-pin 64-pin PD78014 PD780001 PD78014Y A/D converter and 16-bit timer were added to the PD78002 A/D converter was added to the PD78002 64-pin PD78002 PD78002Y Basic subseries for control 42/44-pin PD78083 On-chip UART, capable of operating at a low voltage (1.8 V) 64-pin Inverter control PD780988 64-pin PD780964 A/D converter of the PD780924 was enhanced 64-pin PD780924 On-chip inverter control circuit and UART, EMI-noise reduced version Inverter control, timer, and SIO of the PD780964 were enhanced, and ROM and RAM capacities were expanded. FIPTM drive 100-pin PD780208 I/O and FIP C/D of the PD78044F were enhanced, Display output total: 53 100-pin PD780228 I/O and FIP C/D of the PD78044H were enhanced, Display output total: 48 80-pin PD78044H N-ch open-drain input/output was added to the PD78044F, Display output total: 34 80-pin PD78044F Basic subseries for driving FIP, Display output total: 34 LCD drive 100-pin PD780308 100-pin PD78064B 100-pin PD78064 PD780308Y SIO of the PD78064 was enhanced, and ROM and RAM capacities were expanded EMI-noise reduced version of the PD78064 PD78064Y Basic subseries for driving LCDs, On-chip UART IEBusTM supported 80-pin PD78098B EMI-noise reduced version of the PD78098 80-pin PD78098 IEBus controller was added to the PD78054 Meter control 80-pin PD780973 On-chip automobile meter drive controller/driver Note Under planning 2 Preliminary Data Sheet PD78F0034Y The major functional differences among the Y subseries are shown below. Function Subseries Name Control PD78078Y ROM Capacity 48 K to 60 K 3-wire/2-wire/I2C : 1 ch 3-wire with automatic transmit/receive function : 1 ch I/O VDD MIN. Value 88 1.8 V 61 2.7 V PD78070AY - PD780018AY 48 K to 60 K 3-wire with automatic transmit/receive function : 1 ch Time-division 3-wire : 1 ch I2C bus (multimaster supported) : 1 ch 88 PD780058Y 24 K to 60 K 3-wire/2-wire/I2C : 1 ch 3-wire with automatic transmit/receive function : 1 ch 3-wire/time-division UART : 1 ch 68 1.8 V PD78058FY 48 K to 60 K 69 2.7 V PD78054Y 3-wire/2-wire/I2C : 1 ch 3-wire with automatic transmit/receive function : 1 ch 16 K to 60 K PD780034Y 3-wire/UART : 1 ch 2.0 V 3-wire/UART : 1 ch 8 K to 32 K UART 3-wire I2C bus (multimaster supported) : 1 ch : 1 ch : 1 ch 51 PD78018FY 8 K to 60 K 3-wire/2-wire/I2C : 1 ch 3-wire with automatic transmit/receive function : 1 ch 53 PD78014Y 8 K to 32 K 3-wire/2-wire/SBI/I2C : 1 ch 3-wire with automatic transmit/receive function : 1 ch PD78002Y 8 K to 16 K 3-wire/2-wire/SBI/I2C : 1 ch 48 K to 60 K 3-wire/2-wire/I2C 3-wire/time-division UART 3-wire : 1 ch : 1 ch : 1 ch 3-wire/2-wire/I2C 3-wire/UART : 1 ch : 1 ch PD780024Y LCD Configuration of Serial Interface PD780308Y drive PD78064Y 16 K to 32 K 1.8 V 2.7 V 57 2.0 V Remark The functions other than the serial interface are common to the subseries without Y. Preliminary Data Sheet 3 PD78F0034Y OVERVIEW OF FUNCTION Item Internal memory Function Flash memory 32 KbytesNote High-speed RAM 1024 bytesNote Memory space 64 Kbytes General-purpose registers 8 bits x 32 registers (8 bits x 8 registers x 4 banks) Minimum instruction execution time On-chip minimum instruction execution time cycle modification function When main system clock selected 0.24 s/0.48 s/0.95 s/1.91 s/3.81 s (at 8.38-MHz operation) When subsystem clock selected 122 s (at 32.768-kHz operation) * 16-bit operate * multiply/divide (8 bits x 8 bits, 16 bits / 8 bits) * Bit manipulate (set, reset, test, Boolean operation) * BCD adjust, etc. Instruction set I/O ports Total : 51 * CMOS input : 8 * CMOS I/O : 39 * N-ch open-drain I/O (5-V withstand voltage) : 4 A/D converter * 10-bit resolution x 8 channels Serial interface * 3-wire serial I/O mode : 1 channel * UART mode : 1 channel * I2C bus mode (multimaster supported) : 1 channel Timer * * * * Timer output 3 (8-bit PWM output capable: 2) Clock output 131 kHz, 262 kHz, 524 kHz, 1.05 MHz, 2.10 MHz, 4.19 MHz, 8.38 MHz (at 8.38-MHz operation with main system clock) 32.768 kHz (at 32.768-kHz operation with subsystem clock) Buzzer output 1.02 kHz, 2.05 kHz, 4.10 kHz, 8.19 kHz (at 8.38-MHz operation with main system clock) Vectored interrupt Maskable source Non-maskable Internal : 13, External : 5 Software 16-bit timer/event counter 8-bit timer/event counter Watch timer Watchdog timer : : : : 1 2 1 1 channel channels channel channel Internal : 1 1 Test input Internal : 1, External : 1 Power supply voltage VDD = 2.7 to 5.5 V Operating ambient temperature TA = -40 to +85C Package * 64-pin plastic shrink DIP (750 mils) * 64-pin plastic QFP (14 x 14 mm) * 64-pin plastic LQFP (12 x 12 mm) Note The capacities of the flash memory and the internal high-speed RAM can be changed with the memory size switching register (IMS). 4 Preliminary Data Sheet PD78F0034Y PIN CONFIGURATION (TOP VIEW) * 64-pin Plastic Shrink DIP (750 mils) PD78F0034YCW P40/AD0 1 64 P67/ASTB P41/AD1 2 63 P66/WAIT P42/AD2 3 62 P65/WR P43/AD3 4 61 P64/RD P44/AD4 5 60 P75/BUZ P45/AD5 6 59 P74/PCL P46/AD6 7 58 P73/TI51/TO51 P47/AD7 8 57 P72/TI50/TO50 P50/A8 9 56 P71/TI01 P51/A9 10 55 P70/TI00/TO0 P52/A10 11 54 P03/INTP3/ADTRG P53/A11 12 53 P02/INTP2 P54/A12 13 52 P01/INTP1 P55/A13 14 51 P00/INTP0 P56/A14 15 50 VSS1 P57/A15 16 49 X1 VSS0 VDD0 17 48 X2 18 47 VPP P30 19 46 XT1 P31 P32/SDA0 20 21 45 44 XT2 RESET P33/SCL0 22 43 AVDD P34 23 42 AVREF P35 24 41 P10/ANI0 P36 25 40 P11/ANI1 P20/SI30 26 39 P12/ANI2 P21/SO30 27 38 P13/ANI3 P22/SCK30 28 37 P14/ANI4 P23/RxD0 29 36 P15/ANI5 P24/TxD0 30 35 P16/ANI6 P25/ASCK0 31 34 P17/ANI7 VDD1 32 33 AVSS Cautions 1. Connect the VPP pin directly to VSS0 or V SS1 in normal operation mode. 2. Connect the AVSS pin to VSS0. Remark When the PD78F0034Y is used in application fields that require reduction of the noise generated from inside the microcontroller, the implementation of noise reduction measures, such as supplying voltage to VDD0 and VDD1 independently and connecting VSS0 and VSS1 to different ground lines, is recommended. Preliminary Data Sheet 5 PD78F0034Y * 64-pin Plastic QFP (14 x 14 mm) PD78F0034YGC-AB8 * 64-pin Plastic LQFP (12 x 12 mm) P72/TI50/TO50 P73/TI51/TO51 P74/PCL P75/BUZ P64/RD P65/WR P66/WAIT P67/ASTB P40/AD0 P41/AD1 P42/AD2 P43/AD3 P44/AD4 P45/AD5 P46/AD6 P47/AD7 PD78F0034YGK-8A8 P01/INTP1 P55/A13 6 43 P00/INTP0 P56/A14 7 42 VSS1 P57/A15 8 41 X1 VSS0 9 40 X2 VDD0 10 39 VPP P30 11 38 XT1 P31 12 37 XT2 P32/SDA0 13 36 RESET P33/SCL0 14 35 AVDD P34 15 34 AVREF P35 16 33 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 P71/TI01 P10/ANI0 P11/ANI1 P12/ANI2 44 P13/ANI3 5 P14/ANI4 P54/A12 P15/ANI5 P02/INTP2 P16/ANI6 P03/INTP3/ADTRG 45 P17/ANI7 46 4 AVSS 3 P53/A11 VDD1 P52/A10 P24/TxD0 P70/TI00/TO0 P25/ASCK0 47 P23/RxD0 2 P22/SCK30 P51/A9 P21/SO30 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 P20/SI30 1 P36 P50/A8 Cautions 1. Connect the VPP pin directly to V SS0 or VSS1 in normal operation mode. 2. Connect the AV SS pin to V SS0. Remark When the PD78F0034Y is used in application fields that require reduction of the noise generated from inside the microcontroller, the implementation of noise reduction measures, such as supplying voltage to VDD0 and VDD1 independently and connecting VSS0 and V SS1 to different ground lines, is recommended. 6 Preliminary Data Sheet PD78F0034Y A8 to A15 : Address Bus PCL : Programmable Clock AD0 to AD7 : Address/Data Bus RD : Read Strobe ADTRG : AD Trigger Input RESET : Reset ANI0 to ANI7 : Analog Input RxD0 : Receive Data ASCK0 : Asynchronous Serial Clock SCK30 : Serial Clock ASTB : Address Strobe SCL0 : Serial Clock AVDD : Analog Power Supply SDA0 : Serial Data AVREF : Analog Reference Voltage SI30 : Serial Input AVSS : Analog Ground SO30 : Serial Output BUZ : Buzzer Clock TI00, TI01, TI50, TI51 : Timer Input INTP0 to INTP3 : Interrupt from Peripherals TO0, TO50, TO51 P00 to P03 : Port 0 TxD0 : Transmit Data P10 to P17 : Port 1 VDD0, V DD1 : Power Supply P20 to P25 : Port 2 VPP : Programming Power Supply P30 to P36 : Port 3 VSS0, V SS1 : Ground P40 to P47 : Port 4 WAIT : Wait P50 to P57 : Port 5 WR : Write Strobe P64 to P67 : Port 6 X1, X2 : Crystal (Main System Clock) P70 to P75 : Port 7 XT1, XT2 : Crystal (Subsystem Clock) Preliminary Data Sheet : Timer Output 7 PD78F0034Y BLOCK DIAGRAM TI00/TO0/P70 16-bit TIMER/ EVENT COUNTER PORT0 P00 to P03 TI50/TO50/P72 8-bit TIMER/ EVENT COUNTER50 PORT1 P10 to P17 TI51/TO51/P73 8-bit TIMER/ EVENT COUNTER51 PORT2 P20 to P25 WATCHDOG TIMER PORT3 P30 to P36 PORT4 P40 to P47 PORT5 P50 to P57 PORT6 P64 to P67 PORT7 P70 to P75 TI01/P71 WATCH TIMER SI30/P20 SO30/P21 SCK30/P22 RxD0/P23 TxD0/P24 ASCK0/P25 78K/0 CPU CORE FLASH MEMORY (32 Kbytes) SERIAL INTERFACE30 UART0 RAM (1024 bytes) SDA0/P32 AD0/P40 to AD7/P47 A8/P50 to A15/P57 I2C BUS SCL0/P33 ANI0/P10 to ANI7/P17 AVDD AVSS AVREF INTP0/P00 to INTP3/P03 8 EXTERNAL ACCESS A/D CONVERTER RD/P64 WR/P65 WAIT/P66 ASTB/P67 INTERRUPT CONTROL BUZ/P75 BUZZER OUTPUT PCL/P74 CLOCK OUTPUT CONTROL SYSTEM CONTROL VDD0 VDD1 VSS0 VSS1 VPP Preliminary Data Sheet RESET X1 X2 XT1 XT2 PD78F0034Y CONTENTS 1. DIFFERENCES BETWEEN PD78F0034Y AND MASK ROM VERSIONS ....................................... 10 2. PIN FUNCTIONS ................................................................................................................................. 11 2.1 Port Pins ..................................................................................................................................................... 11 2.2 Non-Port Pins ............................................................................................................................................ 12 2.3 Pin I/O Circuits and Recommended Connection of Unused Pins ..................................................... 14 3. MEMORY SIZE SWITCHING REGISTER (IMS) ................................................................................. 16 4. FLASH MEMORY PROGRAMMING ................................................................................................... 17 4.1 Selection of Transmission Method ......................................................................................................... 17 4.2 Function of Flash Memory Programming .............................................................................................. 18 4.3 Connection of Flashpro II ........................................................................................................................ 18 5. ELECTRICAL SPECIFICATIONS ....................................................................................................... 20 6. PACKAGE DRAWINGS ...................................................................................................................... 38 APPENDIX A. DEVELOPMENT TOOLS ................................................................................................ 41 APPENDIX B. RELATED DOCUMENTS ................................................................................................ 47 Preliminary Data Sheet 9 PD78F0034Y 1. DIFFERENCES BETWEEN PD78F0034Y AND MASK ROM VERSIONS The PD78F0034Y is a product provided with a flash memory that enables on-board writing, erasing, and rewriting of programs with the device mounted on the target system. The functions of the PD78F0034Y (except the functions specified for flash memory) can be made the same as those of the mask ROM versions by setting the memory size switching register (IMS). Table 1-1 shows the differences between the flash memory version (PD78F0034Y) and the mask ROM versions (PD780031Y, 780032Y, 780033Y, and 780034Y). Table 1-1. Differences between PD78F0034Y and Mask ROM Versions PD78F0034 Item Mask ROM Versions Internal ROM type Flash memory Mask ROM Internal ROM capacity 32 Kbytes PD780031Y PD780032Y PD780033Y PD780034Y : : : : Internal high-speed RAM capacity 1024 bytes PD780031Y PD780032Y PD780033Y PD780034Y : 512 bytes 8 Kbytes 16 Kbytes 24 Kbytes 32 Kbytes : 512 bytes : 1024 bytes : 1024 bytes Internal ROM and internal high-speed RAM capacity changeable/not changeable with memory size switching register (IMS) ChangeableNote Not changeable IC pin Not provided Provided VPP pin Provided Not provided Power supply voltage VDD = 2.7 to 5.5 V VDD = 1.8 to 5.5 V Electrical specifications, recommended soldering conditions Refer to the data sheet of individual products. Note Flash memory is set to 32 Kbytes and internal high-speed RAM is set to 1024 bytes by RESET input. Caution There are differences in noise immunity and noise radiation between the flash memory versions and mask ROM versions. When pre-producing an application set with the flash memory version and then mass-producing it with the mask ROM version, be sure to conduct sufficient evaluation for commercial samples (not engineering samples) of the mask ROM version. 10 Preliminary Data Sheet PD78F0034Y 2. PIN FUNCTIONS 2.1 Port Pins (1/2) Pin Name P00 I/O I/O P01 P02 P03 P10 to P17 P20 Function Port 0 4-bit input/output port. Input/output can be specified bit-wise. When used as an input port, an on-chip pull-up resistor can be used by software. Input Port 1 8-bit input only port. I/O P21 P22 P23 Port 2 6-bit input/output port. Input/output can be specified bit-wise. When used as an input port, an on-chip pull-up resistor can be used by software. After Reset Input Alternate Function INTP0 INTP1 INTP2 INTP3/ADTRG Input ANI0 to ANI7 Input SI30 SO30 SCK30 RxD0 P24 TxD0 P25 ASCK0 P30 I/O P31 P32 Port 3 7-bit input/output port. Input/output can be specified bit-wise. N-ch open-drain input/output port. LEDs can be driven directly. Input -- SDA0 P33 SCL0 P34 When used as an input port, an on-chip pullup resistor can be used by software. P35 -- P36 P40 to P47 I/O Port 4 8-bit input/output port. Input/output can be specified bit-wise. When used as an input port, an on-chip pull-up resistor can be used by software. Test input flag (KRIF) is set to 1 by the falling-edge detection. Input AD0 to AD7 P50 to P57 I/O Port 5 8-bit input/output port. LEDs can be driven directly. Input/output can be specified bit-wise. When used as an input port, an on-chip pull-up resistor can be used by software. Input A8 to A15 P64 I/O Port 6 4-bit input/output port. Input/output can be specified bit-wise. When used as an input port, an on-chip pull-up resistor can be used by software. Input RD P65 P66 P67 Preliminary Data Sheet WR WAIT ASTB 11 PD78F0034Y 2.1 Port Pins (2/2) Pin Name P70 I/O I/O P71 P72 P73 Function Port 7 6-bit input/output port. Input/output can be specified bit-wise. When used as an input port, an on-chip pull-up resistor can be used by software. After Reset Input Alternate Function TI00/TO0 TI01 TI50/TO50 TI51/TO51 P74 PCL P75 BUZ 2.2 Non-Port Pins (1/2) Pin Name INTP0 I/O Function After Reset Input External interrupt request input for which the effective edge (rising edge, falling edge, or both rising edge and falling edge) can be specified. Input INTP1 Alternate Function P00 P01 INTP2 P02 INTP3 P03/ADTRG SI30 SO30 Input Serial interface serial data input. Output Serial interface serial data output. Input P20 Input P21 SDA0 I/O Serial interface serial data input/output. Input P32 SCK30 I/O Serial interface serial clock input/output. Input P22 SCL0 RxD0 TxD0 P33 Input Serial data input for asynchronous serial interface. Output Serial data output for asynchronous serial interface. Input P23 Input P24 ASCK0 Input Serial clock input for asynchronous serial interface. Input P25 TI00 Input External count clock input to 16-bit timer (TM0). Capture trigger signal input to TM0 capture register (CR01). Input P70/TO0 TI01 Capture trigger signal input to TM0 capture register (CR00). P71 TI50 External count clock input to 8-bit timer (TM50). P72/TO50 TI51 External count clock input to 8-bit timer (TM51). P73/TO51 TO0 Output 16-bit timer (TM0) output. TO50 8-bit timer (TM50) output (alternate function is 8-bit PWM output). TO51 8-bit timer (TM51) output (alternate function is 8-bit PWM output). Input P70/TI00 Input P72/TI50 P73/TI51 PCL Output Clock output (for trimming of main system clock and subsystem clock). Input P74 BUZ Output Buzzer output. Input P75 Input P40 to P47 AD0 to AD7 I/O Lower address/data bus for extending memory externally. A8 to A15 Output Higher address bus for extending memory externally. Input P50 to P57 RD Output Strobe signal output for read operation of external memory. Input P64 WR Strobe signal output for write operation of external memory. WAIT ASTB 12 Input Inserting wait for accessing external memory. Output Strobe output that externally latches address information output to port 4 and port 5 to access external memory. Preliminary Data Sheet P65 Input P66 Input P67 PD78F0034Y 2.2 Non-Port Pins (2/2) Pin Name I/O Function After Reset Alternate Function ANI0 to ANI7 Input A/D converter analog input. Input P10 to P17 ADTRG Input A/D converter trigger signal input. Input P03/INTP3 AVREF Input A/D converter reference voltage input. -- -- AVDD -- A/D converter analog power supply. Set the voltage equal to VDD0 or VDD1. -- -- AVSS -- A/D converter ground potential. Set the voltage equal to VSS0 or VSS1. -- -- RESET Input System reset input. -- -- X1 Input Connecting crystal resonator for main system clock oscillation. -- -- X2 -- -- -- -- -- -- -- XT1 Input Connecting crystal resonator for subsystem clock oscillation. XT2 -- VDD0 -- Positive power supply for ports. -- -- VSS0 -- Ground potential of ports. -- -- VDD1 -- Positive power supply (except ports). -- -- VSS1 -- Ground potential (except ports). -- -- VPP -- Applying high voltage for program write/verify. Connect directly to VSS0 or VSS1 in normal operation mode. -- -- Preliminary Data Sheet 13 PD78F0034Y 2.3 Pin I/O Circuits and Recommended Connection of Unused Pins Table 2-1 shows the types of pin I/O circuits and recommended connection of unused pins. Refer to Figure 2-1 about the configuration of each type of I/O circuit. Table 2-1. Pin I/O Circuit Type Pin Name Input/output Circuit Type Input/Output 8-C Input Independently connect to VSS0 via a resistor. P10/ANI0 to P17/ANI7 25 Input Independently connect to VDD0 or VSS0 via a resistor. P20/SI30 8-C Input/output P21/SO30 5-H P22/SCK30 8-C P00/INTP0 Recommended Connection of Unused Pins P01/INTP1 P02/INTP2 P03/INTP3 P23/RxD0 P24/TxD0 5-H P25/ASCK0 8-C P30, P31 13-P P32/SDA0 13-R Input/output Independently connect to VDD0 via a resistor. P33/SCL0 P34 8-C P35 5-H P36 8-C P40/AD0 to P47/AD7 5-H Input/output Independently connect to VDD0 via a resistor. P50/A8 to P57/A15 5-H Input/output Independently connect to VDD0 or VSS0 via a resistor. P64/RD Independently connect to VDD0 or VSS0 via a resistor. Input/output P65/WR P66/WAIT P67/ASTB P70/TI00/TO0 8-C P71/TI01 P72/TI50/TO50 P73/TI51/TO51 P74/PCL 5-H P75/BUZ RESET 2 XT1 16 XT2 AVDD AVREF Input Connect to VDD0. -- -- -- Leave open. Connect to VDD0. Connect to VSS0. AVSS VPP 14 Connect directly to VSS0 or VSS1. Preliminary Data Sheet PD78F0034Y Figure 2-1 Pin Input/Output Circuit TYPE 2 TYPE 13-R IN/OUT data output disable N-ch IN VSS0 Schmitt-Triggered Input with Hysteresis Characteristics TYPE 5-H pullup enable data TYPE 16 VDD0 feedback cut-off P-ch P-ch VDD0 P-ch IN/OUT output disable N-ch VSS0 XT1 XT2 input enable TYPE 25 TYPE 8-C VDD0 pullup enable data P-ch Comparator P-ch + - VDD0 N-ch VSS0 VREF (threshold voltage) P-ch IN IN/OUT output disable VSS0 TYPE 13-P data output disable input enable N-ch IN/OUT N-ch VSS0 input enable Preliminary Data Sheet 15 PD78F0034Y 3. MEMORY SIZE SWITCHING REGISTER (IMS) This register sets a part of internal memory not used by software. The memory mapping can be made the same as that of mask ROM versions with different types of internal memory (ROM and RAM). The IMS is set with an 8-bit memory manipulation instruction. RESET input sets the IMS to CFH. Figure 3-1. Format of Memory Size Switching Register 7 IMS 6 5 RAM2 RAM1 RAM0 4 0 3 2 1 0 ROM3 ROM2 ROM1 ROM0 Address After reset R/W FFF0H CFH W ROM3 ROM2 ROM1 ROM0 Selection of Internal ROM Capacity 0 0 1 0 8 Kbytes 0 1 0 0 16 Kbytes 0 1 1 0 24 Kbytes 1 0 0 0 32 Kbytes 1 1 1 1 60 Kbytes (setting prohibited) Other than above Setting prohibited RAM2 RAM1 RAM0 Selection of Internal High-speed RAM Capacity 0 1 0 512 bytes 1 1 0 1024 bytes Other than above Setting prohibited Table 3-1 shows the IMS set value to make the memory mapping the same as those of mask ROM versions. Table 3-1. Set Value of Memory Size Switching Register Target Mask ROM Versions Caution 16 IMS Set Value PD780031Y 42H PD780032Y 44H PD780033Y C6H PD780034Y C8H When using mask ROM versions, set values indicated in Table 3-1 to IMS. Preliminary Data Sheet PD78F0034Y 4. FLASH MEMORY PROGRAMMING Writing to a flash memory can be performed without removing the memory from the target system. Writing is performed connecting the dedicated flash memory programmer (Flashpro II) to the host machine and the target system. Also, it can be performed on an adapter for flash memory writing connected to the Flashpro II. Remark Flashpro II is a product of Naitou Densei Machidaseisakusho Co., Ltd. 4.1 Selection of Transmission Method Writing to a flash memory is performed using the Flashpro II with a serial transmission mode. One of the transmission methods in Table 4-1 is selected. The selection of the transmission method is made by using the format shown in Figure 4-1. Each transmission method is selected by the number of VPP pulses shown in Table 4-1. Table 4-1. Transmission Methods Transmission Method Channels Pin VPP Pulses 3-wire serial I/O 1 SI30/P20 SO30/P21 SCK30/P22 0 UART 1 RxD0/P23 TxD0/P24 ASCK0/P25 8 I2C bus 1 SDA0/P32 SCL0/P33 4 Pseudo 3-wire serial I/O 1 P72/TI50/TO50 (serial clock input) P71/TI01 (serial data output) P70/TI00/TO0 (serial data input) 12 Caution Be sure to select a communication system using the number of VPP pulses shown in Table 4-1. Figure 4-1. Format of Transmission Method Selection VPP pulses 10 V VPP VDD 1 2 n VSS VDD RESET VSS Flash write mode Preliminary Data Sheet 17 PD78F0034Y 4.2 Function of Flash Memory Programming Operations such as writing to a flash memory are performed by various command/data transmission and reception operations according to the selected transmission method. Table 4-2 shows major functions of flash memory programming. Table 4-2. Major Functions of Flash Memory Programming Functions Descriptions Reset Used to stop write operation and detect transmission cycle. Batch verify Compares the entire memory contents with the input data. Batch delete Deletes the entire memory contents. Batch blank check Checks the deletion status of the entire memory. High-speed write Performs write to the flash memory based on the write start address and the number of data to be written (number of bytes). Continuous write Performs continuous write based on the information input with high-speed write operation. Status Used to confirm the current operating mode and operation end. Oscillation frequency setting Sets the frequency of the resonator. Delete time setting Sets the memory delete time. Silicon signature read Outputs the device name and memory capacity, and device block information. 4.3 Connection of Flashpro II The connection of the Flashpro II and the PD78F0034Y differs according to the transmission method (3-wire serial I/O, UART, and I2C bus). The connection for each transmission method is shown in Figures 4-2, 4-3, and 4-4, respectively. Figure 4-2. Connection of Flashpro II for 3-wire Serial I/O System PD78F0034Y Flashpro II VPP VPP VDD VDD RESET RESET SCK SCK30 SO SI30 SI SO30 VSS GND 18 Preliminary Data Sheet PD78F0034Y Figure 4-3. Connection of Flashpro II for UART System PD78F0034Y Flashpro II VPP VPP VDD VDD RESET RESET SO RxD0 SI TxD0 GND VSS Figure 4-4. Connection of Flashpro II for I2C Bus System PD78F0034Y Flashpro II VPP VPP VDD VDD RESET RESET SCK SCL0 SI SDA0 GND VSS Preliminary Data Sheet 19 PD78F0034Y 5. ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings (TA = 25C) Parameter Supply voltage Symbol Test Conditions VDD VPP Unit -0.3 to +6.5 V -0.3 to +11.0 V AVDD -0.3 to VDD + 0.3 V AVREF -0.3 to VDD + 0.3 V AVSS Input voltage Rating -0.3 to +0.3 V VI1 P00 to P03, P10 to P17, P20 to P25, P34 to P36, P40 to P47, P50 to P57, P64 to P67, P70 to P75, X1, X2, XT1, XT2, RESET -0.3 to VDD + 0.3 V VI2 P30 to P33 -0.3 to VDD + 0.3 V -0.3 to VDD + 0.3 V AVSS - 0.3 to AVREF + 0.3 and -0.3 to VDD + 0.3 V N-ch Open-drain Output voltage VO Analog input voltage VAN P10 to P17 High-level output current IOH Per pin -10 mA Total for P00 to P03, P40 to P47, P50 to P57, P64 to P67, P70 to P75 -15 mA Total for P20 to P25, P30 to P36 Low-level output current IOL Note Operating ambient temperature Storage temperature Analog input pin -15 mA Per pin for P00 to P03, P20 to P25, P34 to P36, P40 to P47, P64 to P67, P70 to P75 Peak value 20 mA Effective value 10 mA Per pin for P30 to P33, P50 to P57 Peak value 30 mA Effective value 15 mA Total for P00 to P03, P40 to P47, P64 to P67, P70 to P75 Peak value 50 mA Effective value 20 mA Total for P20 to P25 Peak value 20 mA Effective value 10 mA Total for P30 to P36 Peak value 100 mA Effective value 70 mA Total for P50 to P57 Peak value 100 mA Effective value 70 mA -40 to +85 C -65 to +150 C TA Tstg Note The effective value should be calculated as follows: [Effective value] = [Peak value] x duty Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. 20 Preliminary Data Sheet PD78F0034Y Capacitance (TA = 25C, VDD = VSS = 0 V) Parameter Symbol Test Conditions MIN. TYP. MAX. Unit Input capacitance CIN f = 1 MHz Unmeasured pins returned to 0 V. 15 pF I/O capacitance CIO f = 1 MHz Unmeasured pins returned to 0 V. 15 pF 20 pF P00 P34 P50 P70 to to to to P03, P20 to P25, P36, P40 to P47, P57, P64 to P67, P75, P30 to P33 Remark Unless otherwise specified, the characteristics of the alternate function are the same as those of the port-pin function. Main System Clock Oscillator Characteristics (TA = -40 to 85C, VDD = 2.7 to 5.5 V) Resonator Recommended Circuit Ceramic resonator VPP X2 C1 VPP X2 VDD = 4.5 to 5.5 V Oscillation X1 stabilization time Note 2 After VDD reaches oscillation voltage range MIN. Oscillation VDD = 4.5 to 5.5 V Oscillation frequency (fX)Note 1 C2 C1 X1 Unit 1.0 8.38 MHz 1.0 5.0 TYP. 4 ms 1.0 8.38 MHz 1.0 5.0 10 ms 30 VDD = 4.5 to 5.5 V 1.0 frequency (fX)Note 1 X1 input PD74HCU04 MAX. timeNote 2 X1 input X2 MIN. VDD = 4.5 to 5.5 V Oscillation stabilization External clock Test Conditions frequency (fX)Note 1 C2 Crystal resonator X1 Parameter 8.38 MHz 5.0 VDD = 4.5 to 5.5 V high-/low-level width (tXH , tXL) 50 500 85 500 ns Notes 1. Indicates only oscillator characteristics. Refer to AC Characteristics for instruction execution time. 2. Time required to stabilize oscillation after reset or STOP mode release. Cautions 1. When using the main system clock oscillator, wiring in the area enclosed with the broken line in the above figures should be carried out as follows to avoid an adverse effect from wiring capacitance. * Keep the wiring length as short as possible. * Do not cross the wiring with the other signal lines. * Do not route the wiring near a signal line through which a high fluctuating current flows. * Always keep the ground point of the oscillator to the same potential as VSS1. * Do not ground the capacitor to a ground pattern in which a high current flows. * Do not fetch signals from the oscillator. 2. When the main system clock is stopped and the system is operated by the subsystem clock, switching back to the main system clock should be done after the oscillation stabilization time has been secured by the program. Preliminary Data Sheet 21 PD78F0034Y Subsystem Clock Oscillator Characteristics (TA = -40 to +85C, VDD = 2.7 to 5.5 V) Resonator Crystal resonator XT2 XT1VPP R C4 External clock Parameter Recommended Circuit C3 XT2 PD74HCU04 XT1 Test Conditions Oscillation frequency (fXT)Note 1 Oscillation stabilization timeNote 2 MIN. TYP. MAX. Unit 32 32.768 35 kHz 1.2 2 s VDD = 4.5 to 5.5 V 10 XT1 input frequency (fXT)Note 1 32 100 kHz XT1 input high-/low-level width (tXTH , tXTL) 5 15 s Notes 1. Indicates only oscillator characteristics. Refer to AC Characteristics for instruction execution time. 2. Time required to stabilize oscillation after VDD reaches oscillation voltage MIN. Cautions 1. When using the subsystem clock oscillator, wiring in the area enclosed with the broken line in the above figures should be carried out as follows to avoid an adverse effect from wiring capacitance. * Keep the wiring length as short as possible. * Do not cross the wiring with the other signal lines. * Do not route the wiring near a signal line through which a high fluctuating current flows. * Always keep the ground point of the oscillator to the same potential as VSS1. * Do not ground the capacitor to a ground pattern in which a high current flows. * Do not fetch signals from the oscillator. 2. The subsystem clock oscillator is a low-amplitude circuit in order to achieve a low consumption current, and is more prone to malfunction due to noise than the main system clock oscillator. Particular care is therefore required with the wiring method when the subsystem clock is used. 22 Preliminary Data Sheet PD78F0034Y DC Characteristics (TA = -40 to +85C, VDD = 2.7 to 5.5 V) Parameter Symbol Input voltage, high VIH1 P10 to P17, P21, P24, P35, P40 to P47, P50 to P57, P64 to P67, P74, P75 VIH2 Input voltage, low Output voltage, MAX. Unit 0.7VDD VDD V P00 to P03, P20, P22, P23, P25, P34, P36, P70 to P73, RESET 0.8VDD VDD V VIH3 P30 to P33 (N-ch open-drain) 0.7VDD 5.5 V VIH4 X1, X2 VDD - 0.5 VDD V VIH5 XT1, XT2 0.8VDD VDD V 0.9VDD VDD V VIL1 P10 to P17, P21, P24, P35, P40 to P47, P50 to P57, P64 to P67, P74, P75 0 0.3VDD V VIL2 P00 to P03, P20, P22, P23, P25, P34, P36, P70 to P73, RESET 0 0.2VDD V VIL3 P30 to P33 0 0.3VDD V 0 0.2VDD V 0 0.4 V 0 0.2VDD V VDD = 4.5 to 5.5 V VDD = 4.5 to 5.5 V MIN. TYP. VIL4 X1, X2 VIL5 XT1, XT2 0 0.1VDD V VOH1 VDD = 4.5 to 5.5 V, IOH = -1 mA VDD - 1.0 VDD V IOH = -100 A VDD - 0.5 VDD V 2.0 V 0.4 V 0.5 V high Output voltage, Test Conditions VOL1 VDD = 4.5 to 5.5 V P30 to P33, P50 to P57 VDD = 4.5 to 5.5 V, IOL = 15 mA P00 to P03, P20 to P25, P34 to P36, P40 to P47, P64 to P67, P70 to P75 VDD = 4.5 to 5.5 V, IOL = 1.6 mA low VOL2 IOL = 400 A 0.4 Remark Unless otherwise specified, the characteristics of the alternate function are the same as those of the port-pin function. Preliminary Data Sheet 23 PD78F0034Y DC Characteristics (TA = -40 to +85C, VDD = 2.7 to 5.5 V) Parameter Symbol Input leakage current, high ILIH1 Test Conditions VIN = VDD ILIH2 Input leakage MIN. TYP. MAX. Unit P00 to P03, P10 to P17, P20 to P25, P34 to P36, P40 to P47, P50 to P57, P64 to P67, P70 to P75, RESET 3 A X1, X2, XT1, XT2 20 A ILIH3 VIN = 5.5 V P30 to P33 80 A ILIL1 VIN = 0 V P00 to P03, P10 to P17, P20 to P25, P34 to P36, P40 to P47, P50 to P57, P64 to P67, P70 to P75, RESET -3 A ILIL2 X1, X2, XT1, XT2 -20 A ILIL3 P30 to P33 -3 A current, low Output leakage current, low ILOH VOUT = VDD 3 A Output leakage current, low ILOL VOUT = 0 V -3 A Software pullup resistance R VIN = 0 V, P00 to P03, P20 to P25, P34 to P36, P40 to P47, P50 to P57, P64 to P67, P70 to P75 90 k Power supply currentNote 1 I DD1 8.38-MHz crystal oscillation operating mode VDD = 5.0 V 10% 9.5 19.0 mA IDD2 8.38-MHz crystal oscillation HALT mode VDD = 5.0 V 10% 1.6 3.2 mA IDD3 32.768-kHz crystal oscillation VDD = 5.0 V 10% 100 200 A VDD = 3.0 V 10% 70 140 A 32.768-kHz crystal oscillation HALT modeNote 2 VDD = 5.0 V 10% 25 55 A VDD = 3.0 V 10% 5 15 A XT1 = VDD1, STOP mode When feedback resistor is used VDD = 5.0 V 10% 1 30 A VDD = 3.0 V 10% 0.5 10 A XT1 = VDD1, STOP mode VDD = 5.0 V 10% 0.1 30 A When feedback resistor is not used VDD = 3.0 V 10% 0.05 10 A operating IDD4 IDD5 IDD6 modeNote 2 15 30 Notes 1. Does not include the current flowing into the on-chip pull-up resistor, the AVREF current, and port current. 2. When the main system clock is stopped. Remark Unless otherwise specified, the characteristics of the alternate function are the same as those of the port-pin function. 24 Preliminary Data Sheet PD78F0034Y AC Characteristics (1) Basic Operation (TA = -40 to +85C, V DD = 2.7 to 5.5 V) Parameter Symbol Cycle time (Min. instruction execution time) TCY Test Conditions Operating with VDD = 4.5 to 5.5 V main system clock Operating with subsystem clock TI00, TI01 input tTIH0, tTIL0 high-/low-level width TI50, TI51 input frequency fTI5 TI50, TI51 input tTIH5, tTIL5 3.5 V VDD 5.5 V MIN. MAX. Unit 0.24 32 s 0.8 32 s 125 s 40Note 1 TYP. 122 2/fsam + 0.1Note 2 s 0.2Note 2 s 2/fsam + 0 4 MHz 100 ns 1 s 10 s high-/low-level width Interrupt request input high-/low -level width tINTH, tINTL RESET tRSL INTP0 to INTP3, P40 to P47 low-level width Notes 1. Value when using the external clock. When using a crystal resonator, the value becomes 114 s (MIN.). 2. Selection of fsam = f X, f X/4, fX/64 is possible with bits 0 and 1 (PRM00, PRM01) of prescaler mode register 0 (PRM0). However, if the TI00 valid edge is selected as the count clock, the value becomes fsam = fX/8. Preliminary Data Sheet 25 PD78F0034Y TCY vs VDD (at main system clock operation) 32.0 Cycle time TCY [ s] 10.0 Operation Guaranteed Range 5.0 2.0 1.0 0.8 0.4 0.24 0.1 0 1.0 2.0 3.0 4.0 4.5 5.0 5.5 6.0 2.7 Supply voltage VDD [V] 26 Preliminary Data Sheet PD78F0034Y (2) Read/Write Operation (TA = -40 to + 85C, VDD = 4.5 to 5.5 V) (1/2) Parameter ASTB high-level width Symbol Test Conditions MIN. MAX. Unit tASTH 0.5tCY Address setup time tADS tCY - 40 ns Address hold time tADH 6 ns Data input time from address tADD1 Address output time from RD tRDAD Data input time from RD tRDD1 tADD2 0 tRDD2 ns (2 + 2n)tCY - 54 ns (3 + 2n)tCY - 60 ns 100 ns (2 + 2n)tCY - 87 ns (3 + 2n)tCY - 93 ns Read data hold time tRDH 0 ns RD low-level width tRDL1 (1.5 + 2n)tCY - 33 ns tRDL2 (2.5 + 2n)tCY - 33 ns WAIT input time from RD WAIT input time from WR WAIT low-level width tRDWT1 0.5tCY - 43 ns tRDWT2 tCY - 43 ns tWRWT 0.5tCY - 25 ns (2 + 2n)tCY ns tWTL (0.5 + 2n)tCY + 10 Write data setup time tWDS 60 ns Write data hold time tWDH 6 ns WR low-level width tWRL1 (1.5 + 2n)tCY - 15 ns RD delay time from ASTB tASTRD 6 ns WR delay time from ASTB tASTWR 2tCY - 15 ns ASTB delay time from RD in external fetch tRDAST 0.8tCY - 15 1.2tCY ns Address hold time from tRDADH 0.8tCY - 15 1.2tCY + 30 ns Write data output time from RD tRDWD 40 Write data output time from WR tWRWD 10 60 ns Address hold time from WR tWRADH 0.8tCY - 15 1.2tCY + 30 ns RD delay time from WAIT tWTRD 0.8tCY 2.5tCY + 25 ns WR delay time from WAIT tWTWR 0.8tCY 2.5tCY + 25 ns RD in external fetch ns Remarks 1. tCY = T CY/4 2. n indicates the number of waits. Preliminary Data Sheet 27 PD78F0034Y (2) Read/Write Operation (TA = -40 to + 85C, VDD = 2.7 to 4.5 V) (2/2) Parameter ASTB high-level width Symbol Test Conditions MIN. MAX. Unit tASTH 0.5tCY ns Address setup time tADS 0.5tCY - 54 ns Address hold time tADH 10 ns Data input time from address tADD1 (2 + 2n)tCY - 108 ns tADD2 (3 + 2n)tCY - 120 ns Address output time from RD tRDAD 200 ns Data input time from RD tRDD1 0 (2 + 2n)tCY - 148 ns tRDD2 (3 + 2n)tCY - 162 ns Read data hold time tRDH 0 ns RD low-level width tRDL1 (1.5 + 2n)tCY - 40 ns tRDL2 (2.5 + 2n)tCY - 40 ns WAIT input time from RD WAIT input time from WR WAIT low-level width tRDWT1 0.5tCY - 60 ns tRDWT2 tCY - 60 ns tWRWT 0.5tCY - 50 ns (2 + 2n)tCY ns tWTL (0.5 + 2n)tCY + 10 Write data setup time tWDS 60 ns Write data hold time tWDH 10 ns WR low-level width tWRL1 (1.5 + 2n)tCY - 30 ns RD delay time from ASTB tASTRD 10 ns WR delay time from ASTB tASTWR 2tCY - 30 ASTB delay time from RD in external fetch tRDAST 0.8tCY - 30 1.2t CY ns Address hold time from RD in external fetch tRDADH 0.8tCY - 30 1.2tCY + 60 ns ns Write data output time from RD tRDWD 40 Write data output time from WR tWRWD 20 120 ns Address hold time from WR tWRADH 0.8tCY - 30 1.2tCY + 60 ns RD delay time from WAIT tWTRD 0.5tCY 2.5tCY + 50 ns WR delay time from WAIT tWTWR 0.5tCY 2.5tCY + 50 ns Remarks 1. tCY = T CY/4 2. n indicates the number of waits. 28 Preliminary Data Sheet ns PD78F0034Y (3) Serial Interface (T A = -40 to +85C, V DD = 2.7 to 5.5 V) (a) 3-wire serial I/O mode (SCK30 ... Internal clock output) Parameter SCK30 cycle time Symbol tKCY1 SCK30 high-/low-level width tKH1, tKL1 SI30 setup time (to SCK30, SCK31) tSIK1 Test Conditions VDD = 4.5 to 5.5 V VDD = 4.5 to 5.5 V VDD = 4.5 to 5.5 V SI30 hold time tKSI1 (from SCK30, SCK31) SO30 output delay time from SCK30 tKSO1 MIN. TYP. MAX. Unit 954 ns 1600 ns tKCY1/2 - 50 ns tKCY1/2 - 100 ns 100 ns 150 ns 400 ns C = 100 pFNote 300 ns MAX. Unit Note C is the load capacitance of the SCK30, SO30 output lines. (b) 3-wire serial I/O mode (SCK30 ... External clock input) Parameter SCK30 Symbol TYP. ns 1600 ns 400 ns 800 ns tSIK2 100 ns SI30 hold time (from SCK30) tKSI2 400 ns SO30 output delay tKSO2 C = 100 pFNote 300 ns tR2, tF2 When using external device expansion function 160 ns 700 ns 1000 ns tKH2, tKL2 VDD = 4.5 to 5.5 V MIN. 800 SCK30, high-/low-level tKCY2 Test Conditions VDD = 4.5 to 5.5 V width SI30 setup time (to SCK30) time from SCK30 SCK30 rise fall time When not using external device expansion function When using 16-bit timer output function When not using 16-bit timer output function Note C is the load capacitance of the SO30 output line. Preliminary Data Sheet 29 PD78F0034Y (c) UART mode (Dedicated baud rate generator output) Parameter Symbol Transfer rate Test Conditions MIN. TYP. VDD = 4.5 to 5.5 V MAX. Unit 125000 bps 78125 bps MAX. Unit (d) UART mode (External clock input) Parameter ASCK0 cycle time ASCK0 high-/low-level width Symbol tKCY3 Test Conditions VDD = 4.5 to 5.5 V tKH3, VDD = 4.5 to 5.5 V tKL3 Transfer rate MIN. TYP. 800 ns 1600 ns 400 ns 800 ns VDD = 4.5 to 5.5 V ASCK0 rise, fall time tR3, tF3 VDD = 4.5 to 5.5 V, when not using external device expansion function 39063 bps 19531 bps 1000 ns 160 ns MAX. Unit (e) UART mode (Infrared ray data transfer mode) Parameter Symbol Test Conditions Transfer rate VDD = 4.5 to 5.5 V 115200 bps Bit rate allowable error VDD = 4.5 to 5.5 V 0.87 % Output pulse width VDD = 4.5 to 5.5 V 1.2 0.24/fbrNote s Input pulse width VDD = 4.5 to 5.5 V 4/fX Note fbr: specified baud rate 30 TYP. Preliminary Data Sheet s PD78F0034Y (f) I2C bus Mode Standard Mode Parameter Symbol MIN. MAX. High-speed Mode MIN. MAX. Unit SCL0 clock frequency fCLK 0 100 0 400 kHz Bus free time (between stop and start conditions) tBUF 4.7 -- 1.3 -- s Hold timeNote 1 tHD:STA 4.0 -- 0.6 -- s SCL0 clock low-level width tLOW 4.7 -- 1.3 -- s SCL0 clock high-level width tHIGH 4.0 -- 0.6 -- s Start/restart condition setup time tSU:STA 4.7 -- 0.6 -- s Data hold time tHD:DAT 5.0 -- -- -- s 0Note 2 -- 0Note 2 0.9Note 3 s 250 -- 100Note 4 CBUS compatible master I2C bus Data setup time tSU:DAT SDA0 and SCL0 signal rise time tR -- 1000 20 + -- ns 0.1CbNote 5 300 ns Note 5 300 ns SDA0 and SCL0 signal fall time tF -- 300 20 + 0.1Cb Stop condition setup time tSU:STO 4.0 -- 0.6 -- s Spike pulse width controlled by input filter tSP -- -- 0 50 ns Capacitive load per each bus line Cb -- 400 -- 400 pF Notes 1. On start condition, the first clock pulse is generated after this period. 2. To fulfill undefined area of the SCL0 falling edge, it is necessary for the device to provide internally SDA0 signal (on VIHmin. of SCL0 signal) with at least 300 ns of hold time. 3. If the device does not extend the SCL0 signal low hold time (tLOW ), only maximum data hold time (tHD:DAT) needs to be fulfilled. 4. The high-speed mode I2C bus is available in the standard mode I2C bus system. At this time, the conditions described below must be satisfied. * If the device does not extend the SCL0 signal low state hold time tSU:DAT 250 ns * If the device extends the SCL0 signal low state hold time Be sure to transmit the next data bit to the SDA0 line before the SCL0 line is released (tRmax. + tSU:DAT = 1000 + 250 = 1250 ns by standard mode I2C bus specification). 5. Cb : total capacitance per one bus line (unit : pF) Preliminary Data Sheet 31 PD78F0034Y AC Timing Test Point (Excluding X1, XT1 Input) 0.8 VDD 0.2 VDD 0.8 VDD 0.2 VDD Test Points Clock Timing 1/fX tXL tXH VIH4 (MIN.) X1 Input VIL4 (MAX.) 1/fXT tXTL tXTH VIH5 (MIN.) VIL5 (MAX.) XT1 Input TI Timing tTIL0 tTIH0 TI00, TI01 1/fTI5 tTIL5 tTIH5 TI50, TI51 32 Preliminary Data Sheet PD78F0034Y Read/Write Operation External Fetch (No Wait) : A8 to A15 Higher 8-Bit Address Lower 8-Bit Address tADD1 Hi-z AD0 to AD7 tADS tASTH Instruction Code tRDADH tRDD1 tADH tRDAST ASTB RD tRDL1 tASTRD tRDH External Fetch (Wait Insertion) : A8 to A15 Higher 8-Bit Address Lower 8-Bit Address tADD1 Hi-z AD0 to AD7 Instruction Code tRDADH tRDD1 tADS tASTH tADH tRDAST ASTB RD tASTRD tRDL1 tRDH WAIT tRDWT1 tWTL Preliminary Data Sheet tWTRD 33 PD78F0034Y External Data Access (No Wait) : A8 to A15 Higher 8-Bit Address Lower 8-Bit Address tADD2 Hi-z AD0 to AD7 Read Data Hi-z Hi-z Write Data tRDD2 tADS tADH tRDH tASTH ASTB RD tASTRD tRDWD tRDL2 tWDH tWDS tWRWD WR tASTWR tWRL1 tWRADH External Data Access (Wait Insertion) : A8 to A15 Higher 8-Bit Address Lower 8-Bit Address tADD2 Hi-z AD0 to AD7 Read Data Hi-z Hi-z Write Data tRDD2 tADS tADH tRDH tASTH ASTB tASTRD RD tRDWD tRDL2 tWDH tWDS tWRWD WR tASTWR tWRL1 tWRADH WAIT tRDWT2 tWTRD tWTL 34 Preliminary Data Sheet tWRWT tWTL tWTWR PD78F0034Y Serial Transfer Timing 3-wire Serial I/O Mode : tKCYm tKLm tKHm tFn tRn SCK30 tSIKm SI30 tKSIm Input Data tKSOm SO30 Output Data m = 1, 2 n=2 UART Mode (External Clock Input) : t KCY3 t KL3 t KH3 tR3 tF3 ASCK0 I2C Bus Mode tR SCL0 tHD:DAT tHD:STA tHIGH tSU:DAT tF tSU:STA tHD:STA tSP tSU:STO SDA0 tBUF Stop condition Start condition Restart condition Preliminary Data Sheet Stop condition 35 PD78F0034Y A/D Converter Characteristics (TA = -40 to 85C, VDD = AVDD = AVREF = 2.7 to 5.5 V, AVSS = VSS = 0 V) Parameter Symbol Test Conditions Resolution Overall errorNote MIN. TYP. MAX. Unit 10 10 10 bit 0.4 % 0.7 % 14 200 s 20 200 s 0 AVREF + 0.3 V AVREF = 4.5 to 5.5 V Conversion time TCONV Analog input voltage AVREF = 4.5 to 5.5 V VIAN Reference voltage AVREF 2.7 AVREF resistance RAIREF 10 AVDD V 20 k Note Excluding quantization error (1/2LSB). Shown as a percentage of the full scale value. Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics (TA = -40 to +85C) Parameter Symbol Data retention power supply voltage VDDDR Data retention IDDDR power supply current Release signal set time tSREL Oscillation stabilization wait time tWAIT Test Conditions MIN. TYP. 1.6 VDDDR = 1.6 V Subsystem clock stops and feed-back resistor disconnected 0.1 MAX. Unit 5.5 V 10 A s 0 Release by RESET 217/fx ms Release by interrupt request Note ms Note Selection of 212/fX and 214/fX to 217/fX is possible with bits 0 to 2 (OSTS0 to OSTS2) of the oscillation stabilization time select register (OSTS). Data Retention Timing (STOP Mode Release by RESET) Internal Reset Operation HALT Mode Operating Mode STOP Mode Data Retention Mode VDD VDDDR tSREL STOP Instruction Execution RESET tWAIT 36 Preliminary Data Sheet PD78F0034Y Data Retention Timing (Standby Release Signal: STOP Mode Release by Interrupt Request Signal) HALT Mode Operating Mode STOP Mode Data Retention Mode VDD VDDDR tSREL STOP Instruction Execution Standby Release Signal (Interrupt Request) tWAIT Interrupt Request Input Timing tINTL tINTH INTP0 to INTP2 tINTL INTP3 RESET Input Timing tRSL RESET Preliminary Data Sheet 37 PD78F0034Y 6. PACKAGE DRAWINGS 64-PIN PLASTIC SHRINK DIP (750 mils) (Unit: mm) 64 33 1 32 A K J L I H F D C N B M R M G NOTES 1. Controlling dimension millimeter. 2. Each lead centerline is located within 0.17 mm (0.007 inch) of its true position (T.P.) at maximum material condition. 3. Item "K" to center of leads when formed parallel. ITEM MILLIMETERS INCHES A 58.0+0.68 -0.20 2.283+0.028 -0.008 B 1.78 MAX. 0.070 MAX. C 1.778 (T.P.) 0.070 (T.P.) D 0.500.10 0.020+0.004 -0.005 F 0.9 MIN. 0.035 MIN. G 3.20.3 0.1260.012 H 0.51 MIN. 0.020 MIN. I 4.05+0.26 -0.20 0.159+0.011 -0.008 J 5.08 MAX. 0.200 MAX. K 19.05 (T.P.) 0.750 (T.P.) L 17.00.2 0.669+0.009 -0.008 M 0.25 +0.10 -0.05 0.010+0.004 -0.003 N 0.17 0.007 R 0 to 15 0 to 15 P64C-70-750A,C-3 38 Preliminary Data Sheet PD78F0034Y 64-PIN PLASTIC QFP (14 x 14) (Unit: mm) A B 48 49 33 32 detail of lead end S C D Q 64 1 R 17 16 F J G H I M P K S N S L M NOTE 1. Controlling dimension ITEM millimeter. 2. Each lead centerline is located within 0.15 mm (0.006 inch) of its true position (T.P.) at maximum material condition. MILLIMETERS INCHES A 17.60.4 B 14.00.2 0.6930.016 0.551 +0.009 -0.008 C 14.00.2 0.551 +0.009 -0.008 D 17.60.4 0.6930.016 F G 1.0 1.0 0.039 0.039 H 0.37 +0.08 -0.07 0.015 +0.003 -0.004 0.006 I 0.15 J 0.8 (T.P.) 0.031 (T.P.) K 1.80.2 0.0710.008 L 0.80.2 0.031 +0.009 -0.008 M 0.17 +0.08 -0.07 0.007 +0.003 -0.004 N 0.10 0.004 P 2.550.1 0.1000.004 Q 0.10.1 0.0040.004 R S 55 2.85 MAX. 55 0.113 MAX. P64GC-80-AB8-4 Preliminary Data Sheet 39 PD78F0034Y 64-PIN PLASTIC LQFP (12 x 12) (Unit: mm) A B 33 32 detail of lead end Q R D C S 48 49 F 64 17 16 1 H I M J K M P G N L NOTE ITEM Each lead centerline is located within 0.13 mm (0.005 inch) of its true position (T.P.) at maximum material condition. MILLIMETERS INCHES A 14.80.4 0.5830.016 B 12.00.2 0.472 +0.009 -0.008 C 12.00.2 0.472 +0.009 -0.008 D 14.80.4 0.5830.016 F 1.125 0.044 G 1.125 0.044 H 0.300.10 0.012 +0.004 -0.005 I 0.13 0.005 J 0.65 (T.P.) 0.026 (T.P.) K 1.40.2 0.0550.008 L 0.60.2 0.024 +0.008 -0.009 M 0.15 +0.10 -0.05 0.006 +0.004 -0.003 N 0.10 0.004 P Q 1.4 0.055 R 0.1250.075 55 0.0050.003 55 S 1.7 MAX. 0.067 MAX. P64GK-65-8A8-1 40 Preliminary Data Sheet PD78F0034Y APPENDIX A. DEVELOPMENT TOOLS The following development tools are available for system development using the PD78F0034Y. Be sure to refer to (5) Cautions on using development tools. (1) Language Processing Software RA78K/0 Assembler package common to 78K/0 Series CC78K/0 C compiler package common to 78K/0 Series DF780034 Device file common to PD780034 Subseries CC78K/0-L C compiler library source file common to 78K/0 Series (2) Flash Memory Writing Tools Flashpro II (FL-PR2) Flash programmer dedicated to on-chip flash memory microcontroller FA-64CW FA-64GC FA-64GKNote Adapter for flash writing Note Under development (3) Debugging Tool * When using in-circuit emulator IE-78K0-NS IE-78K0-NSNote In-circuit emulator common to 78K/0 Series IE-70000-MC-PS-B IE-70000-98-IF-C Note IE-70000-CD-IFNote IE-70000-PC-IF-C Note IE-780034-NS-EM1Note Power supply unit for IE-78K0-NS Interface adapter when using PC-9800 series as host machine (excluding notebook PCs) PC card and interface cable when using notebook PC of PC-9800 series as host machine Interface adapter when using IBM PC/ATTM or compatible as host machine Emulation board to emulate PD780034 Subseries NP-64CW Emulation probe for 64-pin plastic shrink DIP (CW type) NP-64GC Emulation probe for 64-pin plastic QFP (GC-AB8 type) NP-64GKNote Emulation probe for 64-pin plastic LQFP (GK-8A8 type) TGK-064SBW Conversion adapter for connecting target system board designed to allow mounting of 64-pin plastic LQFP (GK-8A8 type) and NP-64GK. EV-9200GC-64 Socket to be mounted on target system board manufactured for 64-pin plastic QFP (GC-AB8 type) ID78K0-NS Note Integrated debugger for IE-78K0-NS SM78K0 System simulator common to 78K/0 Series DF780034 Device file common to PD780034 Subseries Note Under development Preliminary Data Sheet 41 PD78F0034Y * When using in-circuit emulator IE-78001-R-A IE-78001-R-ANote In-circuit emulator common to 78K/0 Series IE-70000-98-IF-B IE-70000-98-IF-CNote Interface adapter when using PC-9800 series as host machine (excluding notebook PCs) IE-70000-PC-IF-B IE-70000-PC-IF-CNote Interface adapter when using IBM PC/AT or compatible as host machine IE-78000-R-SV3 Interface adapter and cable when using EWS as host machine IE-780034-NS-EM1Note Emulation board to emulate PD780034 Subseries IE-78K0-R-EX1 Note Emulation probe conversion board to use IE-780034-NS-EM1 on IE-78001-R-A EP-78240CW-R Emulation probe for 64-pin plastic shrink DIP (CW type) EP-78240GC-R Emulation probe for 64-pin plastic QFP (GC-AB8 type) EP-78012GK-R Emulation probe for 64-pin plastic LQFP (GK-8A8 type) TGK-064SBW Conversion adapter for connecting target system board and EP-78012GK-R designed to allow mounting of 64-pin plastic LQFP (GK-8A8). EV-9200GC-64 Socket to be mounted on target system board manufactured for 64-pin plastic QFP (GC-AB8 type) ID78K0 Integrated debugger for IE-78001-R-A SM78K0 System simulator common to 78K/0 Series DF780034 Device file common to PD780034 Subseries Note Under development (4) Real-time OS RX78K/0 Real-time OS for 78K/0 Series MX78K0 OS for 78K/0 Series 42 Preliminary Data Sheet PD78F0034Y (5) Cautions on using development tools * The ID-78K0-NS, ID78K0, and SM78K0 are used in combination with the DF780034. * The CC78K/0 and RX78K/0 are used in combination with the RA78K/0 and the DF780034. * The Flashpro II, FA-64CW, FA-64GC, FA64GK, NP-64CW, NP64GC, and NP-64GK are products made by Naitou Densei Machidaseisakusho (044-822-3813). Contact an NEC distributor regarding the purchase of these products. * The TGK-064SBW is a product made by TOKYO ELETECH CORPORATION. Refer to: Daimaru Kogyo, Ltd. Tokyo Electronic Components Division (03-3820-7112) Osaka Electronic Components Division (06-244-6672) * For third party development tools, see the 78K/0 Series Selection Guide (U11126E). * The host machines and OSs supporting each software are as follows. Host Machine [OS] Software PC PC-9800 series [WindowsTM] IBM PC/AT or compatibles [Japanese/English Windows] EWS HP9000 series 700TM [HP-UXTM] SPARCstationTM [SunOSTM] NEWSTM (RISC) [NEWS-OSTM] RA78K/0 Note CC78K/0 Note ID78K0-NS - ID78K0 - RX78K/0 Note MX78K0 Note SM78K0 Note DOS-based software Preliminary Data Sheet 43 PD78F0034Y Conversion Socket Drawing (EV-9200GC-64) and Footprints Figure A-1. EV-9200GC-64 Drawing (for reference only) A N O L K T J C D S F Q M R B E EV-9200GC-64 1 P No.1 pin index G H I EV-9200GC-64-G0 ITEM 44 MILLIMETERS INCHES A 18.8 0.74 B 14.1 0.555 C 14.1 0.555 D 18.8 0.74 E 4-C 3.0 4-C 0.118 F 0.8 0.031 G 6.0 0.236 H 15.8 0.622 I 18.5 0.728 J 6.0 0.236 K 15.8 0.622 L 18.5 0.728 M 8.0 0.315 N 7.8 0.307 O 2.5 0.098 P 2.0 0.079 Q 1.35 0.053 R 0.35 0.1 0.014+0.004 -0.005 S 2.3 0.091 T 1.5 0.059 Preliminary Data Sheet PD78F0034Y Figure A-2. EV-9200GC-64 Footprints (for reference only) G J H D E F K I L C B A EV-9200GC-64-P1E ITEM MILLIMETERS A 19.5 B 14.8 INCHES 0.768 0.583 C 0.80.02 x 15=12.00.05 D +0.003 0.80.02 x 15=12.00.05 0.031+0.002 -0.001 x 0.591=0.472 -0.002 0.031+0.002 -0.001 x 0.591=0.472 +0.003 -0.002 E 14.8 0.583 F 19.5 0.768 G 6.00 0.08 0.236 +0.004 -0.003 H 6.00 0.08 0.236 +0.004 -0.003 I 0.5 0.02 0.197 +0.001 -0.002 J 2.36 0.03 0.093 +0.001 -0.002 K 2.2 0.1 0.087 +0.004 -0.005 L 1.57 0.03 0.062 +0.001 -0.002 Caution Dimensions of mount pad for EV-9200 and that for target device (QFP) may be different in some parts. For the recommended mount pad dimensions for QFP, refer to "SEMICONDUCTOR DEVICE MOUNTING TECHNOLOGY MANUAL" (C10535E). Preliminary Data Sheet 45 PD78F0034Y Conversion Adapter Drawing (TGK-064SBW) Figure A-3. TGK-064SBW Drawing (for reference only) A B K L X M C T G F E D H I J Protrusion height U S V Q W R N O P a Z e Y d k j h i c b f g ITEM A MILLIMETERS 18.4 ITEM MILLIMETERS INCHES a 0.3 0.012 B 0.65x15=9.75 0.026x0.591=0.384 b 1.85 0.073 C D 0.65 7.75 0.026 0.305 c d 3.5 2.0 0.138 0.079 E F G 10.15 12.55 14.95 0.400 0.494 0.589 e f 3.9 1.325 0.052 g 1.325 0.052 H 0.65x15=9.75 0.026x0.591=0.384 I 11.85 0.467 h i 5.9 0.8 0.232 0.031 J K 18.4 C 2.0 0.724 C 0.079 j k 2.4 2.7 0.094 0.106 L M 12.45 10.25 0.490 0.404 N O 7.7 10.02 0.303 0.394 P 14.92 0.587 Q R 11.1 1.45 0.437 0.057 S 1.45 0.057 T U 4- 1.3 1.8 4- 0.051 0.071 V W X Y Z 5.0 0.197 5.3 0.209 4-C 1.0 4-C 0.039 3.55 0.9 0.140 0.035 Note: Product made by TOKYO ELETECH Corporation. 46 INCHES 0.724 Preliminary Data Sheet 0.154 TGK-064SBW-G0E PD78F0034Y APPENDIX B. RELATED DOCUMENTS Device Related Documents Document Name Document No. Document No. (English) (Japanese) PD780024, 780024Y, 780034, 780034Y Subseries User's Manual U12022E U12022J PD780031Y, 780032Y, 780033Y, 780034Y Data Sheet U12166E U12166J PD78F0034Y Data Sheet This document U11994J 78K/0 Series User's Manual-Instruction U12326E U12326J 78K/0 Series Instruction Table -- U10903J 78K/0 Series Instruction Set -- U10904J PD780034Y Subseries Special Function Register Table -- To be prepared Development Tool Documents (User's Manual) Document Name RA78K0 Assembler Package Operation U11802E U11802J Assembly Language U11801E U11801J Structured Assembly Language U11789E U11789J RA78K Series Structured Assembler Preprocessor CC78K0 C Compiler CC78K/0 C Compiler Application Note Document No. Document No. (English) (Japanese) EEU-1402 U12323J Operation U11517E U11517J Language U11518E U11518J Programming Know-how EEA-1208 U13034J CC78K Series Library Source File U12322E U12322J IE-78K0-NS To be prepared To be prepared IE-78001-R-A To be prepared To be prepared IE-780034-NS-EM1 To be prepared To be prepared EP-78240 U10332E EEU-986 EP-78012GK-R EEU-1538 EEU-5012 SM78K0 System Simulator-Windows based Reference U10181E U10181J SM78K Series System Simulator External Part User Open Interface Specifications U10092E U10092J ID78K0-NS Integrated Debugger Reference To be prepared U12900J ID78K0 Integrated Debugger -- EWS based Reference ID78K0 Integrated Debugger -- PC based Reference U11539E U11539J ID78K0 Integrated Debugger -- Windows based Guide U11649E U11649J Caution -- U11151J The above related documents are subject to change without notice. Be sure to read the latest documents before designing. Preliminary Data Sheet 47 PD78F0034Y Embedded Software Documents (User's Manual) Document Name 78K/0 Series Real-time OS 78K/0 Series OS MX78K0 Document No. Document No. (English) (Japanese) Basics U11537E U11537J Installation U11536E U11536J Basics U12257E U12257J Other Documents Document Name IC Package Manual Document No. Document No. (English) (Japanese) C10943X Semiconductor Device Mounting Technology Manual C10535E C10535J Quality Grades on NEC Semiconductor Devices C11531E C11531J NEC Semiconductor Device Reliability/Quality Control System C10983E C10983J Guide to Prevent Damage for Semiconductor Devices by Electrostatic Discharge (ESD) C11892E C11892J Guide to Quality Assurance for Semiconductor Devices MEI-1202 Microcomputer Product Series Guide Caution -- The above related documents are subject to change without notice. Be sure to read the latest documents before designing. 48 -- U11416J Preliminary Data Sheet PD78F0034Y [MEMO] Preliminary Data Sheet 49 PD78F0034Y NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function. 50 Preliminary Data Sheet PD78F0034Y Regional Information Some information contained in this document may vary from country to country. Before using any NEC product in your application, please contact the NEC office in your country to obtain a list of authorized representatives and distributors. They will verify: * Device availability * Ordering information * Product release schedule * Availability of related technical literature * Development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, AC supply voltages, and so forth) * Network requirements In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. NEC Electronics Inc. (U.S.) NEC Electronics (Germany) GmbH NEC Electronics Hong Kong Ltd. Santa Clara, California Tel: 408-588-6000 800-366-9782 Fax: 408-588-6130 800-729-9288 Benelux Office Eindhoven, The Netherlands Tel: 040-2445845 Fax: 040-2444580 Hong Kong Tel: 2886-9318 Fax: 2886-9022/9044 NEC Electronics Hong Kong Ltd. Velizy-Villacoublay, France Tel: 01-30-67 58 00 Fax: 01-30-67 58 99 Seoul Branch Seoul, Korea Tel: 02-528-0303 Fax: 02-528-4411 NEC Electronics (France) S.A. NEC Electronics Singapore Pte. Ltd. Milton Keynes, UK Tel: 01908-691-133 Fax: 01908-670-290 Spain Office Madrid, Spain Tel: 01-504-2787 Fax: 01-504-2860 United Square, Singapore 1130 Tel: 65-253-8311 Fax: 65-250-3583 NEC Electronics Italiana s.r.1. NEC Electronics (Germany) GmbH Milano, Italy Tel: 02-66 75 41 Fax: 02-66 75 42 99 Scandinavia Office Taeby, Sweden Tel: 08-63 80 820 Fax: 08-63 80 388 NEC Electronics (France) S.A. NEC Electronics (Germany) GmbH Duesseldorf, Germany Tel: 0211-65 03 02 Fax: 0211-65 03 490 NEC Electronics (UK) Ltd. NEC Electronics Taiwan Ltd. Taipei, Taiwan Tel: 02-719-2377 Fax: 02-719-5951 NEC do Brasil S.A. Cumbica-Guarulhos-SP, Brasil Tel: 011-6465-6810 Fax: 011-6465-6829 J98. 2 Preliminary Data Sheet 51 PD78F0034Y Purchase of NEC I 2C components conveys a license under the Philips I 2C Patent Rights to use these components in an I 2C system, provided that the system conforms to the I 2C Standard Specification as defined by Philips. FIP and IEBus are trademarks of NEC Corporation. Windows is a registered trademark or a trademark of Microsoft Corporation in the United States and/or other countries. PC/AT is a trademark of International Business Machines Corporation. HP9000 series 700 and HP-UX are trademarks of Hewlett-Packard Company. SPARCstation is a trademark of SPARC International, Inc. SunOS is a trademark of Sun Microsystems, Inc. NEWS and NEWS-OS are trademarks of Sony Corporation. The related documents indicated in this publication may include preliminary versions. However, preliminary versions are not marked as such. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. NEC devices are classified into the following three quality grades: "Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. The recommended applications of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device before using it in a particular application. Standard: Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact an NEC sales representative in advance. Anti-radioactive design is not implemented in this product. M4 96.5