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©
1997
PRELIMINARY DATA SHEET
MOS INTEGRATED CIRCUIT
8-BIT SINGLE-CHIP MICROCONTROLLER
µ
PD78F0034Y
DESCRIPTION
The
µ
PD78F0034Y is a product of the
µ
PD780034Y Subseries in the 78K/0 Series and equivalent to the
µ
PD780034Y with a flash memory in place of internal ROM.
The
µ
PD78F0034Y incorporates a flash memory, which can be programmed and erased without being removed
from the substrate.
Functions are described in detail in the following user’s manuals. Be sure to read them before designing.
µ
PD780024, 780024Y, 780034, 780034Y Subseries User’s Manual : U12022E
78K/0 Series User’s Manual — Instructions : U12326E
FEATURES
•I
2
C bus serial interface supporting multimaster
• Pin-compatible with mask ROM versions (except VPP pin)
• Flash memory : 32 Kbytes
• Internal high-speed RAM : 1024 bytesNote
• Power supply voltage : VDD = 2.7 to 5.5 V
Note The flash memory and internal high-speed RAM capacities can be changed with the memory size
switching register (IMS).
Remark For the differences between the flash memory versions and the mask ROM versions, refer to 1.
DIFFERENCES BETWEEN
µ
PD78F0034Y AND MASK ROM VERSIONS.
ORDERING INFORMATION
Part Number Package Internal ROM
µ
PD78F0034YCW 64-pin plastic shrink DIP (750 mils) Flash memory
µ
PD78F0034YGC-AB8 64-pin plastic QFP (14 × 14 mm) Flash memory
µ
PD78F0034YGK-8A8 64-pin plastic LQFP (12 × 12 mm) Flash memory
The information in this document is subject to change without notice.
The mark shows major revised points.
Document No. U11994EJ1V0DS00 (1st edition)
Date Published March 1998 N CP (K)
Printed in Japan
µ
PD78F0034Y
2 Preliminary Data Sheet
78K/0 SERIES DEVELOPMENT
The products in the 78K/0 Series are listed below. The names enclosed in boxes are subseries names.
Note Under planning
PD78014
PD78002
PD78083 PD78002Y
100-pin
100-pin
100-pin
64-pin
64-pin
64-pin
42/44-pin
Control
Y subseries products are compatible with I2C bus.
Timer was added to the PD78054, and external interface function was enhanced
EMI-noise reduced version of the PD78078
ROM-less versions of the PD78078
A/D converter and 16-bit timer were added to the PD78002
A/D converter was added to the PD78002
Basic subseries for control
On-chip UART, capable of operating at a low voltage (1.8 V)
PD780018AY
100-pin Serial I/O of the PD78078Y was enhanced, and only selected functions are provided
PD78078
PD78070A
PD78075B
PD78070AY
µ
µ
µµ
µ
µµ
µ
µµ
µ
µ
µ
µ
µ
µ
Inverter control
PD78096464-pin
µ
A/D converter of the PD780924 was enhanced
PD78078Y
µ
PD78018F
PD780001
PD78018FY
PD78014Y
80-pin
80-pin
64-pin
78K/0
Series
Products in mass production
Products under development
EMI-noise reduced version of the PD78054
UART and D/A converter were added to the PD78014, and I/O was enhanced
Low-voltage (1.8 V) operation versions of the PD78014 with several ROM and RAM capacities available
A/D converter of the PD780024 was enhanced
EMI-noise reduced version of the PD78018F
On-chip inverter control circuit and UART, EMI-noise reduced version
Serial I/O of the PD78018F was enhanced
Serial I/O of the PD78054 was enhanced, EMI-noise reduced version
PD78005880-pin
µ
µµ
PD780034
PD780024
PD78014H
PD780034Y
PD780024Y
64-pin
64-pin
64-pin
µµ
µµ
µ
µ
µ
µ
µ
µ
µ
µ
µ
FIPTM drive
PD78044F
100-pin
80-pin
80-pin
µ
µ
I/O and FIP C/D of the PD78044F were enhanced, Display output total: 53
I/O and FIP C/D of the PD78044H were enhanced, Display output total: 48
N-ch open-drain input/output was added to the PD78044F, Display output total: 34
Basic subseries for driving FIP, Display output total: 34
µµ
100-pin
PD78092464-pin
µ
PD780308
PD78064B
PD78064
100-pin
100-pin
100-pin
µ
µ
SIO of the PD78064 was enhanced, and ROM and RAM capacities were expanded
EMI-noise reduced version of the PD78064
Basic subseries for driving LCDs, On-chip UART
µ
PD780308Y
µ
PD78064Y
µ
LCD drive
µµ
IEBusTM supported
Meter control
PD7809880-pin
µ
IEBus controller was added to the PD78054
PD780973
80-pin
µ
On-chip automobile meter drive controller/driver
PD78054
µ
PD78054Y
µ
PD78058FY
µ
PD780058YNote
µ
PD78058F
µ
PD78044H
µ
µ
PD780228
PD780208
µ
µ
PD78098864-pin
µ
Inverter control, timer, and SIO of the PD780964 were enhanced, and ROM and RAM
capacities were expanded.
µ
PD78098B80-pin
µ
EMI-noise reduced version of the PD78098
µµ
µ
PD78F0034Y
3Preliminary Data Sheet
The major functional differences among the Y subseries are shown below.
Function ROM Capacity Configuration of Serial Interface I/O VDD MIN.
Subseries Name Value
Control
µ
PD78078Y 48 K to 60 K 3-wire/2-wire/I2C : 1 ch 88 1.8 V
3-wire with automatic transmit/receive function : 1 ch
µ
PD78070AY – 3-wire/UART : 1 ch 61 2.7 V
µ
PD780018AY 48 K to 60 K 3-wire with automatic transmit/receive function : 1 ch 88
Time-division 3-wire : 1 ch
I2C bus (multimaster supported) : 1 ch
µ
PD780058Y 24 K to 60 K 3-wire/2-wire/I2C : 1 ch 68 1.8 V
3-wire with automatic transmit/receive function : 1 ch
3-wire/time-division UART : 1 ch
µ
PD78058FY 48 K to 60 K 3-wire/2-wire/I2C : 1 ch 69 2.7 V
3-wire with automatic transmit/receive function : 1 ch
µ
PD78054Y 16 K to 60 K 3-wire/UART : 1 ch 2.0 V
µ
PD780034Y 8 K to 32 K UART : 1 ch 51 1.8 V
3-wire : 1 ch
µ
PD780024Y I2C bus (multimaster supported) : 1 ch
µ
PD78018FY 8 K to 60 K 3-wire/2-wire/I2C : 1 ch 53
3-wire with automatic transmit/receive function : 1 ch
µ
PD78014Y 8 K to 32 K 3-wire/2-wire/SBI/I2C : 1 ch 2.7 V
3-wire with automatic transmit/receive function : 1 ch
µ
PD78002Y 8 K to 16 K 3-wire/2-wire/SBI/I2C : 1 ch
LCD
µ
PD780308Y 48 K to 60 K 3-wire/2-wire/I2C : 1 ch 57 2.0 V
drive 3-wire/time-division UART : 1 ch
3-wire : 1 ch
µ
PD78064Y 16 K to 32 K 3-wire/2-wire/I2C : 1 ch
3-wire/UART : 1 ch
Remark The functions other than the serial interface are common to the subseries without Y.
µ
PD78F0034Y
4 Preliminary Data Sheet
OVERVIEW OF FUNCTION
Item Function
Internal Flash memory 32 KbytesNote
memory High-speed RAM 1024 bytesNote
Memory space 64 Kbytes
General-purpose registers 8 bits × 32 registers (8 bits × 8 registers × 4 banks)
Minimum instruction execution time On-chip minimum instruction execution time cycle modification function
When main system 0.24
µ
s/0.48
µ
s/0.95
µ
s/1.91
µ
s/3.81
µ
s (at 8.38-MHz operation)
clock selected
When subsystem 122
µ
s (at 32.768-kHz operation)
clock selected
Instruction set • 16-bit operate • multiply/divide (8 bits × 8 bits, 16 bits ÷ 8 bits)
• Bit manipulate (set, reset, test, Boolean operation)
• BCD adjust, etc.
I/O ports Total : 51
• CMOS input : 8
• CMOS I/O : 39
• N-ch open-drain I/O (5-V withstand voltage) : 4
A/D converter • 10-bit resolution × 8 channels
Serial interface • 3-wire serial I/O mode : 1 channel
• UART mode : 1 channel
• I2C bus mode (multimaster supported) : 1 channel
Timer • 16-bit timer/event counter : 1 channel
• 8-bit timer/event counter : 2 channels
• Watch timer : 1 channel
• Watchdog timer : 1 channel
Timer output 3 (8-bit PWM output capable: 2)
Clock output 131 kHz, 262 kHz, 524 kHz, 1.05 MHz, 2.10 MHz, 4.19 MHz, 8.38 MHz (at 8.38-MHz
operation with main system clock)
32.768 kHz (at 32.768-kHz operation with subsystem clock)
Buzzer output 1.02 kHz, 2.05 kHz, 4.10 kHz, 8.19 kHz (at 8.38-MHz operation with main system clock)
Vectored interrupt Maskable Internal : 13, External : 5
source Non-maskable Internal : 1
Software 1
Test input Internal : 1, External : 1
Power supply voltage VDD = 2.7 to 5.5 V
Operating ambient temperature TA = –40 to +85°C
Package • 64-pin plastic shrink DIP (750 mils)
• 64-pin plastic QFP (14 × 14 mm)
• 64-pin plastic LQFP (12 × 12 mm)
Note The capacities of the flash memory and the internal high-speed RAM can be changed with the memory
size switching register (IMS).
µ
PD78F0034Y
5Preliminary Data Sheet
PIN CONFIGURATION (TOP VIEW)
• 64-pin Plastic Shrink DIP (750 mils)
µ
PD78F0034YCW
Cautions 1. Connect the VPP pin directly to VSS0 or VSS1 in normal operation mode.
2. Connect the AVSS pin to VSS0.
Remark When the
µ
PD78F0034Y is used in application fields that require reduction of the noise generated
from inside the microcontroller, the implementation of noise reduction measures, such as supplying
voltage to VDD0 and VDD1 independently and connecting VSS0 and VSS1 to different ground lines, is
recommended.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
P67/ASTB
P66/WAIT
P65/WR
P64/RD
P75/BUZ
P74/PCL
P73/TI51/TO51
P72/TI50/TO50
P71/TI01
P70/TI00/TO0
P03/INTP3/ADTRG
P02/INTP2
P01/INTP1
P00/INTP0
V
SS1
X1
X2
V
PP
XT1
XT2
RESET
AV
DD
AV
REF
P10/ANI0
P11/ANI1
P12/ANI2
P13/ANI3
P14/ANI4
P15/ANI5
P16/ANI6
P17/ANI7
AV
SS
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
P40/AD0
P41/AD1
P42/AD2
P43/AD3
P44/AD4
P45/AD5
P46/AD6
P47/AD7
P50/A8
P51/A9
P52/A10
P53/A11
P54/A12
P55/A13
P56/A14
P57/A15
V
SS0
V
DD0
P30
P31
P32/SDA0
P33/SCL0
P34
P35
P36
P20/SI30
P21/SO30
P22/SCK30
P23/RxD0
P24/TxD0
P25/ASCK0
V
DD1
µ
PD78F0034Y
6 Preliminary Data Sheet
• 64-pin Plastic QFP (14 × 14 mm)
µ
PD78F0034YGC-AB8
• 64-pin Plastic LQFP (12 × 12 mm)
µ
PD78F0034YGK-8A8
Cautions 1. Connect the VPP pin directly to VSS0 or VSS1 in normal operation mode.
2. Connect the AVSS pin to VSS0.
Remark When the
µ
PD78F0034Y is used in application fields that require reduction of the noise generated
from inside the microcontroller, the implementation of noise reduction measures, such as supplying
voltage to VDD0 and VDD1 independently and connecting VSS0 and VSS1 to different ground lines, is
recommended.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
P50/A8
P51/A9
P52/A10
P53/A11
P54/A12
P55/A13
P56/A14
P57/A15
V
SS0
V
DD0
P30
P31
P32/SDA0
P33/SCL0
P34
P35
P36
P20/SI30
P21/SO30
P22/SCK30
P23/RxD0
P24/TxD0
P25/ASCK0
V
DD1
AV
SS
P17/ANI7
P16/ANI6
P15/ANI5
P14/ANI4
P13/ANI3
P12/ANI2
P11/ANI1
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
P71/TI01
P70/TI00/TO0
P03/INTP3/ADTRG
P02/INTP2
P01/INTP1
P00/INTP0
V
SS1
X1
X2
V
PP
XT1
XT2
RESET
AV
DD
AV
REF
P10/ANI0
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
P47/AD7
P46/AD6
P45/AD5
P44/AD4
P43/AD3
P42/AD2
P41/AD1
P40/AD0
P67/ASTB
P66/WAIT
P65/WR
P64/RD
P75/BUZ
P74/PCL
P73/TI51/TO51
P72/TI50/TO50
µ
PD78F0034Y
7Preliminary Data Sheet
A8 to A15 : Address Bus PCL : Programmable Clock
AD0 to AD7 : Address/Data Bus RD : Read Strobe
ADTRG : AD Trigger Input RESET : Reset
ANI0 to ANI7 : Analog Input RxD0 : Receive Data
ASCK0 : Asynchronous Serial Clock SCK30 : Serial Clock
ASTB : Address Strobe SCL0 : Serial Clock
AVDD : Analog Power Supply SDA0 : Serial Data
AVREF : Analog Reference Voltage SI30 : Serial Input
AVSS : Analog Ground SO30 : Serial Output
BUZ : Buzzer Clock TI00, TI01, TI50, TI51 : Timer Input
INTP0 to INTP3 : Interrupt from Peripherals TO0, TO50, TO51 : Timer Output
P00 to P03 : Port 0 TxD0 : Transmit Data
P10 to P17 : Port 1 VDD0, VDD1 : Power Supply
P20 to P25 : Port 2 VPP : Programming Power Supply
P30 to P36 : Port 3 VSS0, VSS1 : Ground
P40 to P47 : Port 4 WAIT : Wait
P50 to P57 : Port 5 WR : Write Strobe
P64 to P67 : Port 6 X1, X2 : Crystal (Main System Clock)
P70 to P75 : Port 7 XT1, XT2 : Crystal (Subsystem Clock)
µ
PD78F0034Y
8 Preliminary Data Sheet
BLOCK DIAGRAM
TI00/TO0/P70 16-bit TIMER/
EVENT COUNTER
SERIAL
INTERFACE30
INTERRUPT
CONTROL
BUZZER OUTPUT
CLOCK OUTPUT
CONTROL
78K/0
CPU CORE
PORT0
PORT1
PORT2
PORT3
PORT4
PORT5
PORT6
PORT7 P70 to P75
P64 to P67
P50 to P57
P40 to P47
P30 to P36
P20 to P25
P10 to P17
P00 to P03
EXTERNAL
ACCESS
SYSTEM
CONTROL
RESET
X1
X2
XT1
XT2
RD/P64
WR/P65
WAIT/P66
ASTB/P67
AD0/P40 to
AD7/P47
A8/P50 to
A15/P57
FLASH
MEMORY
(32 Kbytes)
RAM
(1024 bytes)
A/D CONVERTER
I
2
C BUS
V
DD0
V
DD1
V
SS0
V
SS1
V
PP
WATCHDOG TIMER
WATCH TIMER
8-bit TIMER/
EVENT COUNTER50
8-bit TIMER/
EVENT COUNTER51
TI50/TO50/P72
TI51/TO51/P73
SI30/P20
SO30/P21
SCK30/P22
SDA0/P32
SCL0/P33
UART0
RxD0/P23
TxD0/P24
ASCK0/P25
AV
DD
AV
SS
AV
REF
BUZ/P75
PCL/P74
ANI0/P10 to
ANI7/P17
INTP0/P00 to
INTP3/P03
TI01/P71
µ
PD78F0034Y
9Preliminary Data Sheet
CONTENTS
1. DIFFERENCES BETWEEN
µ
PD78F0034Y AND MASK ROM VERSIONS....................................... 10
2. PIN FUNCTIONS ................................................................................................................................. 11
2.1 Port Pins..................................................................................................................................................... 11
2.2 Non-Port Pins ............................................................................................................................................ 12
2.3 Pin I/O Circuits and Recommended Connection of Unused Pins ..................................................... 14
3. MEMORY SIZE SWITCHING REGISTER (IMS) ................................................................................. 16
4. FLASH MEMORY PROGRAMMING................................................................................................... 17
4.1 Selection of Transmission Method......................................................................................................... 17
4.2 Function of Flash Memory Programming.............................................................................................. 18
4.3 Connection of Flashpro II ........................................................................................................................ 18
5. ELECTRICAL SPECIFICATIONS .......................................................................................................20
6. PACKAGE DRAWINGS ......................................................................................................................38
APPENDIX A. DEVELOPMENT TOOLS ................................................................................................41
APPENDIX B. RELATED DOCUMENTS ................................................................................................ 47
µ
PD78F0034Y
10 Preliminary Data Sheet
1. DIFFERENCES BETWEEN
µ
PD78F0034Y AND MASK ROM VERSIONS
The
µ
PD78F0034Y is a product provided with a flash memory that enables on-board writing, erasing, and
rewriting of programs with the device mounted on the target system.
The functions of the
µ
PD78F0034Y (except the functions specified for flash memory) can be made the same
as those of the mask ROM versions by setting the memory size switching register (IMS).
Table 1-1 shows the differences between the flash memory version (
µ
PD78F0034Y) and the mask ROM
versions (
µ
PD780031Y, 780032Y, 780033Y, and 780034Y).
Table 1-1. Differences between
µ
PD78F0034Y and Mask ROM Versions
Item
µ
PD78F0034 Mask ROM Versions
Internal ROM type Flash memory Mask ROM
Internal ROM capacity 32 Kbytes
µ
PD780031Y : 8 Kbytes
µ
PD780032Y : 16 Kbytes
µ
PD780033Y : 24 Kbytes
µ
PD780034Y : 32 Kbytes
Internal high-speed RAM capacity 1024 bytes
µ
PD780031Y : 512 bytes
µ
PD780032Y : 512 bytes
µ
PD780033Y : 1024 bytes
µ
PD780034Y : 1024 bytes
Internal ROM and internal high-speed
ChangeableNote Not changeable
RAM capacity changeable/not changeable
with memory size switching register (IMS)
IC pin Not provided Provided
VPP pin Provided Not provided
Power supply voltage VDD = 2.7 to 5.5 V VDD = 1.8 to 5.5 V
Electrical specifications, Refer to the data sheet of individual products.
recommended soldering conditions
Note Flash memory is set to 32 Kbytes and internal high-speed RAM is set to 1024 bytes by RESET input.
Caution There are differences in noise immunity and noise radiation between the flash memory
versions and mask ROM versions. When pre-producing an application set with the flash
memory version and then mass-producing it with the mask ROM version, be sure to conduct
sufficient evaluation for commercial samples (not engineering samples) of the mask ROM
version.
µ
PD78F0034Y
11
Preliminary Data Sheet
2. PIN FUNCTIONS
2.1 Port Pins (1/2)
Pin Name I/O Function
After Reset
Alternate
Function
P00 I/O Input INTP0
P01 INTP1
P02 INTP2
P03
INTP3/ADTRG
P10 to P17 Input Input ANI0 to ANI7
P20 I/O Input SI30
P21 SO30
P22 SCK30
P23 RxD0
P24 TxD0
P25 ASCK0
P30 I/O Input —
P31
P32 SDA0
P33 SCL0
P34 —
P35
P36
P40 to P47 I/O Input AD0 to AD7
P50 to P57 I/O Input A8 to A15
P64 I/O Input RD
P65 WR
P66 WAIT
P67 ASTB
Port 0
4-bit input/output port.
Input/output can be specified bit-wise.
When used as an input port, an on-chip pull-up resistor can be used by
software.
Port 1
8-bit input only port.
Port 2
6-bit input/output port.
Input/output can be specified bit-wise.
When used as an input port, an on-chip pull-up resistor can be used by
software.
Port 3 N-ch open-drain input/output port.
7-bit input/output port. LEDs can be driven directly.
Input/output can be specified
bit-wise.
When used as an input port, an on-chip pull-
up resistor can be used by software.
Port 4
8-bit input/output port.
Input/output can be specified bit-wise.
When used as an input port, an on-chip pull-up resistor can be used by
software.
Test input flag (KRIF) is set to 1 by the falling-edge detection.
Port 5
8-bit input/output port.
LEDs can be driven directly.
Input/output can be specified bit-wise.
When used as an input port, an on-chip pull-up resistor can be used by
software.
Port 6
4-bit input/output port.
Input/output can be specified bit-wise.
When used as an input port, an on-chip pull-up resistor can be used by
software.
µ
PD78F0034Y
12 Preliminary Data Sheet
2.1 Port Pins (2/2)
Pin Name I/O Function
After Reset
Alternate
Function
P70 I/O Input TI00/TO0
P71 TI01
P72 TI50/TO50
P73 TI51/TO51
P74 PCL
P75 BUZ
2.2 Non-Port Pins (1/2)
Pin Name I/O Function
After Reset
Alternate
Function
INTP0 Input External interrupt request input for which the effective edge (rising edge, Input P00
INTP1 falling edge, or both rising edge and falling edge) can be specified. P01
INTP2 P02
INTP3 P03/ADTRG
SI30 Input Serial interface serial data input. Input P20
SO30 Output Serial interface serial data output. Input P21
SDA0 I/O Serial interface serial data input/output. Input P32
SCK30 I/O Serial interface serial clock input/output. Input P22
SCL0 P33
RxD0 Input Serial data input for asynchronous serial interface. Input P23
TxD0 Output Serial data output for asynchronous serial interface. Input P24
ASCK0 Input Serial clock input for asynchronous serial interface. Input P25
TI00 Input External count clock input to 16-bit timer (TM0). Input P70/TO0
Capture trigger signal input to TM0 capture register (CR01).
TI01 Capture trigger signal input to TM0 capture register (CR00). P71
TI50 External count clock input to 8-bit timer (TM50). P72/TO50
TI51 External count clock input to 8-bit timer (TM51). P73/TO51
TO0 Output 16-bit timer (TM0) output. Input P70/TI00
TO50 8-bit timer (TM50) output (alternate function is 8-bit PWM output). Input P72/TI50
TO51 8-bit timer (TM51) output (alternate function is 8-bit PWM output). P73/TI51
PCL Output Clock output (for trimming of main system clock and subsystem clock). Input P74
BUZ Output Buzzer output. Input P75
AD0 to AD7 I/O Lower address/data bus for extending memory externally. Input P40 to P47
A8 to A15 Output Higher address bus for extending memory externally. Input P50 to P57
RD Output Strobe signal output for read operation of external memory. Input P64
WR Strobe signal output for write operation of external memory. P65
WAIT Input Inserting wait for accessing external memory. Input P66
ASTB Output Strobe output that externally latches address information output to Input P67
port 4 and port 5 to access external memory.
Port 7
6-bit input/output port.
Input/output can be specified bit-wise.
When used as an input port, an on-chip pull-up resistor can be used by
software.
µ
PD78F0034Y
13
Preliminary Data Sheet
2.2 Non-Port Pins (2/2)
Pin Name I/O Function
After Reset
Alternate
Function
ANI0
to
ANI7 Input A/D converter analog input. Input P10 to P17
ADTRG Input A/D converter trigger signal input. Input P03/INTP3
AVREF Input A/D converter reference voltage input. — —
AVDD — A/D converter analog power supply. — —
Set the voltage equal to VDD0 or VDD1.
AVSS — A/D converter ground potential. — —
Set the voltage equal to VSS0 or VSS1.
RESET Input System reset input. — —
X1 Input Connecting crystal resonator for main system clock oscillation. — —
X2 — ——
XT1 Input Connecting crystal resonator for subsystem clock oscillation. — —
XT2 — ——
VDD0 — Positive power supply for ports. — —
VSS0 — Ground potential of ports. — —
VDD1 — Positive power supply (except ports). — —
VSS1 — Ground potential (except ports). — —
VPP — Applying high voltage for program write/verify. Connect directly to VSS0 ——
or VSS1 in normal operation mode.
µ
PD78F0034Y
14 Preliminary Data Sheet
2.3 Pin I/O Circuits and Recommended Connection of Unused Pins
Table 2-1 shows the types of pin I/O circuits and recommended connection of unused pins.
Refer to Figure 2-1 about the configuration of each type of I/O circuit.
Table 2-1. Pin I/O Circuit Type
Pin Name Input/output Circuit Type Input/Output Recommended Connection of Unused Pins
P00/INTP0 8-C Input Independently connect to VSS0 via a resistor.
P01/INTP1
P02/INTP2
P03/INTP3
P10/ANI0 to P17/ANI7 25 Input Independently connect to VDD0 or VSS0 via a resistor.
P20/SI30 8-C Input/output
P21/SO30 5-H
P22/SCK30 8-C
P23/RxD0
P24/TxD0 5-H
P25/ASCK0 8-C
P30, P31 13-P Input/output Independently connect to VDD0 via a resistor.
P32/SDA0 13-R
P33/SCL0
P34 8-C Independently connect to VDD0 or VSS0 via a resistor.
P35 5-H
P36 8-C
P40/AD0 to P47/AD7 5-H Input/output Independently connect to VDD0 via a resistor.
P50/A8 to P57/A15 5-H Input/output Independently connect to VDD0 or VSS0 via a resistor.
P64/RD Input/output
P65/WR
P66/WAIT
P67/ASTB
P70/TI00/TO0 8-C
P71/TI01
P72/TI50/TO50
P73/TI51/TO51
P74/PCL 5-H
P75/BUZ
RESET 2 Input —
XT1 16 Connect to VDD0.
XT2 — Leave open.
AVDD — Connect to VDD0.
AVREF Connect to VSS0.
AVSS
VPP Connect directly to VSS0 or VSS1.
µ
PD78F0034Y
15
Preliminary Data Sheet
Figure 2-1 Pin Input/Output Circuit
TYPE 2
Schmitt-Triggered Input with Hysteresis Characteristics
IN
TYPE 8-C
data
output
disable
P-ch
IN/OUT
V
DD0
N-ch
P-ch
V
DD0
pullup
enable
TYPE 5-H
data
output
disable
P-ch
IN/OUT
V
DD0
N-ch
input
enable
P-ch
V
DD0
pullup
enable
TYPE 16
data
output disable
IN/OUT
N-ch
data
output disable
IN/OUT
N-ch
TYPE 13-R
input
enable
V
SS0
TYPE 25
V
SS0
V
SS0
V
SS0
P-ch
feedback
cut-off
XT1 XT2
TYPE 13-P
input
enable
Comparator +
–
P-ch
N-ch
V
REF
(threshold voltage)
V
SS0
IN
µ
PD78F0034Y
16 Preliminary Data Sheet
3. MEMORY SIZE SWITCHING REGISTER (IMS)
This register sets a part of internal memory not used by software. The memory mapping can be made the same
as that of mask ROM versions with different types of internal memory (ROM and RAM).
The IMS is set with an 8-bit memory manipulation instruction.
RESET input sets the IMS to CFH.
Figure 3-1. Format of Memory Size Switching Register
Table 3-1 shows the IMS set value to make the memory mapping the same as those of mask ROM versions.
Table 3-1. Set Value of Memory Size Switching Register
Target Mask ROM Versions IMS Set Value
µ
PD780031Y 42H
µ
PD780032Y 44H
µ
PD780033Y C6H
µ
PD780034Y C8H
Caution When using mask ROM versions, set values indicated in Table 3-1 to IMS.
IMS RAM2 RAM1 RAM0 0 ROM3 ROM2 ROM1 ROM0
ROM3
0
0
0
1
ROM2
0
1
1
0
ROM1
1
0
1
0
ROM0
0
0
0
0
Selection of Internal ROM Capacity
8 Kbytes
16 Kbytes
24 Kbytes
32 Kbytes
1 1 1 1 60 Kbytes (setting prohibited)
Other than above Setting prohibited
76543210
FFF0H CFH W
Address After reset R/W
RAM2
0
1
RAM1
1
1
RAM0
0
0
Selection of Internal High-speed RAM Capacity
512 bytes
1024 bytes
Other than above Setting prohibited
µ
PD78F0034Y
17
Preliminary Data Sheet
4. FLASH MEMORY PROGRAMMING
Writing to a flash memory can be performed without removing the memory from the target system. Writing is
performed connecting the dedicated flash memory programmer (Flashpro II) to the host machine and the target
system.
Also, it can be performed on an adapter for flash memory writing connected to the Flashpro II.
Remark Flashpro II is a product of Naitou Densei Machidaseisakusho Co., Ltd.
4.1 Selection of Transmission Method
Writing to a flash memory is performed using the Flashpro II with a serial transmission mode. One of the
transmission methods in Table 4-1 is selected. The selection of the transmission method is made by using the
format shown in Figure 4-1. Each transmission method is selected by the number of VPP pulses shown in Table
4-1.
Table 4-1. Transmission Methods
Transmission Method Channels Pin VPP Pulses
3-wire serial I/O 1 SI30/P20 0
SO30/P21
SCK30/P22
UART 1 RxD0/P23 8
TxD0/P24
ASCK0/P25
I2C bus 1 SDA0/P32 4
SCL0/P33
Pseudo 3-wire serial I/O 1 P72/TI50/TO50 12
(serial clock input)
P71/TI01
(serial data output)
P70/TI00/TO0
(serial data input)
Caution Be sure to select a communication system using the number of VPP pulses shown in Table
4-1.
Figure 4-1. Format of Transmission Method Selection
1
10 V
V
PP
pulses
Flash write mode
V
PP
RESET
V
DD
V
SS
V
DD
V
SS
2n
µ
PD78F0034Y
18 Preliminary Data Sheet
4.2 Function of Flash Memory Programming
Operations such as writing to a flash memory are performed by various command/data transmission and
reception operations according to the selected transmission method. Table 4-2 shows major functions of flash
memory programming.
Table 4-2. Major Functions of Flash Memory Programming
Functions Descriptions
Reset Used to stop write operation and detect transmission cycle.
Batch verify Compares the entire memory contents with the input data.
Batch delete Deletes the entire memory contents.
Batch blank check Checks the deletion status of the entire memory.
High-speed write Performs write to the flash memory based on the write start address and the number of data
to be written (number of bytes).
Continuous write Performs continuous write based on the information input with high-speed write operation.
Status Used to confirm the current operating mode and operation end.
Oscillation frequency setting Sets the frequency of the resonator.
Delete time setting Sets the memory delete time.
Silicon signature read Outputs the device name and memory capacity, and device block information.
4.3 Connection of Flashpro II
The connection of the Flashpro II and the
µ
PD78F0034Y differs according to the transmission method (3-wire
serial I/O, UART, and I2C bus). The connection for each transmission method is shown in Figures 4-2, 4-3, and
4-4, respectively.
Figure 4-2. Connection of Flashpro II for 3-wire Serial I/O System
Flashpro II
V
PP
V
PP
V
DD
V
SS
V
DD
RESET
SCK30
SI30
SO30
PD78F0034Y
RESET
SCK
SO
SI
GND
µ
µ
PD78F0034Y
19
Preliminary Data Sheet
Figure 4-3. Connection of Flashpro II for UART System
Figure 4-4. Connection of Flashpro II for I2C Bus System
Flashpro II
VPPVPP
VDD
VSS
VDD
RESET
RxD0
TxD0
PD78F0034Y
RESET
SO
SI
GND
µ
V
PP
V
DD
RESET
SCK
SI
GND
Flashpro II PD78F0034Y
V
PP
V
DD
RESET
SCL0
µ
V
SS
SDA0
Preliminary Data Sheet20
µ
PD78F0034Y
5. ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings (TA = 25°C)
Parameter Symbol Test Conditions Rating Unit
Supply voltage VDD –0.3 to +6.5 V
VPP –0.3 to +11.0 V
AVDD –0.3 to VDD + 0.3 V
AVREF –0.3 to VDD + 0.3 V
AVSS –0.3 to +0.3 V
Input voltage VI1
P00 to P03, P10 to P17, P20 to P25, P34 to P36, P40 to P47,
–0.3 to VDD + 0.3 V
P50 to P57, P64 to P67, P70 to P75, X1, X2, XT1, XT2,
RESET
VI2 P30 to P33 N-ch Open-drain –0.3 to VDD + 0.3 V
Output voltage VO–0.3 to VDD + 0.3 V
Analog input voltage
VAN P10 to P17 Analog input pin AVSS – 0.3 to AVREF + 0.3 V
and –0.3 to VDD + 0.3
High-level output IOH Per pin –10 mA
current
Total for P00 to P03, P40 to P47, P50 to P57, P64 to P67, P70 to P75
–15 mA
Total for P20 to P25, P30 to P36 –15 mA
Low-level output IOL Note
Per pin for P00 to P03, P20 to P25, P34 to
Peak value 20 mA
current
P36, P40 to P47, P64 to P67, P70 to P75
Effective value 10 mA
Per pin for P30 to P33, P50 to P57 Peak value 30 mA
Effective value 15 mA
Total for P00 to P03, P40 to P47, Peak value 50 mA
P64 to P67, P70 to P75 Effective value 20 mA
Total for P20 to P25 Peak value 20 mA
Effective value 10 mA
Total for P30 to P36 Peak value 100 mA
Effective value 70 mA
Total for P50 to P57 Peak value 100 mA
Effective value 70 mA
Operating ambient TA –40 to +85 °C
temperature
Storage Tstg –65 to +150 °C
temperature
Note The effective value should be calculated as follows: [Effective value] = [Peak value] × √duty
Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for
any parameter. That is, the absolute maximum ratings are rated values at which the product
is on the verge of suffering physical damage, and therefore the product must be used under
conditions that ensure that the absolute maximum ratings are not exceeded.
µ
PD78F0034Y
Preliminary Data Sheet 21
Capacitance (TA = 25°C, VDD = VSS = 0 V)
Parameter Symbol Test Conditions MIN. TYP. MAX. Unit
Input CIN f = 1 MHz 15 pF
capacitance Unmeasured pins returned to 0 V.
I/O CIO f = 1 MHz P00 to P03, P20 to P25, 15 pF
capacitance Unmeasured pins P34 to P36, P40 to P47,
returned to 0 V. P50 to P57, P64 to P67,
P70 to P75,
P30 to P33 20 pF
Remark Unless otherwise specified, the characteristics of the alternate function are the same as those of the
port-pin function.
Main System Clock Oscillator Characteristics (TA = –40 to 85°C, VDD = 2.7 to 5.5 V)
Recommended
Circuit TYP. MAX.
8.38
5.0
4
8.38
5.0
10
30
8.38
5.0
500
500
Unit
MHz
ms
MHz
ms
MHz
ns
Resonator
Ceramic
resonator
Crystal
resonator
External
clock
Parameter
Oscillation
frequency (fX)Note 1
Oscillation
stabilization time
Note 2
Oscillation
frequency (fX)Note 1
Oscillation
stabilization time
Note 2
X1 input
frequency (fX)Note 1
X1 input
high-/low-level width
(tXH , tXL)
MIN.
1.0
1.0
1.0
1.0
1.0
50
85
Test Conditions
VDD = 4.5 to 5.5 V
After VDD reaches oscil-
lation voltage range MIN.
VDD = 4.5 to 5.5 V
VDD = 4.5 to 5.5 V
VDD = 4.5 to 5.5 V
VDD = 4.5 to 5.5 V
Notes 1. Indicates only oscillator characteristics. Refer to AC Characteristics for instruction execution time.
2. Time required to stabilize oscillation after reset or STOP mode release.
Cautions 1. When using the main system clock oscillator, wiring in the area enclosed with the broken
line in the above figures should be carried out as follows to avoid an adverse effect from
wiring capacitance.
• Keep the wiring length as short as possible.
• Do not cross the wiring with the other signal lines.
• Do not route the wiring near a signal line through which a high fluctuating current flows.
• Always keep the ground point of the oscillator to the same potential as VSS1.
• Do not ground the capacitor to a ground pattern in which a high current flows.
• Do not fetch signals from the oscillator.
2. When the main system clock is stopped and the system is operated by the subsystem
clock, switching back to the main system clock should be done after the oscillation
stabilization time has been secured by the program.
X2V
PP
X1
C1C2
X2V
PP
X1
C1C2
X2 X1
PD74HCU04
µ
Preliminary Data Sheet22
µ
PD78F0034Y
MIN.
32
32
Resonator
Crystal
resonator
External
clock
Parameter
Oscillation
frequency (fXT)Note 1
Oscillation
stabilization time
Note 2
XT1 input
frequency (fXT)Note 1
XT1 input
high-/low-level width
(tXTH , tXTL)
Test Conditions TYP.
32.768
1.2
MAX.
35
2
10
100
Unit
kHz
s
kHz
VDD = 4.5 to 5.5 V
Recommended Circuit
515
µ
s
Subsystem Clock Oscillator Characteristics (TA = –40 to +85°C, VDD = 2.7 to 5.5 V)
Notes 1. Indicates only oscillator characteristics. Refer to AC Characteristics for instruction execution time.
2. Time required to stabilize oscillation after VDD reaches oscillation voltage MIN.
Cautions 1. When using the subsystem clock oscillator, wiring in the area enclosed with the broken
line in the above figures should be carried out as follows to avoid an adverse effect from
wiring capacitance.
• Keep the wiring length as short as possible.
• Do not cross the wiring with the other signal lines.
• Do not route the wiring near a signal line through which a high fluctuating current flows.
• Always keep the ground point of the oscillator to the same potential as VSS1.
• Do not ground the capacitor to a ground pattern in which a high current flows.
• Do not fetch signals from the oscillator.
2. The subsystem clock oscillator is a low-amplitude circuit in order to achieve a low
consumption current, and is more prone to malfunction due to noise than the main system
clock oscillator. Particular care is therefore required with the wiring method when the
subsystem clock is used.
C3
XT2 XT1V
PP
R
C4
XT1XT2
µ
PD74HCU04
µ
PD78F0034Y
Preliminary Data Sheet 23
Parameter Symbol Test Conditions MIN. TYP. MAX. Unit
Input voltage, VIH1
P10 to P17, P21, P24, P35, P40 to P47,
0.7VDD VDD V
high
P50 to P57, P64 to P67, P74, P75
VIH2 P00 to P03, P20, P22, P23, P25, 0.8VDD VDD V
P34, P36, P70 to P73, RESET
VIH3 P30 to P33 0.7VDD 5.5 V
(N-ch open-drain)
VIH4 X1, X2 VDD – 0.5 VDD V
VIH5 XT1, XT2 VDD = 4.5 to 5.5 V 0.8VDD VDD V
0.9VDD VDD V
Input voltage, VIL1
P10 to P17, P21, P24, P35, P40 to P47,
0 0.3VDD V
low
P50 to P57, P64 to P67, P74, P75
VIL2 P00 to P03, P20, P22, P23, P25, 0 0.2VDD V
P34, P36, P70 to P73, RESET
VIL3 P30 to P33 VDD = 4.5 to 5.5 V 0 0.3VDD V
0 0.2VDD V
VIL4 X1, X2 0 0.4 V
VIL5 XT1, XT2 VDD = 4.5 to 5.5 V 0 0.2VDD V
0 0.1VDD V
Output voltage, VOH1 VDD = 4.5 to 5.5 V, IOH = –1 mA VDD – 1.0 VDD V
high IOH = –100
µ
AVDD – 0.5 VDD V
Output voltage, VOL1 P30 to P33, P50 to P57 VDD = 4.5 to 5.5 V, 0.4 2.0 V
low IOL = 15 mA
P00 to P03, P20 to P25, VDD = 4.5 to 5.5 V, 0.4 V
P34 to P36, P40 to P47, IOL = 1.6 mA
P64 to P67, P70 to P75
VOL2 IOL = 400
µ
A 0.5 V
DC Characteristics (TA = –40 to +85°C, VDD = 2.7 to 5.5 V)
Remark Unless otherwise specified, the characteristics of the alternate function are the same as those of the
port-pin function.
Preliminary Data Sheet24
µ
PD78F0034Y
Parameter Symbol Test Conditions MIN. TYP. MAX. Unit
Input leakage ILIH1 VIN = VDD
P00 to P03, P10 to P17, P20 to P25,
3
µ
A
current, high
P34 to P36, P40 to P47, P50 to P57,
P64 to P67, P70 to P75,
RESET
ILIH2 X1, X2, XT1, XT2 20
µ
A
ILIH3 VIN = 5.5 V P30 to P33 80
µ
A
Input leakage ILIL1 VIN = 0 V
P00 to P03, P10 to P17, P20 to P25,
–3
µ
A
current, low
P34 to P36, P40 to P47, P50 to P57,
P64 to P67, P70 to P75,
RESET
ILIL2 X1, X2, XT1, XT2 –20
µ
A
ILIL3 P30 to P33 –3
µ
A
Output leakage ILOH VOUT = VDD 3
µ
A
current, low
Output leakage ILOL VOUT = 0 V –3
µ
A
current, low
Software pull- R VIN = 0 V, 15 30 90 kΩ
up resistance P00 to P03, P20 to P25, P34 to P36, P40 to P47,
P50 to P57, P64 to P67, P70 to P75
Power supply IDD1
8.38-MHz crystal oscillation
VDD = 5.0 V ±10% 9.5 19.0 mA
currentNote 1 operating mode
IDD2
8.38-MHz crystal oscillation
VDD = 5.0 V ±10% 1.6 3.2 mA
HALT mode
IDD3
32.768-kHz crystal oscillation
VDD = 5.0 V ±10% 100 200
µ
A
operating modeNote 2 VDD = 3.0 V ±10% 70 140
µ
A
IDD4
32.768-kHz crystal oscillation
VDD = 5.0 V ±10% 25 55
µ
A
HALT modeNote 2 VDD = 3.0 V ±10% 5 15
µ
A
IDD5
XT1 = VDD1, STOP mode
VDD = 5.0 V ±10% 1 30
µ
A
When feedback resistor is used
VDD = 3.0 V ±10% 0.5 10
µ
A
IDD6
XT1 = VDD1, STOP mode
VDD = 5.0 V ±10% 0.1 30
µ
A
When feedback resistor is not used
VDD = 3.0 V ±10% 0.05 10
µ
A
DC Characteristics (TA = –40 to +85°C, VDD = 2.7 to 5.5 V)
Notes 1. Does not include the current flowing into the on-chip pull-up resistor, the AVREF current, and port
current.
2. When the main system clock is stopped.
Remark Unless otherwise specified, the characteristics of the alternate function are the same as those of the
port-pin function.
µ
PD78F0034Y
Preliminary Data Sheet 25
Parameter Symbol Test Conditions MIN. TYP. MAX. Unit
Cycle time TCY Operating with VDD = 4.5 to 5.5 V 0.24 32
µ
s
(Min. instruction main system clock 0.8 32
µ
s
execution time) Operating with subsystem clock 40Note 1 122 125
µ
s
TI00, TI01 input tTIH0, tTIL0 3.5 V ≤ VDD ≤ 5.5 V
2/f
sam
+ 0.1
Note 2
µ
s
high-/low-level width
2/f
sam
+ 0.2
Note 2
µ
s
TI50, TI51 input fTI5 0 4 MHz
frequency
TI50, TI51 input tTIH5, tTIL5 100 ns
high-/low-level
width
Interrupt request tINTH, tINTL INTP0 to INTP3, P40 to P47 1
µ
s
input high-/low
-level width
RESET tRSL 10
µ
s
low-level width
AC Characteristics
(1) Basic Operation
(TA = –40 to +85°C, VDD = 2.7 to 5.5 V)
Notes 1. Value when using the external clock. When using a crystal resonator, the value becomes 114
µ
s
(MIN.).
2. Selection of fsam = fX, fX/4, fX/64 is possible with bits 0 and 1 (PRM00, PRM01) of prescaler mode
register 0 (PRM0). However, if the TI00 valid edge is selected as the count clock, the value becomes
fsam = fX/8.
Preliminary Data Sheet26
µ
PD78F0034Y
TCY vs VDD (at main system clock operation)
32.0
5.0
1.0
2.0
0.8
0.4
0.24
0.1
Supply voltage V
DD
[V]
Cycle time T
CY
[ s]
0
10.0
1.0 2.0 3.0 4.0 5.0 6.0
4.5 5.5
2.7
Operation
Guaranteed
Range
µ
µ
PD78F0034Y
Preliminary Data Sheet 27
Parameter Symbol Test Conditions MIN. MAX. Unit
ASTB high-level width tASTH 0.5tCY ns
Address setup time tADS tCY – 40 ns
Address hold time tADH 6ns
Data input time from address tADD1 (2 + 2n)tCY – 54 ns
tADD2 (3 + 2n)tCY – 60 ns
Address output time from RD↓tRDAD 0 100 ns
Data input time from RD↓tRDD1 (2 + 2n)tCY – 87 ns
tRDD2 (3 + 2n)tCY – 93 ns
Read data hold time tRDH 0ns
RD low-level width tRDL1 (1.5 + 2n)tCY – 33 ns
tRDL2 (2.5 + 2n)tCY – 33 ns
WAIT↓ input time from RD↓tRDWT1 0.5tCY – 43 ns
tRDWT2 tCY – 43 ns
WAIT↓ input time from WR↓tWRWT 0.5tCY – 25 ns
WAIT low-level width tWTL (0.5 + 2n)tCY + 10 (2 + 2n)tCY ns
Write data setup time tWDS 60 ns
Write data hold time tWDH 6ns
WR low-level width tWRL1 (1.5 + 2n)tCY – 15 ns
RD↓ delay time from ASTB↓tASTRD 6ns
WR↓ delay time from ASTB↓tASTWR 2tCY – 15 ns
ASTB↑ delay time from tRDAST 0.8tCY – 15 1.2tCY ns
RD↑ in external fetch
Address hold time from tRDADH 0.8tCY – 15 1.2tCY + 30 ns
RD↑ in external fetch
Write data output time from RD↑tRDWD 40 ns
Write data output time from WR↓tWRWD 10 60 ns
Address hold time from WR↑tWRADH 0.8tCY – 15 1.2tCY + 30 ns
RD↑ delay time from WAIT↑tWTRD 0.8tCY 2.5tCY + 25 ns
WR↑ delay time from WAIT↑tWTWR 0.8tCY 2.5tCY + 25 ns
(2) Read/Write Operation (TA = –40 to + 85°C, VDD = 4.5 to 5.5 V) (1/2)
Remarks 1. tCY = TCY/4
2. n indicates the number of waits.
Preliminary Data Sheet28
µ
PD78F0034Y
Parameter Symbol Test Conditions MIN. MAX. Unit
ASTB high-level width tASTH 0.5tCY ns
Address setup time tADS 0.5tCY – 54 ns
Address hold time tADH 10 ns
Data input time from address tADD1 (2 + 2n)tCY – 108 ns
tADD2 (3 + 2n)tCY – 120 ns
Address output time from RD↓tRDAD 0 200 ns
Data input time from RD↓tRDD1 (2 + 2n)tCY – 148 ns
tRDD2 (3 + 2n)tCY – 162 ns
Read data hold time tRDH 0ns
RD low-level width tRDL1 (1.5 + 2n)tCY – 40 ns
tRDL2 (2.5 + 2n)tCY – 40 ns
WAIT↓ input time from RD↓tRDWT1 0.5tCY – 60 ns
tRDWT2 tCY – 60 ns
WAIT↓ input time from WR↓tWRWT 0.5tCY – 50 ns
WAIT low-level width tWTL (0.5 + 2n)tCY + 10 (2 + 2n)tCY ns
Write data setup time tWDS 60 ns
Write data hold time tWDH 10 ns
WR low-level width tWRL1 (1.5 + 2n)tCY – 30 ns
RD↓ delay time from ASTB↓tASTRD 10 ns
WR↓ delay time from ASTB↓tASTWR 2tCY – 30 ns
ASTB↑ delay time from tRDAST 0.8tCY – 30 1.2tCY ns
RD↑ in external fetch
Address hold time from tRDADH 0.8tCY – 30 1.2t CY + 60 ns
RD↑ in external fetch
Write data output time from RD↑tRDWD 40 ns
Write data output time from WR↓tWRWD 20 120 ns
Address hold time from WR↑tWRADH 0.8tCY – 30 1.2tCY + 60 ns
RD↑ delay time from WAIT↑tWTRD 0.5tCY 2.5tCY + 50 ns
WR↑ delay time from WAIT↑tWTWR 0.5tCY 2.5tCY + 50 ns
(2) Read/Write Operation (TA = –40 to + 85°C, VDD = 2.7 to 4.5 V) (2/2)
Remarks 1. tCY = TCY/4
2. n indicates the number of waits.
µ
PD78F0034Y
Preliminary Data Sheet 29
Parameter Symbol Test Conditions MIN. TYP. MAX. Unit
SCK30 tKCY2 VDD = 4.5 to 5.5 V 800 ns
1600 ns
SCK30, high-/low-level tKH2, tKL2 VDD = 4.5 to 5.5 V 400 ns
width 800 ns
SI30 setup time tSIK2 100 ns
(to SCK30↑)
SI30 hold time tKSI2 400 ns
(from SCK30↑)
SO30 output delay tKSO2 C = 100 pF Note 300 ns
time from SCK30↓
SCK30 rise fall time tR2, tF2 When using external device 160 ns
expansion function
When not using external When using 700 ns
device expansion function 16-bit timer
output
function
When not 1000 ns
using 16-bit
timer
output
function
Parameter Symbol Test Conditions MIN. TYP. MAX. Unit
SCK30 cycle time tKCY1 VDD = 4.5 to 5.5 V 954 ns
1600 ns
SCK30 high-/low-level tKH1, tKL1 VDD = 4.5 to 5.5 V tKCY1/2 – 50 ns
width tKCY1/2 – 100 ns
SI30 setup time tSIK1 VDD = 4.5 to 5.5 V 100 ns
(to SCK30, SCK31↑)150 ns
SI30 hold time tKSI1 400 ns
(from SCK30, SCK31↑)
SO30 output delay tKSO1 C = 100 pFNote 300 ns
time from SCK30↓
(3) Serial Interface (TA = –40 to +85°C, VDD = 2.7 to 5.5 V)
(a) 3-wire serial I/O mode (SCK30 ... Internal clock output)
Note C is the load capacitance of the SCK30, SO30 output lines.
(b) 3-wire serial I/O mode (SCK30 ... External clock input)
Note C is the load capacitance of the SO30 output line.
Preliminary Data Sheet30
µ
PD78F0034Y
Parameter Symbol Test Conditions MIN. TYP. MAX. Unit
Transfer rate VDD = 4.5 to 5.5 V 125000 bps
78125 bps
Parameter Symbol Test Conditions MIN. TYP. MAX. Unit
ASCK0 cycle time tKCY3 VDD = 4.5 to 5.5 V 800 ns
1600 ns
ASCK0 high-/low-level width tKH3, VDD = 4.5 to 5.5 V 400 ns
tKL3 800 ns
Transfer rate VDD = 4.5 to 5.5 V 39063 bps
19531 bps
ASCK0 rise, fall time tR3, VDD = 4.5 to 5.5 V, 1000 ns
tF3 when not using external
device expansion function
160 ns
Parameter Symbol Test Conditions TYP. MAX. Unit
Transfer rate VDD = 4.5 to 5.5 V 115200 bps
Bit rate allowable error VDD = 4.5 to 5.5 V ±0.87 %
Output pulse width VDD = 4.5 to 5.5 V 1.2
0.24/fbr
Note
µ
s
Input pulse width VDD = 4.5 to 5.5 V 4/fX
µ
s
(c) UART mode (Dedicated baud rate generator output)
(d) UART mode (External clock input)
(e) UART mode (Infrared ray data transfer mode)
Note fbr: specified baud rate
µ
PD78F0034Y
Preliminary Data Sheet 31
(f) I2C bus Mode
Standard Mode High-speed Mode Unit
Parameter Symbol MIN. MAX. MIN. MAX.
SCL0 clock frequency fCLK 0 100 0 400 kHz
Bus free time tBUF 4.7 — 1.3 —
µ
s
(between stop and start conditions)
Hold timeNote 1 tHD:STA 4.0 — 0.6 —
µ
s
SCL0 clock low-level width tLOW 4.7 — 1.3 —
µ
s
SCL0 clock high-level width tHIGH 4.0 — 0.6 —
µ
s
Start/restart condition setup time tSU:STA 4.7 — 0.6 —
µ
s
Data hold time CBUS compatible master tHD:DAT 5.0 — — —
µ
s
I2C bus 0Note 2 —0
Note 2 0.9Note 3
µ
s
Data setup time tSU:DAT 250 — 100Note 4 —ns
SDA0 and SCL0 signal rise time tR— 1000 20 + 0.1CbNote 5 300 ns
SDA0 and SCL0 signal fall time tF— 3 00 20 + 0.1CbNote 5 300 ns
Stop condition setup time tSU:STO 4.0 — 0.6 —
µ
s
Spike pulse width controlled by input filter tSP —— 050ns
Capacitive load per each bus line Cb — 400 — 400 pF
Notes 1. On start condition, the first clock pulse is generated after this period.
2. To fulfill undefined area of the SCL0 falling edge, it is necessary for the device to provide internally
SDA0 signal (on VIHmin. of SCL0 signal) with at least 300 ns of hold time.
3. If the device does not extend the SCL0 signal low hold time (tLOW), only maximum data hold time
(tHD:DAT) needs to be fulfilled.
4. The high-speed mode I2C bus is available in the standard mode I2C bus system. At this time, the
conditions described below must be satisfied.
• If the device does not extend the SCL0 signal low state hold time
tSU:DAT ≥ 250 ns
• If the device extends the SCL0 signal low state hold time
Be sure to transmit the next data bit to the SDA0 line before the SCL0 line is released (tRmax. +
tSU:DAT = 1000 + 250 = 1250 ns by standard mode I2C bus specification).
5. Cb : total capacitance per one bus line (unit : pF)
Preliminary Data Sheet32
µ
PD78F0034Y
AC Timing Test Point (Excluding X1, XT1 Input)
Clock Timing
TI Timing
0.8 V
DD
0.2 V
DD
0.8 V
DD
0.2 V
DD
Test Points
tXL tXH
1/fX
VIH4 (MIN.)
VIL4 (MAX.)
tXTL tXTH
1/fXT
VIH5 (MIN.)
VIL5 (MAX.)
X1 Input
XT1 Input
t
TIL0
t
TIH0
TI00, TI01
1/f
TI5
t
TIH5
t
TIL5
TI50, TI51
µ
PD78F0034Y
Preliminary Data Sheet 33
Read/Write Operation
External Fetch (No Wait) :
External Fetch (Wait Insertion) :
tASTH tADH
tADD1
Hi-z
tADS tRDD1 tRDADH
tRDAST
tASTRD tRDL1 tRDH
A8 to A15
AD0 to AD7
ASTB
RD
Higher 8-Bit Address
Instruction
Code
Lower 8-Bit
Address
t
ASTH
t
ADH
t
ADD1
Hi-z
t
ADS
t
RDADH
t
RDAST
t
ASTRD
t
RDL1
t
RDH
A8 to A15
AD0 to AD7
ASTB
RD
t
WTRD
t
WTL
t
RDWT1
WAIT
t
RDD1
Higher 8-Bit Address
Instruction
Code
Lower 8-Bit
Address
Preliminary Data Sheet34
µ
PD78F0034Y
External Data Access (No Wait) :
External Data Access (Wait Insertion) :
t
ASTRD
t
ASTH
t
ADH
t
ADD2
Hi-z
t
ADS
t
RDL2
A8 to A15
AD0 to AD7
ASTB
RD
t
WDS
t
WRL1
WR
t
RDH
Hi-z
Hi-z
t
WRWD
t
ASTWR
t
WRADH
Higher 8-Bit Address
Write DataRead Data
Lower
8-Bit
Address
t
RDD2
t
WDH
t
RDWD
t
ASTRD
t
ASTH
t
ADH
t
ADD2
Hi-z
t
ADS
t
RDL2
A8 to A15
AD0 to AD7
ASTB
RD
t
WDS
t
WRL1
WR
t
RDH
Hi-z
Hi-z
t
WRWD
t
ASTWR
t
WRADH
Higher 8-Bit Address
Write DataRead Data
Lower
8-Bit
Address
t
RDD2
t
WDH
t
RDWT2
t
WTL
t
WRWT
t
WTWR
t
WTL
WAIT
t
WTRD
t
RDWD
µ
PD78F0034Y
Preliminary Data Sheet 35
Serial Transfer Timing
3-wire Serial I/O Mode :
UART Mode (External Clock Input) :
tKCYm
tKLm tKHm
SCK30
SI30
SO30
tSIKm tKSIm
tKSOm
Input Data
Output Data
tRn tFn
m = 1, 2
n = 2
t
KCY3
t
KH3
t
KL3
t
F3
t
R3
ASCK0
I2C Bus Mode
SCL0
SDA0
t
HD:STA
t
BUF
t
HD:DAT
t
HIGH
t
F
t
SU:DAT
t
SU:STA
t
HD:STA
t
SP
t
SU
:
STO
t
R
Stop
condition Start
condition Stop
condition
Restart
condition
Preliminary Data Sheet36
µ
PD78F0034Y
Parameter Symbol Test Conditions MIN. TYP. MAX. Unit
Resolution 10 10 10 bit
Overall errorNote AVREF = 4.5 to 5.5 V ±0.4 %
±0.7 %
Conversion time TCONV AVREF = 4.5 to 5.5 V 14 200
µ
s
20 200
µ
s
Analog input voltage VIAN 0
AVREF + 0.3
V
Reference voltage AVREF 2.7 AVDD V
AVREF resistance RAIREF 10 20 kΩ
Parameter Symbol Test Conditions MIN. TYP. MAX. Unit
Data retention power VDDDR 1.6 5.5 V
supply voltage
Data retention IDDDR VDDDR = 1.6 V 0.1 10
µ
A
power supply Subsystem clock stops and feed-back resistor
current disconnected
Release signal set time
tSREL 0
µ
s
Oscillation stabilization tWAIT Release by RESET 217/fx ms
wait time Release by interrupt request Note ms
A/D Converter Characteristics (TA = –40 to 85°C, VDD = AVDD = AVREF = 2.7 to 5.5 V, AVSS = VSS = 0 V)
Note Excluding quantization error (±1/2LSB). Shown as a percentage of the full scale value.
Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics (TA = –40 to +85°C)
Note Selection of 212/fX and 214/fX to 217/fX is possible with bits 0 to 2 (OSTS0 to OSTS2) of the oscillation
stabilization time select register (OSTS).
Data Retention Timing (STOP Mode Release by RESET)
t
SREL
t
WAIT
V
DD
RESET
STOP Mode
Data Retention Mode
Internal Reset Operation
HALT Mode
Operating Mode
V
DDDR
STOP Instruction Execution
µ
PD78F0034Y
Preliminary Data Sheet 37
Data Retention Timing (Standby Release Signal: STOP Mode Release by Interrupt Request Signal)
Interrupt Request Input Timing
RESET Input Timing
t
SREL
t
WAIT
V
DD
STOP Instruction Execution
STOP Mode
Data Retention Mode
HALT Mode
Operating Mode
Standby Release Signal
(Interrupt Request)
V
DDDR
INTP0 to INTP2
INTP3
t
INTL
t
INTH
t
INTL
t
RSL
RESET
µ
PD78F0034Y
Preliminary Data Sheet
38
6. PACKAGE DRAWINGS
I
J
GHF
DN
M
CB
MR
64 33
321
K
L
NOTES
1. Controlling dimension millimeter.
P64C-70-750A,C-3
ITEM MILLIMETERS INCHES
B
C
D
F
G
H
J
K
1.778 (T.P.)
3.2±0.3
0.51 MIN.
1.78 MAX.
L
M
0.17
0.25
19.05 (T.P.)
5.08 MAX.
17.0±0.2
N0 to 15°
0.50±0.10
0.9 MIN.
R
0.070 MAX.
0.020
0.035 MIN.
0.126±0.012
0.020 MIN.
0.200 MAX.
0.750 (T.P.)
0.669
0.010
0.007
0 to 15°
+0.004
–0.003
0.070 (T.P.)
+0.10
–0.05
+0.004
–0.005
64-PIN PLASTIC SHRINK DIP (750 mils) (Unit: mm)
2. Each lead centerline is located within 0.17 mm (0.007 inch) of
its true position (T.P.) at maximum material condition.
3. Item "K" to center of leads when formed parallel.
A 58.0 2.283+0.028
–0.008
+0.68
–0.20
I 4.05 0.159+0.011
–0.008
+0.26
–0.20
A
+0.009
–0.008
µ
PD78F0034Y
Preliminary Data Sheet 39
64-PIN PLASTIC QFP (14 x 14) (Unit: mm)
ITEM MILLIMETERS INCHES
I
J 0.8 (T.P.)
0.15 0.006
0.031 (T.P.)
A 17.6±0.4 0.693±0.016
B 14.0±0.2 0.551+0.009
–0.008
C 14.0±0.2 0.551+0.009
–0.008
D 17.6±0.4 0.693±0.016
F
G 1.0
1.0 0.039
0.039
H 0.37 0.015
P64GC-80-AB8-4
L 0.8±0.2 0.031+0.009
–0.008
M 0.17 0.007
N 0.10 0.004
+0.08
–0.07
+0.08
–0.07
Q 0.1±0.1 0.004±0.004
R
S 2.85 MAX.
5°±5°5°±5°
0.113 MAX.
+0.003
–0.004
NOTE
1. Controlling dimension millimeter.
2. Each lead centerline is located within 0.15 mm (0.006 inch) of
its true position (T.P.) at maximum material condition.
M
QR
K
M
L
P
G
F
HI
S
detail of lead end
K 1.8±0.2 0.071±0.008
P 2.55±0.1 0.100±0.004
+0.003
–0.004
48
49 32
64
117
16
33
S
A
B
CD
J
NS
µ
PD78F0034Y
Preliminary Data Sheet
40
64-PIN PLASTIC LQFP (12 x 12) (Unit: mm)
ITEM MILLIMETERS INCHES
D
F
G
K
I
J
1.125
1.125
1.4±0.2
0.65 (T.P.)
0.13
14.8±0.4
Q
0.583±0.016
0.044
0.044
0.055±0.008
0.005
0.026 (T.P.)
P64GK-65-8A8-1
A
F
NOTE
Each lead centerline is located within 0.13 mm (0.005 inch) of
its true position (T.P.) at maximum material condition.
C 12.0±0.2 0.472
M 0.15 0.006
0.125±0.075 0.005±0.003
+0.004
–0.003
+0.009
–0.008
A 14.8±0.4 0.583±0.016
H 0.30±0.10 0.012+0.004
–0.005
L 0.6±0.2 0.024+0.008
–0.009
N 0.10 0.004
P 1.4 0.055
S
R1.7 MAX.
5°±5°0.067 MAX.
5°±5°
+0.10
–0.05
B 12.0±0.2 0.472+0.009
–0.008
M
48
49 32
64 117
16
33
B
GHI J
C
D
P
NL
K
M
detail of lead end
S
Q
R
µ
PD78F0034Y
Preliminary Data Sheet 41
APPENDIX A. DEVELOPMENT TOOLS
The following development tools are available for system development using the
µ
PD78F0034Y.
Be sure to refer to (5) Cautions on using development tools.
(1) Language Processing Software
RA78K/0 Assembler package common to 78K/0 Series
CC78K/0 C compiler package common to 78K/0 Series
DF780034 Device file common to
µ
PD780034 Subseries
CC78K/0-L C compiler library source file common to 78K/0 Series
(2) Flash Memory Writing Tools
Flashpro II (FL-PR2) Flash programmer dedicated to on-chip flash memory microcontroller
FA-64CW Adapter for flash writing
FA-64GC
FA-64GKNote
Note Under development
(3) Debugging Tool
• When using in-circuit emulator IE-78K0-NS
IE-78K0-NSNote In-circuit emulator common to 78K/0 Series
IE-70000-MC-PS-B Power supply unit for IE-78K0-NS
IE-70000-98-IF-CNote Interface adapter when using PC-9800 series as host machine (excluding notebook PCs)
IE-70000-CD-IFNote PC card and interface cable when using notebook PC of PC-9800 series as host machine
IE-70000-PC-IF-CNote Interface adapter when using IBM PC/ATTM or compatible as host machine
IE-780034-NS-EM1Note Emulation board to emulate
µ
PD780034 Subseries
NP-64CW Emulation probe for 64-pin plastic shrink DIP (CW type)
NP-64GC Emulation probe for 64-pin plastic QFP (GC-AB8 type)
NP-64GKNote Emulation probe for 64-pin plastic LQFP (GK-8A8 type)
TGK-064SBW Conversion adapter for connecting target system board designed to allow mounting of 64-pin
plastic LQFP (GK-8A8 type) and NP-64GK.
EV-9200GC-64 Socket to be mounted on target system board manufactured for 64-pin plastic QFP (GC-AB8 type)
ID78K0-NSNote Integrated debugger for IE-78K0-NS
SM78K0 System simulator common to 78K/0 Series
DF780034 Device file common to
µ
PD780034 Subseries
Note Under development
µ
PD78F0034Y
Preliminary Data Sheet
42
• When using in-circuit emulator IE-78001-R-A
IE-78001-R-ANote In-circuit emulator common to 78K/0 Series
IE-70000-98-IF-B Interface adapter when using PC-9800 series as host machine (excluding notebook PCs)
IE-70000-98-IF-CNote
IE-70000-PC-IF-B Interface adapter when using IBM PC/AT or compatible as host machine
IE-70000-PC-IF-CNote
IE-78000-R-SV3 Interface adapter and cable when using EWS as host machine
IE-780034-NS-EM1Note Emulation board to emulate
µ
PD780034 Subseries
IE-78K0-R-EX1Note Emulation probe conversion board to use IE-780034-NS-EM1 on IE-78001-R-A
EP-78240CW-R Emulation probe for 64-pin plastic shrink DIP (CW type)
EP-78240GC-R Emulation probe for 64-pin plastic QFP (GC-AB8 type)
EP-78012GK-R Emulation probe for 64-pin plastic LQFP (GK-8A8 type)
TGK-064SBW Conversion adapter for connecting target system board and EP-78012GK-R designed to allow
mounting of 64-pin plastic LQFP (GK-8A8).
EV-9200GC-64 Socket to be mounted on target system board manufactured for 64-pin plastic QFP (GC-AB8 type)
ID78K0 Integrated debugger for IE-78001-R-A
SM78K0 System simulator common to 78K/0 Series
DF780034 Device file common to
µ
PD780034 Subseries
Note Under development
(4) Real-time OS
RX78K/0 Real-time OS for 78K/0 Series
MX78K0 OS for 78K/0 Series
µ
PD78F0034Y
Preliminary Data Sheet 43
Host Machine PC EWS
[OS] PC-9800 series [WindowsTM] HP9000 series 700TM [HP-UXTM]
IBM PC/AT or compatibles SPARCstationTM [SunOSTM]
Software [Japanese/English Windows] NEWSTM (RISC) [NEWS-OSTM]
RA78K/0 √Note √
CC78K/0 √Note √
ID78K0-NS √–
ID78K0 √√
SM78K0 √–
RX78K/0 √Note √
MX78K0 √Note √
(5) Cautions on using development tools
• The ID-78K0-NS, ID78K0, and SM78K0 are used in combination with the DF780034.
• The CC78K/0 and RX78K/0 are used in combination with the RA78K/0 and the DF780034.
• The Flashpro II, FA-64CW, FA-64GC, FA64GK, NP-64CW, NP64GC, and NP-64GK are products made by
Naitou Densei Machidaseisakusho (044-822-3813).
Contact an NEC distributor regarding the purchase of these products.
• The TGK-064SBW is a product made by TOKYO ELETECH CORPORATION.
Refer to: Daimaru Kogyo, Ltd.
Tokyo Electronic Components Division (03-3820-7112)
Osaka Electronic Components Division (06-244-6672)
• For third party development tools, see the 78K/0 Series Selection Guide (U11126E).
• The host machines and OSs supporting each software are as follows.
Note DOS-based software
µ
PD78F0034Y
Preliminary Data Sheet
44
Conversion Socket Drawing (EV-9200GC-64) and Footprints
Figure A-1. EV-9200GC-64 Drawing (for reference only)
A
F
1
E
EV-9200GC-64
B
D
C
M
N
L
K
R
Q
I
H
P
O
S
T
J
G
No.1 pin index
EV-9200GC-64-G0
ITEM MILLIMETERS INCHES
A
B
C
D
E
F
G
H
I
J
K
L
M
N
O
P
Q
R
S
T
18.8
14.1
14.1
18.8
4-C 3.0
0.8
6.0
15.8
18.5
6.0
15.8
18.5
8.0
7.8
2.5
2.0
1.35
0.35±0.1
2.3
1.5
0.74
0.555
0.555
0.74
4-C 0.118
0.031
0.236
0.622
0.728
0.236
0.622
0.728
0.315
0.307
0.098
0.079
0.053
0.014
0.091
0.059
+0.004
–0.005
φ
φ
φ
φ
µ
PD78F0034Y
Preliminary Data Sheet 45
Figure A-2. EV-9200GC-64 Footprints (for reference only)
F
E
D
G
HI
JK
L
C
B
A
0.031 × 0.591=0.472
0.031 × 0.591=0.472
EV-9200GC-64-P1E
ITEM MILLIMETERS INCHES
A
B
C
D
E
F
G
H
I
J
K
L
19.5
14.8
14.8
19.5
6.00±0.08
6.00±0.08
0.5±0.02
2.36±0.03
2.2±0.1
1.57±0.03
0.768
0.583
0.583
0.768
0.236
0.236
0.197
0.093
0.087
0.062
0.8±0.02 × 15=12.0±0.05
0.8±0.02 × 15=12.0±0.05
φ
φ
φ
+0.002
–0.001 +0.003
–0.002
+0.002
–0.001 +0.003
–0.002
+0.004
–0.003
+0.004
–0.003
+0.001
–0.002
φ
φ
φ
+0.001
–0.002
+0.004
–0.005
+0.001
–0.002
Dimensions of mount pad for EV-9200 and that for
target device (QFP) may be different in some parts. For
the recommended mount pad dimensions for QFP,
refer to "SEMICONDUCTOR DEVICE MOUNTING
TECHNOLOGY MANUAL" (C10535E).
Caution
µ
PD78F0034Y
Preliminary Data Sheet
46
Conversion Adapter Drawing (TGK-064SBW)
Figure A-3. TGK-064SBW Drawing (for reference only)
ITEM MILLIMETERS INCHES
b 1.85 0.073
c 3.5 0.138
a 0.3 0.012
d 2.0 0.079
h 5.9 0.232
i 0.8 0.031
j 2.4 0.094
e 3.9 0.154
f 1.325
g 1.325 0.052
0.052
ITEM MILLIMETERS INCHES
B
0.65x15=9.75 0.026x0.591=0.384
C 0.65 0.026
A 18.4 0.724
D
H
0.65x15=9.75 0.026x0.591=0.384
I 11.85 0.467
J 18.4 0.724
E 10.15 0.400
F 12.55 0.494
K C 2.0 C 0.079
L 12.45 0.490
M
Q 11.1 0.437
R 1.45 0.057
S 1.45 0.057
N 7.7 0.303
O 10.02
P 14.92 0.587
0.394
W 5.3 0.209
X 4-C 1.0 4-C 0.039
Y 3.55 0.140
T 4- 1.3 4- 0.051
U 1.8
V 5.0 0.197
0.071
Z 0.9 0.035
7.75
10.25
0.305
0.404
G 14.95 0.589
φ
φ
φ
φ
φ
φ
φ
φ
k 2.7 0.106
TGK-064SBW-G0E
φφ
H
A
h
a
g
Z
c
L
Q
N
B
C
IJ
K
GFED
MX
R
S
W
O
P
Protrusion height
U
T
V
k
j
i
Y
e
d
b
f
Note: Product made by TOKYO ELETECH Corporation.
µ
PD78F0034Y
Preliminary Data Sheet 47
APPENDIX B. RELATED DOCUMENTS
Device Related Documents
Document Name Document No. Document No.
(English) (Japanese)
µ
PD780024, 780024Y, 780034, 780034Y Subseries User’s Manual U12022E U12022J
µ
PD780031Y, 780032Y, 780033Y, 780034Y Data Sheet U12166E U12166J
µ
PD78F0034Y Data Sheet
This document
U11994J
78K/0 Series User’s Manual-Instruction U12326E U12326J
78K/0 Series Instruction Table — U10903J
78K/0 Series Instruction Set — U10904J
µ
PD780034Y Subseries Special Function Register Table —
To be prepared
Development Tool Documents (User’s Manual)
Document Name Document No. Document No.
(English) (Japanese)
RA78K0 Assembler Package Operation U11802E U11802J
Assembly Language U11801E U11801J
Structured Assembly Language U11789E U11789J
RA78K Series Structured Assembler Preprocessor EEU-1402 U12323J
CC78K0 C Compiler Operation U11517E U11517J
Language U11518E U11518J
CC78K/0 C Compiler Application Note Programming Know-how EEA-1208 U13034J
CC78K Series Library Source File U12322E U12322J
IE-78K0-NS
To be prepared To be prepared
IE-78001-R-A
To be prepared To be prepared
IE-780034-NS-EM1
To be prepared To be prepared
EP-78240 U10332E EEU-986
EP-78012GK-R EEU-1538 EEU-5012
SM78K0 System Simulator-Windows based Reference U10181E U10181J
SM78K Series System Simulator External Part User Open U10092E U10092J
Interface Specifications
ID78K0-NS Integrated Debugger Reference
To be prepared
U12900J
ID78K0 Integrated Debugger — EWS based Reference — U11151J
ID78K0 Integrated Debugger — PC based Reference U11539E U11539J
ID78K0 Integrated Debugger — Windows based Guide U11649E U11649J
Caution The above related documents are subject to change without notice. Be sure to read the latest
documents before designing.
µ
PD78F0034Y
Preliminary Data Sheet
48
Embedded Software Documents (User’s Manual)
Document Name Document No. Document No.
(English) (Japanese)
78K/0 Series Real-time OS Basics U11537E U11537J
Installation U11536E U11536J
78K/0 Series OS MX78K0 Basics U12257E U12257J
Other Documents
Document Name Document No. Document No.
(English) (Japanese)
IC Package Manual C10943X
Semiconductor Device Mounting Technology Manual C10535E C10535J
Quality Grades on NEC Semiconductor Devices C11531E C11531J
NEC Semiconductor Device Reliability/Quality Control System C10983E C10983J
Guide to Prevent Damage for Semiconductor Devices by Electrostatic Discharge (ESD) C11892E C11892J
Guide to Quality Assurance for Semiconductor Devices MEI-1202 —
Microcomputer Product Series Guide — U11416J
Caution The above related documents are subject to change without notice. Be sure to read the latest
documents before designing.
µ
PD78F0034Y
Preliminary Data Sheet 49
[MEMO]
µ
PD78F0034Y
Preliminary Data Sheet
50
NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note: Strong electric field, when exposed to a MOS device, can cause destruction
of the gate oxide and ultimately degrade the device operation. Steps must
be taken to stop generation of static electricity as much as possible, and
quickly dissipate it once, when it has occurred. Environmental control must
be adequate. When it is dry, humidifier should be used. It is recommended
to avoid using insulators that easily build static electricity. Semiconductor
devices must be stored and transported in an anti-static container, static
shielding bag or conductive material. All test and measurement tools including
work bench and floor should be grounded. The operator should be grounded
using wrist strap. Semiconductor devices must not be touched with bare
hands. Similar precautions need to be taken for PW boards with semiconductor
devices on it.
2 HANDLING OF UNUSED INPUT PINS FOR CMOS
Note: No connection for CMOS device inputs can be cause of malfunction. If no
connection is provided to the input pins, it is possible that an internal input
level may be generated due to noise, etc., hence causing malfunction. CMOS
devices behave differently than Bipolar or NMOS devices. Input levels of
CMOS devices must be fixed high or low by using a pull-up or pull-down
circuitry. Each unused pin should be connected to VDD or GND with a resistor,
if it is considered to have a possibility of being an output pin. All handling
related to the unused pins must be judged device by device and related
specifications governing the devices.
3 STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note: Power-on does not necessarily define initial status of MOS device. Production
process of MOS does not define the initial operation status of the device.
Immediately after the power source is turned ON, the devices with reset
function have not yet been initialized. Hence, power-on does not guarantee
out-pin levels, I/O settings or contents of registers. Device is not initialized
until the reset signal is received. Reset operation must be executed immediately
after power-on for devices having reset function.
µ
PD78F0034Y
Preliminary Data Sheet 51
NEC Electronics Inc. (U.S.)
Santa Clara, California
Tel: 408-588-6000
800-366-9782
Fax: 408-588-6130
800-729-9288
NEC Electronics (Germany) GmbH
Duesseldorf, Germany
Tel: 0211-65 03 02
Fax: 0211-65 03 490
NEC Electronics (UK) Ltd.
Milton Keynes, UK
Tel: 01908-691-133
Fax: 01908-670-290
NEC Electronics Italiana s.r.1.
Milano, Italy
Tel: 02-66 75 41
Fax: 02-66 75 42 99
NEC Electronics Hong Kong Ltd.
Hong Kong
Tel:2886-9318
Fax: 2886-9022/9044
NEC Electronics Hong Kong Ltd.
Seoul Branch
Seoul, Korea
Tel: 02-528-0303
Fax: 02-528-4411
NEC Electronics Singapore Pte. Ltd.
United Square, Singapore 1130
Tel:65-253-8311
Fax: 65-250-3583
NEC Electronics Taiwan Ltd.
Taipei, Taiwan
Tel: 02-719-2377
Fax: 02-719-5951
NEC do Brasil S.A.
Cumbica-Guarulhos-SP, Brasil
Tel: 011-6465-6810
Fax: 011-6465-6829
NEC Electronics (Germany) GmbH
Benelux Office
Eindhoven, The Netherlands
Tel:040-2445845
Fax: 040-2444580
NEC Electronics (France) S.A.
Velizy-Villacoublay, France
Tel:01-30-67 58 00
Fax: 01-30-67 58 99
NEC Electronics (France) S.A.
Spain Office
Madrid, Spain
Tel: 01-504-2787
Fax: 01-504-2860
NEC Electronics (Germany) GmbH
Scandinavia Office
Taeby, Sweden
Tel: 08-63 80 820
Fax: 08-63 80 388
Regional Information
Some information contained in this document may vary from country to country. Before using any NEC
product in your application, please contact the NEC office in your country to obtain a list of authorized
representatives and distributors. They will verify:
• Device availability
• Ordering information
• Product release schedule
• Availability of related technical literature
• Development environment specifications (for example, specifications for third-party tools and
components, host computers, power plugs, AC supply voltages, and so forth)
• Network requirements
In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary
from country to country.
J98. 2
µ
PD78F0034Y
No part of this document may be copied or reproduced in any form or by any means without the prior written
consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in
this document.
NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property
rights of third parties by or arising from use of a device described herein or any other liability arising from use
of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other
intellectual property rights of NEC Corporation or others.
While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices,
the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or
property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety
measures in its design, such as redundancy, fire-containment, and anti-failure features.
NEC devices are classified into the following three quality grades:
"Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a
customer designated "quality assurance program" for a specific application. The recommended applications of
a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device
before using it in a particular application.
Standard: Computers, office equipment, communications equipment, test and measurement equipment,
audio and visual equipment, home electronic appliances, machine tools, personal electronic
equipment and industrial robots
Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support)
Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems or medical equipment for life support, etc.
The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books.
If customers intend to use NEC devices for applications other than those specified for Standard quality grade,
they should contact an NEC sales representative in advance.
Anti-radioactive design is not implemented in this product.
M4 96.5
FIP and IEBus are trademarks of NEC Corporation.
Windows is a registered trademark or a trademark of Microsoft Corporation in the United
States and/or other countries.
PC/AT is a trademark of International Business Machines Corporation.
HP9000 series 700 and HP-UX are trademarks of Hewlett-Packard Company.
SPARCstation is a trademark of SPARC International, Inc.
SunOS is a trademark of Sun Microsystems, Inc.
NEWS and NEWS-OS are trademarks of Sony Corporation.
The related documents indicated in this publication may include preliminary versions. However, preliminary
versions are not marked as such.
Purchase of NEC I2C components conveys a license under the Philips I2C Patent Rights to use
these components in an I2C system, provided that the system conforms to the I2C Standard
Specification as defined by Philips.
