Product Folder Sample & Buy Technical Documents Support & Community Tools & Software SN74AVC2T245 SCES692D - JUNE 2008 - REVISED FEBRUARY 2016 SN74AVC2T245 Dual-Bit Dual-Supply Bus Transceiver with Configurable Level-Shifting / Voltage Translation and Tri-State Outputs 1 Features 3 Description * * This dual-bit noninverting bus transceiver uses two separate configurable power-supply rails. The A port is designed to track VCCA. VCCA accepts any supply voltage from 1.2 V to 3.6 V. The B port is designed to track VCCB. VCCB accepts any supply voltage from 1.2 V to 3.6 V. This allows for universal low-voltage bidirectional translation between any of the 1.2 V, 1.5 V, 1.8 V, 2.5 V, and 3.3 V voltage nodes. 1 * * * * * * * Each Channel Has Independent Direction Control Control Inputs VIH/VIL Levels Are Referenced to VCCA Voltage Fully Configurable Dual-Rail Design Allows Each Port to Operate Over the Full 1.2 V to 3.6 V Power-Supply Range I/Os Are 4.6 V Tolerant Ioff Supports Partial-Power-Down Mode Operation VCC Isolation Feature - If Either VCC Input is at GND, Both Ports are in High-Impedance State Typical Data Rates - 500 Mbps (1.8 V to 3.3 V Level-Shifting) - 320 Mbps (<1.8 V to 3.3 V Level-Shifting) - 320 Mbps (Translate to 2.5 V or 1.8 V) - 280 Mbps (Translate to 1.5 V) - 240 Mbps (Translate to 1.2 V) Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II ESD Protection Exceeds JESD 22 - 5000 V Human-Body Model (A114-A) - 200 V Machine Model (A115-A) - 1500 V Charged-Device Model (C101) The SN74AVC2T245 control pins (DIR1, DIR2, and OE) are supplied by VCCA. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. The VCC isolation feature ensures that if either VCC input is at GND, both ports are in the high-impedance state. 2 Applications * * * * The SN74AVC2T245 is designed for asynchronous communication between two data buses. The logic levels of the direction-control (DIR) input and the output-enable (OE) activate either the B-port outputs or the A-port outputs or place both output ports into the high-impedance mode . The device transmits data from the A bus to the B bus when the B-port outputs are activated and from the B bus to the A bus when the A-port outputs are activated. The input circuitry on both A and B ports always is active and must have a logic HIGH or LOW level applied to prevent excess ICC and ICCZ. Personal Electronics Industrial Enterprise Telecom To ensure the high-impedance state during power up or power down, OE must be connected to VCC through a pull-up resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. Logic Diagram (Positive Logic) Device Information(1) DIR1 PART NUMBER SN74AVC2T245 OE PACKAGE UQFN (10) BODY SIZE (NOM) 1.80 mm x 1.40 mm (1) For all available packages, see the orderable addendum at the end of the datasheet. A1 B1 (1) Shown for a single channel 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. SN74AVC2T245 SCES692D - JUNE 2008 - REVISED FEBRUARY 2016 www.ti.com Table of Contents 1 2 3 4 5 6 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Pin Configuration and Functions ......................... Specifications......................................................... 6.1 6.2 6.3 6.4 6.5 6.6 6.7 6.8 6.9 6.10 6.11 6.12 7 1 1 1 2 3 4 Absolute Maximum Ratings ..................................... 4 ESD Ratings.............................................................. 4 Recommended Operating Conditions ...................... 4 Thermal Information .................................................. 5 Electrical Characteristics .......................................... 6 Switching Characteristics: VCCA = 1.2 V ................... 7 Switching Characteristics: VCCA = 1.5 V 0.1 V....... 7 Switching Characteristics: VCCA = 1.8 V 0.15 V..... 8 Switching Characteristics: VCCA = 2.5 V 0.2 V....... 8 Switching Characteristics: VCCA = 3.3 V 0.3 V..... 9 Operating Characteristics........................................ 9 Typical Characteristics .......................................... 10 Parameter Measurement Information ................ 11 8 Detailed Description ............................................ 12 8.1 8.2 8.3 8.4 9 Overview ................................................................. Functional Block Diagram ....................................... Feature Description................................................. Device Functional Modes........................................ 12 12 12 13 Application and Implementation ........................ 14 9.1 Application Information............................................ 14 9.2 Typical Application ................................................. 14 10 Power Supply Recommendations ..................... 16 11 Layout................................................................... 16 11.1 Layout Guidelines ................................................. 16 11.2 Layout Example .................................................... 16 12 Device and Documentation Support ................. 17 12.1 12.2 12.3 12.4 Community Resources.......................................... Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 17 17 17 17 13 Mechanical, Packaging, and Orderable Information ........................................................... 17 4 Revision History Changes from Revision C (July 2015) to Revision D * Made changes to Pin Configuration and Functions .............................................................................................................. 1 Changes from Revision B (June 2015) to Revision C * Page Page The Ordering Information table (formally on page 1) contained a Top-Side Marking of TQ_. The table has been replaced with the Package Option Addendum in Mechanical, Packaging, and Orderable Information. VC_ was added to the device marking . ............................................................................................................................................. 17 Changes from Revision A (May 2012) to Revision B Page * Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section .............................. 1 * Removed the Ordering Information table. ............................................................................................................................. 1 2 Submit Documentation Feedback Copyright (c) 2008-2016, Texas Instruments Incorporated Product Folder Links: SN74AVC2T245 SN74AVC2T245 www.ti.com SCES692D - JUNE 2008 - REVISED FEBRUARY 2016 5 Pin Configuration and Functions VCCA VCCB RSW PACKAGE 10-PIN UQFN TOP VIEW 7 A1 A2 DIR1 6 8 5 9 4 10 3 2 DIR2 OE 1 B1 B2 GND Pin Functions PIN NAME DESCRIPTION NO. (UQFN) VCCA 7 Supply Voltage A VCCB 6 Supply Voltage B GND 3 Ground A1 8 Output or input depending on state of DIR. Output level depends on VCCA. A2 9 Output or input depending on state of DIR. Output level depends on VCCA. B1 5 Output or input depending on state of DIR. Output level depends on VCCB. 4 Output or input depending on state of DIR. Output level depends on VCCB. B2 DIR1,DIR2 OE 10,1 2 Direction Pin, Connect to GND or to VCCA Tri-state output-mode enables. Pull OE high to place all outputs in 3-state mode. Referenced to VCCA Submit Documentation Feedback Copyright (c) 2008-2016, Texas Instruments Incorporated Product Folder Links: SN74AVC2T245 3 SN74AVC2T245 SCES692D - JUNE 2008 - REVISED FEBRUARY 2016 www.ti.com 6 Specifications 6.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) (1) MIN MAX -0.5 4.6 I/O ports (A port) -0.5 4.6 I/O ports (B port) -0.5 4.6 Control inputs -0.5 4.6 A port -0.5 4.6 B port -0.5 4.6 A port -0.5 VCCA + 0.5 B port -0.5 VCCB + 0.5 VCCA Supply voltage VCCB UNIT V VI Input voltage (2) VO Voltage applied to any output in the high-impedance or power-off state (2) VO Voltage applied to any output in the high or low state (2) IIK Input clamp current VI < 0 -50 mA IOK Output clamp current VO < 0 -50 mA IO Continuous output current (3) Continuous current through VCCA, VCCB, or GND V V V 50 mA 100 mA TJ Junction Temperature -40 150 C Tstg Storage temperature range -65 150 C (1) (2) (3) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. The input voltage and output negative-voltage ratings may be exceeded if the input and output current ratings are observed. The output positive-voltage rating may be exceeded up to 4.6 V maximum if the output current rating is observed. 6.2 ESD Ratings VALUE V(ESD) (1) (2) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) 5000 Charged-device model (CDM), per JEDEC specification JESD22C101 (2) 1500 (2) (3) VCCI VCCA Supply voltage VCCB Supply voltage VIL VIH (1) (2) (3) 4 V JEDEC document JEP155 states that 500 V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250 V CDM allows safe manufacturing with a standard ESD control process. 6.3 Recommended Operating Conditions (1) VIH UNIT High-level input voltage Low-level input voltage High-level input voltage Data inputs (1) Data inputs (1) DIR (referenced to VCCA) (2) VCCO MIN MAX 1.2 3.6 V 1.2 3.6 V 1.2 V to 1.95 V VCCI x 0.65 1.95 V to 2.7 V 1.6 2.7 V to 3.6 V 2 V 1.2 V to 1.95 V VCCI x 0.35 1.95 V to 2.7 V 0.7 2.7 V to 3.6 V 0.8 1.2 V to 1.95 V VCCA x 0.65 1.95 V to 2.7 V 1.6 2.7 V to 3.6 V 2 UNIT V V VCCI is the VCC associated with the input port. VCCO is the VCC associated with the output port. All unused data inputs of the device must be held at VCCI or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. Submit Documentation Feedback Copyright (c) 2008-2016, Texas Instruments Incorporated Product Folder Links: SN74AVC2T245 SN74AVC2T245 www.ti.com SCES692D - JUNE 2008 - REVISED FEBRUARY 2016 Recommended Operating Conditions(1) (2) (3) (continued) VCCI VIL Low-level input voltage VI Input voltage DIR (referenced to VCCA) (2) VCCO MIN MAX 1.2 V to 1.95 V VCCA x 0.35 1.95 V to 2.7 V 0.7 2.7 V to 3.6 V VO Output voltage IOH IOL 3.6 Active state 0 VCCO 3-state 0 3.6 Low-level output current t/v Input transition rise or fall rate TA Operating free-air temperature V 0.8 0 High-level output current UNIT 1.1 V to 1.2 V -3 1.4 V to 1.6 V -6 1.65 V to 1.95 V -8 2.3 V to 2.7 V -9 3 V to 3.6 V -12 1.1 V to 1.2 V 3 1.4 V to 1.6 V 6 1.65 V to 1.95 V 8 2.3 V to 2.7 V 9 3 V to 3.6 V 12 -40 V V mA mA 5 ns/V 85 C 6.4 Thermal Information SN74AVC2T245 THERMAL METRIC (1) RSW (UQFN) UNIT 10 PINS RJA Junction-to-ambient thermal resistance 109.1 C/W RJC(top) Junction-to-case (top) thermal resistance 57.9 C/W RJB Junction-to-board thermal resistance 57.0 C/W JT Junction-to-top characterization parameter 2.7 C/W JB Junction-to-board characterization parameter 57.0 C/W RJC(bot) Junction-to-case (bottom) thermal resistance 18.4 C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953. Submit Documentation Feedback Copyright (c) 2008-2016, Texas Instruments Incorporated Product Folder Links: SN74AVC2T245 5 SN74AVC2T245 SCES692D - JUNE 2008 - REVISED FEBRUARY 2016 www.ti.com 6.5 Electrical Characteristics over recommended operating free-air temperature range (unless otherwise noted) (1) (2) PARAMETER TEST CONDITIONS IOH = -100 A VCCA MIN TYP MAX 1.05 1.65 V 1.65 V 1.2 IOH = -9 mA 2.3 V 2.3 V 1.75 IOH = -12 mA 3V 3V 2.3 0.95 1.2 V to 3.6 V 1.2 V to 3.6 V V 0.2 1.2 V 1.2 V 1.4 V 1.4 V 0.35 1.65 V 1.65 V 0.45 IOL = 9 mA 2.3 V 2.3 V 0.55 IOL = 12 mA 3V 3V 0.7 IOL = 6 mA IOL = 8 mA VI = VIL II Control inputs Ioff A or B port VI or VO = 0 to 3.6 V IOZ A or B port VI = VCCA or GND 1.2 V to 3.6 V 1.2 V to 3.6 V VO = VCCO or GND, VI = VCCI or GND, OE = VIH 0.25 0.025 0.25 1 0V 0 V to 3.6 V 0.1 1 5 0 V to 3.6 V 0V 0.1 1 5 3.6 V 3.6 V 0.5 2.5 5 1.2 V to 3.6 V 1.2 V to 3.6 V VI = VCCI or GND, IO = 0 VI = VCCI or GND, IO = 0 ICCA + ICCB VI = VCCI or GND, IO = 0 Ci Control inputs 0 V to 3.6 V -2 0 V to 3.6 V 0V 8 Cio A or B port VO = 3.3 V or GND A A A A 8 0V 0 V to 3.6 V 8 0 V to 3.6 V 0V -2 1.2 V to 3.6 V 1.2 V to 3.6 V VI = 3.3 V or GND V 8 0V 1.2 V to 3.6 V 1.2 V to 3.6 V ICCB UNIT VCCO - 0.2 1.4 V IOL = 3 mA 6 MIN 1.4 V VI = VIH IOL = 100 A (1) (2) MAX 1.2 V IOH = -8 mA ICCA -40C to 85C 1.2 V IOH = -6 mA VOL TA = 25C 1.2 V to 3.6 V 1.2 V to 3.6 V IOH = -3 mA VOH VCCB A 16 A 3.3 V 3.3 V 3.5 4.5 pF 3.3 V 3.3 V 6 7 pF VCCO is the VCC associated with the output port. VCCI is the VCC associated with the input port. Submit Documentation Feedback Copyright (c) 2008-2016, Texas Instruments Incorporated Product Folder Links: SN74AVC2T245 SN74AVC2T245 www.ti.com SCES692D - JUNE 2008 - REVISED FEBRUARY 2016 6.6 Switching Characteristics: VCCA = 1.2 V over recommended operating free-air temperature range, VCCA = 1.2 V (unless otherwise noted) (see Figure 3) PARAMETER FROM (INPUT) TO (OUTPUT) A B B A OE A OE B OE A OE B tPLH tPHL tPLH tPHL tPZH tPZL tPZH tPZL tPHZ tPLZ tPHZ tPLZ VCCB = 1.2 V VCCB = 1.5 V 0.1 V VCCB = 1.8 V 0.15 V VCCB = 2.5 V 0.2 V VCCB = 3.3 V 0.3 V TYP TYP TYP TYP TYP 2.5 2.1 1.9 1.9 1.9 2.5 2.1 1.9 1.9 1.9 2.5 2.2 2 1.8 1.7 2.5 2.2 2 1.8 1.7 3.8 3.1 2.7 2.6 3 3.8 3.1 2.7 2.6 3 3.7 3.7 3.7 3.7 3.7 3.7 3.7 3.7 3.7 3.7 4.4 3.6 3.5 3.3 4.1 4.4 3.6 3.5 3.3 4.1 4.2 4.2 4.3 4.1 4.2 4.2 4.2 4.3 4.1 4.2 UNIT ns ns ns ns ns ns 6.7 Switching Characteristics: VCCA = 1.5 V 0.1 V over recommended operating free-air temperature range, VCCA = 1.5 V 0.1 V (see Figure 3) PARAMETER tPLH tPHL tPLH tPHL tPZH tPZL tPZH tPZL tPHZ tPLZ tPHZ tPLZ FROM (INPUT) TO (OUTPUT) A B B A OE A OE B OE A OE B VCCB = 1.2 V VCCB = 1.5 V 0.1 V VCCB = 1.8 V 0.15 V VCCB = 2.5 V 0.2 V VCCB = 3.3 V 0.3 V TYP MIN MAX MIN MAX MIN MAX MIN MAX 2.2 0.3 4.4 0.2 3.9 0.1 3.6 0.1 3.9 2.2 0.3 4.4 0.2 3.9 0.1 3.6 0.1 3.9 2 0.6 5.1 0.4 4.9 0.2 4.6 0.1 4.5 2 0.6 5.1 0.4 4.9 0.2 4.6 0.1 4.5 3.4 1.1 7.1 0.9 6.2 0.7 5.5 0.1 6.4 3.4 1.1 7.1 0.9 6.2 0.7 5.5 0.1 6.4 2.5 1.1 8.2 1.1 8.2 1.1 8.2 1.1 8.2 2.5 1.1 8.2 1.1 8.2 1.1 8.2 1.1 8.2 4.1 1.2 7.1 0.8 6.7 0.4 5.6 1 74 4.1 1.2 7.1 0.8 6.7 0.4 5.6 1 7.4 3.3 0.3 7.4 0.2 5.7 0.3 5.6 0.3 5.6 3.3 0.3 7.4 0.2 5.7 0.3 5.6 0.3 5.6 Submit Documentation Feedback Copyright (c) 2008-2016, Texas Instruments Incorporated Product Folder Links: SN74AVC2T245 UNIT ns ns ns ns ns ns 7 SN74AVC2T245 SCES692D - JUNE 2008 - REVISED FEBRUARY 2016 www.ti.com 6.8 Switching Characteristics: VCCA = 1.8 V 0.15 V over recommended operating free-air temperature range, VCCA = 1.8 V 0.15 V (see Figure 3) PARAMETER tPLH tPHL tPLH tPHL tPZH tPZL tPZH tPZL tPHZ tPLZ tPHZ tPLZ FROM (INPUT) TO (OUTPUT) A B B A OE A OE B OE A OE B VCCB = 1.2 V VCCB = 1.5 V 0.1 V VCCB = 1.8 V 0.15 V VCCB = 2.5 V 0.2 V VCCB = 3.3 V 0.3 V UNIT TYP MIN MAX MIN MAX MIN MAX MIN MAX 2 0.1 4.1 0.1 3.6 0.1 3.1 0.1 3.3 2 0.1 4.1 0.1 3.6 0.1 3.1 0.1 3.3 1.9 0.4 4.3 0.1 4.1 0.1 3.8 0.1 3.7 1.9 0.4 4.3 0.1 4.1 0.1 3.8 0.1 3.7 3.2 0.8 6.7 0.4 5.8 0.4 4.8 0.3 4.6 3.2 0.8 6.7 0.4 5.8 0.4 4.8 0.3 4.6 1.9 0.2 6.7 0.2 6.6 0.2 6.7 0.2 6.7 1.9 0.2 6.7 0.2 6.6 0.2 6.7 0.2 6.7 3.8 0.7 6.2 0.3 6.5 0.1 5.2 0.8 6.5 3.8 0.7 6.2 0.3 6.5 0.1 5.2 0.8 6.5 3.4 0.1 6.8 0.1 6.8 0.1 6.7 0.1 6.7 3.4 0.1 6.8 0.1 6.8 0.1 6.7 0.1 6.7 ns ns ns ns ns ns 6.9 Switching Characteristics: VCCA = 2.5 V 0.2 V over recommended operating free-air temperature range, VCCA = 2.5 V 0.2 V (see Figure 3) PARAMETER tPLH tPHL tPLH tPHL tPZH tPZL tPZH tPZL tPHZ tPLZ tPHZ tPLZ 8 FROM (INPUT) TO (OUTPUT) A B B A OE A OE B OE A OE B VCCB = 1.2 V VCCB = 1.5 V 0.1 V VCCB = 1.8 V 0.15 V VCCB = 2.5 V 0.2 V VCCB = 3.3 V 0.3 V TYP MIN MAX MIN MAX MIN MAX MIN MAX 1.9 0.1 3.8 0.1 3.2 0.1 2.7 0.1 2.6 1.9 0.1 3.8 0.1 3.2 0.1 2.7 0.1 2.6 1.8 0.5 3.4 0.2 3.1 0.1 2.8 0.1 2.6 1.8 0.5 3.4 0.2 3.1 0.1 2.8 0.1 2.6 3.1 0.7 6.2 0.5 5.2 0.3 4.1 0.3 3.6 3.1 0.7 6.2 0.5 5.2 0.3 4.1 0.3 3.6 1.4 0.4 4.5 0.4 4.5 0.4 4.5 0.4 4.5 1.4 0.4 4.5 0.4 4.5 0.4 4.5 0.4 4.5 3.6 0.2 5.2 0.1 5.4 0.1 4.5 0.7 6 3.6 0.2 5.2 0.1 5.4 0.1 4.5 0.7 6 2.1 0.1 4.7 0.1 4.6 0.1 4.7 0.1 4.7 2.1 0.1 4.7 0.1 4.6 0.1 4.7 0.1 4.7 Submit Documentation Feedback UNIT ns ns ns ns ns ns Copyright (c) 2008-2016, Texas Instruments Incorporated Product Folder Links: SN74AVC2T245 SN74AVC2T245 www.ti.com SCES692D - JUNE 2008 - REVISED FEBRUARY 2016 6.10 Switching Characteristics: VCCA = 3.3 V 0.3 V over recommended operating free-air temperature range, VCCA = 3.3 V 0.3 V (see Figure 3) PARAMETER FROM (INPUT) TO (OUTPUT) A B B A OE A OE B OE A OE B tPLH tPHL tPLH tPHL tPZH tPZL tPZH tPZL tPHZ tPLZ tPHZ tPLZ VCCB = 1.2 V VCCB = 1.5 V 0.1 V VCCB = 1.8 V 0.15 V VCCB = 2.5 V 0.2 V VCCB = 3.3 V 0.3 V TYP MIN MAX MIN MAX MIN MAX MIN MAX 1.8 0.1 3.6 0.1 3 0.1 2.6 0.1 2.4 1.8 0.1 3.6 0.1 3 0.1 2.6 0.1 2.4 1.9 0.5 3.4 0.2 2.9 0.1 2.5 0.1 2.3 1.9 0.5 3.4 0.2 2.9 0.1 2.5 0.1 2.3 3.1 0.9 5.9 0.5 5 0.3 3.8 0.3 3.3 3.1 0.9 5.9 0.5 5 0.3 3.8 0.3 3.3 1.2 0.4 3.6 0.4 3.6 0.4 3.6 0.4 3.6 1.2 0.4 3.6 0.4 3.6 0.4 3.6 0.4 3.6 3.4 0.1 4.6 0.1 4.7 0.3 4.8 0.7 4.5 3.4 0.1 4.6 0.1 4.7 0.3 4.8 0.7 4.5 2.9 0.1 5.4 0.1 5.3 0.1 5.3 0.1 5.3 2.9 0.1 5.4 0.1 5.3 0.1 5.3 0.1 5.3 UNIT ns ns ns ns ns ns 6.11 Operating Characteristics TA = 25C VCCA = VCCB = 1.2 V VCCA = VCCB = 1.5 V VCCA = VCCB = 1.8 V VCCA = VCCB = 2.5 V VCCA = VCCB = 3.3 V TYP TYP TYP TYP TYP 3 3 3 3 4 1 1 1 2 2 12 13 13 15 15 Outputs disabled 1 2 2 2 2 Outputs enabled 12 13 13 14 16 1 2 2 2 2 3 3 3 4 4 1 1 1 2 2 PARAMETER A to B CpdA (1) B to A A to B CpdB (1) B to A (1) TEST CONDITIONS Outputs enabled Outputs disabled Outputs enabled Outputs disabled Outputs enabled CL = 0, f = 10 MHz, tr = tf = 1 ns CL = 0, f = 10 MHz, tr = tf = 1 ns Outputs disabled UNIT pF pF Power dissipation capacitance per transceiver. Refer to the TI application report, CMOS Power Consumption and Cpd Calculation, SCAA035 Submit Documentation Feedback Copyright (c) 2008-2016, Texas Instruments Incorporated Product Folder Links: SN74AVC2T245 9 SN74AVC2T245 SCES692D - JUNE 2008 - REVISED FEBRUARY 2016 www.ti.com 1.4 5.6 1.2 5.4 1.0 5.2 VOH Voltage (V) VOL Voltage (V) 6.12 Typical Characteristics 0.8 0.6 0.4 4.8 4.6 o -40 C o 25 C 0.2 5.0 o -40 C o 25 C 4.4 o o 85 C 85 C 4.2 0 0 10 20 40 60 80 100 0 -20 -40 -60 -80 IOL Current (mA) IOH Current (mA) Figure 1. VOL Voltage vs IOL Current Figure 2. VOH Voltage vs IOH Current Submit Documentation Feedback -100 Copyright (c) 2008-2016, Texas Instruments Incorporated Product Folder Links: SN74AVC2T245 SN74AVC2T245 www.ti.com SCES692D - JUNE 2008 - REVISED FEBRUARY 2016 7 Parameter Measurement Information 2 x VCCO S1 RL From Output Under Test Open GND CL (see Note A) TEST S1 tpd tPLZ/tPZL tPHZ/tPZH Open 2 x VCCO GND RL tw LOAD CIRCUIT VCCI VCCI/2 Input VCCO CL RL VTP 1.2 V 1.5 V 0.1 V 1.8 V 0.15 V 2.5 V 0.2 V 3.3 V 0.3 V 15 pF 15 pF 15 pF 15 pF 15 pF 2 kW 2 kW 2 kW 2 kW 2 kW 0.1 V 0.1 V 0.15 V 0.15 V 0.3 V VCCI/2 0V VOLTAGE WAVEFORMS PULSE DURATION VCCA Output Control (low-level enabling) VCCA/2 VCCA/2 0V tPLZ tPZL VCCI Input VCCI/2 VCCI/2 0V tPLH Output tPHL VOH VCCO/2 VOL VCCO/2 VCCO Output Waveform 1 S1 at 2 x VCCO (see Note B) VCCO/2 VOL + VTP VOL tPHZ tPZH Output Waveform 2 S1 at GND (see Note B) VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES VCCO/2 VOH - VTP VOH 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50 W, dv/dt 1 V/ns. D. The outputs are measured one at a time, with one transition per measurement. E. t PLH and tPHL are the same as tpd. F. VCCI is the VCC associated with the input port. G. VCCO is the VCC associated with the output port. Figure 3. Load and Circuit and Voltage Waveforms Submit Documentation Feedback Copyright (c) 2008-2016, Texas Instruments Incorporated Product Folder Links: SN74AVC2T245 11 SN74AVC2T245 SCES692D - JUNE 2008 - REVISED FEBRUARY 2016 www.ti.com 8 Detailed Description 8.1 Overview The SN74AVC2T245 is a dual-bit, dual-supply noninverting bidirectional voltage level translation. Pins A and control pins (DIR and OE) are supported by VCCA and pins B are supported by VCCB. The A port can accept I/O voltages ranging from 1.2 V to 3.6 V, while the B port can accept I/O voltages from 1.2 V to 3.6 V. A high on DIR allows data transmission from A to B and a low on DIR allows data transmission from B to A when OE is set to low. When OE is set to high, both A and B are in the high-impedance state. This device is fully specified for partial-power-down applications using off output current (Ioff). The VCC isolation feature ensures that if either VCC input is at GND, both ports are put in a high-impedance state. 8.2 Functional Block Diagram DIR1 OE A1 B1 Figure 4. Logic Diagram (Positive Logic) 8.3 Feature Description 8.3.1 Fully Configurable Dual-Rail Design Allows Each Port to Operate Over the Full 1.2 V to 3.6 V Power-Supply Range Both VCCA and VCCB can be supplied at any voltage from 1.2 V to 3.6 V making the device suitable for translating between any of the low voltage nodes (1.2 V, 1.8 V, 2.5 V, and 3.3 V). 8.3.2 Partial-Power-Down Mode Operation This device is fully specified for partial-power-down applications using off output current (Ioff). The Ioff circuitry will prevent backflow current by disabling I/O output circuits when device is in partial power-down mode. 8.3.3 VCC Isolation The VCC isolation feature ensures that if either VCCA or VCCB are at GND, both ports will be in a high-impedance state (IOZ). This prevents false logic levels from being presented to either bus. 12 Submit Documentation Feedback Copyright (c) 2008-2016, Texas Instruments Incorporated Product Folder Links: SN74AVC2T245 SN74AVC2T245 www.ti.com SCES692D - JUNE 2008 - REVISED FEBRUARY 2016 8.4 Device Functional Modes The SN74AVC2T245 is a voltage level translator that can operate from1.2 V to 3.6 V (VCCA) and 1.2 V to 3.6 V (VCCB). The signal translation requires direction control and output enable control. The table below enlists the operation of the part for the respective states of the control inputs. Table 1. Function Table (1) (Each Transceiver) CONTROL INPUTS (1) OUTPUT CIRCUITS OPERATION OE DIR1 A PORT B PORT L L Enabled Hi-Z B data to A data L H Hi-Z Enabled A data to B data H X Hi-Z Hi-Z Isolation Input circuits of the data I/Os are always active. Submit Documentation Feedback Copyright (c) 2008-2016, Texas Instruments Incorporated Product Folder Links: SN74AVC2T245 13 SN74AVC2T245 SCES692D - JUNE 2008 - REVISED FEBRUARY 2016 www.ti.com 9 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI's customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 9.1 Application Information The SN74AVC2T45 is used to shift IO voltage levels from one voltage domain to another. Bus A and bus B have independent power supplies, and a direction pin is used to control the direction of data flow. Unused data ports must not be floating; tie the unused port input and output to ground directly. 9.1.1 Enable Times Calculate the enable times for the SN74AVC16T45 using the following formulas: tPZH (DIR to A) = tPLZ tPZL (DIR to A) = tPHZ tPZH (DIR to B) = tPLZ tPZL (DIR to B) = tPHZ (DIR (DIR (DIR (DIR to to to to B) + B) + A) + A) + tPLH (B to tPHL (B to tPLH (A to tPHL (A to A) A) B) B) (1) (2) (3) (4) In a bidirectional application, these enable times provide the maximum delay from the time the DIR bit is switched until an output is expected. For example, if the SN74AVC2T245 initially is transmitting from A to B, then the DIR bit is switched; the B port of the device must be disabled before presenting it with an input. After the B port has been disabled, an input signal applied to it appears on the corresponding A port after the specified propagation delay. 9.2 Typical Application 3.0 V 1.8 V 1 k VCCA VCCB OE Peripheral DIR1 Processor UART Tx A1 B1 Rx Rx A2 B2 Tx DIR2 SN1203086 GND Figure 5. Typical Application of the SN74AVC2T245 9.2.1 Design Requirements This device uses drivers which are enabled depending on the state of the DIR pin. The designer must know the intended flow of data and take care not to violate any of the high or low logic levels. Unused data inputs must not be floating, as this can cause excessive internal leakage on the input CMOS structure. Tie any unused input and output ports directly to ground. For this design example, use the parameters listed in Table 2. 14 Submit Documentation Feedback Copyright (c) 2008-2016, Texas Instruments Incorporated Product Folder Links: SN74AVC2T245 SN74AVC2T245 www.ti.com SCES692D - JUNE 2008 - REVISED FEBRUARY 2016 Table 2. Design Parameters DESIGN PARAMETER EXAMPLE VALUE Input voltage range 1.2 V to 3.6 V Output voltage range 1.2 V to 3.6 V 9.2.2 Detailed Design Procedure To begin the design process, determine the following: 9.2.2.1 Input Voltage Ranges Use the supply voltage of the device that is driving the SN74AVC2T245 device to determine the input voltage range. For a valid logic high the value must exceed the VIH of the input port. For a valid logic low the value must be less than the VIL of the input port. 9.2.2.2 Output Voltage Range Use the supply voltage of the device that the SN74AVC2T245 device is driving to determine the output voltage range. 9.2.3 Application Curves 3.5 Input Output 3 Magnitude (V) 2.5 2 1.5 1 0.5 0 -0.5 D001 Figure 6. 3.3 V to 1.8 V Level-Shifting With 1-MHz Square Wave Submit Documentation Feedback Copyright (c) 2008-2016, Texas Instruments Incorporated Product Folder Links: SN74AVC2T245 15 SN74AVC2T245 SCES692D - JUNE 2008 - REVISED FEBRUARY 2016 www.ti.com 10 Power Supply Recommendations The SN74AVC2T245 device uses two separate configurable power-supply rails, VCCA and VCCB. VCCA accepts any supply voltage from 1.2 V to 3.6 V and VCCB accepts any supply voltage from 1.2 V to 3.6 V. The A port and B port are designed to track VCCA and VCCB respectively allowing for low-voltage bidirectional translation between any of the 1.2 V, 1.5 V, 1.8 V, 2.5 V, 3.3 V and 5 V voltage nodes. 11 Layout 11.1 Layout Guidelines To * * * ensure reliability of the device, following common printed-circuit-board layout guidelines is recommended. Bypass capacitors should be used on power supplies. Short trace lengths should be used to avoid excessive loading. Placing pads on the signal paths for loading capacitors or pullup resistors to help adjust rise and fall times of signals depending on the system requirements. 11.2 Layout Example LEGEND VIA to Power Plane Polygonal Copper Pour VIA to GND Plane (Inner Layer) Bypass Capacitor Bypass Capacitor 8 A1 To Controller 9 A2 10 DIR1 VCCA From Controller 7 6 VCCA VCCB SN74AVC2T245 DIR2 OE 1 2 B1 5 To System B2 4 From System GND 3 Keep OE high until VCCA and VCCB are powered up VCCA Figure 7. Recommended Layout Example 16 Submit Documentation Feedback Copyright (c) 2008-2016, Texas Instruments Incorporated Product Folder Links: SN74AVC2T245 SN74AVC2T245 www.ti.com SCES692D - JUNE 2008 - REVISED FEBRUARY 2016 12 Device and Documentation Support 12.1 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2ETM Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support. 12.2 Trademarks E2E is a trademark of Texas Instruments. All other trademarks are the property of their respective owners. 12.3 Electrostatic Discharge Caution These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 12.4 Glossary SLYZ022 -- TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 13 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. Submit Documentation Feedback Copyright (c) 2008-2016, Texas Instruments Incorporated Product Folder Links: SN74AVC2T245 17 PACKAGE OPTION ADDENDUM www.ti.com 9-Jan-2018 PACKAGING INFORMATION Orderable Device Status (1) SN74AVC2T245RSWR ACTIVE Package Type Package Pins Package Drawing Qty UQFN RSW 10 3000 Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Green (RoHS & no Sb/Br) CU NIPDAU | CU NIPDAUAG Level-1-260C-UNLIM Op Temp (C) Device Marking (4/5) -40 to 85 (TQ7, TQO, TQR, TQ V) (TQH, TQJ, TQY) (VCH, VCO) (VCJ, VCR) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. 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Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 9-Jan-2018 Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 3-Aug-2017 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant SN74AVC2T245RSWR UQFN RSW 10 3000 180.0 9.5 1.6 2.0 0.8 4.0 8.0 Q1 SN74AVC2T245RSWR UQFN RSW 10 3000 180.0 8.4 1.59 2.09 0.72 4.0 8.0 Q1 SN74AVC2T245RSWR UQFN RSW 10 3000 179.0 8.4 1.7 2.1 0.7 4.0 8.0 Q1 SN74AVC2T245RSWR UQFN RSW 10 3000 180.0 9.5 1.16 1.16 0.5 4.0 8.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 3-Aug-2017 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN74AVC2T245RSWR UQFN RSW 10 3000 189.0 185.0 36.0 SN74AVC2T245RSWR UQFN RSW 10 3000 202.0 201.0 28.0 SN74AVC2T245RSWR UQFN RSW 10 3000 203.0 203.0 35.0 SN74AVC2T245RSWR UQFN RSW 10 3000 184.0 184.0 19.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated (TI) reserves the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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