Dual 12-/14-/16-Bit, LVDS Interface 600 MSPS DACs AD9780/AD9781/AD9783 Preliminary Technical Data FEATURES GENERAL DESCRIPTION High dynamic range, dual DAC parts Low noise and intermodulation distortion Single carrier WCDMA ACLR = 80 dBc @ 61.44 MHz IF Innovative switching output stage permits useable outputs beyond Nyquist frequency LVCMOS inputs with dual-port or optional interleaved single-port operation Differential analog current outputs are programmable from 8.6 mA to 31.7 mA full scale Auxiliary 10-bit current DACs with source/sink capability for external offset nulling Internal 1.2 V precision reference voltage source Operates from 1.8 V and 3.3 V supplies 315 mW power dissipation Small footprint, RoHS compliant, 72-lead LFCSP The AD9780/AD9781/AD9783 include pin-compatible, high dynamic range, dual digital-to-analog converters (DACs) with 12-/14-/16-bit resolutions, and sample rates of up to 600 MSPS. The devices include specific features for direct conversion transmit applications, including gain and offset compensation, and they interface seamlessly with analog quadrature modulators such as the ADL5370. APPLICATIONS 1. Low noise and intermodulation distortion (IMD) enables high quality synthesis of wideband signals. 2. Proprietary switching output for enhanced dynamic performance. 3. Programmable current outputs and dual auxiliary DACs provide flexibility and system enhancements. A proprietary, dynamic output architecture permits synthesis of analog outputs even above Nyquist by shifting energy away from the fundamental and into the image frequency. Full programmability is provided through a serial peripheral interface (SPI) port. Some pin-programmable features are also offered for those applications without a controller. PRODUCT HIGHLIGHTS Wireless infrastructure WCDMA, CDMA2000, TD-SCDMA, WiMAX Wideband communications LMDS/MMDS, point-to-point RF signal generators, arbitrary waveform generators FUNCTIONAL BLOCK DIAGRAM AD9783 DUAL LVDS DAC CLKP 16-BIT I DAC IOUT1P 16-BIT Q DAC IOUT2P INTERFACE LOGIC GAIN DAC IOUT1N IOUT2N GAIN DAC OFFSET DAC AUX1P OFFSET DAC AUX2P AUX1N AUX2N 06936-001 RSET CSB SCLK SDO SDIO SERIAL PERIPHERAL INTERFACE INTERNAL REFERENCE AND BIAS REFIO LVDS INTERFACE D(15:0) VIA, VIB DEINTERLEAVING LOGIC CLKN Figure 1 Rev. PrG Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 (c)2007 Analog Devices, Inc. All rights reserved. AD9780/AD9781/AD9783 Preliminary Technical Data TABLE OF CONTENTS Features .............................................................................................. 1 General Operation of the Serial Interface ............................... 18 Applications ....................................................................................... 1 Instruction Byte .......................................................................... 18 General Description ......................................................................... 1 MSB/LSB Transfers .................................................................... 19 Product Highlights ........................................................................... 1 Serial Interface Port Pin Descriptions ..................................... 19 Functional Block Diagram .............................................................. 1 SPI Register Map ............................................................................ 20 Specifications..................................................................................... 3 SPI Register Descriptions .............................................................. 21 DC Specifications ......................................................................... 3 SPI Port, RESET, and Pin Mode ............................................... 23 Digital Specifications ................................................................... 4 Parallel Data Port Interface ....................................................... 23 AC Specifications.......................................................................... 4 Optimizing the Parallel Port Timing ....................................... 23 Absolute Maximum Ratings............................................................ 5 Driving the CLK Input .............................................................. 25 Thermal Resistance ...................................................................... 5 Full-Scale Current Generation ................................................. 25 ESD Caution .................................................................................. 5 DAC Transfer Function ............................................................. 26 Pin Configuration and Function Descriptions ............................. 6 Analog Modes of Operation ..................................................... 26 Typical Performance Characteristics ............................................. 9 Power Dissipation....................................................................... 27 Terminology .................................................................................... 17 Outline Dimensions ....................................................................... 29 Theory of Operation ...................................................................... 18 Ordering Guide .......................................................................... 29 Serial Peripheral Interface ......................................................... 18 Rev. PrG | Page 2 of 32 Preliminary Technical Data AD9780/AD9781/AD9783 SPECIFICATIONS DC SPECIFICATIONS TMIN to TMAX, AVDD33 = 3.3 V, DVDD33 = 3.3 V, DVDD18 = 1.8 V, CVDD18 = 1.8 V, IOUTFS = 20 mA maximum sample rate, unless otherwise noted. Table 1. Parameter RESOLUTION ACCURACY Differential Nonlinearity (DNL) Integral Nonlinearity (INL) MAIN DAC OUTPUTS Offset Error Gain Error (with Internal Reference) Full-Scale Output Current1 Output Compliance Range Output Resistance Gain DAC Monotonicity Guaranteed MAIN DAC TEMPERATURE DRIFT Offset Gain Reference Voltage AUX DAC OUTPUTS Resolution Full-Scale Output Current Output Compliance Range (Source) Output Compliance Range (Sink) Output Resistance AUX DAC Monotonicity Guaranteed REFERENCE Internal Reference Voltage Output Resistance ANALOG SUPPLY VOLTAGES AVDD33 CVDD18 DIGITAL SUPPLY VOLTAGES DVDD33 DVDD18 POWER CONSUMPTION fDAC = 500 MSPS, IF = 20 MHz fDAC = 600 MSPS, IF = 10 MHz Power-Down Mode SUPPLY CURRENTS2 AVDD33 CVDD18 DVDD33 DVDD18 1 2 Min AD9780 Typ Max 12 Min 0.13 0.25 -0.001 8.66 -1.0 0 2 20.2 AD9781 Typ Max 14 Min 0.5 1 +0.001 -0.001 31.66 +1.0 8.66 -1.0 2 4 +0.001 -0.001 31.66 +1.0 8.66 -1.0 LSB LSB 10 10 10 0.04 100 30 0.04 100 30 0.04 100 30 ppm/C ppm/C ppm/C +0.001 31.66 +1.0 1 1 1 Bits mA V V M 1.2 5 1.2 5 1.2 5 V k -2 0 0.8 10 0 2 20.2 Unit Bits % FSR % FSR mA V M 10 0 2 20.2 AD9783 Typ Max 16 +2 1.6 1.6 -2 0 0.8 10 +2 1.6 1.6 -2 0 0.8 +2 1.6 1.6 3.13 1.70 3.3 1.8 3.47 1.90 3.13 1.70 3.3 1.8 3.47 1.90 3.13 1.70 3.3 1.8 3.47 1.90 V V 3.13 1.70 3.3 1.8 3.47 1.90 3.13 1.70 3.3 1.8 3.47 1.90 3.13 1.70 3.3 1.8 3.47 1.90 V V VxI 440 3 VxI VxI 5 VxI 440 3 VxI 5 VxI 440 3 35 mW mW mW 55 34 13 68 58 38 15 85 55 34 13 68 58 38 15 85 55 34 13 68 58 38 15 85 mA mA mA mA Based on a 10 k external resistor. FDAC = 500 MSPS, FOUT = 20 MHz. Rev. PrG | Page 3 of 32 AD9780/AD9781/AD9783 Preliminary Technical Data DIGITAL SPECIFICATIONS TMIN to TMAX, AVDD33 = 3.3 V, DVDD33 = 3.3 V, DVDD18 = 1.8 V, CVDD18 = 1.8 V, IOUTFS = 20 mA, maximum sample rate, unless otherwise noted. Table 2. Parameter DAC CLOCK INPUT (CLKP, CLKN) Peak-to-Peak Voltage at CLKP and CLKN Common-Mode Voltage Maximum Clock Rate SERIAL PERIPHERAL INTERFACE (CMOS Interface) Maximum Clock Rate (SCLK) Minimum Pulse Width High Minimum Pulse Width Low DIGITAL INPUT DATA (LVDS Interface) Input Voltage Range, VIA or VIB Input Differential Threshold, VIDTH Input Differential Hysteresis, VIDTHH to VIDTHL Input Differential Input Impedance, Maximum LVDS Input Rate (Per DAC) Min Typ Max Unit 400 300 600 800 400 1600 500 mV mV MSPS 40 12.5 12.5 MHz ns ns 1600 +100 mV mV mV MSPS 800 -100 20 80 600 120 AC SPECIFICATIONS TMIN to TMAX, AVDD33 = 3.3 V, DVDD33 = 3.3 V, DVDD18 = 1.8 V, CVDD18 = 1.8 V, IOUTFS = 20 mA, maximum sample rate, unless otherwise noted. Table 3. Parameter SPURIOUS FREE DYNAMIC RANGE (SFDR) fDAC = 600 MSPS, fOUT = 20 MHz fDAC = 600 MSPS, fOUT = 120 MHz fDAC = 600 MSPS, fOUT = 480 MHz (Mix Mode) fDAC = 600 MSPS, fOUT = 580 MHz (Mix Mode) TWO-TONE INTERMODULATION DISTORTION (IMD) fDAC = 600 MSPS, fOUT = 20 MHz fDAC = 600 MSPS, fOUT = 120 MHz fDAC = 600 MSPS, fOUT = 480 MHz (Mix Mode) fDAC = 600 MSPS, fOUT = 580 MHz (Mix Mode) NOISE SPECTRAL DENSITY (NSD) One-Tone fDAC = 600 MSPS, fOUT = 40 MHz fDAC = 600 MSPS, fOUT = 120 MHz fDAC = 600 MSPS, fOUT = 480 MHz (Mix Mode) fDAC = 600 MSPS, fOUT = 580 MHz (Mix Mode) WCDMA ADJACENT CHANNEL LEAKAGE RATIO (ACLR), SINGLE CARRIER fDAC = 491.52 MSPS, fOUT = 20 MHz fDAC = 491.52 MSPS, fOUT = 80 MHz fDAC = 491.52 MSPS, fOUT = 411.52 MHz fDAC = 491.52 MSPS, fOUT = 471.52 MHz AD9780 Min Typ Max AD9781 Min Typ Max AD9783 Min Typ Max Unit 79 67 58 58 78 66 62 56 80 68 59 60 dBc dBc dBc dBc 91 80 60.5 58 93 75 61.5 59 86 79 66 59 dBc dBc dBc dBc -157 -154.5 -152 -152 -162 -156.5 -152 -151 -165 -157 -153 -152 dBc dBc dBc dBc -81 -80 -71 -69 -82.5 -82.5 -68 -69 -82 -81 -69 -70 dBc dBc dBc dBc Rev. PrG | Page 4 of 32 Preliminary Technical Data AD9780/AD9781/AD9783 ABSOLUTE MAXIMUM RATINGS Table 4. Parameter AVDD33, DVDD33 DVDD18, CVDD18 AGND DGND CGND REFIO With Respect to AGND, DGND, CGND AGND, DGND, CGND DGND, CGND AGND, CGND AGND, DGND AGND IOUT1P, IOUT1N, IOUT2P, IOUT2N, AUX1P, AUX1N, AUX2P, AUX2N D15 to D0 AGND CLKP, CLKN CGND CSB, SCLK, SDIO, SDO DGND Junction Temperature Storage Temperature DGND THERMAL RESISTANCE Rating -0.3 V to +3.6 V Thermal resistance tested using JEDEC standard 4-layer thermal test board with no airflow. -0.3 V to +1.98 V Table 5. -0.3 V to +0.3 V -0.3 V to +0.3 V -0.3 V to +0.3 V -0.3 V to AVDD33 + 0.3 V -1.0 V to AVDD33 + 0.3 V -0.3 V to DVDD33 + 0.3 V -0.3 V to CVDD18 + 0.3 V -0.3 V to DVDD33 + 0.3 V +125C -65C to +150C Package Type CP-72-1 (Exposed Pad Soldered to PCB) JA 25 Unit C/W Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD CAUTION Rev. PrG | Page 5 of 32 AD9780/AD9781/AD9783 Preliminary Technical Data 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 AVDD33 AVDD33 AVSS IOUT1P IOUT1N AVSS AUX1P AUX1N AVSS AUX2N AUX2P AVSS IOUT2N IOUT2P AVSS AVDD33 AVDD33 REFIO PIN CONFIGURATION AND FUNCTION DESCRIPTIONS AD9780 (TOP VIEW) D6P D6N D5P D5N D4P D4N DCOP DCON DVDD33 DVSS DCIP DCIN D3P D3N D2P D2N D1P D1N NC = NO CONNECT PIN 1 INDICATOR 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 FS ADJ RESET CSB SCLK SDIO SDO DVSS DVDD18 NC NC NC NC NC NC NC NC D0N D0P 06936-002 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 CVDD18 CVSS CLKP CLKN CVSS CVDD18 DVSS DVDD18 D11P D11N D10P D10N D9P D9N D8P D8N D7P D7N Figure 2. AD9780 Pin Configuration Table 6. AD9780 Pin Function Descriptions Pin No. 1, 6 2, 5 3, 4 7, 28, 48 8, 47 9, 10 11 to 24, 31 to 36 25, 26 27 29, 30 37, 38 39 to 46 49 50 51 52 53 54 55 56, 57, 71, 72 58, 61, 64, 67, 70 59 60 62, 63 65, 66 68 69 Mnemonic CVDD18 CVSS CLKP, CLKN DVSS DVDD18 D11P, D11N D10P to D1P, D10N toD1N DCOP, DCON DVDD33 DCIP, DCIN D0P, D0N NC SDO SDIO SCLK CSB RESET FS ADJ REFIO AVDD33 AVSS IOUT2P IOUT2N AUX2P,AUX2N AUX1N,AUX1P IOUT1N IOUT1P Description Clock Supply Voltage (1.8 V). Clock Supply Return. Differential DAC Sampling Clock Input. Digital Common. Digital Supply Voltage (1.8 V). LVDS Data Input (MSB) LVDS Data Inputs. Differential Data Clock Output. LVDS clock at the DAC sample rate. Digital Input and Output Pad Ring Supply Voltage (3.3 V). Differential Data Clock Input. LVDS clock aligned with input data. LVDS Data Input (LSB). No Connection. Leave these pins floating. Serial Port Data Output. Serial Port Data Input (4-Wire Mode). Bidirectional serial data line (3-wire mode). Serial Port Clock Input. Serial Port Chip Select (Active Low). Chip Reset (Active High). Full-Scale Current Output Adjust. Analog Reference Input/Output (1.2 V Nominal). Analog Supply Voltage (3.3 V). Analog Common. DAC Current Output. Full-scale current is sourced when all data bits are 1s. Complementary DAC Current Output. Full-scale current is sourced when all data bits are 0s. Differential Auxiliary DAC current output (Channel 2). Differential Auxiliary DAC current output (Channel 1). Complementary DAC Current Output. Full-scale current is sourced when all data bits are 0s. DAC Current Output. Full-scale current is sourced when all data bits are 1s. Rev. PrG | Page 6 of 32 AD9780/AD9781/AD9783 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 AVDD33 AVDD33 AVSS IOUT1P IOUT1N AVSS AUX1P AUX1N AVSS AUX2N AUX2P AVSS IOUT2N IOUT2P AVSS AVDD33 AVDD33 REFIO Preliminary Technical Data AD9781 (TOP VIEW) D8P D8N D7P D7N D6P D6N DCOP DCON DVDD33 DVSS DCIP DCIN D5P D5N D4P D4N D3P D3N NC = NO CONNECT PIN 1 INDICATOR 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 FS ADJ RESET CSB SCLK SDIO SDO DVSS DVDD18 NC NC NC NC D0N D0P D1N D1P D2N D2P 06936-003 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 CVDD18 CVSS CLKP CLKN CVSS CVDD18 DVSS DVDD18 D13P D13N D12P D12N D11P D11N D10P D10N D9P D9N Figure 3. AD9781 Pin Configuration Table 7. AD9781 Pin Function Descriptions Pin No. 1, 6 2, 5 3, 4 7, 28, 48 8, 47 9, 10 11 to 24, 31 to 40 25, 26 27 29, 30 41, 42 43 to 46 49 50 51 52 53 54 55 56, 57, 71, 72 58, 61, 64, 67, 70 59 60 62, 63 65, 66 68 69 Mnemonic CVDD18 CVSS CLKP, CLKN DVSS DVDD18 D13P, D13N D12P, D12N to D1P, D1N DCOP,DCON DVDD33 DCIP, DCIN D0P, D0N NC SDO SDIO SCLK CSB RESET FS ADJ REFIO AVDD33 AVSS IOUT2P IOUT2N AUX2P,AUX2N AUX1N,AUX1P IOUT1N IOUT1P Description Clock Supply Voltage (1.8 V). Clock Supply Return. Differential DAC Sampling Clock Input. Digital Common. Digital Supply Voltage (1.8 V). LVDS Data Input (MSB). LVDS Data Inputs. Differential Data Clock Output. LVDS clock at the DAC sample rate. Digital Input and Output pad ring supply voltage (3.3 V). Differential Data Clock Input. LVDS clock aligned with input data. LVDS Data Input (LSB). No connection. Leave these pins floating. Serial Port Data Output. Serial Port Data Input (4-Wire Mode). Bidirectional serial data line (3-wire mode). Serial Port Clock Input. Serial Port Chip Select (Active Low). Chip Reset (Active High). Full-Scale Current Output Adjust. Analog Reference Input/Output (1.2 V nominal). Analog Supply Voltage (3.3 V). Analog Common. DAC Current Output. Full-scale current is sourced when all data bits are 1s. Complementary DAC Current Output. Full-scale current is sourced when all data bits are 0s. Differential Auxiliary DAC current output (Channel 2). Differential Auxiliary DAC current output (Channel 1). Complementary DAC Current Output. Full-scale current is sourced when all data bits are 0s. DAC Current Output. Full-scale current is sourced when all data bits are 1s. Rev. PrG | Page 7 of 32 Preliminary Technical Data 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 AVDD33 AVDD33 AVSS IOUT1P IOUT1N AVSS AUX1P AUX1N AVSS AUX2N AUX2P AVSS IOUT2N IOUT2P AVSS AVDD33 AVDD33 REFIO AD9780/AD9781/AD9783 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 PIN 1 INDICATOR AD9783 (TOP VIEW) 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 FS ADJ RESET CSB SCLK SDIO SDO DVSS DVDD18 D0N D0P D1N D1P D2N D2P D3N D3P D4N D4P 06936-004 D10P D10N D9P D9N D8P D8N DCOP DCON DVDD33 DVSS DCIP DCIN D7P D7N D6P D6N D5P D5N 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 CVDD18 CVSS CLKP CLKN CVSS CVDD18 DVSS DVDD18 D15P D15N D14P D14N D13P D13N D12P D12N D11P D11N Figure 4. AD9783 Pin Configuration Table 8. AD9783 Pin Function Descriptions Pin No. 1, 6 2, 5 3, 4 7, 28, 48 8, 47 9, 10 11 to 24, 31 to 44 25, 26 27 29, 30 45, 46 49 50 51 52 53 54 55 56, 57, 71, 72 58, 61, 64, 67, 70 59 60 62, 63 65, 66 68 69 Mnemonic CVDD18 CVSS CLKP, CLKN DVSS DVDD18 D15P, D15N D14P, D14N to D1P, D1N DCOP, DCON DVDD33 DCIP, DCIN D0P, D0N SDO SDIO SCLK CSB RESET FS ADJ REFIO AVDD33 AVSS IOUT2P IOUT2N AUX2P,AUX2N AUX1N,AUX1P IOUT1N IOUT1P Description Clock Supply Voltage (1.8 V). Clock Supply Return. Differential DAC Sampling Clock Input. Digital Common. Digital Supply Voltage (1.8 V). LVDS Data Input (MSB). LVDS Data Inputs. Differential Data Clock Output. LVDS clock at the DAC sample rate. Digital Input and Output Pad Ring Supply Voltage (3.3 V). Differential Data Clock Input. LVDS clock aligned with input data. LVDS Data Input (LSB). Serial Port Data Output. Serial Port Data Input (4-Wire Mode). Bidirectional serial data line (3-wire mode). Serial Port Clock Input. Serial Port Chip Select (Active Low). Chip RESET (active High). Full-Scale Current Output Adjust. Analog Reference Input/Output (1.2 V nominal). Analog Supply Voltage (3.3 V). Analog Common. DAC Current Output. Full-scale current is sourced when all data bits are 1s. Complementary DAC Current Output. Full-scale current is sourced when all data bits are 0s. Differential Auxiliary DAC Current Output (Channel 2). Differential Auxiliary DAC Current Output (Channel 1). Complementary DAC Current Output. Full-scale current is sourced when all data bits are 0s. DAC Current Output. Full-scale current is sourced when all data bits are 1s. Rev. PrG | Page 8 of 32 Preliminary Technical Data AD9780/AD9781/AD9783 TYPICAL PERFORMANCE CHARACTERISTICS 0.4 1.5 0.2 1.0 0 0.5 -0.2 -0.4 LSB LSB 0 -0.5 -0.6 -0.8 -1.0 -1.0 -1.5 -1.2 -2.0 0 16384 32768 49152 65535 CODE -1.6 0 16384 32768 49152 65535 CODE Figure 5. AD9783 INL 85C 06936-008 -1.4 06936-005 -2.5 Figure 8. AD9783 DNL 85C 5 0.4 0.2 4 0 3 -0.2 -0.4 LSB LSB 2 1 -0.6 -0.8 0 -1.0 -1 -1.2 -2 16384 32768 49152 65535 CODE -1.6 0 16384 32768 49152 65535 CODE Figure 6. AD9783 INL 25C 06936-009 0 06936-006 -3 -1.4 Figure 9. AD9783 DNL 25C 5 1.0 4 0.8 0.6 3 0.4 LSB 0.2 1 0 -0.2 0 -0.4 -1 -0.6 -2 -0.8 0 16384 32768 49152 CODE 65535 Figure 7. AD9783 INL -40C -1.0 0 16384 32768 49152 CODE Figure 10. AD9783 DNL -40C Rev. PrG | Page 9 of 32 65535 06936-010 -3 06936-007 LSB 2 AD9780/AD9781/AD9783 Preliminary Technical Data 0.059 0.4 0.3 0.2 -0.060 0.1 LSB LSB 0 -0.1 -0.179 -0.2 -0.3 -0.297 -0.4 0 4096 8192 12288 16383 CODE -0.416 06936-011 -0.6 0 4096 8192 12288 16383 CODE Figure 11. AD9781 INL 85C 06936-014 -0.5 Figure 14. AD9781 DNL 20mA FS 85C 0.1 0.6 0.4 0 0.2 -0.1 LSB LSB 0 -0.2 -0.4 -0.2 -0.3 -0.6 4096 8192 12288 16383 CODE -0.5 0 0.1 0 0 -0.1 -0.1 LSB 0.1 -0.2 -0.3 -0.4 -0.4 -0.5 -0.5 2048 3072 CODE 16383 -0.2 -0.3 4096 06936-013 LSB 0.2 1024 12288 Figure 15. AD9781 DNL -40C 0.2 0 8192 CODE Figure 12. AD9781 INL -40C -0.6 4096 Figure 13. AD9780 INL -40C -0.6 0 1024 2048 3072 CODE Figure 16. AD9780 INL 85C Rev. PrG | Page 10 of 32 4096 06936-016 0 06936-012 -1.0 06936-015 -0.4 -0.8 Preliminary Technical Data 90 100 85 95 90 250MSPS 80 85 400MSPS 75 +25C 80 70 SFDR (dBc) SFDR (dBc) AD9780/AD9781/AD9783 600MSPS 65 60 -40C 75 70 65 +85C 60 55 55 50 50 45 0 60 120 180 240 300 360 420 480 540 600 fOUT (MHz) 40 100 95 95 90 90 IMD (dBc) 150 180 210 240 270 300 250MSPS 70 65 75 600MSPS 400MSPS 70 65 60 10mA 55 50 50 45 45 30 60 90 120 150 180 210 240 270 300 fOUT (MHz) 40 06936-018 0 Figure 18. AD9783 SFDR vs. FOUT Over Analog Output, 25C, 600 MSPS 60 120 180 240 300 360 420 480 600 Figure 21. AD9783 IMD vs. FOUT Over FDAC in Baseband and Mix Modes 95 95 90 90 85 85 20mA 80 -3dBFS 30mA 75 IMD (dBc) 75 70 65 540 fOUT (MHz) 100 80 0 06936-021 55 -6dBFS 10mA 65 60 0dBFS 60 70 55 55 50 50 45 45 30 60 90 120 150 180 fOUT (MHz) 210 240 270 300 40 06936-019 0 Figure 19. AD9783 SFDR vs. FOUT Over Digital Input Level, 25C, 600 MSPS 0 30 60 90 120 150 180 210 240 270 300 fOUT (MHz) Figure 22. AD9783 IMD vs. FOUT Over Analog Output, 25C, 600 MSPS Rev. PrG | Page 11 of 32 06936-022 SFDR (dBc) 120 80 30mA 75 60 SFDR (dBc) 90 85 20mA 80 40 60 Figure 20. AD9783 SFDR vs. FOUT Over Temperature, 600 MSPS 100 40 30 fOUT (MHz) Figure 17. AD9783 SFDR vs. FOUT Over FDAC in Baseband and Mix Modes 85 0 06936-020 45 06936-017 40 AD9780/AD9781/AD9783 95 Preliminary Technical Data -140 0dBFS 90 -143 -3dBFS 85 -146 -6dBFS 80 -149 NSD (dBm/Hz) 70 65 60 45 -167 30 60 90 120 150 180 210 240 270 300 -170 06936-023 0 fOUT (MHz) Figure 23. AD9783 IMD vs. FOUT Over Digital Input Level, 25C, 600MSPS -140 -143 85 120 180 240 300 360 420 480 540 600 -146 -40C -149 +25C 70 65 +85C 60 +85C -152 -155 -158 55 -161 50 -164 45 -167 30 60 90 120 150 180 210 240 270 300 fOUT (MHz) -170 06936-024 0 Figure 24. AD9783 IMD vs. FOUT Over Temperature, 600MSPS 50 100 150 150 150 300 Figure 27. AD9783 1-Tone NSD vs. FOUT Over Temperature, 600MSPS -140 -143 -143 250MSPS 0 fOUT (MHz) -140 -146 -40C +25C 06936-027 NSD (dBm/Hz) 75 IMD (dBc) 60 Figure 26. AD9783 8-Tone NSD vs. FOUT Over FDAC Baseband and Mix Modes 90 80 0 fOUT (MHz) 95 -146 400MSPS -149 NSD (dBm/Hz) -149 -152 -155 -158 600MSPS -152 -155 -161 -164 -164 -167 -167 60 120 180 240 300 360 fOUT (MHz) 420 480 540 600 -170 06936-025 0 Figure 25. AD9783 1-Tone NSD vs. FOUT Over FDAC Baseband and Mix Modes +25C -158 -161 -170 600MSPS 06936-026 -164 40 400MSPS -158 50 40 250MSPS -155 -161 55 NSD (dBm/Hz) -152 +85C -40C 0 50 100 150 200 250 300 fOUT (MHz) Figure 28. AD9783 8-Tone NSD vs. FOUT Over Temperature, 600MSPS Rev. PrG | Page 12 of 32 06936-028 IMD (dBc) 75 AD9780/AD9781/AD9783 -50 -50 -55 -55 -60 -60 245.76MSPS -70 -75 -85 -85 100 200 300 400 500 fOUT (MHz) Figure 29. AD9783 ACLR For First Adjacent Band 1-Carrier WCDMA Baseband and Mix Modes -90 -55 -55 -60 -60 -65 -65 ACLR (dBc) -50 245.76MSPS 491.52MSPS -75 -70 200 300 400 500 -3dB -75 -80 -80 -85 -85 0dB 0 100 200 300 400 500 fOUT (MHz) -90 Figure 30. AD9783 ACLR For Second Adjacent Band 1-Carrier WCDMA Baseband and Mix Modes 0 -55 -60 -60 -65 -65 ACLR (dBc) -55 491.52MSPS -75 300 400 500 Figure 33. AD9783 ACLR for Second Adjacent Channel 2-Carrier WCDMA Over Digital Input Level Baseband and Mix Modes, 491.52 MSPS -50 245.76MSPS 200 fOUT (MHz) -50 -70 100 06936-033 -90 100 Figure 32. AD9783 ACLR for First Adjacent Channel 2-Carrier WCDMA Over Digital Input Level Baseband and Mix Modes, 491.52 MSPS -50 -70 0 fOUT (MHz) 06936-030 ACLR (dBc) -3dB -75 -80 0 0dB -70 -80 -90 ACLR (dBc) -65 06936-032 ACLR (dBc) 491.52MSPS -65 06936-029 ACLR (dBc) Preliminary Technical Data -70 -3dB -75 -80 -80 -85 -85 0 100 200 300 400 500 -90 06936-031 -90 fOUT (MHz) Figure 31. AD9783 ACLR For Third Adjacent Band 1-Carrier WCDMA Baseband and Mix Modes 06936-034 0dB 0 100 200 300 400 500 fOUT (MHz) Figure 34. AD9783 ACLR for Third Adjacent Channel 2-Carrier WCDMA Over Digital Input Level Baseband and Mix Modes, 491.52 MSPS Rev. PrG | Page 13 of 32 AD9780/AD9781/AD9783 Preliminary Technical Data 0 -50 -0.5 -55 -1.0 0dB -65 -70 -3dB -75 NORMAL MODE -1.5 AMPLITUDE (dBm) ACLR (dBc) -60 -2.0 -2.5 -3.0 MIX MODE -3.5 -80 -4.0 -85 100 200 300 400 500 fOUT (MHz) Figure 35. AD9783 ACLR for First Adjacent Channel 4-Carrier WCDMA Over Digital Input Level Baseband and Mix Modes, 491.52 MSPS 0.8 -55 0.6 -60 0.4 -3dB LSB 0dB -75 240 300 360 420 480 540 600 -0.2 -0.4 -85 -0.6 100 180 0 -80 0 120 0.2 -70 -90 60 Figure 38. Nominal Power In The Fundamental, 20 mA FS 600 MSPS -50 -65 0 fOUT (MHz) 200 300 400 500 fOUT (MHz) -0.8 06936-036 ACLR (dBc) -5.0 0 4096 8192 12288 16383 CODE 06936-039 0 06936-038 -4.5 06936-035 -90 Figure 39. AD9781 INL 20 mA FS Figure 36. AD9783 ACLR for Second Adjacent Channel 4-Carrier WCDMA Over Digital Input Level Baseband and Mix Modes, 491.52 MSPS 0.1 -50 -55 0 -60 -3dB LSB ACLR (dBc) -0.1 -65 -70 -75 0dB -0.2 -0.3 -80 0 100 200 300 fOUT (MHz) 400 500 06936-037 -90 Figure 37. AD9783 ACLR for Third Adjacent Channel 4-Carrier WCDMA Over Digital Input Level Baseband and Mix Modes, 491.52 MSPS Rev. PrG | Page 14 of 32 -0.5 0 4096 8192 12288 CODE Figure 40. AD9781 DNL 20 mA FS 16383 06936-040 -0.4 -85 Preliminary Technical Data AD9780/AD9781/AD9783 100 -50 95 -55 90 85 -60 75 70 65 60 55 FIRST ADJACENT CHANNEL -65 -70 -75 SECOND ADJACENT CHANNEL -85 45 0 60 120 180 240 300 360 420 480 540 600 fOUT (MHz) -90 06936-041 40 THIRD ADJACENT CHANNEL -80 50 Figure 41. AD9781 SFDR vs. FOUT in Baseband and Mix Modes, 600 MSPS 0 100 200 300 400 500 fOUT (MHz) 06936-044 ACLR (dBc) SFDR (dBc) 80 Figure 44. AD9781 ACLR For 1-Carrier WCDMA Baseband and Mix Modes, 491.52 MSPS 100 0.2 95 90 0.1 85 0 75 -0.1 70 LSB IMD (dBc) 80 65 60 -0.2 -0.3 55 -0.4 50 45 0 60 120 180 240 300 360 420 480 540 600 fOUT (MHz) -0.6 0 1024 2048 3072 4096 CODE Figure 42. AD9781 IMD vs. FOUT in Baseband and Mix Modes, 600 MSPS 06936-045 -0.5 06936-042 40 Figure 45. AD9780 INL 20 mA FS -140 0.04 -142 -144 0.02 -146 -148 0 1-TONE -152 -0.02 -154 -156 LSB NSD (dBm/Hz) -150 -158 -160 -0.06 8-TONE -162 -0.04 -164 -0.08 -166 0 60 120 180 240 300 360 fOUT (MHz) 420 480 540 600 06936-043 -170 Figure 43. AD9781 1-Tone, 8-Tone NSD vs. FOUT in Baseband and Mix Modes, 600 MSPS Rev. PrG | Page 15 of 32 -0.12 0 1024 2048 3072 CODE Figure 46. AD9780 DNL, 20 mA FS 4096 06936-046 -0.10 -168 AD9780/AD9781/AD9783 Preliminary Technical Data 100 -140 95 -142 -144 -146 85 -148 80 -150 NSD (dBm/Hz) 75 70 65 -156 -158 -160 55 -162 8-TONES -164 50 -166 45 120 180 240 300 360 420 480 540 600 -170 06936-047 60 Figure 47. AD9780 SFDR vs. FOUT in Baseband and Mix Modes, 600 MSPS 0 60 120 180 240 360 420 480 540 600 Figure 49. AD9780 1-Tone, 8-Tone NSD vs. FOUT in Baseband and Mix Modes, 600 MSPS 100 -50 95 -55 90 85 -60 ACLR (dBc) 80 75 70 65 60 55 FIRST ADJACENT CHANNEL -65 -70 -75 SECOND ADJACENT CHANNEL -80 50 -85 45 0 100 200 300 fOUT (MHz) 400 500 600 -90 06936-048 40 300 fOUT (MHz) 06936-049 -168 0 fOUT (MHz) IMD (dBc) -154 60 40 1-TONE -152 0 100 200 300 fOUT (MHz) Figure 48. AD9780 IMD vs. FOUT in Baseband and Mix Modes, 600 MSPS THIRD ADJACENT CHANNEL 400 500 06936-050 SFDR (dBc) 90 Figure 50. AD9780 ACLR For 1-Carrier WCDMA Baseband and Mix Modes, 491.52 MSPS Rev. PrG | Page 16 of 32 Preliminary Technical Data AD9780/AD9781/AD9783 TERMINOLOGY Linearity Error (Integral Nonlinearity or INL) Linearity error is defined as the maximum deviation of the actual analog output from the ideal output, determined by a straight line drawn from zero scale to full scale. Differential Nonlinearity (DNL) DNL is the measure of the variation in analog value, normalized to full scale, associated with a 1 LSB change in digital input code. Monotonicity A DAC is monotonic if the output either increases or remains constant as the digital input increases. Offset Error The deviation of the output current from the ideal of zero is called offset error. For IOUTA, 0 mA output is expected when the inputs are all 0s. For IOUTB, 0 mA output is expected when all inputs are set to 1. Gain Error The difference between the actual and ideal output span. The actual span is determined by the difference between the output when all inputs are set to 1 and the output when all inputs are set to 0. Output Compliance Range The range of allowable voltage at the output of a current-output DAC. Operation beyond the maximum compliance limits can cause either output stage saturation or breakdown, resulting in nonlinear performance. Temperature Drift Temperature drift is specified as the maximum change from the ambient (25C) value to the value at either TMIN or TMAX. For offset and gain drift, the drift is reported in ppm of full-scale range (FSR) per degree Celsius. For reference drift, the drift is reported in ppm per degree Celsius. Power Supply Rejection The maximum change in the full-scale output as the supplies are varied from minimum to maximum specified voltages. Settling Time The time required for the output to reach and remain within a specified error band around its final value, measured from the start of the output transition. Spurious Free Dynamic Range (SFDR) The difference, in decibels, between the peak amplitude of the output signal and the peak spurious signal between dc and the frequency equal to half the input data rate. Total Harmonic Distortion (THD) THD is the ratio of the rms sum of the first six harmonic components to the rms value of the measured fundamental. It is expressed as a percentage or in decibels. Signal-to-Noise Ratio (SNR) SNR is the ratio of the rms value of the measured output signal to the rms sum of all other spectral components below the Nyquist frequency, excluding the first six harmonics and dc. The value for SNR is expressed in decibels. Adjacent Channel Leakage Ratio (ACLR) The ratio in dBc between the measured power within a channel relative to its adjacent channel. Complex Image Rejection In a traditional two-part upconversion, two images are created around the second IF frequency. These images have the effect of wasting transmitter power and system bandwidth. By placing the real part of a second complex modulator in series with the first complex modulator, either the upper or lower frequency image near the second IF can be rejected. Rev. PrG | Page 17 of 32 AD9780/AD9781/AD9783 Preliminary Technical Data THEORY OF OPERATION The AD9780/AD9781/AD9783 combine many features to make them very attractive for wired and wireless communications systems. The dual DAC architecture facilitates easy interface to common quadrature modulators when designing single sideband transmitters. In addition, the speed and performance of the devices allows wider bandwidths and more carriers to be synthesized than in previously available products. All features and options are software programmable through the SPI port. SERIAL PERIPHERAL INTERFACE SDO SCLK AD9780 SPI PORT CSB 06936-051 SDIO Figure 51. SPI Port The serial peripheral interface (SPI) port is a flexible, synchronous serial communications port allowing easy interface to many industry-standard microcontrollers and microprocessors. The port is compatible with most synchronous transfer formats including both the Motorola SPI(R) and Intel(R) SSR protocols. The interface allows read and write access to all registers that configure the AD9780/AD9781/AD9783. Single or multiple byte transfers are supported as well as MSB-first or LSB-first transfer formats. Serial data input/output can be accomplished through a single bidirectional pin (SDIO) or through two unidirectional pins (SDIO/SDO). The serial port configuration is controlled by Register 0x00, Bits<7:6>. It is important to note that any change made to the serial port configuration occurs immediately upon writing to the last bit of this byte. Therefore, it is possible with a multibyte transfer to write to this register and change the configuration in the middle of a communication cycle. Care must be taken to compensate for the new configuration within the remaining bytes of the current communication cycle. Use of a single-byte transfer when changing the serial port configuration is recommended to prevent unexpected device behavior. GENERAL OPERATION OF THE SERIAL INTERFACE There are two phases to any communication cycle with the AD9780/AD9781/AD9783: Phase1 and Phase 2. Phase 1 is the instruction cycle, which writes an instruction byte into the device. This byte provides the serial port controller with information regarding Phase 2 of the communication cycle: the data transfer cycle. The Phase 1 instruction byte defines whether the upcoming data transfer is a read or write, the number of bytes in the data transfer, and a reference register address for the first byte of the data transfer. A logic high on the CSB pin followed by a logic low resets the SPI port to its initial state and defines the start of the instruction cycle. From this point, the next eight rising SCLK edges define the eight bits of the instruction byte for the current communication cycle. The remaining SCLK edges are for Phase 2 of the communication cycle, which is the data transfer between the serial port controller and the system controller. Phase 2 can be a transfer of 1, 2, 3, or 4 data bytes as determined by the instruction byte. Using multibyte transfers is usually preferred although single-byte data transfers are useful to reduce CPU overhead or when only a single register access is required. All serial port data is transferred to and from the device in synchronization with the SCLK pin. Input data is always latched on the rising edge of SCLK whereas output data is always valid after the falling edge of SCLK. Register contents change immediately upon writing to the last bit of each transfer byte. Anytime synchronization is lost, the device has the ability to asynchronously terminate an I/O operation whenever the CSB pin is taken to logic high. Any unwritten register content data is lost if the I/O operation is aborted. Taking CSB low then resets the serial port controller and restarts the communication cycle. INSTRUCTION BYTE The instruction byte contains the information shown in Table 9. Table 9. MSB B7 R/W B6 N1 B5 N0 B4 A4 B3 A3 B2 A2 B1 A1 LSB B0 A0 Bit 7, R/W, determines whether a read or a write data transfer occurs after the instruction byte write. Logic high indicates a read operation. Logic 0 indicates a write operation. Bits<6:5>, N1 and N0, determine the number of bytes to be transferred during the data transfer cycle. The bits decode as shown in Table 10. Table 10. Byte Transfer Count N1 0 0 1 1 Rev. PrG | Page 18 of 32 N0 0 1 0 1 Description Transfer one byte Transfer two bytes Transfer three bytes Transfer four bytes Preliminary Technical Data AD9780/AD9781/AD9783 Serial Port Data I/O (SDIO) Data is always written into the device on this pin. However, SDIO can also function as a bidirectional data output line. The configuration of this pin is controlled by Register 0x00, Bit 7. The default is Logic 0, which configures the SDIO pin as unidirectional. Serial Port Data Output (SDO) Data is read from this pin for protocols that use separate lines for transmitting and receiving data. The configuration of this pin is controlled by Register 0x00, Bit 7. If this bit is set to a Logic 1, the SDO pin does not output data and is set to a high impedance state. MSB/LSB TRANSFERS When using MSB-first format (LSBFIRST = 0), the instruction and data bit must be written from MSB to LSB. Multibyte data transfers in MSB-first format start with an instruction byte that includes the register address of the most significant data byte. Subsequent data bytes are loaded into sequentially lower address locations. In MSB-first mode, the serial port internal address generator decrements for each byte of the multibyte data transfer. When using LSB-first format (LSBFIRST = 1), the instruction and data bit must be written from LSB to MSB. Multibyte data transfers in LSB-first format start with an instruction byte that includes the register address of the least significant data byte. Subsequent data bytes are loaded into sequentially higher address locations. In LSB-first mode, the serial port internal address generator increments for each byte of the multibyte data transfer. INSTRUCTION CYCLE DATA TRANSFER CYCLE CSB SCLK SDIO R/W N1 N0 A4 A3 A2 A1 A0 SDO D7 D6N D5N D30 D20 D10 D00 D7 D6N D5N D30 D20 D10 D00 06936-052 The serial port can support both MSB-first and LSB-first data formats. This functionality is controlled by Register 0x00, Bit 6. The default is Logic 0, which is MSB-first format. Figure 52. Serial Register Interface, MSB First INSTRUCTION CYCLE DATA TRANSFER CYCLE CSB SCLK SDIO A0 A1 A2 A3 A4 N0 N1 R/W D00 D10 D20 D4 N D5N D6N D7N D00 D10 D2 0 D4 N D5N D6N D7N SDO 06936-053 Bits<4:0>, A4, A3, A2, A1, and A0, determine which register is accessed during the data transfer of the communications cycle. For multibyte transfers, this address is a starting or ending address depending on the current data transfer mode. For MSBfirst format, the specified address is an ending address or the most significant address in the current cycle. Remaining register addresses for multiple byte data transfers are generated internally by the serial port controller by decrementing from the specified address. For LSB-first format, the specified address is a beginning address or the least significant address in the current cycle. Remaining register addresses for multiple byte data transfers are generated internally by the serial port controller by incrementing from the specified address. Figure 53. Serial Register Interface Timing LSB First Use of a single-byte transfer when changing the serial port data format is recommended to prevent unexpected device behavior. tS fSCLK -1 CSB tPWH Chip Select Bar (CSB) Active low input starts and gates a communication cycle. It allows more than one device to be used on the same serial communication lines. CSB must stay low during the entire communication cycle. Incomplete data transfers are aborted anytime the CSB pin goes high. SDO and SDIO pins go to a high impedance state when this input is high. tPWL SCLK tDS SDIO tDH INSTRUCTION BIT 7 INSTRUCTION BIT 6 06936-054 SERIAL INTERFACE PORT PIN DESCRIPTIONS Figure 54. Timing Diagram for SPI Write Register CSB Serial Clock (SCLK) SCLK tDV SDIO SDO Rev. PrG | Page 19 of 32 DATA BIT N DATA BIT N - 1 Figure 55. Timing Diagram for SPI Read Register 06936-055 The serial clock pin is used to synchronize data to and from the device and to run the internal state machines. The maximum frequency of SCLK is 40 MHz. All data input is registered on the rising edge of SCLK. All data is driven out on the falling edge of SCLK. AD9780/AD9781/AD9783 Preliminary Technical Data SPI REGISTER MAP Table 11. Register Name SPI Control Data Control Power Down Setup and Hold Timing Adjust Seek Addr 0x00 0x02 0x03 0x04 0x05 0x06 Default 0x00 0x00 0x00 0x00 0x00 0x00 Mix Mode DAC1 FSC DAC1 FSC MSBs AUXDAC1 AUXDAC1 MSB DAC2 FSC DAC2 FSC MSBs AUXDAC2 AUXDAC2 MSB BIST Control BIST Result 1 Low BIST Result 1 High BIST Result 2 Low BIST Result 2 High Hardware Version 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F 0x10 0x11 0x12 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F 0x00 0xF9 0x01 0x00 0x00 0xF9 0x01 0x00 0x00 0x00 0x00 0x00 0x00 0x00 N/A Bit 7 SDIO_DIR DATA PD_DCO SET<3:0> Bit 6 LSBFIRST ONEPORT PD_INPT Bit 5 RESET PD_AUX2 Bit 4 Bit 3 Bit 2 INVDCO PD_AUX1 PD_BIAS PD_CLK HLD<3:0> SAMP_DLY<4:0> LVDS Low DAC1MIX<1:0> Bit 1 Bit 0 PD_DAC2 PD_DAC1 LVDS SEEK High DAC2MIX<1:0> DAC1FSC<7:0> DAC1FSC<9:8> AUXDAC1<7:0> AUX1SGN AUX1DIR DAC2FSC<7:0> AUXDAC1<9:8> DAC2FSC<9:8> AUXDAC2<7:0> AUX2SGN AUX2DIR BISTEN BISTRD BISTRES1<7:0> BISTRES1<15:8> BISTRES2<7:0> BISTRES2<15:8> VERSION<3:0> AUXDAC2<9:8> BISTCLR Rev. PrG | Page 20 of 32 DEVICE<2:0> Preliminary Technical Data AD9780/AD9781/AD9783 SPI REGISTER DESCRIPTIONS Reading these registers returns previously written values for all defined register bits, unless otherwise noted. Table 12. Register SPI Control Address 0x00 Bit 7 Name SDIO_DIR Function 0, Operate SPI in 4-wire mode. The SDI pin operates as an input only pin. 1, Operate SPI in 3-wire mode. The SDI pin operates as a bidirectional data line. 0, MSB first per SPI Standard 1, LSB first per SPI Standard Note: Only Change LSB/MSB order in single-byte instructions to avoid erratic behavior due to bit order errors. 0, Execute Software reset of SPI and controllers, reload default register values except register 0x00. 1, Set Software reset, write 0 on the next (or any following) cycle to release the reset. 6 LSBFIRST 5 RESET 7 DATA 4 7 6 5 4 3 2 1 0 7:4 INVDCO PD_DCO PD_INPT PD_AUX2 PD_AUX1 PD_BIAS PD_CLK PD_DAC2 PD_DAC1 SET<3:0> 0, DAC input data is two's compliment binary format. 1, DAC input data is unsigned binary format. 1, Inverts the Data Clock Output. Used for adjusting timing of input data. 1, Power down Data Clock Output driver circuit. 1, Power Down Input.. 1, Power down AUX2 DAC 1, Power down AUX1 DAC. 1, Power down Voltage Reference Bias circuit. 1, Power down DAC Clock input circuit.. 1, Power down DAC2 1, Power down DAC1. 4-bit value used to determine input data setup timing. 3:0 HLD<3:0> 4-bit value used to determine input data hold timing. Data Control 0x02 Power Down 0x03 Setup and Hold 0x04 Timing Adjust Seek 0x05 4:0 SAMP_DLY<4:0> 5-bit values used to optimally posiion input data relative to internal sampling clock. 0x06 2 LVDS High 1 LVDS Low 0 SEEK 3:2 DAC1MIX<1:0> 1:0 DAC2MIX<1:0> One of the LVDS inputs is above the input voltage limits of the IEEE reduced link specification One of the LVDS inputs is below the input voltage limits of the IEEE reduced link specification Indicator bit used with LVDS_SET and LVDS_HLD to determine input data timing margin. 00 - Selects Normal Mode, DAC2. 01 - Selects Return to Zero mode, DAC2. 10 - Selects Return to Zero mode, DAC2. 11 - Selects Mix mode, DAC2. 00 - Selects Normal Mode, DAC1. 01 - Selects Return to Zero mode, DAC1. 10 - Selects Return to Zero mode, DAC1. 11 - Selects Mix mode, DAC1. DAC1 Full-Scale 10 bit adjustment word. 0x3FF, Sets DAC Full-Scale Output Current to the maximum value of 31.68mA . 0x200, Sets DAC Full-Scale Output Current to the nominal value of 20.0mA. 0x000, Sets DAC Full-Scale Output Current to the minimum value of 8.64mA. Mix Mode DAC1 FSC 0x0A 0x0B 0x0C DAC1FSC<9:0> Rev. PrG | Page 21 of 32 AD9780/AD9781/AD9783 Register AUXDAC1 Address 0x0D 0x0E DAC2 FSC 0x0F 0x10 AUXDAC2 0x11 0x12 Bit 7:0 1:0 Name AUXDAC1<9:0> AUXDAC1<9:8> 7 AUX1SGN 6 AUX1DIR BISTEN BISTRD BISTCLR BISTRES1<15:0> Function AUXDAC1 output current adjustment word. 0x3FF, Sets AUXDAC1 Output Current to 2.0 mA. 0x200, Sets AUXDAC1 Output Current to 1.0 mA. 0x000, Sets AUXDAC1 Output Current to 0.0 mA. 0, AUX1_P output pin is active. 1, AUX1_N output pin is active. 0, Configures AUX1 DAC output to source current. 1, Configures AUX1 DAC output to sink current. DAC2 Full-Scale 10 bit adjustment word. 0x3FF, Sets DAC Full-Scale Output Current to the maximum value of 31.68mA . 0x200, Sets DAC Full-Scale Output Current to the nominal value of 20.0mA. 0x000, Sets DAC Full-Scale Output Current to the minimum value of 8.64mA. AUX DAC2 output current adjustment word. 0, AUX2_P output pin is active. 1, AUX2_N output pin is active. 0, Configures AUX2 DAC output to source current. 1, Configures AUX1 DAC output to sink current. 0x3FF, Sets AUXDAC2 Output Current to 2.0 mA. 0x200, Sets AUXDAC2 Output Current to 1.0 mA. 0x000, Sets AUXDAC2 Output Current to 0.0 mA. 1, Enables and starts Built In Self Test. 1, Transfers BIST result registers to SPI for readback. 1, Reset BIST logic and clear BIST result registers. Sixteen bit result generated by BIST 1. BISTRES2<15:0> Sixteen bit result generated by BIST 2. VERSION<3:0> DEVICE<3:0> Read only register. Indicates the version of the chip. Read only register. Indicates the device type. DAC2FSC<9:0> 7:0 7 AUXDAC2<9:0> AUX2SGN 6 AUX2DIR 1:0 BIST Control 0x1A BIST Result1 0x1B 0x1C 0x1D 0x1E 0x1F BIST Result2 Hardware Version 7 6 5 7:0 7:0 7:0 7:0 7:4 3:0 Preliminary Technical Data Rev. PrG | Page 22 of 32 Preliminary Technical Data AD9780/AD9781/AD9783 In general, when the AD9780/AD9781/AD9783 are powered up, an active high pulse applied to the RESET pin should follow. This insures the default state of all control register bits. In addition, once the RESET pin goes low, the SPI port can be activated, so, CSB should be held high. For applications without a controller, the AD9780/AD9781/ AD9783 also supports pin mode operation, which allows some functional options to be pin, selected without the use of the SPI port. Pin mode is enabled anytime the RESET pin is held high. In pin mode, the four SPI port pins take on secondary functions as shown in Table 13. other words, it should be implemented as a seventeenth DATA line with an alternating (010101...) bit sequence. DATA[15:0] DCLK_IN SET_DLY HLD_DLY DSS SDO Q DAC DDCI SEEK FF DDSS CLK CLOCK DISTRIBUTION SMP_DLY DCLK_OUT Figure 56. AD9873 Digital Data Port Pin Mode Function DATA (Register 0x02, Bit 7), bit value (1/0) equals pin state (high/low) Enable Mix Mode, if CSB is high, Register 0x0A is set to 0x05 putting both DAC1 and DAC2 into mix mode Enable full power-down, if SDO is high, Register 0x03 is set to 0xFF PARALLEL DATA PORT INTERFACE The parallel port data interface consists of 18 differential LVDS signals, DCO, DCI, and the sixteen DATA lines (DATA[15:0]), as shown in Figure 56. DCO is the output clock generated by theAD9780/AD9781/AD9783 that is used to clock out the data from the digital data engine. The DATA lines transmit the multiplexed I and Q data words for the I and Q DACs respectively. The DCI provides timing information about the parallel data as well as signals the I/Q status of the data. As shown in Figure 56, the incoming LVDS data is latched by an internally generated clock referred to as the data sampling signal (DSS). DSS is a delayed version of the main DAC clock signal CLKP/CLKN. Optimal positioning of the rising and falling edges of DSS with respect to the incoming DATA signals results in the most robust transmission of the DAC data. Positioning the edges of DSS with respect to the DATA signals is achieved by selecting the value of a programmable delay element, SMP. A procedure for determining optimal value of SMP is given in the Optimizing the Parallel Port Timing section. In addition to properly positioning the DSS edges, maximizing the opening of the eye in the DCLK_IN and DATA signals improves the reliability of the data port interface. The two sources of degradation that reduce the eye in the DCLK_IN and DATA signals are the jitter on these signals and the skew between them. Therefore, it is recommended that the DCLK_IN be generated in the same manner as the DATA signals with the same output driver and data line routing. In OPTIMIZING THE PARALLEL PORT TIMING Before outlining the procedure for determining the delay for SMP (that is, the positioning of DSS with respect to the DATA signals), it is worthwhile describing the simplified block diagram of the digital data port. As can be seen in Figure 56, the DATA signals are latched-in on the rising and falling edges of DSS. From there, the data is demultiplexed and retimed before being sent to the DACs. The DCLK_IN signal provides timing information about the parallel data as well as indicating the destination (that is, I DAC or Q DAC) of the data. A delayed version of DCI is generated by a delay element, SET and is referred to as DDCI. DDCI is sampled by a delayed version of the DSS signal, labeled as DDSS in Figure 56. DDSS is simply DSS delayed by a period of time, HLD. The pair of delays, SET and HLD allow accurate timing information to be extracted from DCLK_IN. Increasing the delay of the HLD block, results in DCLK_IN being sampled later in it's cycle. Increasing the delay of the SET block, results in DCLK_IN being sampled earlier in it's cycle. The result of this sampling is stored and can be queried by reading the SEEK bit. Since DSS and DCLK_IN are the same frequency, the SEEK bit should be a constant value. By varying the SET and HLD delay blocks and seeing the effect on the SEEK bit, the setup and hold timing of DSS with respect to DCLK_IN (and hence, DATA) can be measured. 0ps 2500ps 5000ps t1 DATA I0 7500ps 10000ps t2 Q0 I1 t3 Q1 I2 Q2 DCLK_IN tHLD0 tHLD0 DSS SAMPLE 1 SAMPLE 2 SAMPLE 3 SAMPLE 4 SAMPLE 5 SAMPLE 6 Figure 57. Digital Data Timing The incremental units of SET, HLD, and SMP are in units of real time, not fractions of a clock cycle. The nominal step size Rev. PrG | Page 23 of 32 06936-072 CSB RETIMING AND DEMUX FF Table 13. SPI Pin Functions (Pin Mode) Pin Name SDIO I DAC FF 06936-071 SPI PORT, RESET, AND PIN MODE AD9780/AD9781/AD9783 Preliminary Technical Data Use the following steps to ensure the AD9780/AD9781/AD9783 is configured for a valid sampling time of the DATA signals. Generally speaking, the procedure begins by finding the point in its cycle that DCI is sampled by the rising edge of DSS. Based on this information, a value of SMP is programmed to establish a new and improved sampling point. This new sampling point is then double checked to make sure it is optimally set. 2. 3. 4. 5. Set the values of SMP, SET, and HLD to zero. Read and record the value of the SEEK bit. With SMP and SET set to 0, increment the HLD until the SEEK bit toggles and record the HLD value. This measures the hold time as shown in figure 2. With SMP and HLD set to 0, increment the SET until the SEEK bit toggles and record the SET value. This measures the set-up time as shown in Figure 57. Using the values of SMP, HLD, and SET, the value of SMP can now be determined. If SEEK = 1, and HLD and SET are within 2 counts of each other, then the sampling edge is well positioned and it is unnecesary to increase the SMP delay. Also, if SEEK = 1 and HLD and SET are both greater than 12, then there is a sufficient timing margin and it is unneccesary to increase the SMP delay. 6. If SEEK = 1, and SET is more than two counts higher than HLD, then your timing resembles that shown in Figure 58. Program the value of SMP to be SMP = PER - 40 x (SET - HLD) 9. After programming the calculated value of SMP, verification that the sampling edge occurs in the middle of the valid data window can be done as follows. Set both SET and HLD to zero. Increment SET until the SEEK bit goes low and record that value. Reset SET to zero. Increment HLD until SEEK goes low and record that value. The recorded values of SET and HLD should be within two unit delays of each other if SMP was set correctly. It should be noted that the values of SET and HLD should both be a minimum of 4. If either value is lower than this, then you should check for excessive jitter on your DCLK_IN line, and that the frequency of DCLK_IN does not exceed the datasheet maximum. Another consideration in the timing of the digital data port is the propagation delay variation from DATACLK_OUT to DATACLK_IN. If this varies significantly (more than 25% of SET or HLD) over time due to temperature changes or other effects, then repeat this timing calibration procedure accordingly. 0ns t1 DATA t4 t3 Q1 I2 Q2 I3 t5 Q3 I4 ORIGINAL DSS_ORIG tHLD tSMP_DLY tSET 160 NEW Figure 58. Digital Data Timing Calibration 0ns I0 10ns t2 Q0 I1 15ns t3 Q1 I2 t4 Q2 I3 t5 Q3 I4 DCLK_IN tSET0 tHLD0 ORIGINAL DSS_ORIG (HLD - SET ) DSS_NEW 4 5ns t1 DATA If SEEK = 0, then your timing resembles that shown in Figure 60. Program the value of SMP to be SMP = I1 tHLD0 tSET0 This moves the sampling edge of DSS from the position marked Orig to the position marked New in the figure. 8. t2 Q0 15ns DSS_NEW If SEEK = 1, and HLD is more than two counts higher than SET, then your timing resembles that shown in Figure 59. Program the value of SMP to be SMP = I0 10ns DCLK_IN Where PER is the period of the DAC Clock (CLK) period in picoseconds. This moves the sampling edge of DSS from the position marked Orig, to the position marked New in the figure. 7. 5ns 06936-073 1. the position marked Orig, to the position marked New in the figure. PER + 80 x (HLD - SET ) 320 Where PER is the period of the DAC Clock (CLK) period in picoseconds. This moves the sampling edge of DSS from Rev. PrG | Page 24 of 32 tSET tHLD tSMP_DLY NEW Figure 59. Digital Data Timing Calibration 06936-074 for SET and HLD is 80 psec. The nominal step size for SMP is 160 ps. Note that the value of SMP refers to Register 5, Bits[4:0], SET refers to Register 4, Bits[7:4], and HLD refers to Register 4, Bits[3:0]. Preliminary Technical Data 5ns t1 DATA I0 10ns t2 I1 Q0 t3 Q1 I2 VCM = 400mV 15ns t4 Q2 I3 t5 Q3 CVDD18 1k I4 DSS_ORIG CGND Figure 63. DACCLK VCM Generator Circuit ORIGINAL tHLD tSET FULL-SCALE CURRENT GENERATION tSMP_DLY DSS_NEW NEW Figure 60. Digital Data Timing Calibration DRIVING THE CLK INPUT The CLK input requires a low jitter differential drive signal. It is a PMOS input differential pair powered from the 1.8 V supply, therefore, it is important to maintain the specified 400 mV input common-mode voltage. Each input pin can safely swing from 200 mV p-p to 1 V p-p about the 400 mV common-mode voltage. While these input levels are not directly LVDScompatible, CLK can be driven by an offset ac-coupled LVDS signal, as shown in Figure 61. 0.1F LVDS_P_IN CLKP 50 VCM = 400mV Internal Reference Full-scale current on the I DAC and Q DAC can be set from 8.66 mA to 31.66 mA. Initially, the 1.2 V band gap reference is used to set up a current in an external resistor connected to FSADJ (Pin54). A simplified block diagram of the reference circuitry is shown in Figure 64. The recommended value for the external resistor is 10 k, which sets up an IREFERENCE in the resistor of 120 A, which in turn provides a DAC output fullscale current of 20 mA. Because the gain error is a linear function of this resistor, a high precision resistor improves gain matching to the internal matching specification of the devices. Internal current mirrors provide a current-gain scaling, where I DAC or Q DAC gain is a 10-bit word in the SPI port register. The default value for the DAC gain registers gives a full-scale current output (IFS) of approximately 20 mA, where IFS is equal to: I FS = (86.6 + (0.220 x DAC gain)) x 1000 / R LVDS_N_IN CLKN 0.1F 06936-056 50 Figure 61. LVDS DACCLK Drive Circuit AD9783 If a clean sine clock is available, it can be transformer-coupled to CLK, as shown in Figure 61. Use of a CMOS or TTL clock is also acceptable for lower sample rates. It can be routed through a CMOS to LVDS translator, then ac-coupled, as described in this section. Alternatively, it can be transformer-coupled and clamped, as shown in Figure 62. TTL OR CMOS CLK INPUT 1nF tHLD0 06936-075 tSET0 0.1F 06936-058 1nF 0.1F 287 DCLK_IN 1.2V BAND GAP I DAC GAIN I DAC REFIO 0.1F DAC FULL SCALE REFERENCE CURRENT CURRENT SCALING FS ADJ 10k Q DAC GAIN Q DAC 06936-059 0ns AD9780/AD9781/AD9783 Figure 64. Reference Circuitry 50 CLKP 35 25 A simple bias network for generating VCM is shown in Figure 63. It is important to use CVDD18 and CGND for the clock bias circuit. Any noise or other signal that is coupled onto the clock is multiplied by the DAC digital input signal and can degrade the DAC's performance. 20 15 10 5 0 256 512 DAC GAIN CODE 768 Figure 65. IFS vs. DAC Gain Code Rev. PrG | Page 25 of 32 1024 06936-060 Figure 62. TTL or CMOS DACCLK Drive Circuit IFS (mA) VCM = 400mV 30 06936-057 CLKN 50 BAV99ZXCT HIGH SPEED DUAL DIODE AD9780/AD9781/AD9783 Preliminary Technical Data DAC TRANSFER FUNCTION Each DAC output of the AD9780/AD9781/AD9783 drives two complementary current outputs, IOUTP and IOUTN. IOUTP provides a near IFS when all bits are high. For example, DAC CODE = 2N - 1, where: N = 12-/14-/16-bits for AD9780/AD9781/AD9783 respectively), while IOUTN provides no current. The current output appearing at IOUTP and IOUTN is a function of both the input code and IFS and can be expressed as IOUTP = (DAC DATA/2N) x IFS N (1) N IOUTN = ((2 - 1) - DAC DATA)/2 x IFS (2) from dc to fDAC. Additionally, there is a second subtle effect on the output spectrum. The shifted spectrum is also shaped by a second Sinc function with a first null at 2 x fDAC. The reason for this shaping is that the data is not continuously varying at twice the clock rate, but is simply repeated. In the return-to-zero mode, the output is set to mid-scale every other half clock cycle. The output is similar to the DAC output in normal mode except that the output pulses are half the width and half the area. Because the output pulses have half the width, the sinc function is scaled in frequency by two and has a first null at 2 x fDAC. Because the area of the pulses is half that of the pulses in normal mode, the output power is half the normal mode output power. INPUT DATA D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 N where DAC DATA = 0 to 2 - 1 (decimal representation). DAC CLK VOUTN = IOUTN x RLOAD (4) Note that to achieve the maximum output compliance of 1 V at the nominal 20 mA output current, RLOAD must be set to 50 . Also note that the full-scale value of VOUTP and VOUTN should not exceed the specified output compliance range to maintain specified distortion and linearity performance. There are two distinct advantages to operating the AD9780/ AD9781/AD9783 differentially. First, differential operation helps cancel common-mode error sources associated with IOUTP and IOUTN, such as noise, distortion, and dc offsets. Second, the differential code dependent current and subsequent output voltage (VDIFF) is twice the value of the single-ended voltage output (VOUTP or VOUTN), providing 2x signal power to the load. VDIFF = (IOUTP - IOUTN) x RLOAD (5) ANALOG MODES OF OPERATION TheAD9780/AD9781/AD9783 utilizes a proprietery quadswitch architecture that lowers the distortion of the DAC by eliminating a code dependent glitch that occurs with conventional dual-switch architectures. This architecture eliminates the code dependent glitches, but creates a constant glitch at a rate of 2 x fDAC. For communications systems and other applications requiring good frequency domain performance from the DAC, this is seldom problematic. 4-SWITCH DAC OUTPUT (RETURN-TOZERO MODE) t 06936-061 (3) t Figure 66. Mix Mode and RZ DAC Waveforms The functions that shape the output spectrums for the three modes of operation; normal mode, mix mode and return-tozero mode, are shown in Figure 67. Switching between the analog modes reshapes the sinc roll off inherent at the DAC output. This ability to change modes in the AD9780/ AD9781/AD9783 make the parts suitable for direct IF applications. The user can place a carrier anywhere in the first three nyquist zones depending on the operating mode selected. The performance and maximum amplitude in all three nyquist zones is impacted by this sinc roll off depending on where the carrier is placed, as shown in Figure 67. 0 MIX RZ -10 The quad-switch architecture also supports two additional modes of operation; mix mode and return-to-zero mode. The waveforms of these two modes are shown in Figure 66. In the mix mode, the output is inverted every other half clock cycle. This effectively chops the DAC output at the sample rate. This chopping has the effect of frequency shifting the sinc roll-off Rev. PrG | Page 26 of 32 NORMAL -20 -30 -40 0 0.5 1.0 (fS) 1.5 2.0 Figure 67. Transfer Function for Each Analog Operating Mode 06936-062 VOUTP = IOUTP x RLOAD 4-SWITCH DAC OUTPUT (fS MIX MODE) T(f) (dB) The two current outputs typically drive a resistive load directly or via a transformer. If dc coupling is required, IOUTP and IOUTN should be connected to matching resistive loads (RLOAD) that are tied to analog common (AVSS). The single-ended voltage output appearing at the IOUTP and IOUTN pins is Preliminary Technical Data AD9780/AD9781/AD9783 Auxiliary DACS 0.50 Two auxiliary DACs are provided on the AD9780/AD9781/ AD9783. A functional diagram is shown in Figure 68. The auxiliary DACs are current output devices with two output pins, AUXP and AUXN. The active pin can be programmed to either source or sink current. When either sinking or sourcing, the fullscale current magnitude is 2 mA. The available compliance range at the auxiliary DAC outputs depends on whether the output is configured to a sink or source current. When sourcing current, the compliance voltage is 0 V to 1.6 V but when sinking current the output compliance voltage is reduced to 0.8 V to 1.6 V. Either output can be used, but only one output of the AUX DAC (P or N) is active at any time. The inactive pin is always in a high impedance state (>100 k). 0.45 0.40 POWER (W) 0.35 0.30 0.25 0.20 0.15 0.10 0 0 100 200 300 400 500 600 CLOCK SPEED (MSPS) 06936-065 0.05 Figure 70. Power Dissipation, I Data Only, Single DAC Mode 0mA TO 2mA 0.200 AUXP VBIAS 0.175 AUXN 0.150 Figure 68. Auxiliary DAC Functional Diagram In a single sideband transmitter application, the combination of the input referred dc offset voltage of the quadrature modulator and the DAC output offset voltage can result in local oscillator (LO) feedthrough at the modulator output, which degrades system performance. The auxiliary DACs can be used to remove the dc offset and the resulting LO feedthrough. The circuit configuration for using the auxiliary DACs for performing dc offset correction depends on the details of the DAC and modulator interface. An example of a dc-coupled configuration with low-pass filtering is outlined in the Figure 69. 0.075 DVDD18 CVDD 0.025 0 0 100 200 300 400 500 600 CLOCK SPEED (MSPS) Figure 71. Power Dissipation, Digital 1.8 V Supply, Clock 1.8 V Supply I Data Only 0.200 0.175 0.150 POWER (W) AUX DAC1 OR DAC2 0.100 0.050 QUADRATURE MODULATOR V+ AD9783 0.125 06936-066 POSITIVE OR NEGATIVE POWER (W) SINK OR SOURCE 06936-063 0mA TO 2mA QUAD MOD I OR Q INPUTS 0.125 AVDD33 0.100 0.075 0.050 DVDD3 DAC1 OR DAC2 OPTIONAL PASSIVE FILTERING 25 TO 50 0 0 100 200 300 400 CLOCK SPEED (MSPS) 25 TO 50 06936-064 AD9783 500 600 06936-067 0.025 Figure 72. Power Dissipation, Digital 3.3 V Supply, Analog 3.3 V Supply, I Data Only Figure 69. DAC DC Coupled to Quadrature Modulator with Passive DC Shift POWER DISSIPATION Figure 70 through Figure 75 show the power dissipation of the part in single DAC and dual DAC modes. Rev. PrG | Page 27 of 32 AD9780/AD9781/AD9783 Preliminary Technical Data 0.200 0.50 0.45 AVDD33 0.175 0.40 0.150 0.30 POWER (W) POWER (W) 0.35 0.25 0.20 0.125 0.100 0.075 0.15 0.050 0.10 100 200 300 400 500 600 0 CLOCK SPEED (MSPS) Figure 73. . Power Dissipation, I and Q Data Only, Dual DAC Mode POWER (W) 0.150 0.125 0.100 DVDD18 0.050 CVDD 0 100 200 300 400 CLOCK SPEED (MSPS) 500 600 06936-069 0 200 300 400 500 600 Figure 75. Power Dissipation, Digital 3.3 V Supply, Analog 3.3 V Supply I and Q Data Dual DAC Mode 0.175 0.025 100 CLOCK SPEED (MSPS) 0.200 0.075 0 06936-070 0 06936-068 0 DVDD3 0.025 0.05 Figure 74. Power Dissipation, Digital 1.8 V Supply, Clock 1.8 V Supply I and Q Data Dual DAC Mode Rev. PrG | Page 28 of 32 Preliminary Technical Data AD9780/AD9781/AD9783 OUTLINE DIMENSIONS 0.30 0.23 0.18 0.60 MAX 10.00 BSC SQ 0.60 MAX 55 54 PIN 1 INDICATOR 0.50 BSC 9.75 BSC SQ TOP VIEW 72 1 PIN 1 INDICATOR 4.70 BSC SQ EXPOSED PAD (BOTTOM VIEW) 0.50 0.40 0.30 0.80 MAX 0.65 TYP 12 MAX 9.00 REF EXPOSED PAD MUST BE SOLDERED TO PCB AND CONNECTED TO AVSS. 0.05 MAX 0.02 NOM SEATING PLANE 0.20 REF COMPLIANT TO JEDEC STANDARDS MO-220-VNND-3 042407-0 1.00 0.85 0.80 18 19 37 36 Figure 76. 72-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 10 mm x 10 mm, Very Thin Quad (CP-72-1) Dimensions shown in millimeters ORDERING GUIDE Model AD9780BCPZ1 AD9780BCPZRL71 AD9781BCPZ1 AD9781BCPZRL71 AD9783BCPZ1 AD9783BCPZRL71 AD9780-EB1 AD9781-EB1 AD9783-EB1 1 Temperature Range -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C Package Description 72-Lead LFCSP 72-Lead LFCSP 72-Lead LFCSP 72-Lead LFCSP 72-Lead LFCSP 72-Lead LFCSP Evaluation Board Evaluation Board Evaluation Board Z = RoHS Compliant Part. Rev. PrG | Page 29 of 32 Package Option CP-72-1 CP-72-1 CP-72-1 CP-72-1 CP-72-1 CP-72-1 AD9780/AD9781/AD9783 Preliminary Technical Data NOTES Rev. PrG | Page 30 of 32 Preliminary Technical Data AD9780/AD9781/AD9783 NOTES Rev. PrG | Page 31 of 32 AD9780/AD9781/AD9783 Preliminary Technical Data NOTES (c)2007 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. PR06936-0-9/07(PrG) Rev. PrG | Page 32 of 32